Method for manufacturing semiconductor device

Abstract

One embodiment of the present invention provides a method for manufacturing a semiconductor device with high reliability. The method includes the following steps: forming an oxide semiconductor film at a first temperature; processing the oxide semiconductor film into an island shape; forming a component to be a source electrode and a drain electrode by a sputtering method without performing a process at a temperature higher than the first temperature; processing the component to form the source electrode and the drain electrode; forming a first barrier film after forming a protective insulating film; adding excess oxygen or oxygen radicals to the protective insulating film through the first barrier film; diffusing the excess oxygen or oxygen radicals into the oxide semiconductor film by performing a heat treatment at a second temperature lower than 400°C; and forming a second barrier film after removing a portion of the first barrier film and a portion of the protective insulating film by wet etching.

Description

[0001] This application is a divisional application of an application filed on January 28, 2016, with PCT application number PCT / IB2016 / 050417, which entered the Chinese national phase on August 2, 2017, with Chinese application number 201680008319.6, and with the invention name “Method for manufacturing a semiconductor device”. Technical Field

[0002] One embodiment of the present invention relates to a semiconductor device including an oxide semiconductor film and a display device including the semiconductor device. Another embodiment of the present invention relates to a method for manufacturing a semiconductor device including an oxide semiconductor film.

[0003] Note that one embodiment of the present invention is not limited to the above-mentioned technical field. The technical field of one embodiment of the invention disclosed in this specification, etc. relates to an object, method or manufacturing method. In addition, the present invention relates to a process, machine, product or composition of matter. In particular, one embodiment of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a storage device, a driving method thereof or a manufacturing method thereof.

[0004] In this specification, etc., semiconductor devices refer to all devices that can work by utilizing semiconductor characteristics. Semiconductor elements such as transistors, semiconductor circuits, computing devices, and storage devices are all forms of semiconductor devices. Camera devices, display devices, liquid crystal display devices, light-emitting devices, electro-optical devices, power generation devices (including thin-film solar cells and organic thin-film solar cells, etc.) and electronic devices sometimes include semiconductor devices. Background Art

[0005] The technology of forming a transistor (also called a field effect transistor (FET) or a thin film transistor (TFT)) by using a semiconductor film formed on a substrate having an insulating surface has attracted attention. Such transistors are widely used in electronic devices such as integrated circuits (ICs) and image display devices (display devices). As semiconductor films that can be applied to transistors, semiconductor materials represented by silicon are widely known. As other materials, oxide semiconductors have attracted attention.

[0006] A highly reliable semiconductor device has been disclosed in which a transistor using an oxide semiconductor has stable electrical characteristics (for example, see Patent Document 1). In this semiconductor device, oxide semiconductor films of different compositions are stacked, an oxide semiconductor film containing a large amount of In is located on the channel side, and an oxide semiconductor film containing a large amount of a stabilizer such as Ga is located on the back channel side.

[0007] [References]

[0008] [Patent Document]

[0009] [Patent Document 1] Japanese Patent Application Publication No. 2013-175715 Summary of the invention

[0010] Oxide semiconductor films containing a large amount of In may have a small energy band gap (E g )(For example, E g Less than 3.0 eV). g Smaller oxide semiconductor film than E g Larger oxide semiconductor films (e.g., E g is greater than 3.0 eV and less than 3.5 eV) is more affected by light. g When a transistor having a relatively small oxide semiconductor film is subjected to a stress test in which a negative bias voltage is applied by irradiating light (a photo-negative GBT (negative gate bias temperature) stress test), the reliability of the transistor may be reduced.

[0011] The photo-negative GBT stress test is an accelerated test that can evaluate the change in transistor characteristics caused by long-term use under light irradiation in a short period of time. In particular, the change in the threshold voltage of the transistor before and after the photo-negative GBT stress test (△V th ) is an important indicator for checking reliability. The change in threshold voltage (△V th ) is smaller, the higher the reliability of the transistor.

[0012] In the case of using a glass substrate to manufacture a semiconductor device including an oxide semiconductor film, the glass substrate may be deformed when the process temperature is high. The glass substrate is significantly deformed when the glass substrate has the following large sizes: 6th generation (1500mm×1850mm), 7th generation (1870mm×2200mm), 8th generation (2200mm×2400mm), 9th generation (2400mm×2800mm), 10th generation (2950mm×3400mm). Therefore, it is necessary to reduce the temperature in the process of manufacturing the semiconductor device.

[0013] In view of the above problems, an object of one embodiment of the present invention is to suppress the variation of electrical characteristics and improve reliability in a transistor including an oxide semiconductor film containing a large amount of In. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption. Another object of one embodiment of the present invention is to provide a novel semiconductor device. Another object of one embodiment of the present invention is to provide a method for manufacturing a novel semiconductor device. Another object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with high reliability at a lower temperature. Another object of one embodiment of the present invention is to provide a novel method for manufacturing a display device.

[0014] Note that the description of the above-mentioned purpose does not prevent the existence of other purposes. In one embodiment of the present invention, it is not necessary to achieve all of the above-mentioned purposes. Purposes other than the above-mentioned purpose are obvious from the description of the specification, etc., and can be extracted from the specification, etc.

[0015] One embodiment of the present invention is a method for manufacturing a semiconductor device, comprising the following steps: forming an oxide semiconductor film at a first temperature; then, processing the oxide semiconductor film into an island shape; then, forming a component that will become a source electrode and a drain electrode by a sputtering method without performing a process at a temperature higher than the first temperature; processing the component to form a source electrode and a drain electrode; then, forming a first barrier film after forming a first protective insulating film and / or a second protective insulating film; adding excess oxygen or oxygen radicals to the second protective insulating film through the first barrier film; diffusing the excess oxygen or oxygen radicals into the oxide semiconductor film by performing a heat treatment at a second temperature lower than 400°C; and forming a second barrier film after removing the first barrier film or a portion of the first barrier film and a portion of the second protective insulating film by wet etching.

[0016] In the above embodiment, the first barrier film is preferably an indium tin oxide film, an indium tin silicon oxide film, or an indium oxide film.

[0017] In the above embodiment, the second barrier film is preferably a silicon nitride oxide film or a silicon nitride film.

[0018] Another embodiment of the present invention is a method for manufacturing a semiconductor device, comprising the following steps: forming an oxide semiconductor film at a first temperature; then, processing the oxide semiconductor film into an island shape; then, forming a component that will become a source electrode and a drain electrode by a sputtering method without performing a process at a temperature higher than the first temperature; processing the component to form a source electrode and a drain electrode; then, after forming a first protective insulating film and / or a second protective insulating film, forming a metal oxide film by a sputtering method as a first barrier film, thereby adding excess oxygen or oxygen free radicals to the second protective insulating film; and diffusing the excess oxygen or oxygen free radicals into the oxide semiconductor film by performing a heat treatment at a second temperature lower than 400°C.

[0019] In the above embodiment, the metal oxide film is preferably an aluminum oxide film, a hafnium oxide film, or a yttrium oxide film.

[0020] In the above method, the oxide semiconductor film preferably has a stacked structure of a first oxide semiconductor film having an atomic ratio of In:M (aluminum, gallium, yttrium or tin):Zn=4:α1 (1.5≤α1≤2.5):α2 (2.5≤α2≤3.5) and a second oxide semiconductor film having an atomic ratio of In:M:Zn=1:β1 (0.8≤β1≤1.2):β2 (0.8≤β2≤1.2).

[0021] In the above embodiment, the oxide semiconductor film preferably includes CAAC-OS.

[0022] In the above embodiment, the second temperature is preferably lower than 375° C. In the above embodiment, the second temperature is preferably 340° C. or higher and 360° C. or lower.

[0023] Another embodiment of the present invention is a method for manufacturing a semiconductor device, comprising the following steps: forming an oxide semiconductor film at a first temperature; processing the oxide semiconductor film into an island shape; forming a component to be a source electrode and a drain electrode on the oxide semiconductor film by a sputtering method; processing the component to form a source electrode and a drain electrode; forming a first protective insulating film and a second protective insulating film on the oxide semiconductor film, the source electrode and the drain electrode; heating the first protective insulating film and the second protective insulating film at a second temperature higher than the first temperature; forming a first barrier film on the second protective insulating film; adding excess oxygen or oxygen radicals to the second protective insulating film through the first barrier film; removing a portion of the first barrier film and a portion of the second protective insulating film by wet etching; and forming a second barrier film on the second protective insulating film at a third temperature higher than the first temperature. One or both of the second temperature and the third temperature are the highest temperatures in the process of the above steps.

[0024] In the above method, the oxide semiconductor film preferably has a stacked structure of a first oxide semiconductor film having an atomic ratio of In:M (aluminum, gallium, yttrium or tin):Zn=4:α1 (1.5≤α1≤2.5):α2 (2.5≤α2≤3.5) and a second oxide semiconductor film having an atomic ratio of In:M:Zn=1:β1 (0.8≤β1≤1.2):β2 (0.8≤β2≤1.2).

[0025] In the above aspect, the oxide semiconductor film preferably includes a crystal portion, and the crystal portion preferably has c-axis orientation.

[0026] In the above embodiment, the first temperature is preferably lower than 340° C. In the above embodiment, the first temperature is preferably 100° C. or higher and 200° C. or lower.

[0027] In the above embodiment, the second temperature is preferably lower than 375° C. In the above embodiment, the second temperature is preferably 340° C. or higher and 360° C. or lower.

[0028] Another embodiment of the present invention is a method for manufacturing a semiconductor device, comprising the following steps: forming an oxide semiconductor film at a first temperature; processing the oxide semiconductor film into an island shape; forming a member to be a source electrode and a drain electrode on the oxide semiconductor film by a sputtering method; processing the member to form the source electrode and the drain electrode; forming a first protective insulating film and a second protective insulating film on the oxide semiconductor film, the source electrode and the drain electrode; heating the first protective insulating film and the second protective insulating film at a second temperature higher than the first temperature; forming a metal oxide film on the second protective insulating film to add excess oxygen or oxygen radicals to the second protective insulating film; and heating the second protective insulating film at a third temperature higher than the first temperature to diffuse the excess oxygen or oxygen radicals into the oxide semiconductor film. One or both of the second temperature and the third temperature are the highest temperatures in the process.

[0029] Another embodiment of the present invention is a method for manufacturing a semiconductor device, comprising the following steps: forming an oxide semiconductor film at a first temperature; processing the oxide semiconductor film into an island shape; forming a member to be a source electrode and a drain electrode on the oxide semiconductor film by a sputtering method; processing the member to form a source electrode and a drain electrode; forming a first protective insulating film and a second protective insulating film on the oxide semiconductor film, the source electrode and the drain electrode; heating the first protective insulating film and the second protective insulating film at a second temperature higher than the first temperature; and forming a metal oxide film on the second protective insulating film at a third temperature higher than the first temperature to add excess oxygen or oxygen radicals to the second protective insulating film, and diffuse the oxygen, excess oxygen or oxygen radicals in the second protective insulating film into the oxide semiconductor film. One or both of the second temperature and the third temperature are the highest temperatures in the process of the above steps.

[0030] In the above embodiment, the metal oxide film is preferably an aluminum oxide film, a hafnium oxide film, or a yttrium oxide film.

[0031] In the above method, the oxide semiconductor film preferably has a stacked structure of a first oxide semiconductor film having an atomic ratio of In:M (aluminum, gallium, yttrium or tin):Zn=4:α1 (1.5≤α1≤2.5):α2 (2.5≤α2≤3.5) and a second oxide semiconductor film having an atomic ratio of In:M:Zn=1:β1 (0.8≤β1≤1.2):β2 (0.8≤β2≤1.2).

[0032] In the above aspect, the oxide semiconductor film preferably includes a crystal portion, and the crystal portion preferably has c-axis orientation.

[0033] In the above embodiment, the first temperature is preferably lower than 340° C. In the above embodiment, the first temperature is preferably 100° C. or higher and 200° C. or lower.

[0034] In the above embodiment, one or both of the second temperature and the third temperature are preferably lower than 375° C. In the above embodiment, one or both of the second temperature and the third temperature are preferably 340° C. or higher and 360° C. or lower.

[0035] According to one embodiment of the present invention, in a semiconductor device using a transistor including an oxide semiconductor, changes in electrical characteristics can be suppressed and reliability can be improved. According to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided. According to one embodiment of the present invention, a novel method for manufacturing a semiconductor device can be provided. According to one embodiment of the present invention, a method for manufacturing a semiconductor device with high reliability at a lower temperature can be provided. According to one embodiment of the present invention, a novel display device can be provided.

[0036] Note that the description of these effects does not prevent the existence of other effects. One mode of the present invention does not need to achieve all of the above effects. Effects other than these effects are obvious from the description of the specification, drawings, claims, etc., and effects other than these effects can be extracted from the description of the specification, drawings, claims, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figures 1A to 1C It is a cross-sectional view showing an example of a manufacturing process of a semiconductor device.

[0038] FIG. 2A to FIG. 2C It is a cross-sectional view showing an example of a manufacturing process of a semiconductor device.

[0039] FIG. 3A to FIG. 3C It is a cross-sectional view showing an example of a manufacturing process of a semiconductor device.

[0040] FIG. 4A to FIG. 4C It is a cross-sectional view showing an example of a manufacturing process of a semiconductor device.

[0041] FIG. 5A to FIG. 5C A cross-sectional view showing an example of a manufacturing process of a semiconductor device and a cross-sectional view and a plan view of one embodiment of a semiconductor device.

[0042] Fig. 6A and Figure 6B A plan view and a cross-sectional view showing one embodiment of a semiconductor device.

[0043] FIG. 7A to FIG. 7C It is a cross-sectional view showing an example of a manufacturing process of a semiconductor device.

[0044] Figure 8 The band structure is shown.

[0045] Fig.9A and Fig. 9B This is a cross-sectional view showing one embodiment of a semiconductor device.

[0046] FIG. 10A to FIG. 10D It is a Cs-corrected high-resolution TEM image of a cross section of CAAC-OS and a schematic cross-sectional view of CAAC-OS.

[0047] FIG. 11A to FIG. 11D This is a Cs-corrected high-resolution TEM image of the plane of CAAC-OS.

[0048] FIG. 12A to FIG. 12C Structural analysis of CAAC-OS and a single crystal oxide semiconductor by XRD is shown.

[0049] Fig.13A and Fig. 13B An electron diffraction pattern of CAAC-OS is shown.

[0050] Fig.14 The figure shows the changes in the crystal part of In-Ga-Zn oxide caused by electron irradiation.

[0051] Fig.15A and Fig. 15B Schematic diagram showing the film formation model of CAAC-OS and nc-OS.

[0052] FIG. 16A to FIG. 16C InGaZnO 4 of crystals and particles.

[0053] 17A to 17D is a schematic diagram showing a film formation model of CAAC-OS.

[0054] Fig.18 This is a plan view showing one embodiment of a display device.

[0055] Fig.19 This is a cross-sectional view showing one embodiment of a display device.

[0056] Fig. 20 This is a cross-sectional view showing one embodiment of a display device.

[0057] FIG. 21A to FIG. 21C 1 is a block diagram and a circuit diagram showing a display device.

[0058] Fig. 22 A display module is shown.

[0059] FIG. 23A to FIG. 23G An electronic device is shown.

[0060] Fig.24 The circuit structure of a semiconductor device is shown.

[0061] FIG. 25A to FIG. 25C The I of the transistor in the embodiment is shown. d -V g characteristic. DETAILED DESCRIPTION

[0062] The following describes the embodiments with reference to the accompanying drawings. A person skilled in the art can easily understand that the embodiments can be implemented in a plurality of different forms, and the methods and details can be transformed into various forms without departing from the purpose and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the contents described in the embodiments shown below.

[0063] In the accompanying drawings, for the sake of clarity, the size, thickness of the layer or the area are sometimes exaggerated. Therefore, one embodiment of the present invention is not necessarily limited to the above-mentioned dimensions. In addition, the accompanying drawings are schematic diagrams showing ideal examples, so one embodiment of the present invention is not limited to the shapes or values ​​shown in the accompanying drawings.

[0064] In this specification, ordinal numbers such as “first”, “second”, and “third” are used to avoid confusion among constituent elements, and are not intended to limit the number.

[0065] In this specification, when describing the positional relationship of components with reference to the drawings, for the sake of convenience, words and phrases such as "upper" and "lower" are used to indicate the configuration. In addition, the positional relationship of the components is appropriately changed according to the direction in which each component is described. Therefore, the above-mentioned positional relationship is not limited to the words and phrases described in this specification, and other words and phrases can be appropriately used to describe it according to the situation.

[0066] In this specification, etc., a transistor is an element including at least three terminals: a gate, a drain, and a source. The transistor has a channel region between a drain (drain terminal, a drain region, or a drain electrode) and a source (source terminal, a source region, or a source electrode), and current can flow through the drain, the channel region, and the source. Note that in this specification, etc., the channel region refers to a region where current mainly flows.

[0067] In addition, for example, when transistors with different polarities are used or when the direction of current changes during circuit operation, the functions of the source and drain may be interchanged. Therefore, in this specification, "source" and "drain" may be interchanged.

[0068] In this specification, etc., "electrical connection" includes the case where components are connected to each other through "elements having some kind of electrical function". "Elements having some kind of electrical function" are not particularly limited as long as they can transmit and receive electrical signals between the above-mentioned components. In addition to electrodes and wiring, examples of "elements having some kind of electrical function" are switching elements such as transistors, resistors, inductors, capacitors, and elements having various functions.

[0069] In this specification and the like, a “silicon oxynitride film” refers to a film containing more oxygen than nitrogen in its composition, and a “silicon nitride oxide film” refers to a film containing more nitrogen than oxygen in its composition.

[0070] In this specification and the like, when describing the configuration of the present invention using drawings, common reference numerals are used for the same components in different drawings.

[0071] In this specification, etc., "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. "Approximately parallel" refers to a state where the angle formed by two straight lines is greater than -30° and less than 30°. In addition, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°. "Approximately perpendicular" refers to a state where the angle formed by two straight lines is greater than 60° and less than 120°.

[0072] In this specification, "film" and "layer" may be interchanged depending on the situation. For example, "conductive layer" may be replaced by "conductive film". Also, "insulating film" may be replaced by "insulating layer".

[0073] Implementation Method 1

[0074] In this embodiment, refer to Figures 1A to 1C , FIG. 2A to FIG. 2C , FIG. 3A to FIG. 3C , FIG. 4A to FIG. 4C , FIG. 5A to FIG. 5C , Fig. 6A and Figure 6B , FIG. 7A to FIG. 7C , Figure 8 , Fig.9A and Fig. 9B A semiconductor device and a method for manufacturing the semiconductor device according to one embodiment of the present invention will be described.

[0075] <Structural Example 1 of Semiconductor Device>

[0076] Figure 5C FIG. 1 is a top view of a transistor 100 which is a semiconductor device according to one embodiment of the present invention. Figure 5B It is along Figure 5CThe cross-sectional view along the dotted line X1-X2 and the Figure 5C In addition, Figures 1A to 1C , FIG. 2A to FIG. 2C , FIG. 3A to FIG. 3C , FIG. 4A to FIG. 4C as well as Figure 5A Yes Description Figure 5B A cross-sectional view of a manufacturing process of transistor 100 is shown. Figures 1A to 1C , FIG. 2A to FIG. 2C , FIG. 3A to FIG. 3C , FIG. 4A to FIG. 4C as well as Figure 5A and Figure 5B In the figure, the left side shows a cross-sectional view along the dashed line X1-X2, and the right side shows a cross-sectional view along the dashed line Y1-Y2.

[0077] In addition, Figure 5C For the sake of convenience, a part of the components of the transistor 100 (for example, an insulating film used as a gate insulating film) is omitted. The direction of the dot-dash line X1-X2 is sometimes referred to as the channel length direction, and the direction of the dot-dash line Y1-Y2 is sometimes referred to as the channel width direction. Figure 5C Similarly, part of the components may be omitted in a plan view of a transistor described later.

[0078] The transistor 100 includes: a conductive film 104 serving as a gate electrode on a substrate 102; an insulating film 106 on the substrate 102 and the conductive film 104; an insulating film 107 on the insulating film 106; an oxide semiconductor film 108 on the insulating film 107; a conductive film 112a serving as a source electrode electrically connected to the oxide semiconductor film 108; and a conductive film 112b serving as a drain electrode electrically connected to the oxide semiconductor film 108. On the transistor 100, specifically, insulating films 114, 116, and 118 are provided on the conductive films 112a, 112b, and the oxide semiconductor film 108. The insulating films 114, 116, and 118 have the function of protective insulating films of the transistor 100. The insulating film 114, the insulating film 116, and the insulating film 118 are referred to as a first protective insulating film, a second protective insulating film, and a third protective insulating film, respectively.

[0079] The oxide semiconductor film 108 includes a first oxide semiconductor film 108 a located on one side of the conductive film 104 and a second oxide semiconductor film 108 b over the first oxide semiconductor film 108 a. The conductive film 104 functions as a gate electrode. The insulating films 106 and 107 function as gate insulating films of the transistor 100.

[0080] In—M (M is aluminum, gallium, yttrium, or tin) oxide or In—M—Zn oxide can be used as the oxide semiconductor film 108. In particular, In—M—Zn oxide is preferably used as the oxide semiconductor film 108.

[0081] The atomic number ratio of the first oxide semiconductor film 108a is preferably In:M:Zn=4:α1(1.5≤α1≤2.5):α2(2.5≤α2≤3.5). The atomic number ratio of the second oxide semiconductor film 108b is preferably In:M:Zn=1:β1(0.8≤β1≤1.2):β2(0.8≤β2≤1.2).

[0082] When the first oxide semiconductor film 108a has the above atomic ratio, that is, the atomic ratio of In is greater than the atomic ratio of M, the field effect mobility (abbreviated as mobility or μFE) of the transistor 100 can be improved. Specifically, the field effect mobility of the transistor 100 can be higher than 10 cm 2 / Vs, preferably higher than 30cm 2 / Vs.

[0083] For example, by using the above-mentioned transistor with high field effect mobility for a gate driver that generates a gate signal (particularly, a demultiplexer connected to the output terminal of a shift register included in the gate driver), a semiconductor device or display device with a narrow frame width can be provided.

[0084] On the other hand, when the first oxide semiconductor film 108a has a composition in which the atomic number ratio of In is greater than the atomic number ratio of M, the electrical characteristics of the transistor 100 when irradiated with light are likely to change. However, in a semiconductor device according to one embodiment of the present invention, a second oxide semiconductor film 108b is formed on the first oxide semiconductor film 108a. Since the atomic number ratio of In in the second oxide semiconductor film 108b is smaller than that of the first oxide semiconductor film 108a, the E of the second oxide semiconductor film 108b is g Therefore, the oxide semiconductor film 108 having a stacked-layer structure of the first oxide semiconductor film 108 a and the second oxide semiconductor film 108 b has high resistance to a light negative bias stress test.

[0085] When irradiated with light, the amount of light absorbed by the oxide semiconductor film 108 having the stacked-layer structure is reduced. Therefore, changes in the electrical characteristics of the transistor 100 due to irradiation with light can be reduced.

[0086] When oxygen defects are formed in the oxide semiconductor film 108 included in the transistor 100, electrons are generated as carriers, so that the transistor 100 tends to have a normally-on characteristic. Note that a normally-on transistor is one that turns on when the gate voltage V g When the current is 0V (for example, the current between the drain and the source (I ds )) flows. Therefore, in order to obtain stable transistor characteristics, it is important to reduce oxygen defects in the oxide semiconductor film 108, especially to reduce oxygen defects in the first oxide semiconductor film 108a. In the structure of a transistor of one embodiment of the present invention, excess oxygen is introduced into the insulating film on the oxide semiconductor film 108, here, the insulating film 114 and / or the insulating film 116 on the oxide semiconductor film 108, so that oxygen moves from the insulating film 114 and / or the insulating film 116 to the oxide semiconductor film 108, thereby filling the oxygen defects in the oxide semiconductor film 108, especially the oxygen defects in the first oxide semiconductor film 108a. Alternatively, when a first barrier film is formed on the insulating film 116, excess oxygen is introduced into the insulating film 116, so that oxygen moves from the insulating film 116 to the oxide semiconductor film 108, thereby filling the oxygen defects in the oxide semiconductor film 108, especially the oxygen defects in the first oxide semiconductor film 108a.

[0087] Preferably, the insulating films 114 and 116 have a region containing oxygen exceeding the stoichiometric composition (oxygen excess region). In other words, the insulating films 114 and 116 are insulating films that can release oxygen. In addition, for example, oxygen is introduced into the insulating films 114 and 116 after film formation to form the oxygen excess region in the insulating films 114 and 116. As a method for introducing oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, a plasma treatment, etc. can be used.

[0088] In order to fill the oxygen vacancies in the first oxide semiconductor film 108a, the thickness of the channel region and the vicinity of the second oxide semiconductor film 108b is preferably reduced. For example, the thickness of the channel region and the vicinity of the second oxide semiconductor film 108b is preferably greater than 1 nm and less than 20 nm, and more preferably greater than 3 nm and less than 10 nm.

[0089] In order to fill oxygen vacancies in the first oxide semiconductor film 108a, the second oxide semiconductor film 108b preferably has high oxygen permeability. When the second oxide semiconductor film 108b has high oxygen permeability, excess oxygen in the insulating films 114 and 116 can be smoothly diffused into the first oxide semiconductor film 108a.

[0090] Thus, in a semiconductor device of one embodiment of the present invention, the oxide semiconductor film is a stacked structure, and the insulating film in contact with the oxide semiconductor film contains excess oxygen, thereby improving the reliability of the semiconductor device. In addition, in one embodiment of the present invention, the temperature in the manufacturing process of the semiconductor device can be reduced (typically below 400°C or below 375°C (preferably above 340°C and below 360°C)). In addition, the manufacturing process of the semiconductor device will be described later.

[0091] Next, other components of the semiconductor device of this embodiment will be described in detail.

[0092] <Substrate>

[0093] There is no particular limitation on the material of the substrate 102 as long as it has heat resistance capable of withstanding subsequent heat treatment. For example, as the substrate 102, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like can be used. In addition, as the substrate 102, a single crystal semiconductor substrate or a polycrystalline semiconductor substrate made of silicon or silicon carbide, a compound semiconductor substrate made of silicon germanium, or the like, an SOI (silicon on insulator) substrate, or the like can also be used. Alternatively, a substrate having a semiconductor element disposed thereon can also be used as the substrate 102. When a glass substrate is used as the substrate 102, a glass substrate of a size of the 6th generation, the 7th generation, the 8th generation, the 9th generation, the 10th generation, or the like can be used. Thus, a large display device can be manufactured. It is preferred to use such a large-area substrate, in which case the manufacturing cost can be reduced.

[0094] In addition, a flexible substrate may be used as the substrate 102, and the transistor 100 may be formed directly on the flexible substrate. Alternatively, a peeling layer may be provided between the substrate 102 and the transistor 100. The peeling layer may be used in the following case: a part or all of the semiconductor device formed on the peeling layer is separated from the substrate 102 and transferred to another substrate. In this case, the transistor 100 may be transferred to a substrate with low heat resistance or a flexible substrate.

[0095] <Conductive Film Used as Gate Electrode, Source Electrode, and Drain Electrode>

[0096] The conductive film 104 used as a gate electrode, the conductive film 112a used as a source electrode, and the conductive film 112b used as a drain electrode can be formed using a metal element selected from chromium (Cr), copper (Cu), aluminum (Al), gold (Au), silver (Ag), zinc (Zn), molybdenum (Mo), tantalum (Ta), titanium (Ti), tungsten (W), manganese (Mn), nickel (Ni), iron (Fe), cobalt (Co), alloys containing the above metal elements as components, or alloys containing a combination of the above metal elements.

[0097] In addition, the conductive films 104, 112a, and 112b may also have a single-layer structure or a stacked structure of two or more layers. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure of a titanium film stacked on an aluminum film, a two-layer structure of a titanium film stacked on a titanium nitride film, a two-layer structure of a tungsten film stacked on a titanium nitride film, a two-layer structure of a tungsten film stacked on a tantalum nitride film or a tungsten nitride film, and a three-layer structure of a titanium film, an aluminum film, and a titanium film stacked in sequence may be cited. In addition, an alloy film or a nitride film containing aluminum and one or more selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium may also be used.

[0098] The conductive films 104, 112a, and 112b can be formed using a light-transmitting conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide added with silicon oxide.

[0099] As the conductive films 104, 112a, and 112b, a Cu-X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) may be used. By using the Cu-X alloy film, a wet etching process may be used during processing, thereby reducing manufacturing costs.

[0100] <Insulating Film Serving as Gate Insulating Film>

[0101] As the insulating films 106 and 107 used as the gate insulating films of the transistor 100, insulating layers including at least one of a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, a hafnium oxide film, a yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, and a neodymium oxide film formed by a plasma enhanced chemical vapor deposition (PECVD) method, a sputtering method, etc. can be used. In addition, a single-layer insulating film or an insulating film of three or more layers formed using a material selected from the above materials can also be used instead of the stacked structure of the insulating films 106 and 107.

[0102] The insulating film 106 functions as a barrier film for suppressing oxygen permeation. For example, when excessive oxygen is supplied to the insulating film 107, the insulating film 114, the insulating film 116, and / or the oxide semiconductor film 108, the insulating film 106 can suppress oxygen permeation.

[0103] The insulating film 107 in contact with the oxide semiconductor film 108 serving as the channel region of the transistor 100 is preferably an oxide insulating film, and preferably includes a region containing oxygen exceeding the stoichiometric composition (oxygen excess region). In other words, the insulating film 107 is an insulating film capable of releasing oxygen. In order to provide an oxygen excess region in the insulating film 107, the insulating film 107 is formed, for example, in an oxygen atmosphere. Alternatively, oxygen may be introduced into the insulating film 107 after film formation to form an oxygen excess region. As a method for introducing oxygen, ion implantation, ion doping, plasma immersion ion implantation, plasma treatment, and the like may be used.

[0104] When hafnium oxide is used as the insulating film 107, the following effects are achieved. The relative dielectric constant of hafnium oxide is higher than that of silicon oxide and silicon oxynitride. Therefore, the insulating film 107 using hafnium oxide can have a thickness thicker than that of the insulating film 107 using silicon oxide, thereby reducing the leakage current caused by the tunnel current. In other words, a transistor with a small off-state current can be provided. Furthermore, compared with hafnium oxide having an amorphous structure, the relative dielectric constant of hafnium oxide having a crystalline structure is higher. Therefore, in order to provide a transistor with a small off-state current, it is preferred to use hafnium oxide having a crystalline structure. As examples of crystalline structures, monoclinic and cubic systems can be cited. Note that one embodiment of the present invention is not limited to the above examples.

[0105] In this embodiment, a silicon nitride film is formed as the insulating film 106, and a silicon oxide film is formed as the insulating film 107. Compared with the silicon oxide film, the silicon nitride film has a higher relative dielectric constant and requires a larger thickness to obtain an electrostatic capacitance equal to that of the silicon oxide film. Therefore, when the silicon nitride film is used as the gate insulating film of the transistor 100, the physical thickness of the insulating film can be increased. Therefore, the decrease in the dielectric withstand voltage of the transistor 100 can be suppressed and the dielectric withstand voltage can be increased, thereby reducing the electrostatic damage of the transistor 100.

[0106] <Oxide Semiconductor Film>

[0107] The oxide semiconductor film 108 can be formed using the above materials. When the oxide semiconductor film 108 contains In-M-Zn oxide, the atomic ratio of the metal elements of the sputtering target used to form the In-M-Zn oxide preferably satisfies In≥M and Zn≥M. As the atomic ratio of the metal elements of such a sputtering target, In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:2, In:M:Zn = 4:2:4.1 are preferred. When the oxide semiconductor film 108 contains In-M-Zn oxide, a target containing polycrystalline In-M-Zn oxide is preferably used as the sputtering target. By using a target containing polycrystalline In-M-Zn oxide, it is easy to form a crystalline oxide semiconductor film 108. Note that there is an error within ±40% between the atomic ratio of the metal elements of the formed oxide semiconductor film 108 and the atomic ratio of the metal elements of the above sputtering target. For example, when using a sputtering target with an atomic ratio of In:Ga:Zn = 4:2:4.1, the atomic ratio of In, Ga, and Zn in the oxide semiconductor film 108 may be about 4:2:3.

[0108] The first oxide semiconductor film 108a can be formed using the above sputtering targets with atomic ratios of In:M:Zn = 2:1:3, In:M:Zn = 3:1:2, In:M:Zn = 4:2:4.1, etc. The atomic ratio of the first oxide semiconductor film 108a is preferably In:M:Zn = 4:α1(1.5≤α1≤2.5):α2(2.5≤α2≤3.5).

[0109] In addition, the second oxide semiconductor film 108b can be formed using the above sputtering targets with atomic ratios of In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, etc. The atomic ratio of the second oxide semiconductor film 108b is preferably In:M:Zn = 1:β1(0.8≤β1≤1.2):β2(0.8≤β2≤1.2). Additionally, the atomic ratio of the metal elements of the sputtering target used to form the second oxide semiconductor film 108b does not necessarily have to satisfy In≥M and Zn≥M, and it can also satisfy In<M or Zn<M. For example, the atomic ratio of the sputtering target can be In:M:Zn = 1:3:2, In:M:Zn = 1:3:4, In:M:Zn = 1:3:6.

[0110] The energy gap of the oxide semiconductor film 108 is greater than 2 eV, preferably greater than 2.5 eV, and more preferably greater than 3 eV. By using an oxide semiconductor with a wider energy gap, the off-state current of the transistor 100 can be reduced. It is particularly preferred that an oxide semiconductor film with an energy gap of greater than 2 eV, preferably greater than 2 eV and less than 3.0 eV, be used as the first oxide semiconductor film 108a, and an oxide semiconductor film with an energy gap of greater than 2.5 eV and less than 3.5 eV be used as the second oxide semiconductor film 108b. In addition, it is preferred that the energy gap of the second oxide semiconductor film 108b is greater than the energy gap of the first oxide semiconductor film 108a.

[0111] The thickness of the first oxide semiconductor film 108 a and the second oxide semiconductor film 108 b is both greater than or equal to 3 nm and less than or equal to 200 nm, preferably greater than or equal to 3 nm and less than or equal to 100 nm, and more preferably greater than or equal to 3 nm and less than or equal to 50 nm.

[0112] An oxide semiconductor film having a low carrier density is used as the first oxide semiconductor film 108 a . Thus, the carrier density of the first oxide semiconductor film 108 a can be 1×10 -9 / cm 3 Above and below 8×10 11 / cm 3 , preferably 1×10 -9 / cm 3 Above and below 1×10 11 / cm 3 , more preferably 1×10 -9 / cm 3 Above and below 1×10 10 / cm 3 An oxide semiconductor film having a low carrier density is used as the second oxide semiconductor film 108 b. Thus, the carrier density of the second oxide semiconductor film 108 b can be 1×10 17 / cm 3 Below, preferably 1×10 15 / cm 3 Below, more preferably 1×10 13 / cm 3 Below, more preferably 1×10 11 / cm 3 the following.

[0113] Note that the composition is not limited to the above, and a material having an appropriate composition can be used according to the desired semiconductor characteristics and electrical characteristics of the transistor (for example, field effect mobility, threshold voltage). In addition, in order to obtain the desired semiconductor characteristics of the transistor, it is preferable to appropriately set the carrier density, impurity concentration, defect density, atomic ratio of metal element to oxygen, interatomic distance, density, etc. of the first oxide semiconductor film 108a and the second oxide semiconductor film 108b.

[0114] Preferably, an oxide semiconductor film with a low impurity concentration and a low defect state density is used as the first oxide semiconductor film 108a and the second oxide semiconductor film 108b. In this case, the transistor can have better electrical characteristics. Here, the state of low impurity concentration and low defect state density (small number of oxygen defects) is referred to as "high-purity intrinsic" or "substantially high-purity intrinsic". Because the high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film has fewer carrier generation sources, the carrier density can be reduced. Therefore, a transistor having a channel region formed in the oxide semiconductor film rarely has an electrical characteristic of a negative threshold voltage (rarely a normally-on characteristic). Because the high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film has a lower defect state density, it sometimes has a lower trap state density. In addition, the off-state current of the high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film is extremely small. When the channel width is 1×10 6 In an element with a channel length of 10 μm and a source electrode and a drain electrode voltage (drain voltage) of 1 V to 10 V, the off-state current can be below the measurement limit of the semiconductor parameter analyzer, that is, 1×10 -13 A or below.

[0115] Therefore, a transistor having a channel region formed in the above-mentioned high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film can have electrical characteristics with small variations and high reliability. It takes a long time for the charge captured by the trap energy level of the oxide semiconductor film to disappear, and sometimes it acts like a fixed charge. Therefore, sometimes the electrical characteristics of a transistor having a channel region formed in an oxide semiconductor film with a high trap state density are unstable. Examples of impurities are hydrogen, nitrogen, alkali metals, and alkaline earth metals.

[0116] The hydrogen contained in the oxide semiconductor film reacts with the oxygen bonded to the metal atom to generate water, and at the same time, an oxygen defect is generated in the lattice (or the portion where the oxygen is detached) where oxygen detachment occurs. As hydrogen enters the oxygen defect, electrons are sometimes generated as carriers. In addition, sometimes a part of the hydrogen is bonded to the oxygen bonded to the metal atom to generate electrons as carriers. Therefore, a transistor including an oxide semiconductor film containing hydrogen tends to be normally-on. Therefore, it is preferred to reduce the hydrogen in the oxide semiconductor film 108 as much as possible. Specifically, the hydrogen concentration measured in the oxide semiconductor film 108 using SIMS (secondary ion mass spectrometry) is 2×10 20 atoms / cm 3 Below, preferably 5×10 19 atoms / cm 3 Below, more preferably 1×10 19 atoms / cm 3 Below, more preferably 5×10 18 atoms / cm 3 Below, more preferably 1×10 18 atoms / cm 3 Below, more preferably 5×10 17 atoms / cm 3 Below, more preferably 1×10 16 atoms / cm 3 the following.

[0117] The first oxide semiconductor film 108a preferably includes a region whose hydrogen concentration is lower than that of the second oxide semiconductor film 108b. When the first oxide semiconductor film 108a includes a region whose hydrogen concentration is lower than that of the second oxide semiconductor film 108b, the semiconductor device can have high reliability.

[0118] When the first oxide semiconductor film 108a contains silicon or carbon, which is one of the Group 14 elements, oxygen vacancies increase in the first oxide semiconductor film 108a, so that the first oxide semiconductor film 108a becomes an n-type film. Therefore, the concentration of silicon or carbon in the first oxide semiconductor film 108a or the concentration of silicon or carbon near the interface with the first oxide semiconductor film 108a (the concentration measured by SIMS analysis) is set to 2×10 18 atoms / cm 3 Below, preferably 2×10 17 atoms / cm 3 the following.

[0119] The concentration of the alkali metal or alkaline earth metal in the first oxide semiconductor film 108 a measured by SIMS analysis is 1×10 18 atoms / cm 3Below, preferably 2×10 16 atoms / cm 3 When an alkali metal or alkaline earth metal is bonded to an oxide semiconductor, carriers are generated and the off-state current of the transistor is increased. Therefore, the concentration of the alkali metal or alkaline earth metal in the first oxide semiconductor film 108a is preferably reduced.

[0120] In addition, when nitrogen is contained in the first oxide semiconductor film 108a, electrons as carriers are generated, and the carrier density increases, so that the first oxide semiconductor film 108a is likely to become an n-type film. As a result, a transistor including an oxide semiconductor film containing nitrogen is likely to have a normally-on characteristic. Therefore, it is preferable to reduce nitrogen in the oxide semiconductor film as much as possible. For example, the nitrogen concentration measured by SIMS analysis is preferably 5×10 18 atoms / cm 3 the following.

[0121] For example, the first oxide semiconductor film 108a and the second oxide semiconductor film 108b may also have a non-single-crystal structure, respectively. The non-single-crystal structure includes, for example, the following CAAC-OS (c-axis aligned crystalline oxide semiconductor), a polycrystalline structure, a microcrystalline structure, or an amorphous structure. Among the non-single-crystal structures, the amorphous structure has the highest defect state density, while the CAAC-OS has the lowest defect state density.

[0122] Here, refer to Figure 8 The energy band structures of the oxide semiconductor film 108 and the insulating film in contact with the oxide semiconductor film 108 are described.

[0123] Figure 8 108a, the second oxide semiconductor film 108b, and the insulating film 114. For easy understanding, the energy band structure shows the bottom energy level (E ) of the conduction band of the insulating film 107, the first oxide semiconductor film 108a, the second oxide semiconductor film 108b, and the insulating film 114. c ).

[0124] exist Figure 8 In the energy band structure, a silicon oxide film is used as the insulating films 107 and 114, an oxide semiconductor film formed by using a metal oxide target whose atomic number ratio of metal elements is In:Ga:Zn=4:2:4.1 is used as the first oxide semiconductor film 108a, and a metal oxide film formed by using a metal oxide target whose atomic number ratio of metal elements is In:Ga:Zn=1:1:1.2 is used as the second oxide semiconductor film 108b.

[0125] like Figure 8 As shown, between the first oxide semiconductor film 108a and the second oxide semiconductor film 108b, the conduction band bottom energy level changes smoothly. In other words, the conduction band bottom energy level changes continuously or is continuously connected. In order to achieve such an energy band structure, impurities that form defect energy levels such as trap centers or recombination centers are not present at the interface between the first oxide semiconductor film 108a and the second oxide semiconductor film 108b.

[0126] In order to form a continuous junction between the first oxide semiconductor film 108a and the second oxide semiconductor film 108b, these films are continuously formed without being exposed to the air using a multi-chamber film formation apparatus (sputtering apparatus) provided with a load lock chamber.

[0127] By adopting Figure 8 The first oxide semiconductor film 108a serves as a well, and in the transistor having the stacked structure, a channel region is formed in the first oxide semiconductor film 108a.

[0128] When the second oxide semiconductor film 108b is not provided, a trap level may be formed in the first oxide semiconductor film 108a. However, in the above-described stacked structure, the trap level can be formed in the second oxide semiconductor film 108b. Therefore, the trap level can be kept away from the first oxide semiconductor film 108a.

[0129] In addition, sometimes the trap energy level is farther from the vacuum energy level than the conduction band bottom energy level (Ec) of the first oxide semiconductor film 108a used as the channel region, and electrons are easily accumulated in the trap energy level. When electrons accumulate at the trap energy level, the electrons become negative fixed charges, causing the threshold voltage of the transistor to drift in the positive direction. Therefore, it is preferred that the trap energy level is closer to the vacuum energy level than the conduction band bottom energy level (Ec) of the first oxide semiconductor film 108a. By adopting the above structure, electrons are not easily accumulated at the trap energy level. As a result, the on-state current and field effect mobility of the transistor can be increased.

[0130] exist Figure 8 In the embodiment of the present invention, the conduction band bottom energy level of the second oxide semiconductor film 108b is closer to the vacuum level than that of the first oxide semiconductor film 108a. Typically, the difference between the conduction band bottom energy level of the first oxide semiconductor film 108a and the conduction band bottom energy level of the second oxide semiconductor film 108b is greater than 0.15 eV or greater than 0.5 eV, and less than 2 eV or less than 1 eV. In other words, the difference between the electron affinity of the second oxide semiconductor film 108b and the electron affinity of the first oxide semiconductor film 108a is greater than 0.15 eV or greater than 0.5 eV, and less than 2 eV or less than 1 eV.

[0131] In the above structure, the first oxide semiconductor film 108a becomes the main path of the current and is used as a channel region. In addition, since the second oxide semiconductor film 108b includes one or more of the metal elements included in the first oxide semiconductor film 108a forming the channel region, interface scattering is not easily generated at the interface between the first oxide semiconductor film 108a and the second oxide semiconductor film 108b. As a result, the movement of carriers in the interface is not hindered, so the field effect mobility of the transistor is improved.

[0132] In order to prevent the second oxide semiconductor film 108b from being used as part of the channel region, a material with sufficiently low conductivity is used as the second oxide semiconductor film 108b. Alternatively, a material whose electron affinity (energy level difference between the vacuum energy level and the conduction band bottom energy level) is lower than that of the first oxide semiconductor film 108a and whose conduction band bottom energy level is different from that of the first oxide semiconductor film 108a (band offset) is used as the second oxide semiconductor film 108b. In addition, in order to suppress the difference between the threshold voltages caused by the drain voltage value, it is preferred to use a material whose conduction band bottom energy level is closer to the vacuum energy level by more than 0.2 eV, preferably more than 0.5 eV, than that of the conduction band bottom energy level of the first oxide semiconductor film 108a to form the second oxide semiconductor film 108b.

[0133] The second oxide semiconductor film 108b preferably does not include a spinel crystal structure. When the second oxide semiconductor film 108b includes a spinel crystal structure, the constituent elements of the conductive films 112a and 112b sometimes diffuse into the first oxide semiconductor film 108a at the interface between the spinel crystal structure and other regions. In addition, the second oxide semiconductor film 108b is preferably a CAAC-OS described later, in which case the properties of the constituent elements of the blocking conductive films 112a and 112b, such as copper, are improved.

[0134] The thickness of the second oxide semiconductor film 108b is greater than a thickness that can suppress diffusion of constituent elements of the conductive films 112a and 112b into the first oxide semiconductor film 108a and less than a thickness that suppresses supply of oxygen from the insulating film 114 to the first oxide semiconductor film 108a. For example, when the thickness of the second oxide semiconductor film 108b is greater than or equal to 10 nm, diffusion of constituent elements of the conductive films 112a and 112b into the first oxide semiconductor film 108a can be suppressed. When the thickness of the second oxide semiconductor film 108b is less than or equal to 100 nm, oxygen can be effectively supplied from the insulating films 114 and 116 to the first oxide semiconductor film 108a.

[0135] <Insulating Film Serving as Protective Insulating Film of Transistor>

[0136] The insulating films 114 and 116 have a function of supplying oxygen to the oxide semiconductor film 108. The insulating film 118 has a function of a protective insulating film of the transistor 100. The insulating films 114 and 116 contain oxygen. In addition, the insulating film 114 is an insulating film that allows oxygen to pass through. In addition, the insulating film 114 is also used as a film that mitigates damage to the oxide semiconductor film 108 when the insulating film 116 is formed in a later step.

[0137] As the insulating film 114 , a silicon oxide film, a silicon oxynitride film, or the like can be used, with a thickness of 5 nm to 150 nm, preferably 5 nm to 50 nm.

[0138] It is also preferable that the number of defects in the insulating film 114 is small. Typically, the spin density of a signal at g=2.001 due to dangling bonds of silicon measured by ESR (electron spin resonance) is 3×10 17 spins / cm 3 This is because, if the defect density of the insulating film 114 is high, oxygen is bonded to the defects, and the amount of oxygen permeation in the insulating film 114 is reduced.

[0139] In the insulating film 114, sometimes not all of the oxygen that enters the insulating film 114 from the outside moves to the outside of the insulating film 114, but a part of the oxygen remains in the insulating film 114. In addition, sometimes, while oxygen enters the insulating film 114, oxygen contained in the insulating film 114 moves to the outside of the insulating film 114, and movement of oxygen occurs in the insulating film 114. When an oxide insulating film that allows oxygen to pass is formed as the insulating film 114, oxygen that has been separated from the insulating film 116 provided on the insulating film 114 can be moved to the oxide semiconductor film 108 via the insulating film 114.

[0140] The insulating film 114 can be formed using an oxide insulating film having a low state density due to nitride oxide. Note that the state density due to nitride oxide may be formed at the energy (E) of the valence band top of the oxide semiconductor film. V_OS ) and the energy of the conduction band bottom (E C_OS As the oxide insulating film, a silicon oxynitride film with a small amount of nitride oxide released or an aluminum oxynitride film with a small amount of nitride oxide released can be used.

[0141] In addition, in thermal desorption spectrum analysis, the silicon oxynitride film with a small amount of nitrogen oxide release is a film that releases more ammonia than nitrogen oxide. Typically, the amount of ammonia molecules released by the silicon oxynitride film is 1×10 18 / cm 3 Above and 5×10 19 / cm 3Note that the amount of ammonia released from the film is the amount of ammonia released when the film surface temperature is heated to a temperature of 50° C. to 650° C., preferably 50° C. to 550° C.

[0142] Nitrogen oxides (NO x , x is greater than or equal to 0 and less than or equal to 2, preferably greater than or equal to 1 and less than or equal to 2), typically NO 2 or NO, for example, forms an energy level in the insulating film 114 or the like. This energy level is located in the energy gap of the oxide semiconductor film 108. Therefore, when the nitrogen oxide diffuses to the interface between the insulating film 114 and the oxide semiconductor film 108, this energy level sometimes captures electrons on the insulating film 114 side. As a result, the captured electrons remain near the interface between the insulating film 114 and the oxide semiconductor film 108, and thus the threshold voltage of the transistor drifts in the positive direction.

[0143] During the heat treatment, the nitrogen oxide reacts with ammonia and oxygen. During the heat treatment, the nitrogen oxide contained in the insulating film 114 reacts with ammonia contained in the insulating film 116, so that the nitrogen oxide contained in the insulating film 114 decreases. Therefore, electrons are not easily captured at the interface between the insulating film 114 and the oxide semiconductor film 108.

[0144] By using the above-mentioned oxide insulating film as the insulating film 114 , a drift of a threshold voltage of the transistor can be reduced, thereby reducing variations in electrical characteristics of the transistor.

[0145] By performing a heat treatment in the manufacturing process of the transistor, typically a heat treatment at a temperature lower than 400°C or lower than 375°C (preferably at a temperature of 340°C or higher and 360°C or lower), a first signal having a g value of 2.037 or higher and 2.039 or lower, a second signal having a g value of 2.001 or higher and 2.003 or lower, and a third signal having a g value of 1.964 or higher and 1.966 or lower are observed in the ESR spectrum of the insulating film 114 at a temperature lower than 100K. The split width between the first signal and the second signal and the split width between the second signal and the third signal obtained by the ESR measurement using the X band are approximately 5 mT. The sum of the spin densities of the first signal having a g value of 2.037 or higher and 2.039 or lower, the second signal having a g value of 2.001 or higher and 2.003 or lower, and the third signal having a g value of 1.964 or higher and 1.966 or lower is less than 1×10 18 spins / cm 3 , typically 1×10 17 spins / cm 3 Above and below 1×10 18 spins / cm 3 .

[0146] In the ESR spectrum below 100K, the first signal with a g value of 2.037 to 2.039, the second signal with a g value of 2.001 to 2.003, and the third signal with a g value of 1.964 to 1.966 correspond to the emission of nitrogen oxides (NO x ; x is greater than 0 and less than 2, preferably greater than 1 and less than 2). Typical examples of nitrogen oxides include nitrogen monoxide and nitrogen dioxide. That is, the smaller the total number of spin densities of the first signal having a g value of greater than 2.037 and less than 2.039, the second signal having a g value of greater than 2.001 and less than 2.003, and the third signal having a g value of greater than 1.964 and less than 1.966, the less the nitrogen oxide content of the oxide insulating film.

[0147] The nitrogen concentration of the oxide insulating film measured by SIMS was 6×10 20 atoms / cm 3 the following.

[0148] By forming the oxide insulating film by a PECVD method using silane and nitrous oxide at a substrate temperature of 220° C. to 350° C., a dense film with high hardness can be formed.

[0149] The insulating film 116 is formed using an oxide insulating film whose oxygen content exceeds the stoichiometric composition. The oxide insulating film whose oxygen content exceeds the stoichiometric composition has a portion of oxygen released by heating. In TDS analysis, the oxygen release amount of the oxide insulating film whose oxygen content exceeds the stoichiometric composition is 1.0×10 19 atoms / cm 3 Above, preferably 3.0×10 20 atoms / cm 3 Note that the film surface temperature during the above TDS analysis is preferably 100° C. or higher and 700° C. or lower, or 100° C. or higher and 500° C. or lower.

[0150] As the insulating film 116 , a silicon oxide film, a silicon oxynitride film, or the like can be used with a thickness of greater than or equal to 30 nm and less than or equal to 500 nm, preferably greater than or equal to 50 nm and less than or equal to 400 nm.

[0151] It is preferred that the amount of defects in the insulating film 116 is small. Typically, the spin density of the signal at g=2.001 due to dangling bonds of silicon measured by ESR is less than 1.5×10 18 spins / cm 3 , more preferably 1×10 18 spins / cm 3In addition, since the insulating film 116 is farther from the oxide semiconductor film 108 than the insulating film 114 , the defect density of the insulating film 116 can also be higher than that of the insulating film 114 .

[0152] In addition, since the insulating films 114 and 116 can be formed using insulating films formed of the same type of material, the interface between the insulating films 114 and 116 may not be clearly confirmed. Therefore, in this embodiment, the interface between the insulating films 114 and 116 is shown by a dotted line. Although the two-layer structure of the insulating films 114 and 116 is described in this embodiment, the present invention is not limited to this structure. For example, a single-layer structure of the insulating film 114 or the insulating film 116 may be adopted.

[0153] The insulating film 118 has a function of blocking oxygen, hydrogen, water, alkali metals, alkaline earth metals, and the like. By providing the insulating film 118, oxygen can be prevented from diffusing from the oxide semiconductor film 108 to the outside, oxygen contained in the insulating films 114 and 116 can be prevented from diffusing to the outside, and hydrogen, water, and the like can be prevented from invading the oxide semiconductor film 108 from the outside. As the insulating film 118, for example, a nitride insulating film can be used. The nitride insulating film is formed using silicon nitride, silicon nitride oxide, aluminum nitride, aluminum nitride oxide, and the like. In particular, it is preferred to use silicon nitride oxide or a silicon nitride film as the insulating film 118, in which case oxygen diffusion to the outside can be suppressed.

[0154] As the insulating film 118, an oxide insulating film having a barrier effect on oxygen, hydrogen, water, etc. may be provided instead of the nitride insulating film having a barrier effect on oxygen, hydrogen, water, alkali metals, alkaline earth metals, etc. As the oxide insulating film having a barrier effect on oxygen, hydrogen, water, etc., an aluminum oxide film, an aluminum oxynitride film, a gallium oxide film, a gallium oxynitride film, a yttrium oxide film, an yttrium oxynitride film, a hafnium oxide film, a hafnium oxynitride film, etc. may be cited. As the oxide insulating film having a barrier effect on oxygen, hydrogen, water, etc., an aluminum oxide film, a hafnium oxide film, or a yttrium oxide film is particularly preferably used.

[0155] Although the above-mentioned conductive film, insulating film, oxide semiconductor film and other films can be formed by sputtering or PECVD, these films can also be formed by, for example, thermal CVD (chemical vapor deposition: metal organic chemical vapor deposition) or ALD (atomic layer deposition). As an example of thermal CVD, MOCVD (metal organic chemical vapor deposition: metal organic chemical vapor deposition) can be cited.

[0156] Since the thermal CVD method does not use plasma when forming a film, it has the advantage of not causing defects due to plasma damage.

[0157] A film can be formed on a substrate using thermal CVD by supplying a source gas and an oxidant simultaneously into a chamber, setting the pressure in the chamber to atmospheric pressure or reduced pressure, and reacting the source gas and the oxidant near or on the substrate.

[0158] In addition, film formation using the ALD method can also be performed in the following method: the pressure in the chamber is set to atmospheric pressure or reduced pressure, the source gas used for the reaction is introduced into the chamber in sequence, and then the gas is repeatedly introduced in this order. For example, two or more source gases are supplied into the chamber in sequence by switching each switch valve (also called a high-speed valve). For example, in order to prevent the source gas from mixing, an inert gas (for example, argon or nitrogen) is introduced at the same time or after the first source gas is introduced, and then the second source gas is introduced. Note that when the first source gas and the inert gas are introduced at the same time, the inert gas is used as a carrier gas. In addition, the inert gas can also be introduced at the same time as the second source gas is introduced. In addition, the first source gas can be discharged by vacuum pumping without introducing an inert gas, and then the second source gas can be introduced. The first source gas adheres to the surface of the substrate to form a first layer, and the second source gas introduced thereafter reacts with the first layer, thereby the second layer is stacked on the first layer to form a thin film. By repeatedly introducing the gas in this order until the desired thickness is obtained, a thin film with good step coverage can be formed. Since the thickness of the thin film can be adjusted by the number of times the gas is introduced in sequence, the ALD method can accurately adjust the film thickness and is suitable for the manufacture of micro FETs.

[0159] Various films such as the conductive film, insulating film, oxide semiconductor film, and metal oxide film of the above-mentioned embodiment can be formed by a thermal CVD method such as an MOCVD method. For example, when forming an In-Ga-Zn-O film, trimethylindium, trimethylgallium, and dimethylzinc are used. The chemical formula of trimethylindium is In(CH 3 ) 3 The chemical formula of trimethylgallium is Ga(CH 3 ) 3 The chemical formula of dimethyl zinc is Zn(CH 3 ) 2 . Not limited to the above combination, triethylgallium (chemical formula: Ga(C 2 H 5 ) 3 ) instead of trimethylgallium, and diethylzinc (chemical formula: Zn(C 2 H 5 ) 2 ) instead of dimethyl zinc.

[0160] For example, when forming a hafnium oxide film using an ALD method, the following two gases are used: ozone (O3 ); and a source gas obtained by gasifying a liquid containing a solvent and a hafnium precursor compound (e.g., hafnium alkoxide, hafnium tetrakis dimethylamide (TDMAH) or other hafnium amide). In addition, the chemical formula of hafnium tetrakis dimethylamide is Hf[N(CH 3 ) 2 ] 4 Examples of other material liquids include tetrakis(ethylmethylamide)hafnium.

[0161] For example, when an aluminum oxide film is formed using a film forming apparatus using the ALD method, the following two gases are used: H as an oxidant and 2 O; and a source gas obtained by gasifying a liquid containing a solvent and an aluminum precursor compound (for example, trimethylaluminum (TMA)). In addition, the chemical formula of trimethylaluminum is Al(CH 3 ) 3 Examples of other material liquids include tris(dimethylamide)aluminum, triisobutylaluminum, and aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedione).

[0162] For example, when a silicon oxide film is formed using an ALD film forming apparatus, hexachlorodisilane is attached to the surface of the film to be formed, chlorine contained in the attached material is removed, and an oxidizing gas (e.g., O) is supplied. 2 or nitrous oxide) to react with the attached matter.

[0163] For example, when forming a tungsten film using an ALD film forming apparatus, WF is repeatedly introduced in sequence. 6 Gas and B 2 H 6 The gas forms an initial tungsten film, and then uses WF 6 Gas and H 2 Gas to form a tungsten film. Alternatively, SiH 4 Gas Replacement B 2 H 6 gas.

[0164] For example, when an oxide semiconductor film (for example, an In—Ga—ZnO film) is formed using a film forming apparatus using the ALD method, In(CH 3 ) 3 Gas and O 3 gas to form an In-O layer, and then Ga(CH 3 ) 3 Gas and O 3 The GaO layer was formed by gas, and then Zn(CH 3 ) 2 Gas and O 3The ZnO layer is formed by bubbling with an inert gas such as Ar. Note that the order of these layers is not limited to the above example. In addition, these gases can also be mixed to form a mixed compound layer such as an In-Ga-O layer, an In-Zn-O layer, and a Ga-Zn-O layer. Note that although H obtained by bubbling with an inert gas such as Ar can also be used, 2 O gas replaces O 3 gas, but preferably O containing no H 3 Gas. Alternatively, In(C 2 H 5 ) 3 Gas replaces In(CH 3 ) 3 Gas. Ga(C 2 H 5 ) 3 Gas replaces Ga(CH 3 ) 3 Gas. Zn(CH 3 ) 2 gas.

[0165] <Structural Example 2 of Semiconductor Device>

[0166] Reference Fig. 6A and 6B Description and Figure 5B and 5C 1 and 2. The transistor 100 has a different structure example. Note that when a portion having the same function as that described above is indicated, the same hatching is sometimes used for the portion without particularly adding a reference numeral.

[0167] Fig. 6A FIG. 1 is a top view of a transistor 170 which is a semiconductor device according to one embodiment of the present invention. Figure 6B It is along Fig. 6A The cross-sectional view along the dotted line X1-X2 and the Fig. 6A A cross-sectional view of the dotted line Y1-Y2. Figure 6B In the figure, the left side shows a cross-sectional view along the dashed line X1-X2, and the right side shows a cross-sectional view along the dashed line Y1-Y2.

[0168] The transistor 170 includes: a conductive film 104 on a substrate 102 and serving as a first gate electrode; an insulating film 106 on the substrate 102 and the conductive film 104; an insulating film 107 on the insulating film 106; an oxide semiconductor film 108 on the insulating film 107; an insulating film 114 on the oxide semiconductor film 108; an insulating film 116 on the insulating film 114; a conductive film 112a serving as a source electrode electrically connected to the oxide semiconductor film 108; a conductive film 112b serving as a drain electrode electrically connected to the oxide semiconductor film 108; an insulating film 118 on the insulating film 116; a conductive film 120a on the insulating film 118; and a conductive film 120b on the insulating film 118. The insulating films 114, 116, and 118 function as a second gate insulating film of the transistor 170. The conductive film 120a is electrically connected to the conductive film 112b via an opening 142c provided in the insulating films 114, 116, and 118. In the transistor 170, the conductive film 120a has a function of, for example, a pixel electrode for a display device. In the transistor 170, the conductive film 120b functions as a second gate electrode (also referred to as a back gate electrode).

[0169] like Figure 6B As shown in the right cross-sectional view, the conductive film 120b is connected to the conductive film 104 functioning as the first gate electrode in the openings 142a and 142b provided in the insulating films 106, 107, 114, 116, and 118. Therefore, the conductive film 120b and the conductive film 104 are applied with the same potential.

[0170] In addition, although the structure in which the openings 142a and 142b are provided to connect the conductive film 120b to the conductive film 104 is shown in this embodiment, one embodiment of the present invention is not limited thereto. For example, a structure in which only one of the openings 142a and 142b is formed to connect the conductive film 120b to the conductive film 104, or a structure in which the openings 142a and 142b are not provided and the conductive film 120b is not connected to the conductive film 104 may be adopted. When the conductive film 120b is not connected to the conductive film 104, different potentials can be applied to the conductive film 120b and the conductive film 104.

[0171] like Figure 6BAs shown in the cross-sectional view on the left, the oxide semiconductor film 108 is located opposite to the conductive film 104 used as the first gate electrode and the conductive film 120b used as the second gate electrode, and is sandwiched between the two conductive films used as gate electrodes. The length of the conductive film 120b used as the second gate electrode in the channel length direction and the length of the channel width direction are both greater than the length of the oxide semiconductor film 108 in the channel length direction and the length of the channel width direction. The conductive film 120b covers the entire oxide semiconductor film 108 via the insulating films 114, 116, and 118. Since the conductive film 120b used as the second gate electrode is connected to the conductive film 104 used as the first gate electrode in the openings 142a and 142b provided in the insulating films 106, 107, 114, 116, and 118, the side surface of the oxide semiconductor film 108 in the channel width direction is opposite to the conductive film 120b used as the second gate electrode via the insulating films 114, 116, and 118.

[0172] In other words, in the channel width direction of the transistor 170, the conductive film 104 used as the first gate electrode and the conductive film 120b used as the second gate electrode are connected in an opening provided in the insulating film 106, 107 used as the first gate insulating film and the insulating film 114, 116, 118 used as the second gate insulating film, and the conductive film 104 and the conductive film 120b surround the oxide semiconductor film 108 via the insulating film 106, 107 used as the first gate insulating film and the insulating film 114, 116, 118 used as the second gate insulating film.

[0173] By adopting the above structure, the electric field of the conductive film 104 serving as the first gate electrode and the conductive film 120b serving as the second gate electrode electrically surrounds the oxide semiconductor film 108 included in the transistor 170. As in the transistor 170, a device structure of a transistor in which the electric field of the first gate electrode and the second gate electrode electrically surrounds the oxide semiconductor film having a channel region can be referred to as a surrounded channel (s-channel) structure.

[0174] Since the transistor 170 has an s-channel structure, an electric field for causing a channel can be effectively applied to the oxide semiconductor film 108 using the conductive film 104 used as the first gate electrode. As a result, the current driving capability of the transistor 170 is improved, so that a high on-state current characteristic can be obtained. Since the on-state current can be increased, the size of the transistor 170 can be reduced. In addition, since the transistor 170 has a structure in which the oxide semiconductor film 108 is surrounded by the conductive film 104 used as the first gate electrode and the conductive film 120b used as the second gate electrode, the mechanical strength of the transistor 170 can be improved.

[0175] Note that the other structures of the transistor 170 are the same as those of the above-mentioned transistor 100 , and the same effects as those of the above-mentioned transistor 100 are achieved.

[0176] The transistor structures of this embodiment can be freely combined. For example, Figure 5A and Figure 5B The transistor 100 shown is used as a transistor in a pixel of a display device, and Fig. 6A and Figure 6B The transistor 170 shown is used as a transistor in a gate driver of a display device.

[0177] <Method 1 for manufacturing semiconductor device>

[0178] Next, refer to Figures 1A to 1C , FIG. 2A to FIG. 2C , FIG. 3A to FIG. 3C , FIG. 4A to FIG. 4C , Figure 5A A method for manufacturing the transistor 100 of the semiconductor device according to one embodiment of the present invention will be described in detail. Figures 1A to 1C , FIG. 2A to FIG. 2C , FIG. 3A to FIG. 3C , FIG. 4A to FIG. 4C , Figure 5A It is a cross-sectional view for explaining a method for manufacturing a semiconductor device.

[0179] First, a conductive film is formed on a substrate 102, and processed by a photolithography process and an etching process to form a conductive film 104 serving as a gate electrode. Next, insulating films 106 and 107 serving as gate insulating films are formed on the conductive film 104 (see FIG. 1 ). Figure 1A ).

[0180] In this embodiment, a glass substrate is used as the substrate 102. A 100 nm thick tungsten film is formed by sputtering as the conductive film 104 serving as a gate electrode. A 400 nm thick silicon nitride film as the insulating film 106 and a 50 nm thick silicon oxynitride film as the insulating film 107 are formed by PECVD.

[0181] The insulating film 106 may have a stacked-layer structure of silicon nitride films. Specifically, the insulating film 106 may have a stacked-layer structure of three layers of a first silicon nitride film, a second silicon nitride film, and a third silicon nitride film. An example of this three-layer structure is described below.

[0182] For example, a first silicon nitride film with a thickness of 50 nm can be formed under the following conditions: silane with a flow rate of 200 sccm, nitrogen with a flow rate of 2000 sccm, and ammonia with a flow rate of 100 sccm are supplied to the reaction chamber of the PECVD device as source gases, the pressure in the reaction chamber is controlled to 100 Pa, and a high-frequency power supply of 27.12 MHz is used to supply 2000 W of power.

[0183] A second silicon nitride film with a thickness of 300 nm can be formed under the following conditions: silane with a flow rate of 200 sccm, nitrogen with a flow rate of 2000 sccm and ammonia with a flow rate of 2000 sccm are supplied to the reaction chamber of the PECVD device as source gases, the pressure in the reaction chamber is controlled to 100 Pa, and a high-frequency power supply of 27.12 MHz is used to supply 2000 W of power.

[0184] A third silicon nitride film with a thickness of 50 nm can be formed under the following conditions: silane with a flow rate of 200 sccm and nitrogen with a flow rate of 5000 sccm are supplied to the reaction chamber of the PECVD device as source gases, the pressure in the reaction chamber is controlled to 100 Pa, and a high-frequency power supply of 27.12 MHz is used to supply 2000 W of power.

[0185] In addition, the first silicon nitride film, the second silicon nitride film, and the third silicon nitride film can be formed at a substrate temperature of 350° C. or lower.

[0186] For example, when the insulating film 106 has a three-layer structure of silicon nitride films, when a conductive film including copper (Cu) is used as the conductive film 104, the following effect is achieved.

[0187] The first silicon nitride film can suppress the diffusion of copper (Cu) elements from the conductive film 104. The second silicon nitride film has a function of releasing hydrogen and can improve the withstand voltage of the insulating film used as a gate insulating film. The third silicon nitride film has a small amount of hydrogen released and can suppress the diffusion of hydrogen released from the second silicon nitride film.

[0188] In order to improve interface characteristics between the insulating film 107 and the oxide semiconductor film 108 (specifically, the first oxide semiconductor film 108 a ) to be formed later, the insulating film 107 is preferably an insulating film containing oxygen.

[0189] Next, an oxide semiconductor film 109 is formed on the insulating film 107 at a first temperature. The oxide semiconductor film 109 is formed as follows: first, a first oxide semiconductor film 109a is formed, and then a second oxide semiconductor film 109b is formed (see Figure 1B ).

[0190] The first temperature when forming the oxide semiconductor film 109 is above room temperature and below 340°C, preferably above room temperature and below 300°C, more preferably above 100°C and below 250°C, and further preferably above 100°C and below 200°C. By forming the oxide semiconductor film 109 while heating, the crystallinity of the oxide semiconductor film 109 can be improved. When a large glass substrate (for example, a glass substrate of the 6th to 10th generation) is used as the substrate 102, the substrate 102 may be deformed when the first temperature is above 150°C and below 340°C. However, even if a large glass substrate is used, deformation of the glass substrate can be prevented when the first temperature is above 100°C and below 150°C.

[0191] The substrate temperatures during the formation of the first oxide semiconductor film 109a and the second oxide semiconductor film 109b may be the same or different. Preferably, the first oxide semiconductor film 109a and the second oxide semiconductor film 109b are formed at the same substrate temperature, in which case the manufacturing cost can be reduced.

[0192] In this embodiment, the first oxide semiconductor film 109a is formed by a sputtering method using an In-Ga-Zn metal oxide target (atomic ratio of In:Ga:Zn=4:2:4.1), and then the second oxide semiconductor film 109b is continuously formed by a sputtering method in a vacuum using an In-Ga-Zn metal oxide target (atomic ratio of In:Ga:Zn=1:1:1.2). The first oxide semiconductor film 109a and the second oxide semiconductor film 109b are formed at a substrate temperature of 170°C.

[0193] In the case of forming the oxide semiconductor film 109 by sputtering, a rare gas (typically argon), oxygen, or a mixture of a rare gas and oxygen is appropriately used as a sputtering gas. When a mixture of a rare gas and oxygen is used, it is preferred to increase the proportion of oxygen relative to the rare gas. In addition, the sputtering gas needs to be highly purified. For example, as an oxygen gas or argon gas used as a sputtering gas, a high-purity gas with a dew point of less than -40°C, preferably less than -80°C, more preferably less than -100°C, and further preferably less than -120°C is used, thereby minimizing the mixing of water and the like into the oxide semiconductor film 109.

[0194] When the oxide semiconductor film 109 is formed by a sputtering method, it is preferable to perform high vacuum evacuation (evacuation to 5×10 -7 Pa to 1×10 -4Pa) to remove as much water and the like as possible, which are impurities for the oxide semiconductor film 109. Alternatively, it is preferable to combine a turbomolecular pump and a cold trap to prevent gas (especially gas containing carbon or hydrogen) from flowing back into the processing chamber from the exhaust system.

[0195] Next, the oxide semiconductor film 109 is processed to form an island-shaped oxide semiconductor film 108. Note that the first oxide semiconductor film 109a is processed into the island-shaped first oxide semiconductor film 108a, and the second oxide semiconductor film 109b is processed into the island-shaped second oxide semiconductor film 108b (see Figure 1C ).

[0196] Next, without performing a heating step at a temperature higher than the first temperature, a conductive film 112 to be a source electrode and a drain electrode is formed on the insulating film 107 and the oxide semiconductor film 108 by a sputtering method (see Figure 2A ). In other words, the temperature in the step after the processing of the oxide semiconductor film 109 and the formation of the island-shaped oxide semiconductor film 108 and before the formation of the conductive film 112 is lower than the first temperature.

[0197] In this embodiment, as the conductive film 112, a stacked film in which a tungsten film with a thickness of 50 nm and an aluminum film with a thickness of 400 nm are stacked in sequence is formed by a sputtering method. Although the conductive film 112 has a two-layer structure in this embodiment, one embodiment of the present invention is not limited to this. For example, the conductive film 112 may also have a three-layer structure in which a tungsten film with a thickness of 50 nm, an aluminum film with a thickness of 400 nm, and a titanium film with a thickness of 100 nm are stacked in sequence.

[0198] Next, masks 136a and 136b are formed in desired regions on the conductive film 112 (see Figure 2B ).

[0199] In this embodiment, the masks 136 a and 136 b are formed by forming a photosensitive resin film on the conductive film 112 and patterning the photosensitive resin film by a photolithography process.

[0200] Next, the conductive film 112 is processed by applying an etching material 138 from above the conductive film 112 and the masks 136a and 136b, thereby forming conductive films 112a and 112b separated from each other (see FIG. Figure 2C ).

[0201] In this embodiment, the conductive film 112 is processed using a dry etching device. Note that the processing method of the conductive film 112 is not limited to this. For example, a chemical solution can be used as the etching material 138 and a wet etching device can be used to process the conductive film 112 and the second oxide semiconductor film 108b. Note that when the conductive film 112 is processed using a dry etching device, a finer pattern can be formed compared to the case where the conductive film 112 is processed using a wet etching device. However, when the conductive film 112 is processed using a wet etching device, the manufacturing cost can be reduced compared to the case where the conductive film 112 is processed using a dry etching device.

[0202] Next, an etching material 139 is applied from above the second oxide semiconductor film 108b, the conductive films 112a and 112b, and the masks 136a and 136b to clean the surface (back channel side) of the second oxide semiconductor film 108b (see Figure 3A ).

[0203] For example, the above-mentioned washing can be performed using a chemical solution such as phosphoric acid. By washing with a chemical solution such as phosphoric acid, impurities attached to the surface of the second oxide semiconductor film 108b (for example, elements contained in the conductive films 112a and 112b) can be removed. Note that this washing is not necessarily required and may not be performed in some cases.

[0204] In the step of forming and / or washing the conductive films 112a and 112b, a region of the second oxide semiconductor film 108b not covered with the conductive films 112a or 112b may become thinner than the first oxide semiconductor film 108a.

[0205] However, in the step of forming and / or washing the conductive films 112a and 112b, the region of the second oxide semiconductor film 108b not covered by the conductive film 112a or 112b may not become thinner than the region of the second oxide semiconductor film 108b covered by the conductive film 112a or 112b. Fig.9A and Fig. 9B An example of this case is shown. Fig.9A and Fig. 9B is a cross-sectional view showing an example of a semiconductor device. Fig.9A and Fig. 9B In the figure, the left side and the right side respectively show a cross-sectional view along the dot-dash line X1-X2 and a cross-sectional view along the dot-dash line Y1-Y2. Fig.9A Show Figure 5B The illustrated embodiment is an example of a case where the second oxide semiconductor film 108 b of the transistor 100 is not thinner than a region of the second oxide semiconductor film 108 b covered by the conductive films 112 a and 112 b . Fig. 9BThe second oxide semiconductor film 108b is formed thinner than the first oxide semiconductor film 108a in advance, and the thickness of the region not covered by the conductive films 112a and 112b is set to Figure 5B The transistors 100 shown are an example of being equal.

[0206] Next, the masks 136a and 136b are removed, thereby forming a conductive film 112a serving as a source electrode and a conductive film 112b serving as a drain electrode over the second oxide semiconductor film 108b. The oxide semiconductor film 108 has a stacked-layer structure of a first oxide semiconductor film 108a and a second oxide semiconductor film 108b (see Figure 3B ).

[0207] Next, an insulating film 114 serving as a first protective insulating film and an insulating film 116 serving as a second protective insulating film are formed over the oxide semiconductor film 108 and the conductive films 112a and 112b, and then a first barrier film 131 is formed (see Figure 3C ).

[0208] In addition, after forming the insulating film 114, the insulating film 116 is preferably continuously formed without being exposed to the atmosphere. After forming the insulating film 114, the insulating film 116 is continuously formed without being exposed to the atmosphere by adjusting one or more of the flow rate, pressure, high-frequency power, and substrate temperature of the source gas, thereby reducing the concentration of impurities derived from atmospheric components at the interface between the insulating film 114 and the insulating film 116, and moving oxygen contained in the insulating films 114 and 116 to the oxide semiconductor film 108. Therefore, the amount of oxygen defects in the oxide semiconductor film 108 can be reduced.

[0209] For example, as the insulating film 114, a silicon oxynitride film can be formed by the PECVD method. At this time, as the source gas, a deposition gas containing silicon and an oxidizing gas are preferably used. Typical examples of deposition gases containing silicon include: silane, disilane, trisilane, and fluorinated silane. Examples of oxidizing gases include: nitrous oxide and nitrogen dioxide. The insulating film 114 containing nitrogen and having a small amount of defects can be formed by the PECVD method under the following conditions: the flow rate of the oxidizing gas is greater than 20 times and less than 100 times the flow rate of the above-mentioned deposition gas, preferably greater than 40 times and less than 80 times; and the pressure in the processing chamber is less than 100 Pa, preferably less than 50 Pa.

[0210] In this embodiment, as the insulating film 114, a silicon oxynitride film is formed by a PECVD method under the following conditions: the temperature of the substrate 102 is maintained at 220° C.; silane with a flow rate of 50 sccm and nitrous oxide with a flow rate of 2000 sccm are used as source gases; the pressure in the processing chamber is 20 Pa; a high frequency power of 13.56 MHz and 100 W (power density of 1.6×10 -2 W / cm 2 ) are supplied to the parallel plate electrodes.

[0211] As the insulating film 116, a silicon oxide film or a silicon oxynitride film is formed under the following conditions: the temperature of the substrate in a vacuum-evacuated processing chamber installed in a PECVD device is maintained at 180° C. or higher and 350° C. or lower, a source gas is introduced into the processing chamber and the pressure in the processing chamber is set to 100 Pa or higher and 250 Pa or lower, preferably 100 Pa or higher and 200 Pa or lower, and 0.17 W / cm2 is supplied to an electrode provided in the processing chamber. 2 Above and 0.5W / cm 2 Below, more preferably 0.25W / cm 2 Above and 0.35W / cm 2 The following high frequency power.

[0212] As the film formation conditions of the insulating film 116, the high frequency power having the above power density is supplied to the reaction chamber having the above pressure, thereby improving the decomposition efficiency of the source gas in the plasma, increasing the oxygen radicals, and promoting the oxidation of the source gas, so that the oxygen content in the insulating film 116 exceeds the stoichiometric composition. On the other hand, in the film formed at the substrate temperature within the above range, since the bonding force between silicon and oxygen is weak, part of the oxygen in the film is released by the heat treatment in the subsequent step. As a result, an oxide insulating film whose oxygen content exceeds the stoichiometric composition and part of the oxygen is released by heating can be formed.

[0213] In the step of forming the insulating film 114, the insulating film 114 serves as a protective film for the oxide semiconductor film 108. Therefore, the insulating film 116 can be formed using high-frequency power with high power density while reducing damage to the oxide semiconductor film 108.

[0214] In addition, in the film formation conditions of the insulating film 116, when the flow rate of the deposition gas containing silicon is increased relative to the oxidizing gas, the amount of defects in the insulating film 116 can be reduced. Typically, an oxide insulating layer with a small amount of defects can be formed, that is, the spin density of the signal at g = 2.001 due to the dangling bond of silicon by ESR measurement is less than 6×10 17 spins / cm 3 , preferably 3×1017 spins / cm 3 Below, more preferably 1.5×10 17 spins / cm 3 As a result, the reliability of the transistor can be improved.

[0215] Heat treatment may be performed after forming the insulating films 114 and 116 (that is, after forming the insulating film 116 and before forming the first barrier film 131). By this heat treatment, nitrogen oxides included in the insulating films 114 and 116 can be reduced. By this heat treatment, part of oxygen included in the insulating films 114 and 116 can be moved to the oxide semiconductor film 108 to reduce the amount of oxygen vacancies in the oxide semiconductor film 108.

[0216] The temperature of the heat treatment performed on the insulating films 114 and 116 is typically lower than 400° C., preferably lower than 375° C., more preferably higher than 150° C. and lower than 360° C., and further preferably higher than 350° C. and lower than 360° C. The heat treatment can be performed in an atmosphere of nitrogen, oxygen, ultra-dry air (air having a water content of 20 ppm or less, preferably lower than 1 ppm, and more preferably lower than 10 ppb) or a rare gas (argon, helium, etc.). An electric furnace, an RTA device, etc. can be used for the heat treatment, wherein the nitrogen, oxygen, ultra-dry air or rare gas preferably does not contain hydrogen, water, etc.

[0217] The first barrier film 131 contains oxygen and a metal (at least one of indium, zinc, titanium, aluminum, tungsten, tantalum, molybdenum, hafnium, and yttrium). Indium tin oxide (also referred to as ITO), indium tin silicon oxide (In-Sn-Si oxide, hereinafter referred to as ITSO), or indium oxide is preferably used as the first barrier film 131 because it can cover the unevenness well.

[0218] The first barrier film 131 can be formed by a sputtering method. When the first barrier film 131 is very thin, it is sometimes difficult to suppress the release of oxygen from the insulating film 116 to the outside. On the other hand, when the first barrier film 131 is very thick, it is sometimes difficult to smoothly add oxygen to the insulating film 116. Therefore, the thickness of the first barrier film 131 is preferably greater than 1 nm and less than 20 nm or greater than 2 nm and less than 10 nm. In this embodiment, an ITSO film with a thickness of 5 nm is formed as the first barrier film 131.

[0219] Next, oxygen 140 is added to the insulating film 116 serving as the second protective insulating film via the first barrier film 131. Figure 4A , oxygen added to the insulating film 116 is schematically represented as oxygen 140a.

[0220] As a method of adding oxygen 140 to the insulating film 116 via the first barrier film 131, an ion doping method, an ion implantation method, a plasma treatment method, etc. can be used. The oxygen 140 can also be excess oxygen or oxygen radicals. When adding oxygen 140, by applying a bias voltage to the substrate side, the oxygen 140 can be effectively added to the insulating film 116. As the above-mentioned bias voltage, for example, the power density can be 1 W / cm 2 Above and 5W / cm 2 When the first barrier film 131 is provided on the insulating film 116 and oxygen is added, the first barrier film 131 functions as a protective film that suppresses oxygen from being separated from the insulating film 116. Therefore, more oxygen can be added to the insulating film 116.

[0221] Next, heat treatment is performed at a second temperature lower than 400° C., so that the excess oxygen or the oxygen radicals can be diffused into the oxide semiconductor film 108 (see Figure 4B ).

[0222] exist Figure 4B In the figure, the second temperature heat treatment is schematically represented by arrow 141. The second temperature is lower than 400°C, preferably lower than 375°C, more preferably higher than 340°C and lower than 360°C. The second temperature heat treatment can be carried out in an atmosphere of nitrogen, oxygen, ultra-dry air (air with a water content of 20 ppm or less, preferably 1 ppm or less, more preferably 10 ppb or less) or a rare gas (argon, helium, etc.). An electric furnace, RTA device, etc. can be used in the heat treatment, wherein the nitrogen, oxygen, ultra-dry air or rare gas preferably does not contain hydrogen, water, etc.

[0223] In this embodiment, as the second temperature heat treatment, treatment is performed at 350° C. for 1 hour in a nitrogen atmosphere. Note that the temperature of the second temperature heat treatment is the highest temperature in the step of forming the transistor 100, but a heat treatment at a temperature substantially the same as the second temperature heat treatment may be performed in other steps. For example, the substrate temperature when forming the insulating films 106, 107, 114, 116, and 118 may be the same as the second temperature.

[0224] Next, the first barrier film 131 or a portion thereof and a portion of the insulating film 116 serving as the second protective insulating film are removed using the etching material 142 (see Figure 4C ).

[0225] As a method for removing the first barrier film 131 and a portion of the insulating film 116 serving as the second protective insulating film, dry etching, wet etching, a method combining dry etching and wet etching, etc. can be cited. Note that when dry etching is used, the etching material 142 is an etching gas, and when wet etching is used, the etching material 142 is a chemical solution. In this embodiment, it is preferable to remove the first barrier film 131 by wet etching, in which case the manufacturing cost can be suppressed.

[0226] Next, an insulating film 118 serving as a second barrier film is formed on the insulating film 116 (see Figure 5A ).

[0227] When the insulating film 118 is formed by the PECVD method, the substrate temperature is lower than 400° C., preferably lower than 375° C., more preferably higher than 150° C. and lower than 360° C., and further preferably higher than 350° C. and lower than 360° C. In this case, the insulating film 118 can have a dense structure. In addition, when the substrate temperature when forming the insulating film 118 is within the above range, the second temperature heating treatment after forming the first barrier film 131 can be omitted.

[0228] For example, when a silicon nitride film is formed as an insulating film 118 by a PECVD method, a deposition gas containing silicon, nitrogen, and ammonia are preferably used as source gases. By making the amount of ammonia less than the amount of nitrogen, ammonia dissociates in the plasma to generate active species. The active species cuts the bond between silicon and hydrogen contained in the deposition gas containing silicon and the triple bond between nitrogen molecules. As a result, a silicon nitride film with fewer defects and a dense structure can be formed, in which the bond between silicon and nitrogen is promoted and the bond between silicon and hydrogen is less. On the other hand, when the amount of ammonia is large relative to nitrogen, the decomposition of the deposition gas containing silicon and the decomposition of nitrogen do not progress, resulting in the formation of a non-dense silicon nitride film, in which the bond between silicon and hydrogen remains and there are more defects. Therefore, in the source gas, the flow ratio of nitrogen to ammonia is set to 5:1 or more and 50:1 or less, preferably 10:1 or more and 50:1 or less.

[0229] In this embodiment, as the insulating film 118, a silicon nitride film with a thickness of 50 nm is formed by using a PECVD device and using silane, nitrogen and ammonia as source gases. The flow rate of silane is 50 sccm, the flow rate of nitrogen is 5000 sccm, and the flow rate of ammonia is 100 sccm. The pressure of the processing chamber is 100 Pa, the substrate temperature is 350°C, and a high-frequency power supply of 27.12 MHz is used to supply 1000 W of high-frequency power to the parallel plate electrodes. The PECVD device has an electrode area of ​​6000 cm 2 The parallel plate PECVD device has a power density per unit area of ​​1.7×10 -1 W / cm 2 .

[0230] Alternatively, heat treatment may be performed after forming the insulating film 118 serving as the second barrier film. By performing the heat treatment at the second temperature before forming the insulating film 118 or performing the heat treatment after forming the insulating film 118, excess oxygen or oxygen radicals in the insulating film 116 can be diffused into the oxide semiconductor film 108, thereby filling oxygen vacancies in the oxide semiconductor film 108. Alternatively, the insulating film 118 may be formed while heating is performed, and in this case, excess oxygen or oxygen radicals in the insulating film 116 can be diffused into the oxide semiconductor film 108, thereby filling oxygen vacancies in the oxide semiconductor film 108.

[0231] Through the above process, it can be manufactured Figure 5B Transistor 100 is shown.

[0232] <Method 2 for manufacturing semiconductor device>

[0233] Next, for Figures 1A to 1C , FIG. 2A to FIG. 2C , FIG. 3A to FIG. 3C , FIG. 4A to FIG. 4C and Figure 5A A method for manufacturing the transistor 100 which is different from the manufacturing method shown will be described.

[0234] First, similarly to <Semiconductor device manufacturing method 1>, Figures 1A to 1C , FIG. 2A to FIG. 2C , FIG. 3A to FIG. 3C After that, no FIG. 4A to FIG. 4C , Figure 5A In other words, Figure 3C The structure shown has Figure 5B and Figure 5C The transistor 100 shown has the same function.

[0235] When not FIG. 4A to FIG. 4C , Figure 5A In the process shown, Figure 3C In the structure shown, a metal oxide film is used as the first barrier film 131, and as the metal oxide film, aluminum oxide, hafnium oxide, or yttrium oxide is preferably formed.

[0236] When aluminum oxide, hafnium oxide, or yttrium oxide is formed by sputtering as the first barrier film 131, the sputtering gas preferably contains at least oxygen. Oxygen used as the sputtering gas when forming the first barrier film 131 may become oxygen radicals in plasma, and the oxygen and / or the oxygen radicals may be added to the insulating film 116. In this case, the sputtering gas may be omitted. Figure 4AIn other words, the process of forming the first barrier film 131 can also be used as an oxygen addition process. When the first barrier film 131 is formed (especially in the initial stage of formation), the first barrier film 131 has the function of adding oxygen, and after the first barrier film 131 is formed, the first barrier film 131 has the function of blocking oxygen.

[0237] When aluminum oxide is formed as the first barrier film 131 by sputtering, a mixed layer may be formed near the interface between the insulating film 116 and the first barrier film 131. When the insulating film 116 is a silicon oxynitride film, Al2O3 may be formed as the mixed layer. x Si y O z .

[0238] When aluminum oxide, hafnium oxide, or yttrium oxide is used as the first barrier film 131, since aluminum oxide, hafnium oxide, and yttrium oxide have high insulation and high oxygen barrier properties, it is not necessary to perform Figure 4C The process of removing the first barrier film 131 is shown as well as Figure 5A Therefore, the first barrier film 131 has the same function as the insulating film 118.

[0239] In addition, by forming the first barrier film 131 while heating at a substrate temperature lower than 400° C. (i.e., the second temperature), excess oxygen or oxygen radicals added to the insulating film 116 can be diffused into the oxide semiconductor film 108. Alternatively, by performing heat treatment at a second temperature lower than 400° C. after forming the first barrier film 131, excess oxygen or oxygen radicals added to the insulating film 116 can be diffused into the oxide semiconductor film 108.

[0240] By using aluminum oxide, hafnium oxide, or yttrium oxide as the first barrier film 131 , the manufacturing process of the semiconductor device can be shortened, thereby reducing the manufacturing cost.

[0241] <Method 3 for manufacturing semiconductor device>

[0242] Next, refer to FIG. 7A to FIG. 7C A method for manufacturing the transistor 170 which is one embodiment of the present invention is described. FIG. 7A to FIG. 7C is a cross-sectional view illustrating a method for manufacturing a semiconductor device. FIG. 7A to FIG. 7C In the figure, the left side and the right side respectively show a cross-sectional view along the dot-dash line X1-X2 and a cross-sectional view along the dot-dash line Y1-Y2.

[0243] First, the same steps as those in the above-described method for manufacturing the transistor 100 are performed (see Figures 1A to 1C , FIG. 2A to FIG. 2C , FIG. 3A to FIG. 3C , FIG. 4A to FIG. 4C , Figure 5A process shown).

[0244] Next, a mask is formed on the insulating film 118 by a photolithography process, and an opening 142c is formed in a desired region of the insulating films 114, 116, and 118. In addition, a mask is formed on the insulating film 118 by a photolithography process, and openings 142a and 142b are formed in a desired region of the insulating films 106, 107, 114, 116, and 118. The opening 142c reaches the conductive film 112b. The openings 142a and 142b reach the conductive film 104 (see FIG. 1 ). Fig. 7A ).

[0245] In addition, the openings 142a, 142b, and the opening 142c may be formed in the same process or in different processes. When the openings 142a, 142b, and the opening 142c are formed in the same process, for example, a gray tone mask or a half tone mask may be used. In addition, the openings 142a, 142b may be formed in multiple processes. For example, the insulating films 106, 107 are processed, and then the insulating films 114, 116, 118 are processed.

[0246] Next, a conductive film 120 is formed on the insulating film 118 so as to cover the openings 142a, 142b, and 142c (see Figure 7B ).

[0247] As the conductive film 120, for example, a material containing one selected from indium (In), zinc (Zn), and tin (Sn) can be used. In particular, the conductive film 120 can be formed using a light-transmitting conductive material such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (ITO), indium zinc oxide, and indium tin silicon oxide (ITSO). For example, the conductive film 120 can be formed using a sputtering method. In this embodiment, an ITSO film with a thickness of 110 nm is formed by sputtering.

[0248] Next, a mask is formed on the conductive film 120 by a photolithography process, and the conductive film 120 is processed into a desired shape to form conductive films 120a and 120b (see FIG. Figure 7C ).

[0249] When the conductive films 120a and 120b are formed, for example, dry etching, wet etching, or a method combining dry etching and wet etching is used. In this embodiment, the conductive film 120 is processed into the conductive films 120a and 120b using a wet etching method.

[0250] Through the above steps, we can produce Fig. 6A and Figure 6B Transistor 170 is shown.

[0251] The structure and method described in this embodiment mode can be implemented in combination with the structure and method described in other embodiment modes as appropriate.

[0252] Implementation Method 2

[0253] In this embodiment, a structure of an oxide semiconductor included in a semiconductor device which is one embodiment of the present invention is described in detail below.

[0254] <Structure of Oxide Semiconductor>

[0255] Oxide semiconductors are classified into single crystal oxide semiconductors and non-single crystal oxide semiconductors. Examples of non-single crystal oxide semiconductors include CAAC-OS (c-axis aligned crystalline oxide semiconductor), polycrystalline oxide semiconductors, nc-OS (nanocrystalline oxide semiconductor), a-like OS (amorphous like oxide semiconductor), and amorphous oxide semiconductors.

[0256] From another viewpoint, oxide semiconductors are classified into amorphous oxide semiconductors and crystalline oxide semiconductors. Examples of crystalline oxide semiconductors include single crystal oxide semiconductors, CAAC-OS, polycrystalline oxide semiconductors, and nc-OS.

[0257] It is known that an amorphous structure is generally defined as being in a metastable state and not fixed, having isotropy but not having an inhomogeneous structure. In other words, the bond angle of an amorphous structure is not fixed, and it has short-range order but not long-range order.

[0258] This means that a substantially stable oxide semiconductor cannot be called a completely amorphous oxide semiconductor. In addition, an oxide semiconductor that does not have isotropy (for example, an oxide semiconductor with a periodic structure in a tiny area) cannot be called a completely amorphous oxide semiconductor. Note that a-like OS has a periodic structure in a tiny area, but at the same time has voids and an unstable structure. Therefore, a-like OS has physical properties close to those of an amorphous oxide semiconductor.

[0259] <caac-os>

[0260] First, CAAC-OS is described.

[0261] CAAC-OS is a type of oxide semiconductor including a plurality of c-axis-aligned crystal parts (also referred to as grains).

[0262] In a composite analysis image (also called a high-resolution TEM image) of a bright field image and a diffraction pattern of CAAC-OS obtained using a transmission electron microscope (TEM), multiple particles are observed. However, in a high-resolution TEM image, a clear boundary between particles, i.e., a grain boundary, is not observed. Therefore, in CAAC-OS, a decrease in electron mobility due to grain boundaries is not likely to occur.

[0263] Next, CAAC-OS observed by TEM is described. Fig. 10A A high-resolution TEM image of a cross section of the CAAC-OS obtained by observing from a direction roughly parallel to the sample surface is shown. The high-resolution TEM image is obtained using a spherical aberration corrector function. The high-resolution TEM image obtained using the spherical aberration corrector function is particularly referred to as a Cs-corrected high-resolution TEM image. For example, a Cs-corrected high-resolution TEM image can be obtained using an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd.

[0264] Fig. 10B yes Fig. 10A Enlarged Cs-corrected high-resolution TEM image of area (1). Fig. 10B It is shown that metal atoms are arranged in layers in the particles. Each metal atom layer has a configuration reflecting the projections and depressions of the surface forming the CAAC-OS (hereinafter, this surface is also referred to as the formation surface) or the top surface of the CAAC-OS, and is arranged in parallel to the formation surface or the top surface of the CAAC-OS.

[0265] like Fig. 10B As shown in Figure 1, CAAC-OS has a unique atomic arrangement. Fig. 10C In the figure, the unique atomic arrangement is shown with auxiliary lines. Fig. 10B and Fig. 10C It is shown that the size of the particles is greater than 1 nm or greater than 3 nm, and the size of the gaps generated by the inclination between the particles is about 0.8 nm. Therefore, the particles can also be called nanocrystals (nc). Note that CAAC-OS can also be called an oxide semiconductor with CANC (c-axis aligned nanocrystals: c-axis oriented nanocrystals).

[0266] Here, based on the Cs-corrected high-resolution TEM image, the configuration of the CAAC-OS particles 5100 on the substrate 5120 is schematically represented as a structure of accumulated bricks or blocks (see Fig. 10D ).exist Fig. 10C The tilted portion of the particle observed in Fig. 10D Area 5161 shown.

[0267] Fig.11A A Cs-corrected high-resolution TEM image of the plane of the CAAC-OS observed from a direction substantially perpendicular to the sample surface is shown. Fig. 11B , Fig. 11C and Fig.11D They are Fig.11A Enlarged Cs-corrected high-resolution TEM images of area (1), area (2), and area (3). Fig. 11B , Fig. 11C and Fig.11D It is shown that the metal atoms are arranged in a triangular, quadrangular or hexagonal shape in the particles. However, there is no regularity in the arrangement of the metal atoms between different particles.

[0268] Next, the CAAC-OS analyzed by X-ray diffraction (XRD) is described. For example, when the out-of-plane method is used to analyze the InGaZnO 4 When the structure of the crystallized CAAC-OS is analyzed, as Fig. 12A As shown in Figure 1, a peak appears when the diffraction angle (2θ) is around 31°. This peak originates from InGaZnO 4 From the (009) plane of the crystal, it can be seen that the crystal in the CAAC-OS has c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the formation surface or top surface of the CAAC-OS.

[0269] Note that in the structural analysis of CAAC-OS using the out-of-plane method, in addition to the peak near 2θ of 31°, a peak sometimes appears near 2θ of 36°. The peak near 2θ of 36° indicates that a portion of CAAC-OS contains crystals that do not have c-axis orientation. Preferably, in CAAC-OS analyzed using the out-of-plane method, a peak appears near 2θ of 31° and no peak appears near 2θ of 36°.

[0270] On the other hand, in the structural analysis of CAAC-OS using the in-plane method in which X-rays are incident on the sample from a direction approximately perpendicular to the c-axis, a peak appears at around 56° 2θ. This peak originates from the InGaZnO 4 In CAAC-OS, when 2θ is fixed at about 56° and the sample is rotated about the normal vector of the sample surface (φ axis) for analysis (φ scanning), as shown in FIG. Fig. 12B As shown in Figure 2, no clear peak is observed. In contrast, in InGaZnO 4 In a single crystal oxide semiconductor, when φ scanning is performed with 2θ fixed at about 56°, as shown in FIG. Fig. 12C As shown, six peaks originating from a crystal plane equivalent to the (110) plane were observed. Therefore, structural analysis using XRD showed that there was no regularity in the orientation of the a-axis and the b-axis in CAAC-OS.

[0271] Next, the CAAC-OS analyzed by electron diffraction is described. 4 When the crystallized CAAC-OS is incident on an electron beam with a beam diameter of 300 nm in the direction parallel to the sample surface, Fig.13A The diffraction pattern shown in FIG. 1 (also called selected area transmission electron diffraction pattern) includes the diffraction patterns caused by InGaZnO. 4 Therefore, electron diffraction also shows that the particles contained in CAAC-OS have c-axis orientation, and the c-axis is oriented in a direction roughly perpendicular to the formation surface or top surface of CAAC-OS. On the other hand, Fig. 13B The diffraction pattern obtained when an electron beam with a beam diameter of 300 nm is incident on the same sample in a direction perpendicular to the sample surface is shown. Fig. 13B As shown in FIG. 1 , a ring-shaped diffraction pattern is observed. Therefore, electron diffraction also indicates that the a-axis and b-axis of the particles contained in CAAC-OS are not oriented. Fig. 13B The first ring in the 4 The (010) and (100) planes of the crystal. Fig. 13B The second ring in is caused by the (110) plane, etc.

[0272] As described above, CAAC-OS is an oxide semiconductor with high crystallinity. The crystallinity of an oxide semiconductor may be reduced due to the mixing of impurities or the generation of defects. This means that CAAC-OS has few impurities and defects (for example, oxygen defects).

[0273] In addition, impurities refer to elements other than the main components of oxide semiconductors, such as hydrogen, carbon, silicon or transition metal elements. For example, elements such as silicon that have a stronger bonding force with oxygen than the metal elements contained in the oxide semiconductor will take oxygen from the oxide semiconductor, thereby disrupting the atomic arrangement of the oxide semiconductor, resulting in a decrease in crystallinity. Since heavy metals such as iron or nickel, argon, carbon dioxide, etc. have a large atomic radius (or molecular radius), they will disrupt the atomic arrangement of the oxide semiconductor, resulting in a decrease in crystallinity.

[0274] The properties of an oxide semiconductor containing impurities or defects may sometimes change due to light or heat. For example, impurities contained in an oxide semiconductor may sometimes become a carrier trap or a carrier generation source. In addition, oxygen defects in an oxide semiconductor may sometimes become a carrier trap or a carrier generation source when they capture hydrogen.

[0275] CAAC-OS with few impurities and oxygen defects is an oxide semiconductor with low carrier density. Such an oxide semiconductor is called a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. CAAC-OS has low impurity concentration and defect state density. Therefore, CAAC-OS can be called an oxide semiconductor with stable characteristics.

[0276] <nc-os>

[0277] Next, nc-OS will be described.

[0278] In the high-resolution TEM image of nc-OS, there are areas where the crystalline part can be observed and areas where no clear crystalline part is observed. In most cases, the size of the crystalline part contained in nc-OS is greater than 1nm and less than 10nm or greater than 1nm. Note that oxide semiconductors whose crystalline part size is greater than 10nm and less than 100nm are sometimes called microcrystalline oxide semiconductors. For example, in the high-resolution TEM image of nc-OS, the grain boundaries are sometimes not clearly observed. Note that the source of the nanocrystals may be the same as the particles in CAAC-OS. Therefore, the crystalline part of nc-OS is sometimes referred to as a particle below.

[0279] In nc-OS, the atomic arrangement in a tiny region (for example, a region greater than 1 nm and less than 10 nm, especially a region greater than 1 nm and less than 3 nm) is periodic. There is no regularity in the crystal orientation of nc-OS between different particles. Therefore, no orientation is observed in the entire film. Therefore, according to the analysis method, nc-OS is no different from a-like OS or an amorphous oxide semiconductor. For example, when nc-OS is analyzed using the out-of-plane method using X-rays whose beam diameter is larger than that of the particles, no peak representing the crystal plane is detected. In addition, when electron diffraction is performed on nc-OS using electron beams whose beam diameter is larger than that of the particles (for example, greater than 50 nm), a diffraction pattern similar to a halo pattern is observed. On the other hand, when electron beams whose beam diameter is close to or smaller than that of the particles are irradiated, spots are observed in the nanobeam electron diffraction of nc-OS. In addition, in the nanobeam electron diffraction pattern of nc-OS, circular (annular) areas with high brightness are sometimes observed. In the nanobeam electron diffraction pattern of nc-OS, multiple spots are sometimes observed in the annular area.

[0280] Since there is no regularity in the crystal orientation among particles (nanocrystals), nc-OS can also be called an oxide semiconductor including RANC (random aligned nanocrystals) or an oxide semiconductor including NANC (non-aligned nanocrystals).

[0281] nc-OS is an oxide semiconductor with higher regularity than amorphous oxide semiconductor. Therefore, the defect state density of nc-OS is lower than that of a-like OS and amorphous oxide semiconductor. Note that there is no regularity in crystal orientation between different particles in nc-OS. Therefore, the defect state density of nc-OS is higher than that of CAAC-OS.

[0282] <a-like OS>

[0283] The a-like OS has a structure between nc-OS and amorphous oxide semiconductor.

[0284] In the high-resolution TEM image of a-like OS, voids are sometimes observed. In addition, in the high-resolution TEM image, there are regions where crystal parts are clearly observed and regions where crystal parts are not observed.

[0285] Since a-like OS contains voids, its structure is unstable. In order to prove that a-like OS has an unstable structure compared with CAAC-OS and nc-OS, the structural changes caused by electron irradiation are shown below.

[0286] As samples to be irradiated with electrons, a-like OS (referred to as sample A), nc-OS (referred to as sample B), and CAAC-OS (referred to as sample C) were prepared. Each sample was an In-Ga-Zn oxide.

[0287] First, a high-resolution cross-sectional TEM image of each sample was obtained. The high-resolution cross-sectional TEM image showed that each sample had a crystal part.

[0288] Note that which part is to be the crystal part is determined as follows. 4 The unit lattice of the crystal has a structure in which nine layers, including three In-O layers and six Ga-Zn-O layers, are stacked in layers in the c-axis direction. The spacing between these adjacent layers is equal to the lattice surface spacing (also called d value) of the (009) plane, and its value is 0.29nm obtained by crystal structure analysis. Therefore, the portion where the spacing of the lattice fringes is greater than 0.28nm and less than 0.30nm can be regarded as InGaZnO. 4 Crystalline part. Each lattice fringe corresponds to InGaZnO 4 ab surface of the crystal.

[0289] Fig.14 The variation of the average size of the crystal part (22 parts to 45 parts) of each sample is shown. Note that the crystal part size corresponds to the length of the above-mentioned lattice fringe. Fig.14 Indicates that the crystal part in a-like OS gradually increases in size according to the cumulative amount of electron exposure. Fig.14 As shown in (1) of FIG. 1 , the initial crystal size of about 1.2 nm (also called the initial crystal nucleus) observed by TEM was 4.2×10 8 e - / nm 2 On the other hand, the cumulative irradiation dose of nc-OS and CAAC-OS from the start of electron irradiation to 4.2×10 8 e - / nm 2 In the range of , the size of the crystal part does not change. Fig.14 As shown in (2) and (3) in FIG. 1 , regardless of the cumulative irradiation dose of electrons, the average crystal size of nc-OS and CAAC-OS is approximately 1.4 nm and 2.1 nm, respectively.

[0290] Thus, electron irradiation sometimes causes the growth of crystal parts in a-like OS. On the other hand, in nc-OS and CAAC-OS, there is almost no growth of crystal parts caused by electron irradiation. Therefore, a-like OS has an unstable structure compared with nc-OS and CAAC-OS.

[0291] Since a-like OS contains voids, its density is lower than that of nc-OS and CAAC-OS. Specifically, the density of a-like OS is 78.6% or more and less than 92.3% of a single crystal oxide semiconductor having the same composition. The density of nc-OS and CAAC-OS is 92.3% or more and less than 100% of a single crystal oxide semiconductor having the same composition. Note that it is difficult to form an oxide semiconductor whose density is less than 78% of the density of a single crystal oxide semiconductor.

[0292] For example, in an oxide semiconductor with an atomic ratio of In:Ga:Zn=1:1:1, a single crystal InGaZnO 4 The density is 6.357g / cm 3 Therefore, for example, in an oxide semiconductor with an atomic ratio of In:Ga:Zn=1:1:1, the density of a-like OS is 5.0 g / cm 3 Above and less than 5.9g / cm 3 For example, in an oxide semiconductor with an atomic ratio of In:Ga:Zn=1:1:1, the density of nc-OS and CAAC-OS is 5.9 g / cm 3 Above and less than 6.3g / cm 3 .

[0293] Note that sometimes there is no single crystal oxide semiconductor having a desired composition. In this case, by combining single crystal oxide semiconductors of different compositions in an arbitrary ratio, the density of a single crystal oxide semiconductor corresponding to the desired composition can be estimated. The density of a single crystal oxide semiconductor of the desired composition can be calculated using a weighted average according to the combination ratio of single crystal oxide semiconductors of different compositions. Note that it is preferred to calculate the density by reducing the types of single crystal oxide semiconductors used as much as possible.

[0294] As described above, oxide semiconductors have various structures and various characteristics. Note that the oxide semiconductor may be, for example, a stacked film including two or more of an amorphous oxide semiconductor, an a-like OS, a nc-OS, and a CAAC-OS.

[0295] <Film Formation Model>

[0296] Examples of film formation models of CAAC-OS and nc-OS are described below.

[0297] Fig.15A This is a schematic diagram of the interior of a film forming chamber when CAAC-OS is formed by sputtering.

[0298] The target material 5130 is bonded to the backing plate. A plurality of magnets are arranged at a position opposite to the target material 5130 across the backing plate. The plurality of magnets generate a magnetic field. For the arrangement and structure of the magnets, etc., refer to the description of the film forming chamber described above. The sputtering method that uses the magnetic field of the magnet to increase the film forming speed is called magnetron sputtering.

[0299] The target material 5130 has a polycrystalline structure in which at least one grain includes a cleavage plane.

[0300] As an example, the cleavage plane of the target 5130 including In—Ga—Zn oxide will be described. Fig.16A The target material 5130 includes InGaZnO 4 The structure of the crystal. Note that Fig.16A InGaZnO is shown with the c-axis facing upward and viewed from a direction parallel to the b-axis. 4 The structure of crystallization.

[0301] Fig.16A This means that the oxygen atoms in the Ga-Zn-O layer are arranged very close to the oxygen atoms in the adjacent Ga-Zn-O layer. The oxygen atoms have a negative charge, so the two Ga-Zn-O layers repel each other. As a result, InGaZnO 4 The crystal has a cleavage plane between the two Ga-Zn-O layers.

[0302] The substrate 5120 is arranged opposite to the target 5130, and the distance d (also called the distance between the target and the substrate (TS distance)) is greater than 0.01m and less than 1m, preferably greater than 0.02m and less than 0.5m. The film forming chamber is almost filled with a film forming gas (for example, oxygen gas, argon gas, or a mixed gas containing more than 5vol% oxygen), and the pressure in the film forming chamber is controlled to be greater than 0.01Pa and less than 100Pa, preferably greater than 0.1Pa and less than 10Pa. Here, a voltage of a certain degree or more is applied to the target 5130 to start the discharge and generate plasma. The magnetic field forms a high-density plasma region near the target 5130. In the high-density plasma region, the film forming gas is ionized to generate ions 5101. Examples of ions 5101 include: cations of oxygen (O + ) and argon cations (Ar + ).

[0303] The ions 5101 are accelerated by the electric field toward the target 5130 and collide with the target 5130. At this time, the flat (granular) sputtered particles 5100a and 5100b are peeled off from the cleavage plane and sputtered. Note that the structures of the particles 5100a and 5100b may be distorted by the impact of the collision of the ions 5101.

[0304] Particle 5100a is a flat plate-shaped (granular) sputtered particle having a triangular (e.g., equilateral triangle) plane. Particle 5100b is a flat plate-shaped (granular) sputtered particle having a hexagonal (e.g., regular hexagon) plane. Note that flat plate-shaped (granular) sputtered particles such as particles 5100a and particles 5100b are collectively referred to as particles 5100. The shape of the plane of particle 5100 is not limited to a triangle or a hexagon. For example, sometimes the plane has a shape formed by combining two or more triangles. For example, sometimes it is a quadrangle (e.g., a rhombus) formed by combining two triangles (e.g., equilateral triangles).

[0305] The thickness of the particle 5100 is determined by the type of film-forming gas, etc. The thickness of the particle 5100 is preferably uniform, and the reason is described later. In addition, the sputtered particles are preferably in the form of particles with a small thickness, rather than in the form of particles with a large thickness. For example, the thickness of the particle 5100 is greater than 0.4nm and less than 1nm, preferably greater than 0.6nm and less than 0.8nm. In addition, for example, the width of the particle 5100 is greater than 1nm. The particle 5100 is equivalent to the above Fig.14 For example, when the ions 5101 are made to collide with the target 5130 containing In-Ga-Zn oxide, as shown in FIG. Fig. 16B As shown, particles 5100 including three layers of Ga-Zn-O layer, In-O layer and Ga-Zn-O layer are splashed. Note that Fig. 16C The structure of the particle 5100 is shown when viewed from a direction parallel to the c-axis. Therefore, the particle 5100 has a nano-sized sandwich structure including two Ga-Zn-O layers (bread slices) and an In-O layer (filling).

[0306] Sometimes particle 5100 receives an electric charge when passing through plasma, so that its side is negatively or positively charged. Particle 5100 has an oxygen atom on its side, and the oxygen atom may be negatively charged. In this way, when the side is charged with the same polarity, the charges repel each other, so that particle 5100 can maintain a flat plate shape. When CAAC-OS is In-Ga-Zn oxide, the oxygen atom bonded to the indium atom may be negatively charged. Alternatively, the oxygen atom bonded to the indium atom, gallium atom or zinc atom may be negatively charged. In addition, sometimes particle 5100 grows by bonding with indium atoms, gallium atoms, zinc atoms or oxygen atoms when passing through plasma. This is equivalent to the above-mentioned Fig.14 Here, when the temperature of the substrate 5120 is around room temperature, the particles 5100 no longer grow and thus become nc-OS (see Fig. 15B ). Since the nc-OS can be formed at room temperature, the nc-OS can be formed even when the area of ​​the substrate 5120 is large. Note that in order to grow the particle 5100 in the plasma, it is effective to increase the film forming power in the sputtering method. By increasing the film forming power, the structure of the particle 5100 can be stabilized.

[0307] like Fig.15A and Fig. 15B As shown, the particle 5100 flies in the plasma like a kite and flies to the substrate 5120. Since the particle 5100 has an electric charge, a repulsive force is generated when it approaches an area where other particles 5100 have been deposited. Here, a magnetic field (also called a horizontal magnetic field) parallel to the top surface of the substrate 5120 is generated above the substrate 5120. Since there is a potential difference between the substrate 5120 and the target 5130, a current flows from the substrate 5120 to the target 5130. Therefore, the particle 5100 is subjected to a force (Lorentz force) caused by the action of the magnetic field and the current on the top surface of the substrate 5120. This can be explained by Fleming's left-hand rule.

[0308] The mass of particle 5100 is larger than that of an atom. Therefore, in order to move particle 5100 on the top surface of substrate 5120, it is important to apply some force to particle 5100 from the outside. One of the forces may be the force generated by the action of magnetic field and electric current. In order to increase the force applied to particle 5100, it is preferred to set a region on the top surface of substrate 5120 where the magnetic field parallel to the top surface of substrate 5120 is 10G or more, preferably 20G or more, more preferably 30G or more, and further preferably 50G or more. Alternatively, it is preferred to set a region on the top surface of substrate 5120 where the magnetic field parallel to the top surface of substrate 5120 is 1.5 times or more, preferably 2 times or more, more preferably 3 times or more, and further preferably 5 times or more of the magnetic field perpendicular to the top surface of substrate 5120.

[0309] At this time, the direction of the horizontal magnetic field on the top surface of the substrate 5120 is constantly changing due to the relative movement or rotation of the magnet and / or the substrate 5120. Therefore, on the top surface of the substrate 5120, the particles 5100 are subjected to forces in various directions and can move in various directions.

[0310] In addition, if Fig.15A As shown, when the substrate 5120 is heated, the resistance caused by friction or the like between the particle 5100 and the substrate 5120 is small. As a result, the particle 5100 glides on the top surface of the substrate 5120. The sliding of the particle 5100 occurs in a state where its flat surface is facing the substrate 5120. Then, when the particle 5100 reaches the side of other particles 5100 that have been deposited, the sides of the particle 5100 are bonded to each other. At this time, the oxygen atoms on the side of the particle 5100 are detached. Oxygen defects in CAAC-OS are sometimes filled by the detached oxygen atoms, so CAAC-OS has a low defect state density. Note that the top surface temperature of the substrate 5120 is, for example, above 100°C and less than 500°C, above 150°C and less than 450°C, above 170°C and less than 400°C, or above 170°C and less than 350°C. That is, CAAC-OS can be formed even if the area of ​​the substrate 5120 is large.

[0311] In addition, by heating the particles 5100 on the substrate 5120, the atoms are rearranged, so that the structural distortion caused by the collision of the ions 5101 is reduced. The particles 5100 with reduced distortion are almost single crystals. Since the particles 5100 are almost single crystals, even if the particles 5100 are heated after being bonded to each other, the particles 5100 themselves hardly expand or contract. Therefore, the gaps between the particles 5100 can be prevented from expanding to form defects such as grain boundaries, thereby preventing the generation of cracks.

[0312] CAAC-OS does not have a structure of a single crystal oxide semiconductor like a flat plate, but has an arrangement of a collection of particles 5100 (nanocrystals) stacked like bricks or blocks. In addition, there are no grain boundaries between them. Therefore, even if deformation such as shrinkage of CAAC-OS occurs due to heating during film formation, heating after film formation, or bending, local stress can be relieved or distortion can be relieved. Therefore, the above structure is suitable for flexible semiconductor devices. Note that nc-OS has an arrangement in which particles 5100 (nanocrystals) are stacked in a disordered manner.

[0313] When the ions collide with the target, not only the particles but also zinc oxide and the like may be splashed out. Zinc oxide is lighter than the particles and therefore reaches the top surface of the substrate 5120 first. As a result, the zinc oxide forms a zinc oxide layer 5102 having a thickness of 0.1 nm to 10 nm, 0.2 nm to 5 nm, or 0.5 nm to 2 nm. 17A to 17D It is a cross-sectional schematic diagram.

[0314] like Fig.17A As shown in FIG. 5 , particles 5105a and 5105b are deposited on the zinc oxide layer 5102. Here, the side surfaces of the particles 5105a and 5105b are in contact with each other. In addition, after being deposited on the particles 5105b, the particles 5105c slide on the particles 5105b. In addition, on the other side surfaces of the particles 5105a, a plurality of particles 5103 splashed out from the target together with the zinc oxide are crystallized by heating the substrate 5120, thereby forming a region 5105a1. Note that the plurality of particles 5103 may contain oxygen, zinc, indium, gallium, or the like.

[0315] Then, if Fig. 17B As shown, region 5105a1 is integrated with particle 5105a to form particle 5105a2. In addition, a side surface of particle 5105c is in contact with the other side surface of particle 5105b.

[0316] Then, if Fig. 17C As shown, particle 5105d slides on particle 5105a2 and particle 5105b after being deposited on particle 5105a2 and particle 5105b. In addition, particle 5105e slides on zinc oxide layer 5102 toward the other side of particle 5105c.

[0317] Then, if Fig.17D As shown, the particle 5105d is arranged so that its side surface contacts the side surface of the particle 5105a2. In addition, the side surface of the particle 5105e contacts the other side surface of the particle 5105c. On the other side surface of the particle 5105d, the plurality of particles 5103 sputtered from the target together with the zinc oxide are crystallized by heating the substrate 5120, thereby forming a region 5105d1.

[0318] As described above, the deposited particles come into contact with each other, and then crystal growth occurs on the side of the particles, thereby forming CAAC-OS on the substrate 5120. Therefore, each of the particles of CAAC-OS is larger than the particles of nc-OS. This corresponds to the above Fig.14 The difference in size between (3) and (2).

[0319] When the gaps between particles 5100 are extremely small, sometimes multiple particles form a large particle. The large particle has a single crystal structure. For example, the size of the large particle is sometimes more than 10nm and less than 200nm, more than 15nm and less than 100nm, or more than 20nm and less than 50nm when viewed from the top surface. Therefore, when the channel formation region of the transistor is smaller than the large particle, the region with a single crystal structure can be used as the channel formation region. In addition, when the particle becomes larger, the region with a single crystal structure can be used as the channel formation region, source region, and drain region of the transistor.

[0320] In this way, when a channel formation region or the like of a transistor is formed in a region having a single crystal structure, the frequency characteristics of the transistor can sometimes be improved.

[0321] As in the above model, it can be considered that the particles 5100 are deposited on the substrate 5120. Therefore, even if the formation surface does not have a crystalline structure, CAAC-OS can be formed, which is different from epitaxial growth. For example, even if the top surface (formation surface) of the substrate 5120 is an amorphous structure (for example, the top surface is formed of amorphous silicon oxide), CAAC-OS can be formed.

[0322] In addition, it can be seen that even if the top surface of the substrate 5120 as the formation surface has unevenness, in CAAC-OS, the particles 5100 are arranged according to the shape of the top surface of the substrate 5120. For example, when the top surface of the substrate 5120 is flat at the atomic level, the particles 5100 are arranged so that the flat surface parallel to the ab plane faces downward, thereby forming a layer with uniform thickness, flatness, and high crystallinity. CAAC-OS can be obtained by stacking n (n is a natural number) layers.

[0323] In the case where the top surface of the substrate 5120 has unevenness, n (n is a natural number) layers of particles 5100 arranged along the convex surface are stacked in the formed CAAC-OS. Since the substrate 5120 has unevenness, it is sometimes easy to generate gaps between the particles 5100 in the CAAC-OS. Note that due to the intermolecular force, even on the uneven surface, the particles are arranged in a manner that minimizes the gaps between them. Therefore, even if the formation surface has unevenness, a CAAC-OS with high crystallinity can be obtained.

[0324] Therefore, laser crystallization is not required when forming CAAC-OS, and a uniform film can be formed even on a large-area glass substrate or the like.

[0325] Since CAAC-OS is formed according to such a model, the sputtered particles are preferably in a granular form with a small thickness. Note that if the sputtered particles are in a thick particle form, the orientation of the surface on the substrate 5120 changes, so that the thickness and crystal orientation may not be uniform.

[0326] According to the above film formation model, a CAAC-OS with high crystallinity can be formed even on a formation surface having an amorphous structure.

[0327] The structure described in this embodiment mode can be used in combination with the structures described in other embodiment modes as appropriate.

[0328] Implementation 3

[0329] In this embodiment, refer to Fig.18 , Fig.19 and Fig. 20 An example of a display device including the transistor described in the above embodiment will be described.

[0330] Fig.18 is a plan view showing an example of a display device. Fig.18 The display device 700 shown includes: a pixel portion 702 arranged on a first substrate 701; a source driver circuit portion 704 and a gate driver circuit portion 706 arranged on the first substrate 701; a sealant 712 arranged in a manner surrounding the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706; and a second substrate 705 arranged in a manner opposite to the first substrate 701. The first substrate 701 and the second substrate 705 are sealed by the sealant 712. That is, the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 are sealed by the first substrate 701, the sealant 712, and the second substrate 705. Although in Fig.18 Although not shown in the figure, a display element is provided between the first substrate 701 and the second substrate 705.

[0331] In the display device 700, an FPC (flexible printed circuit) terminal portion 708 electrically connected to the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 is provided in an area different from the area surrounded by the sealant 712 on the first substrate 701. In addition, the FPC 716 is connected to the FPC terminal portion 708, and various signals are supplied to the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 through the FPC 716. In addition, the signal line 710 is connected to the pixel portion 702, the source driver circuit portion 704, the gate driver circuit portion 706, and the FPC terminal portion 708. Various signals are supplied from the FPC 716 to the pixel portion 702, the source driver circuit portion 704, the gate driver circuit portion 706, and the FPC terminal portion 708 through the signal line 710.

[0332] In addition, a plurality of gate drive circuit units 706 may be provided in the display device 700. As an example, the display device 700 is described in which the source drive circuit unit 704 and the gate drive circuit unit 706 are formed on the same first substrate 701 as the pixel unit 702, but the structure is not limited to this. For example, only the gate drive circuit unit 706 may be formed on the first substrate 701, or only the source drive circuit unit 704 may be formed on the first substrate 701. In this case, a substrate having a source drive circuit or a gate drive circuit formed thereon (for example, a drive circuit substrate formed using a single crystal semiconductor film or a polycrystalline semiconductor film) may be mounted on the first substrate 701. There is no particular limitation on the connection method of the separately formed drive circuit substrate, and a COG (chip on glass) method, a wire bonding method, or the like may be used.

[0333] The pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 included in the display device 700 include a plurality of transistors. As the plurality of transistors, transistors of the semiconductor device of one embodiment of the present invention can be used.

[0334] The display device 700 may include various elements. The element may include, for example, a liquid crystal element, an EL (electroluminescent) element (e.g., an EL element including organic and inorganic materials, an organic EL element, or an inorganic EL element), an LED (e.g., a white LED, a red LED, a green LED, a blue LED), a transistor (a transistor that emits light according to an electric current), an electron emission element, an electronic ink, an electrophoretic element, a grating light valve (GLV), a plasma display (PDP), a display element using a microelectromechanical system (MEMS), a digital micromirror device (DMD), a digital microshutter (DMS), MIRASOL (registered trademark), an IMOD (interference measurement adjustment) element, a shutter-type MEMS display element, an optical interference-type MEMS display element, an electrowetting element, a piezoelectric ceramic display, and at least one of a display element including a carbon nanotube. In addition, a display medium that changes by changing contrast, brightness, reflectivity, transmittance, etc. through electrical or magnetic action may also be included. Examples of display devices having EL elements include EL displays. Examples of display devices with electron emission elements are field emission displays (FED) and SED flat-panel displays (SED: surface-conduction electron-emitter display). Examples of display devices with liquid crystal elements include liquid crystal displays (e.g., transmissive liquid crystal displays, semi-transmissive liquid crystal displays, reflective liquid crystal displays, direct-view liquid crystal displays, and projection liquid crystal displays). Examples of display devices with electronic ink or electrophoretic elements are electronic paper. When a semi-transmissive liquid crystal display or a reflective liquid crystal display is used, part or all of the pixel electrode has the function of a reflective electrode. For example, part or all of the pixel electrode contains aluminum, silver, etc. At this time, a storage circuit such as SRAM can be set under the reflective electrode, thereby reducing power consumption.

[0335] As a display mode of the display device 700, a progressive scanning mode or an interlaced scanning mode can be adopted. In addition, the color elements controlled in the pixel when performing color display are not limited to the three colors of R, G and B (R, G and B represent red, green and blue respectively). For example, four pixels including R pixel, G pixel, B pixel and W (white) pixel may be included. Alternatively, as in the PenTile arrangement, the color elements may be composed of two colors in RGB. The two colors may also be different according to each color element. Alternatively, one or more colors such as yellow, cyan, magenta, etc. may be added to RGB. In addition, the size of the display area of ​​each color element point may be different from each other. One embodiment of the disclosed invention is not limited to a display device for color display. The disclosed invention may also be applied to a display device for black and white display.

[0336] In order to obtain a full-color display device by using white light (W) for backlight (for example, organic EL elements, inorganic EL elements, LEDs, fluorescent lamps), a coloring layer (also called a filter) can also be used. As the coloring layer, for example, red (R), green (G), blue (B), yellow (Y), etc. can be appropriately combined. By using a coloring layer, the color reproducibility can be further improved compared to the case where a coloring layer is not used. At this time, by setting an area including a coloring layer and an area not including a coloring layer, the white light in the area not including the coloring layer can be directly used for display. By partially setting an area not including a coloring layer, when displaying a bright image, the brightness reduction caused by the coloring layer can sometimes be reduced and power consumption can be reduced by 20% to 30%. Note that when using self-luminous elements such as organic EL elements or inorganic EL elements for full-color display, each element can also emit light corresponding to colors such as R, G, B, Y, and W. By using self-luminous elements, power consumption can sometimes be further reduced compared to the case where a coloring layer is used.

[0337] In this embodiment, refer to Fig.19 and Fig. 20 A structure including a liquid crystal element and an EL element as a display element will be described. Fig.19 It is along Fig.18 The cross-sectional view of the dot-dash line QR shown in FIG. 1 shows a structure including a liquid crystal element as a display element. On the other hand, Fig. 20 It is along Fig.18 1 is a cross-sectional view taken along a dashed line QR, and shows a structure including an EL element as a display element.

[0338] First of all, Fig.19 and Fig. 20 The common parts between them, and then explain the different parts.

[0339] <Common Parts in Display Devices>

[0340] Fig.19 and Fig. 20 The display device 700 shown includes: a routing wiring section 711; a pixel section 702; a source driver circuit section 704; and an FPC terminal section 708. In addition, the routing wiring section 711 includes a signal line 710. The pixel section 702 includes a transistor 750 and a capacitor 790. The source driver circuit section 704 includes a transistor 752.

[0341] As the transistors 750 and 752 , the above-described transistors can be used.

[0342] The transistor used in this embodiment includes an oxide semiconductor film that is highly purified and in which the formation of oxygen defects is suppressed. In this transistor, the current in the off state (off-state current) can be reduced. Therefore, electrical signals such as image signals can be maintained for a long period of time, and the write interval can be extended in the state where the power is turned on. Therefore, the frequency of refresh work can be reduced, thereby achieving the effect of reducing power consumption.

[0343] In addition, the transistor used in this embodiment can have a high field effect mobility and can therefore be driven at high speed. For example, by using such a transistor capable of high-speed driving in a liquid crystal display device, a switching transistor in a pixel portion and a driving transistor in a driving circuit portion can be formed on one substrate. In other words, a semiconductor device formed of a silicon wafer or the like does not need to be used separately as a driving circuit, thereby reducing the number of components of the semiconductor device. In addition, a transistor capable of high-speed driving can also be used in the pixel portion, thereby providing a high-quality image.

[0344] The capacitor 790 has a structure in which a dielectric is provided between a pair of electrodes. More specifically, a conductive film formed by the same process as a conductive film used as a gate electrode of the transistor 750 is used as one electrode of the capacitor 790, and a conductive film used as a source electrode and a drain electrode of the transistor 750 is used as the other electrode of the capacitor 790. In addition, an insulating film used as a gate insulating film of the transistor 750 is used as a dielectric between the pair of electrodes.

[0345] exist Fig.19 and Fig. 20 In the embodiment, insulating films 764 , 766 , and 768 , an oxide semiconductor film 767 , and a planarizing insulating film 770 are formed over the transistor 750 , the transistor 752 , and the capacitor 790 .

[0346] The insulating films 764, 766, and 768 can be formed using the same material and method as the insulating films 114, 116, and 118 shown in the above embodiment. The oxide semiconductor film 767 can be formed using the same material and method as the oxide semiconductor film 108 shown in the above embodiment. As the planarization insulating film 770, a heat-resistant organic material such as a polyimide resin, an acrylic resin, a polyimide amide resin, a benzocyclobutene resin, a polyamide resin, and an epoxy resin can be used. In addition, the planarization insulating film 770 can also be formed by stacking a plurality of insulating films formed using these materials. In addition, a structure in which the planarization insulating film 770 is not provided can also be adopted.

[0347] The signal line 710 is formed by the same process as the conductive film used as the source electrode and the drain electrode of the transistors 750 and 752. The signal line 710 may be formed using a conductive film formed by a process different from the conductive film used as the source electrode and the drain electrode of the transistors 750 and 752, for example, using a conductive film used as a gate electrode. When the signal line 710 is formed using a material containing copper elements, signal delays caused by wiring resistance are reduced, thereby enabling large-screen display.

[0348] The FPC terminal portion 708 includes a connection electrode 760, an anisotropic conductive film 780, and an FPC 716. The connection electrode 760 is formed by the same process as the conductive film used as the source electrode and the drain electrode of the transistors 750 and 752. The connection electrode 760 and the terminal included in the FPC 716 are electrically connected through the anisotropic conductive film 780.

[0349] For example, a glass substrate can be used as the first substrate 701 and the second substrate 705. A flexible substrate can also be used as the first substrate 701 and the second substrate 705. Examples of the flexible substrate include a plastic substrate.

[0350] A structure 778 is provided between the first substrate 701 and the second substrate 705. The structure 778 is a columnar spacer obtained by selectively etching an insulating film, and is used to control the distance (cell gap) between the first substrate 701 and the second substrate 705. In addition, a spherical spacer can also be used as the structure 778. Although a structure in which the structure 778 is provided on one side of the first substrate 701 is shown in this embodiment mode, one mode of the present invention is not limited to this. For example, the structure 778 can be provided on one side of the second substrate 705, or the structure 778 can be provided on both the first substrate 701 and the second substrate 705.

[0351] In addition, a light-shielding film 738 serving as a black matrix, a coloring film 736 serving as a color filter, and an insulating film 734 in contact with the light-shielding film 738 and the coloring film 736 are provided on the second substrate 705 side.

[0352] <Structural Example of Display Device Using Liquid Crystal Element as Display Element>

[0353] Fig.19 The display device 700 shown includes a liquid crystal element 775. The liquid crystal element 775 includes a conductive film 772, a conductive film 774, and a liquid crystal layer 776. The conductive film 774 is provided on the second substrate 705 side and functions as a counter electrode. Fig.19 The display device 700 shown can display an image by controlling the transmission or non-transmission of light by changing the alignment state of the liquid crystal layer 776 according to the voltage applied between the conductive film 772 and the conductive film 774.

[0354] The conductive film 772 is connected to a conductive film used as a source electrode and a drain electrode of the transistor 750. The conductive film 772 is formed on the planarization insulating film 770 and used as a pixel electrode, that is, one electrode of the display element. The conductive film 772 functions as a reflective electrode. Fig.19 The display device 700 is a so-called reflective color liquid crystal display device in which external light is reflected by the conductive film 772 and displayed through the color film 736.

[0355] As the conductive film 772, a conductive film that transmits visible light or a conductive film that reflects visible light can be used. As the conductive film that transmits visible light, for example, a material containing one selected from indium (In), zinc (Zn), and tin (Sn) is preferably used. As the conductive film that reflects visible light, for example, a material containing aluminum or silver can be used. In this embodiment, a conductive film that reflects visible light is used as the conductive film 772.

[0356] When a conductive film that reflects visible light is used as the conductive film 772, the conductive film may also have a stacked structure. For example, an aluminum film having a thickness of 100 nm is formed as a lower layer, and a silver alloy film (for example, an alloy film containing silver, palladium, and copper) having a thickness of 30 nm is formed as an upper layer. By adopting the above structure, the following effects can be obtained.

[0357] (1) The adhesion between the base film and the conductive film 772 can be improved; (2) The aluminum film and the silver alloy film can be etched together using a chemical solution; (3) The conductive film 772 can have a good cross-sectional shape (for example, a tapered shape). The reason for (3) is considered to be as follows: when etching is performed using a chemical solution, the etching rate of the aluminum film is slower than that of the silver alloy film, or when the lower aluminum film is exposed after etching the upper silver alloy film, electrons are extracted from the metal that is cheaper than the silver alloy film, in other words, aluminum with a higher ionization tendency, thereby suppressing the etching of the silver alloy film and etching the lower aluminum film faster than the silver alloy film.

[0358] exist Fig.19 In the display device 700, a portion of the planarization insulating film 770 of the pixel portion 702 is provided with unevenness. The planarization insulating film 770 is formed using an organic resin film or the like, and the unevenness is formed on the surface of the organic resin film, thereby forming the unevenness. The conductive film 772 used as a reflective electrode is formed along the unevenness. Thus, when external light is incident on the conductive film 772, the light can be diffusely reflected on the surface of the conductive film 772, thereby improving visibility.

[0359] In addition, as Fig.19 The display device 700 shown in the figure is a reflective color liquid crystal display device, but its display mode is not limited to this. For example, a transmissive color liquid crystal display device in which the conductive film 772 is a conductive film that transmits visible light may also be used. When a transmissive color liquid crystal display device is used, it is not necessary to provide a concavoconvex shape on the planarization insulating film 770.

[0360] Although in Fig.19 Although not shown in the figure, an alignment film may be provided on the side of the conductive film 772 and the conductive film 774 that contacts the liquid crystal layer 776. Fig.19 Although not shown in the figure, optical components (optical substrates) such as polarization components, phase difference components, and anti-reflection components may be appropriately provided. For example, circular polarization using a polarization substrate and a phase difference substrate may also be used. In addition, backlight, side light, etc. may also be used as a light source.

[0361] When a liquid crystal element is used as a display element, thermotropic liquid crystal, low molecular liquid crystal, polymer liquid crystal, polymer dispersed liquid crystal, ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. These liquid crystal materials exhibit cholesteric phase, smectic phase, cubic phase, chiral nematic phase, homogeneous phase, etc. depending on the conditions.

[0362] In the case of adopting the transverse electric field method, liquid crystals exhibiting a blue phase that do not require an orientation film can also be used. The blue phase is a type of liquid crystal phase, and refers to the phase that appears just before the transition from the cholesteric phase to the homogeneous phase when the temperature of the cholesteric liquid crystal is raised. Because the blue phase only appears within a narrow temperature range, a liquid crystal composition in which a chiral agent is mixed is used in the liquid crystal layer to expand the above-mentioned temperature range. The liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a fast response speed and is optically isotropic. In addition, the liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent does not require an orientation treatment and has low viewing angle dependence. Since there is no need to set an orientation film, there is no need for friction treatment, so electrostatic damage caused by friction treatment can be prevented, thereby reducing defects and damage to the liquid crystal display device in the manufacturing process.

[0363] When a liquid crystal element is used as a display element, a TN (twisted nematic) mode, an IPS (in-plane-switching) mode, an FFS (fringe field switching) mode, an ASM (axially symmetric aligned micro-cell) mode, an OCB (optical compensated birefringence) mode, an FLC (ferroelectric liquid crystal) mode, and an AFLC (antiFerroelectric liquid crystal) mode can be used.

[0364] In addition, a normally black liquid crystal display device may be used, such as a transmissive liquid crystal display device using a vertical alignment (VA) mode. As vertical alignment modes, several examples may be cited, such as an MVA (multi-domain vertical alignment) mode, a PVA (patterned vertical alignment) mode, an ASV (advanced super view) mode, etc.

[0365] <Display Device Using Light-Emitting Element as Display Element>

[0366] Fig. 20 The display device 700 shown includes a light-emitting element 782. The light-emitting element 782 includes a conductive film 784, an EL layer 786, and a conductive film 788. Fig. 20 The illustrated display device 700 can display an image by emitting light from an EL layer 786 included in a light-emitting element 782 .

[0367] The conductive film 784 is connected to a conductive film used as a source electrode or a drain electrode of the transistor 750. The conductive film 784 is formed on the planarization insulating film 770 and is used as a pixel electrode, that is, an electrode of the display element. As the conductive film 784, a conductive film that transmits visible light or a conductive film that reflects visible light can be used. As the conductive film that transmits visible light, for example, a material containing one selected from indium (In), zinc (Zn) and tin (Sn) is preferably used. As the conductive film that reflects visible light, for example, a material containing aluminum or silver is preferably used.

[0368] exist Fig. 20 In the display device 700 shown, an insulating film 730 is provided on a planarizing insulating film 770 and a conductive film 784. The insulating film 730 covers a portion of the conductive film 784. The light-emitting element 782 has a top emission structure. Therefore, the conductive film 788 has light-transmitting properties and transmits light emitted by the EL layer 786. Although a top emission structure is illustrated in this embodiment mode, one mode of the present invention is not limited thereto. For example, a bottom emission structure that emits light to one side of the conductive film 784 or a double-sided emission structure that emits light to both the conductive film 784 side and the conductive film 788 side may be adopted.

[0369] A coloring film 736 is provided at a position overlapping with the light emitting element 782, and a light shielding film 738 is provided at a position overlapping with the insulating film 730 so as to be included in the routing wiring portion 711 and the source driver circuit portion 704. The coloring film 736 and the light shielding film 738 are covered by the insulating film 734. The sealing film 732 is filled between the light emitting element 782 and the insulating film 734. Fig. 20 The display device 700 shown in the example is provided with the colored film 736 , but one embodiment of the present invention is not limited thereto. When the EL layer 786 is formed by applying materials of different colors, the colored film 736 is not necessarily provided.

[0370] The structure described in this embodiment mode can be used in combination with the structures described in other embodiment modes as appropriate.

[0371] Implementation 4

[0372] In this embodiment, refer to FIG. 21A to FIG. 21C A display device including a semiconductor device according to one embodiment of the present invention will be described.

[0373] Fig.21A The display device shown includes: a region having pixels of display elements (hereinafter referred to as a pixel portion 502); a circuit portion arranged outside the pixel portion 502 and having a circuit for driving the pixels (hereinafter referred to as a driving circuit portion 504); a circuit having a function of protecting the element (hereinafter referred to as a protection circuit 506); and a terminal portion 507. Note that the protection circuit 506 does not necessarily need to be provided.

[0374] A part or all of the driver circuit portion 504 is preferably formed on the same substrate as the pixel portion 502. In this case, the number of components and the number of terminals can be reduced. When a part or all of the driver circuit portion 504 is not formed on the same substrate as the pixel portion 502, a part or all of the driver circuit portion 504 can be mounted by COG or TAB (tape automated bonding).

[0375] The pixel portion 502 includes a circuit for driving display elements arranged in X rows (X is a natural number greater than or equal to 2) and Y columns (Y is a natural number greater than or equal to 2) (hereinafter, such a circuit is referred to as a pixel circuit 501). The driving circuit portion 504 includes a circuit for outputting a signal (scanning signal) for selecting a pixel (hereinafter, such a circuit is referred to as a gate driver 504a), a circuit for supplying a signal (data signal) for driving the display element in the pixel (hereinafter, such a circuit is referred to as a source driver 504b), and other driving circuits.

[0376] The gate driver 504a has a shift register, etc. The gate driver 504a receives a signal for driving the shift register through the terminal portion 507 and outputs a signal. For example, the gate driver 504a receives a start pulse signal, a clock signal, etc. and outputs a pulse signal. The gate driver 504a has a function of controlling the potential of the wiring to which the scan signal is supplied (hereinafter, such wiring is referred to as the scan line GL_1 to GL_X). In addition, a plurality of gate drivers 504a may be provided to control the scan lines GL_1 to GL_X respectively. Alternatively, the gate driver 504a has a function of supplying an initialization signal. However, this is not limited to this, and the gate driver 504a may supply other signals.

[0377] The source driver 504b has a shift register, etc. Through the terminal portion 507, the source driver 504b receives a signal (image signal) for generating a data signal in addition to a signal for driving the shift register. The source driver 504b has a function of generating a data signal written to the pixel circuit 501 based on the image signal. In addition, the source driver 504b has a function of controlling the output of the data signal according to a pulse signal generated by an input start pulse signal, a clock signal, etc. In addition, the source driver 504b has a function of controlling the potential of the wiring (hereinafter, such wiring is referred to as data lines DL_1 to DL_Y) supplied with the data signal. Alternatively, the source driver 504b has a function of supplying an initialization signal. However, it is not limited to this, and the source driver 504b can also supply other signals.

[0378] The source driver 504b includes, for example, a plurality of analog switches, etc. By sequentially turning on the plurality of analog switches, the source driver 504b can output a signal obtained by time-dividing an image signal as a data signal. The source driver 504b can also include a shift register, etc.

[0379] Each of the plurality of pixel circuits 501 is input with a pulse signal through one of the plurality of scanning lines GL supplied with a scanning signal, and is input with a data signal through one of the plurality of data lines DL supplied with a data signal. Each of the plurality of pixel circuits 501 is controlled by a gate driver 504a to write and hold the data signal. For example, a pulse signal is input from the gate driver 504a to the pixel circuit 501 in the mth row and nth column through the scanning line GL_m, and a data signal is input from the source driver 504b to the pixel circuit 501 in the mth row and nth column through the data line DL_n according to the potential of the scanning line GL_m (m is a natural number less than X, and n is a natural number less than Y).

[0380] Fig.21A The protection circuit 506 shown is connected to, for example, a scanning line GL between the gate driver 504a and the pixel circuit 501. Alternatively, the protection circuit 506 is connected to a data line DL between the source driver 504b and the pixel circuit 501. Alternatively, the protection circuit 506 may be connected to a wiring between the gate driver 504a and the terminal portion 507. Alternatively, the protection circuit 506 may be connected to a wiring between the source driver 504b and the terminal portion 507. In addition, the terminal portion 507 refers to a portion having a terminal for inputting power, a control signal, and an image signal from an external circuit to the display device.

[0381] The protection circuit 506 is a circuit that connects a wiring connected to the protection circuit to another wiring when a potential outside a certain range is supplied to the wiring.

[0382] like Fig.21A As shown, by providing a protection circuit 506 for each pixel portion 502 and a driving circuit portion 504, the resistance of the display device to overcurrent caused by ESD (electro static discharge) and the like can be improved. However, the structure of the protection circuit 506 is not limited thereto, for example, the protection circuit 506 can be connected to the gate driver 504a, or the protection circuit 506 can also be connected to the source driver 504b. Alternatively, the protection circuit 506 can also be connected to the terminal portion 507.

[0383] exist Fig.21A , the example in which the driver circuit portion 504 includes a gate driver 504a and a source driver 504b is shown, but the structure is not limited to this. For example, only the gate driver 504a may be formed and a separately prepared substrate having a source driver circuit formed thereon (for example, a driver circuit substrate formed using a single crystal semiconductor film or a polycrystalline semiconductor film) may be mounted.

[0384] Fig.21A The plurality of pixel circuits 501 shown may have, for example, Fig.21B The structure shown.

[0385] Fig.21B The pixel circuit 501 shown includes a liquid crystal element 570, a transistor 550, and a capacitor 560. As the transistor 550, for example, the transistor described in the above embodiment mode can be used.

[0386] The potential of one of the pair of electrodes of the liquid crystal element 570 is appropriately set according to the specifications of the pixel circuit 501. The orientation state of the liquid crystal element 570 is set according to the written data. In addition, a common potential may be supplied to one of the pair of electrodes of the liquid crystal element 570 included in each of the plurality of pixel circuits 501. In addition, the potential supplied to one of the pair of electrodes of the liquid crystal element 570 of the pixel circuit 501 of one row may be different from the potential supplied to one of the pair of electrodes of the liquid crystal element 570 of the pixel circuit 501 of another row.

[0387] As examples of a driving method of a display device including the liquid crystal element 570, the following modes can be cited: TN mode; STN mode; VA mode; ASM (axially symmetric aligned micro-cell) mode; OCB (optically compensated birefringence) mode; FLC (ferroelectric liquid crystal) mode; AFLC (antiFerroelectric liquid crystal) mode; MVA mode; PVA (patterned vertical alignment) mode; IPS mode; FFS mode; or TBA (transverse bend alignment) mode. As other examples of a driving method of a display device, there are ECB (electrically controlled birefringence) mode, PDLC (polymer dispersed liquid crystal) mode, PNLC (polymer network liquid crystal) mode, and guest-host mode. However, the present invention is not limited to these examples, and various liquid crystal elements and driving methods can be applied to the liquid crystal element and its driving method.

[0388] In the pixel circuit 501 at the mth row and the nth column, one of the source electrode and the drain electrode of the transistor 550 is electrically connected to the data line DL_n, and the other of the source electrode and the drain electrode is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. The gate electrode of the transistor 550 is electrically connected to the scanning line GL_m. The transistor 550 has a function of controlling whether to write a data signal by turning on or off.

[0389] One of a pair of electrodes of the capacitor 560 is electrically connected to a wiring to which a potential is supplied (hereinafter referred to as a potential supply line VL), and the other is electrically connected to the other of a pair of electrodes of the liquid crystal element 570. The potential of the potential supply line VL is appropriately set according to the specification of the pixel circuit 501. The capacitor 560 is used as a storage capacitor for storing written data.

[0390] For example, in a Fig.21B In the display device of the pixel circuit 501, by Fig.21A The gate driver 504 a shown sequentially selects the pixel circuits 501 of each row to turn on the transistors 550 and write data signals.

[0391] When the transistor 550 is turned off, the pixel circuit 501 to which the data has been written is held. An image can be displayed by sequentially performing the above steps row by row.

[0392] in addition, Fig.21A The plurality of pixel circuits 501 may have, for example, Fig. 21C The structure shown.

[0393] Fig. 21C The pixel circuit 501 shown includes transistors 552 and 554, a capacitor 562, and a light-emitting element 572. The transistor described in the above embodiment can be used for one or both of the transistors 552 and 554.

[0394] One of a source electrode and a drain electrode of the transistor 552 is electrically connected to a wiring (hereinafter referred to as a signal line DL_n) to which a data signal is supplied. A gate electrode of the transistor 552 is electrically connected to a wiring (hereinafter referred to as a scanning line GL_m) to which a gate signal is supplied.

[0395] The transistor 552 has a function of controlling whether or not a data signal is written by being turned on or off.

[0396] One of a pair of electrodes of the capacitor 562 is electrically connected to a wiring to which a potential is supplied (hereinafter referred to as a potential supply line VL_a), and the other is electrically connected to the other of a source electrode and a drain electrode of the transistor 552 .

[0397] The capacitor 562 is used as a storage capacitor for storing written data.

[0398] One of a source electrode and a drain electrode of the transistor 554 is electrically connected to the potential supply line VL_a, and a gate electrode of the transistor 554 is electrically connected to the other of a source electrode and a drain electrode of the transistor 552 .

[0399] One of the anode and the cathode of the light-emitting element 572 is electrically connected to the potential supply line VL_b, and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor 554 .

[0400] As the light-emitting element 572, for example, an organic electroluminescent element (also referred to as an organic EL element) or the like can be used. Note that the light-emitting element 572 is not limited to an organic EL element, and an inorganic EL element including an inorganic material can also be used.

[0401] A high power supply potential VDD is applied to one of the potential supply line VL_a and the potential supply line VL_b, and a low power supply potential VSS is applied to the other.

[0402] For example, in a Fig. 21C In the display device of the pixel circuit 501, by Fig.21A The gate driver 504a shown sequentially selects the pixel circuits 501 of each row to turn on the transistors 552 and write data signals.

[0403] When the transistor 552 is turned off, the pixel circuit 501 to which the data is written is kept. Furthermore, the amount of current flowing between the source electrode and the drain electrode of the transistor 554 is controlled according to the potential of the written data signal. The light-emitting element 572 emits light at a brightness corresponding to the amount of current flowing. By sequentially performing the above steps row by row, an image can be displayed.

[0404] The structure described in this embodiment mode can be used in combination with the structures described in other embodiment modes as appropriate.

[0405] Implementation method 5

[0406] In this embodiment, refer to Fig. 22 and FIG. 23A to FIG. 23G A display module and an electronic device including a semiconductor device according to one embodiment of the present invention will be described.

[0407] exist Fig. 22 In the display module 8000 shown, a touch panel 8004 connected to an FPC 8003 , a display panel 8006 connected to an FPC 8005 , a backlight 8007 , a frame 8009 , a printed circuit board 8010 , and a battery 8011 are provided between an upper cover 8001 and a lower cover 8002 .

[0408] For example, the semiconductor device which is one embodiment of the present invention can be used for the display panel 8006 .

[0409] The shapes and sizes of the upper cover 8001 and the lower cover 8002 may be appropriately changed according to the sizes of the touch panel 8004 and the display panel 8006 .

[0410] The touch panel 8004 may be a resistive film touch panel or an electrostatic capacitance touch panel, and may be formed in a manner overlapping with the display panel 8006. The counter substrate (sealing substrate) of the display panel 8006 may have a touch panel function. In addition, a light sensor may be provided in each pixel of the display panel 8006 to form an optical touch panel.

[0411] Backlight 8007 includes light source 8008. Note that although Fig. 22 2 shows a structure in which the light source 8008 is arranged on the backlight 8007, but one embodiment of the present invention is not limited to this structure. For example, a structure in which the light source 8008 is arranged at the end of the backlight 8007 and a light diffusion plate is also arranged may be adopted. When a self-luminous light-emitting element such as an organic EL element is used, or when a reflective panel is used, the backlight 8007 is not necessarily required to be provided.

[0412] The frame 8009 protects the display panel 8006 and has an electromagnetic shielding function for shielding electromagnetic waves generated by the operation of the printed circuit board 8010. The frame 8009 may also have a function as a heat sink.

[0413] The printed circuit board 8010 is provided with a power supply circuit and a signal processing circuit for outputting a video signal and a clock signal. As a power supply for supplying power to the power supply circuit, an external commercial power supply or a power supply using a separately provided battery 8011 can be used. When a commercial power supply is used, the battery 8011 can be omitted.

[0414] The display module 8000 may also be provided with components such as a polarizing plate, a phase difference plate, and a prism sheet.

[0415] FIG. 23A to FIG. 23G 9000, a display unit 9001, a speaker 9003, an operation key 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (a sensor having a function of measuring the following factors: force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, electricity, radiation, flow, humidity, inclination, vibration, smell or infrared), a microphone 9008, etc.

[0416] FIG. 23A to FIG. 23G The electronic device shown may have various functions, such as: a function of displaying various information (static images, dynamic images, text images, etc.) on a display unit; a function of a touch panel; a function of displaying a calendar, date, or time, etc.; a function of controlling processing by using various software (programs); a function of wireless communication; a function of connecting to various computer networks by using a wireless communication function; a function of sending or receiving various data by using a wireless communication function; a function of reading a program or data stored in a recording medium and displaying it on a display unit; etc. Note that FIG. 23A to FIG. 23G The functions of the electronic device shown are not limited thereto, and the electronic device may have various functions. FIG. 23A to FIG. 23G Although not shown in the figure, the electronic device may also include multiple display units. The electronic device may include a camera, etc., and may have the following functions: a function of taking a still image; a function of taking a moving image; a function of storing the taken image in a recording medium (an external recording medium or a recording medium built into the camera); a function of displaying the taken image on a display unit; etc.

[0417] Next, FIG. 23A to FIG. 23G The electronic device shown is described in detail.

[0418] Fig.23A 9001 is a three-dimensional diagram of a portable information terminal 9100. The display unit 9001 of the portable information terminal 9100 is flexible and can be assembled along the curved surface of the frame 9000. In addition, the display unit 9001 includes a touch sensor, and the screen can be operated by touching it with a finger or a stylus pen. For example, by touching an icon displayed on the display unit 9001, an application can be started.

[0419] Fig. 23B 9101 is a three-dimensional diagram of a portable information terminal 9101. The portable information terminal 9101 has one or more functions of, for example, a telephone, an electronic notebook, and an information reading system. Specifically, the portable information terminal 9101 can be used as a smart phone. Fig. 23B The speaker 9003, the connection terminal 9006, the sensor 9007, etc. are not shown in the figure, but the portable information terminal 9101 can also be connected with Fig.23A The portable information terminal 9100 shown in the figure is provided with a speaker 9003, a connection terminal 9006, a sensor 9007, etc. at the same position. The portable information terminal 9101 can display text and image information on its multiple surfaces. For example, three operation buttons 9050 (also referred to as operation icons, or simply icons) can be displayed on one surface of the display unit 9001. In addition, information 9051 represented by a dotted rectangle can be displayed on other surfaces of the display unit 9001. Examples of information 9051 include notifications from SNS (social networking services), displays indicating that an email or phone call has been received, etc.; titles of emails or SNS, etc.; senders of emails or SNS, etc.; date; time; battery power; antenna reception strength. Alternatively, operation buttons 9050, etc. can be displayed at the location where information 9051 is displayed instead of information 9051.

[0420] Fig.23C 9102 is a three-dimensional diagram of a portable information terminal 9102. The portable information terminal 9102 has a function of displaying information on three or more surfaces of the display unit 9001. Here, information 9052, information 9053, and information 9054 are displayed on different surfaces. For example, a user of the portable information terminal 9102 can confirm its display (here, information 9053) while placing the portable information terminal 9102 in a jacket pocket. Specifically, the phone number or name of the person calling is displayed at a position where such information can be viewed from above the portable information terminal 9102. Therefore, the user can confirm the display without taking the portable information terminal 9102 out of the pocket, and can decide whether to answer the call.

[0421] Fig.23D It is a stereoscopic diagram of a watch-type portable information terminal 9200. The portable information terminal 9200 can execute various applications such as mobile phones, e-mails, article reading and editing, music playback, network communications, computer games, etc. The display surface of the display unit 9001 is curved, and images can be displayed on the curved display surface. The portable information terminal 9200 can adopt short-range wireless communication based on communication standards. For example, by utilizing the mutual communication between the portable information terminal 9200 and a headset capable of wireless communication, a hands-free call can be made. In addition, the portable information terminal 9200 includes a connection terminal 9006, and data can be exchanged directly with other information terminals through a connector. In addition, charging can also be performed through the connection terminal 9006. In addition, wireless power supply can also be used for charging without using the connection terminal 9006.

[0422] Fig.23E , Fig.23F , Figure 23G The three-dimensional diagram of the portable information terminal 9201 that can be folded shows: an unfolded state; a state converted from the unfolded state to the folded state or from the folded state to the unfolded state; and a folded state. The portable information terminal 9201 has good portability in the folded state. When the portable information terminal 9201 is in the unfolded state, the seamless large display area can provide high visibility. The display unit 9001 of the portable information terminal 9201 is supported by three frames 9000 connected by hinges 9055. By folding the portable information terminal 9201 at the connection between the two frames 9000 using the hinges 9055, the portable information terminal 9201 can be reversibly changed from the unfolded state to the folded state. For example, the portable information terminal 9201 can be bent with a curvature radius of more than 1 mm and less than 150 mm.

[0423] The electronic device described in this embodiment has a display unit for displaying certain information. However, the semiconductor device of one embodiment of the present invention can also be used in an electronic device that does not include a display unit. In addition, the display unit of the electronic device described in this embodiment may not be flexible and display images on a flat surface, and is not limited to a mode that can display images on a curved display surface or a mode that can be folded.

[0424] The structure described in this embodiment mode can be used in combination with the structures described in other embodiment modes as appropriate.

[0425] Implementation 6

[0426] In this embodiment, refer to Fig.24 An example of a circuit structure of a semiconductor device will be described in which data can be retained even when power is not supplied and there is no limit to the number of times data can be written.

[0427] <Circuit Structure>

[0428] Fig.24 An example of a circuit structure of a semiconductor device is shown. Fig.24 In the embodiment, the first wiring (1st Line) is electrically connected to one of the source electrode and the drain electrode of the p-type transistor 1280a. In addition, the other of the source electrode and the drain electrode of the p-type transistor 1280a is electrically connected to one of the source electrode and the drain electrode of the n-type transistor 1280b. In addition, the other of the source electrode and the drain electrode of the n-type transistor 1280b is electrically connected to one of the source electrode and the drain electrode of the n-type transistor 1280c.

[0429] The second wiring (2nd Line) is electrically connected to one of the source electrode and the drain electrode of the transistor 1282. In addition, the other of the source electrode and the drain electrode of the transistor 1282 is electrically connected to one electrode of the capacitor 1281 and the gate electrode of the n-type transistor 1280c.

[0430] The third wiring (3rd Line) is electrically connected to the gate electrodes of the p-type transistor 1280a and the n-type transistor 1280b. In addition, the fourth wiring (4th Line) is electrically connected to the gate electrode of the transistor 1282. In addition, the fifth wiring (5th Line) is electrically connected to the other electrode of the capacitor 1281 and the other of the source electrode and the drain electrode of the n-type transistor 1280c. In addition, the sixth wiring (6th Line) is electrically connected to the other of the source electrode and the drain electrode of the p-type transistor 1280a and one of the source electrode and the drain electrode of the n-type transistor 1280b.

[0431] Alternatively, the transistor 1282 may be formed using an oxide semiconductor (OS). Fig.24 In FIG. 1 , the transistor 1282 is denoted by “OS”. Alternatively, the transistor 1282 may be formed using a material other than an oxide semiconductor. As the transistor 1282, the transistor 100 or the transistor 170 described in Embodiment 1 can be used.

[0432] In addition, Fig.24 In the embodiment, a floating node (FN) is attached to a connection portion of the other of the source electrode and the drain electrode of the transistor 1282, one electrode of the capacitor 1281, and the gate electrode of the n-type transistor 1280c. When the transistor 1282 is in an off state, the potential applied to the floating node, one electrode of the capacitor 1281, and the gate electrode of the n-type transistor 1280c can be maintained.

[0433] Fig.24 The circuit configuration shown can write, hold, and read data as follows by effectively utilizing the feature of being able to hold the potential of the gate electrode of the n-type transistor 1280c.

[0434] <Data Writing and Retention>

[0435] First, the writing and holding of data are described. The potential of the fourth wiring is set to a potential that turns the transistor 1282 into an on state, thereby turning the transistor 1282 into an on state. Thus, the potential of the second wiring is applied to the gate electrode of the n-type transistor 1280c and the capacitor 1281. In other words, a specified charge is applied to the gate electrode of the n-type transistor 1280c (writing). Then, the potential of the fourth wiring is set to a potential that turns the transistor 1282 into an off state, thereby turning the transistor 1282 into an off state. Thus, the charge applied to the gate electrode of the n-type transistor 1280c is maintained (maintained).

[0436] Since the off-state current of the transistor 1282 is extremely small, the charge of the gate electrode of the n-type transistor 1280c is retained for a long time.

[0437] <Data Reading>

[0438] Next, the reading of data is described. When the potential of the third wiring is a low-level potential, the p-type transistor 1280a becomes an on state and the n-type transistor 1280b becomes an off state. At this time, the potential of the first wiring is applied to the sixth wiring. On the other hand, when the potential of the third wiring is a high-level potential, the p-type transistor 1280a becomes an off state and the n-type transistor 1280b becomes an on state. At this time, the potential of the sixth wiring changes according to the amount of charge maintained at the floating node (FN). Therefore, the data held can be read out (read out) by measuring the potential of the sixth wiring.

[0439] The off-state current of the transistor 1282 using an oxide semiconductor in its channel formation region is extremely small. Since the off-state current of the transistor 1282 using an oxide semiconductor is less than one ten-thousandth of the off-state current of a transistor formed using a silicon semiconductor or the like, the disappearance of the charge stored in the floating node (FN) due to the leakage current of the transistor 1282 can be ignored. That is, the transistor 1282 formed using an oxide semiconductor can realize a non-volatile memory circuit that can retain data even without power supply.

[0440] By applying a semiconductor device including the above circuit structure to a storage device such as a register or a cache memory, it is possible to prevent data in the storage device from being lost due to the supply of power supply voltage being stopped. In addition, after the supply of power supply voltage is restarted, the storage device can be immediately restored to the state before the power supply was stopped. Therefore, when the entire storage device or one or more logic circuits included in the storage device is in a standby state, the power supply can be stopped even for a short time, so low power consumption can be achieved.

[0441] The structure, method, and the like described in this embodiment can be used in combination with the structure, method, and the like described in other embodiments as appropriate.

[0442] Example

[0443] In this embodiment, the manufacturing method is equivalent to Fig. 6A and Figure 6B The transistor 170 is shown as a transistor, and the I d -V g Characteristics are evaluated.

[0444] In this embodiment, samples A1 to A3 shown below are formed and evaluated. Samples A1 to A3 are samples of one embodiment of the present invention. In the transistor of sample A1, the channel length L is 6 μm and the channel width W is 5 μm; in the transistor of sample A2, the channel length L is 6 μm and the channel width W is 50 μm; in the transistor of sample A3, the channel length L is 6 μm and the channel width W is 200 μm. As samples A1 to A3, 10 transistors of the above sizes are formed respectively.

[0445] Next, samples A1 to A3 formed in this embodiment are described. The difference between samples A1 to A3 is only in the size of the channel width W of the transistor, and their manufacturing process is the same. Note that in the following description, the term " Fig. 6A and Figure 6B The symbol used in transistor 170.

[0446] <Method of Manufacturing Samples A1 to A3>

[0447] First, the conductive film 104 is formed on the substrate 102. A glass substrate is used as the substrate 102. The size and thickness of the glass substrate are set to 600 mm x 720 mm and 0.7 mm, respectively. As the conductive film 104, a tungsten film with a thickness of 100 nm is formed by using a sputtering device.

[0448] Next, insulating films 106 and 107 are formed on the substrate 102 and the conductive film 104. As the insulating film 106, a 400 nm thick silicon nitride film is formed using a PECVD apparatus. As the insulating film 107, a 50 nm thick silicon oxynitride film is formed using a PECVD apparatus.

[0449] The insulating film 106 is formed in the following manner. First, a silicon nitride film with a thickness of 50 nm is formed under the following conditions: the substrate temperature is 350°C; a silane gas with a flow rate of 200 sccm, a nitrogen gas with a flow rate of 2000 sccm, and an ammonia gas with a flow rate of 100 sccm are introduced into the processing chamber; the pressure is 100 Pa; and an RF power of 2000 W is supplied to the parallel plate electrodes set in the PECVD device. Next, the ammonia flow rate is changed to 2000 sccm to form a silicon nitride film with a thickness of 300 nm. Finally, the ammonia flow rate is changed to 100 sccm to form a silicon nitride film with a thickness of 50 nm.

[0450] The insulating film 107 is formed under the following conditions: the substrate temperature is 350°C; silane gas with a flow rate of 20 sccm and nitrous oxide gas with a flow rate of 3000 sccm are introduced into the processing chamber; the pressure is 40 Pa; and 100 W of RF power is supplied to the parallel plate electrodes arranged in the PECVD device.

[0451] Next, an oxide semiconductor film 108 is formed over the insulating film 107. The oxide semiconductor film 108 has a stacked-layer structure of a first oxide semiconductor film 108a on one side of the conductive film 104 (serving as a gate electrode) and a second oxide semiconductor film 108b on the first oxide semiconductor film 108a. An IGZO film having a thickness of 10 nm is formed as the first oxide semiconductor film 108a, and an IGZO film having a thickness of 15 nm is formed as the second oxide semiconductor film 108b.

[0452] The first oxide semiconductor film 108a is formed under the following conditions: the substrate temperature is 170°C; argon gas with a flow rate of 140 sccm and oxygen gas with a flow rate of 60 sccm are introduced into the processing chamber; the pressure is 0.6 Pa; and 2500 W of AC power is supplied to the polycrystalline metal oxide sputtering target (having an atomic ratio of In:Ga:Zn=4:2:4.1).

[0453] The second oxide semiconductor film 108b is formed under the following conditions: the substrate temperature is 170°C; argon gas with a flow rate of 100 sccm and oxygen gas with a flow rate of 100 sccm are introduced into the processing chamber; the pressure is 0.6 Pa; and 2500 W of AC power is supplied to the polycrystalline metal oxide sputtering target (having an atomic ratio of In:Ga:Zn=1:1:1.2).

[0454] Next, conductive films 112a and 112b are formed over the insulating film 107 and the oxide semiconductor film 108. The conductive films 112a and 112b are formed by successively forming a 50 nm thick tungsten film, a 400 nm thick aluminum film, and a 100 nm thick titanium film in this order in a vacuum using a sputtering apparatus.

[0455] Next, an insulating film 114 and an insulating film 116 are formed over the insulating film 107, the oxide semiconductor film 108, and the conductive films 112a and 112b. As the insulating film 114, a silicon oxynitride film with a thickness of 50 nm is formed by using a PECVD apparatus. As the insulating film 116, a silicon oxynitride film with a thickness of 400 nm is formed by using a PECVD apparatus. Note that the insulating film 114 and the insulating film 116 are formed continuously in a vacuum by using a PECVD apparatus.

[0456] The insulating film 114 is formed under the following conditions: the substrate temperature is 220°C; silane gas with a flow rate of 50 sccm and nitrous oxide gas with a flow rate of 2000 sccm are introduced into the processing chamber; the pressure is 20 Pa; and 100 W of RF power is supplied to the parallel plate electrodes set in the PECVD device. The insulating film 116 is formed under the following conditions: the substrate temperature is 220°C; silane gas with a flow rate of 160 sccm and nitrous oxide gas with a flow rate of 4000 sccm are introduced into the processing chamber; the pressure is 200 Pa; and 1500 W of RF power is supplied to the parallel plate electrodes set in the PECVD device.

[0457] Next, a first heat treatment is performed at 350° C. for one hour in a nitrogen atmosphere.

[0458] An ITSO film with a thickness of 5 nm is formed on the insulating film 116 by using a sputtering device. The ITSO film is formed under the following conditions: the substrate temperature is room temperature; an argon gas with a flow rate of 72 sccm and an oxygen gas with a flow rate of 5 sccm are introduced into the processing chamber; the pressure is 0.15 Pa; and a metal oxide target (In 2 O 3 :SnO 2 :SiO 2 =85:10:5 [wt. %]) supplies 1000 W of DC power.

[0459] Next, oxygen addition treatment was performed on the insulating film 116 via the ITSO film. The oxygen addition treatment was performed by using an ashing device under the following conditions: substrate temperature was 40° C.; oxygen gas was introduced into the processing chamber at a flow rate of 250 sccm; pressure was 15 Pa; and 4500 W of RF power was supplied to a parallel plate electrode provided in the ashing device for 120 seconds to apply a bias voltage to one side of the substrate.

[0460] Next, the ITSO film is removed to expose the insulating film 116. The ITSO film is removed by etching with a 5% oxalic acid aqueous solution for 300 seconds using a wet etching apparatus and then etching with a 0.5% hydrofluoric acid for 15 seconds.

[0461] Next, an insulating film 118 is formed on the insulating film 116. A 100 nm thick silicon nitride film is formed by using a PECVD apparatus as the insulating film 118. The substrate temperature in the PECVD apparatus when forming the insulating film 118 is 350°C.

[0462] Next, the opening 142c reaching the conductive film 112b and the openings 142a and 142b reaching the conductive film 104 are formed. The openings 142a, 142b, and 142c are formed using a dry etching apparatus.

[0463] Next, a conductive film is formed on the insulating film 118 so as to cover the openings 142a, 142b, and 142c, and the conductive film is processed to form conductive films 120a and 120b. As the conductive films 120a and 120b, an ITSO film having a thickness of 100 nm is formed by using a sputtering device. The composition of the target material used for the ITSO film is the same as the composition of the target material for forming the ITSO film shown above.

[0464] Next, a second heat treatment is performed at 250° C. for one hour in a nitrogen atmosphere.

[0465] Through the above steps, samples A1 to A3 of this embodiment were manufactured. The highest temperature in the steps of manufacturing samples A1 to A3 was 350°C.

[0466] <The I d -V g Features>

[0467] Next, the I d -V g characteristic. FIG. 25A to FIG. 25C The I of samples A1 to A3 are shown. d -V g characteristic. Notice, Fig.25A The I of sample A1 is shown d -V g characteristic, Fig.25B The I of sample A2 is shown d -V g characteristic, Fig.25C The I of sample A3 is shown d -V g Features. FIG. 25A to FIG. 25C In the figure, the first vertical axis represents I d (A), the second vertical axis represents μFE (cm 2 / Vs), the horizontal axis represents V g (V). In addition, FIG. 25A to FIG. 25C In FIG. 1 , 10 transistor characteristics are shown in an overlapping manner.

[0468] In addition, the I d -V g In the measurement, a voltage (hereinafter, this voltage is also referred to as a gate voltage (V g )) and a voltage (V bg ) were changed from -15V to +20V in increments of 0.25V each time. Note that only in the transistor of sample A3, V g and V bg The voltage applied to the conductive film 112a serving as a source electrode (hereinafter, this voltage is also referred to as source voltage (V s )) is 0 V (comm), and a voltage (hereinafter, this voltage is also referred to as a drain voltage (V d )) is 0.1V or 20V. As the field effect mobility (μFE) is shown at V d =The result obtained when 20V.

[0469] Depend on FIG. 25A to FIG. 25C The results shown show that even if the highest temperature in the process is a relatively low 350°C, the FET characteristics are almost independent of the channel width W, and the FET obtains a stable normally-off characteristic. Note that in this embodiment, the normally-off characteristic of the transistor refers to: g = 0V, the current flowing through the drain and source per channel width of 1μm at room temperature is 1×10 -20 Below A, 1×10 -18 A or less, or 1×10 -16 A or less. The transistors of samples A1 to A3 of one embodiment of the present invention exhibit high field effect mobility. In particular, the transistors of samples A2 and A3 exhibit high field effect mobility, exceeding 30 cm 2 / Vs.

[0470] As described above, in a semiconductor device according to one embodiment of the present invention, even at a low process temperature (eg, 350° C.), the semiconductor device can have excellent electrical characteristics (especially, high reliability and high field-effect mobility) by using a stacked oxide semiconductor film.

[0471] The structure shown in this embodiment can also be used in combination with other embodiment modes as appropriate.

[0472] Explanation of symbols

[0473] 100: transistor, 102: substrate, 104: conductive film, 106: insulating film, 107: insulating film, 108: oxide semiconductor film, 108a: oxide semiconductor film, 108b: oxide semiconductor film, 109: oxide semiconductor film, 109a: oxide semiconductor film, 109b: oxide semiconductor film, 112: conductive film, 112a: conductive film, 112b: conductive film, 114: insulating film, 116: insulating film, 118: insulating film, 120: conductive film, 120a: conductive film, 120b: conductive film, 131: barrier film, 136a: mask, 136b: mask, 138: etching material, 139: etching material, 140: oxygen, 140a: oxygen, 141 : Arrow, 142: Etching material, 142a: Opening, 142b: Opening, 142c: Opening, 170: Transistor, 501: Pixel circuit, 502: Pixel portion, 504: Driving circuit portion, 504a: Gate driver, 504b: Source driver, 506: Protection circuit, 507: Terminal portion, 550: Transistor, 552: Transistor, 554: Transistor, 560: Capacitor, 562: Capacitor, 570: Liquid crystal element, 572: Light-emitting element, 700: Display device, 701: Substrate, 702: Pixel portion, 704: Source driver circuit portion, 705: Substrate, 706: Gate driver circuit portion, 708: FPC terminal portion, 710: Signal line, 711: Wiring portion , 712: sealant, 716: FPC, 730: insulating film, 732: sealing film, 734: insulating film, 736: coloring film, 738: light shielding film, 750: transistor, 752: transistor, 760: connecting electrode, 764: insulating film, 766: insulating film, 767: oxide semiconductor film, 768: insulating film, 770: planarizing insulating film, 772: conductive film, 774: conductive film, 775: liquid crystal element, 776: liquid crystal layer, 778: structure, 780: anisotropic conductive film, 782: light emitting element, 784: conductive film, 786: EL layer, 788: conductive film, 790: capacitor, 1280a: p-type transistor, 1280b: n-type transistor, 128 0c: n-type transistor, 1281: capacitor, 1282: transistor, 5100: particle, 5100a: particle, 5100b: particle, 5101: ion, 5102: zinc oxide layer, 5103: particle, 5105a: particle, 5105a1: region, 5105a2: particle, 5105b: particle, 5105c: particle, 5105d: particle, 5105d1: region, 5105e: particle, 5120: substrate, 5130: target, 5161: region, 8000: display module, 8001: upper cover, 8002: lower cover, 8003: FPC, 8004: touch panel, 8005: FPC, 8006: display panel, 8007: backlight,8008: light source, 8009: frame, 8010: printed circuit board, 8011: battery, 9000: housing, 9001: display unit, 9003: speaker, 9005: operation key, 9006: connection terminal, 9007: sensor, 9008: microphone, 9050: operation button, 9051: information, 9052: information, 9053: information, 9054: information, 9055: hinge, 9100: portable information terminal, 9101: portable information terminal, 9102: portable information terminal, 9200: portable information terminal, 9201: portable information terminal,

[0474] This application is based on Japanese Patent Application No. 2015-019938 accepted by the Japan Patent Office on February 4, 2015, the entire contents of which are hereby incorporated by reference.

Claims

1. A method for manufacturing a semiconductor device, include: forming an oxide semiconductor film at a first temperature; processing the oxide semiconductor film into an island shape; depositing materials to be source and drain electrodes on the oxide semiconductor film by a sputtering method; Processing the material to form the source electrode and the drain electrode; forming a protective insulating film on the oxide semiconductor film, the source electrode, and the drain electrode; heating the protective insulating film at a second temperature higher than the first temperature; forming a metal oxide film on the protective insulating film; as well as heating the protective insulating film at a third temperature higher than the first temperature, Wherein in the method, at least one of the second temperature and the third temperature is the highest.

2. The method for manufacturing a semiconductor device according to claim 1, wherein excess oxygen or oxygen radicals are added to the protective insulating film when the metal oxide film is formed, and When the protective insulating film is heated at the third temperature, the excess oxygen or the oxygen radicals diffuse into the oxide semiconductor film.

3. A method for manufacturing a semiconductor device, include: forming an oxide semiconductor film at a first temperature; processing the oxide semiconductor film into an island shape; depositing materials to be source and drain electrodes on the oxide semiconductor film by a sputtering method; Processing the material to form the source electrode and the drain electrode; forming a protective insulating film on the oxide semiconductor film, the source electrode, and the drain electrode; heating the protective insulating film at a second temperature higher than the first temperature; as well as forming a metal oxide film on the protective insulating film at a third temperature higher than the first temperature, Wherein in the method, at least one of the second temperature and the third temperature is the highest.

4. The method for manufacturing a semiconductor device according to claim 1 or 3, The metal oxide film is an aluminum oxide film, a hafnium oxide film or a yttrium oxide film.

5. The method for manufacturing a semiconductor device according to claim 1 or 3, wherein the oxide semiconductor film has a stacked structure including a first oxide semiconductor film having an atomic ratio of In:M:Zn=4:α1:α2 and a second oxide semiconductor film having an atomic ratio of In:M:Zn=1:β1:β2, wherein M is aluminum, gallium, yttrium or tin, Among them, α1 satisfies the relationship of 1.5≤α1≤2.5, Among them, α2 satisfies the relationship of 2.5≤α2≤3.5, where β1 satisfies the relationship 0.8≤β1≤1.2, and Among them, β2 satisfies the relationship of 0.8≤β2≤1.

2.

6. The method for manufacturing a semiconductor device according to claim 1 or 3, wherein the oxide semiconductor film includes a crystal portion, and The crystal part has c-axis orientation.

7. The method for manufacturing a semiconductor device according to claim 1 or 3, The first temperature is lower than 340°C.

8. The method for manufacturing a semiconductor device according to claim 1 or 3, The first temperature is higher than or equal to 100°C and lower than or equal to 200°C.

9. The method for manufacturing a semiconductor device according to claim 1 or 3, Wherein at least one of the second temperature and the third temperature is lower than 375°C.

10. The method for manufacturing a semiconductor device according to claim 1 or 3, At least one of the second temperature and the third temperature is higher than or equal to 340°C and lower than or equal to 360°C.

11. The method for manufacturing a semiconductor device according to claim 1 or 3, The protective insulating film has a stacked structure including a first protective insulating film and a second protective insulating film on the first protective insulating film.

12. The method for manufacturing a semiconductor device according to claim 1 or 3, wherein excess oxygen or oxygen radicals are added to the protective insulating film when the metal oxide film is formed, and When the metal oxide film is formed, the excess oxygen or the oxygen radicals in the protective insulating film diffuse into the oxide semiconductor film.

13. A method for manufacturing a semiconductor device, The following steps are involved: forming an oxide semiconductor film at a first temperature; processing the oxide semiconductor film into an island shape; Depositing the material that will become the source and drain electrodes by sputtering; Processing the material to form the source electrode and the drain electrode; forming a protective insulating film on the oxide semiconductor film, the source electrode, and the drain electrode; as well as forming a metal oxide film as a first barrier film on the protective insulating film by a sputtering method to add excess oxygen or oxygen radicals to the protective insulating film, Here, after processing the oxide semiconductor film and before depositing materials to be the source electrode and the drain electrode by sputtering, a process at a temperature higher than the first temperature is not performed.

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