Storage System and Method of Operating the Same

Abstract

A storage device, a storage system, and / or a method of operating the storage system, comprising: measuring, using a processing circuit, an erase programming interval (EPI) of a memory bank included in a non-volatile memory (NVM), the EPI being a time period from an erase time point of the memory bank to a programming time point; determining, using the processing circuit, a plurality of programming patterns based on the number of data bits stored in each storage cell of the memory bank; selecting, using the processing circuit, a programming pattern of the memory bank from the plurality of programming patterns based on the measured EPI of the memory bank; and performing, using the processing circuit, a programming operation on the memory bank corresponding to the selected programming pattern.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of priority to Korean Patent Application No. 10-2019-0105004, filed on Aug. 27, 2019, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Background Art

[0003] Various example embodiments of the inventive concept relate to a storage system, a storage device, and more particularly, to a storage system having improved threshold voltage distribution characteristics, a storage device having improved threshold voltage distribution characteristics, and / or a method of operating the same.

[0004] A storage system may include a memory controller and a storage device. The storage device may include a non-volatile storage device. As an example of a non-volatile memory (NVM) device, a flash memory device may be used in a portable phone, a digital camera, a personal digital assistant (PDA), a portable computer device, a fixed computer device, and other devices. The flash memory device may include a plurality of blocks, and each block may include a plurality of pages. In the flash memory device, a period of time from an erasure time point of a block until a programming time point of the block may be defined as an erase programming interval (EPI). Due to the characteristics of the flash memory device, when the EPI is long (e.g., has a long duration) during a data write operation, the threshold voltage distribution characteristics of the flash memory device may be degraded, and thus, the reliability of data stored on the flash memory device may be degraded. Summary of the Invention

[0005] According to an aspect of at least one example embodiment of the inventive concept, there is provided a method of operating a storage system including a non-volatile memory. The method includes: measuring, using a processing circuit, an erase programming interval (EPI) of a memory bank, the EPI being a period of time from an erasure time point of the memory bank to a programming time point, the memory bank being included in the non-volatile memory; determining, using the processing circuit, a plurality of programming patterns based on the number of bits of data stored in each storage cell of the memory bank; selecting, using the processing circuit, a programming pattern of the memory bank from the plurality of programming patterns based on the measured EPI of the memory bank; and performing, using the processing circuit, a programming operation on the memory bank corresponding to the selected programming pattern, performing the programming operation on the memory bank including adjusting at least one voltage level of the programming operation based on the selected programming pattern.

[0006] According to another aspect of at least one exemplary embodiment of the inventive concept, there is provided a method of operating a storage system including a non-volatile memory. The method includes: measuring, using a processing circuit, an erase programming interval (EPI) of a storage block of the non-volatile memory in response to a write request received from a host, the EPI being a time period from an erase time point of the storage block to a program time point; and performing a program operation on the storage block in a first program mode or a second program mode based on a duration of the EPI, using the processing circuit, the first program mode including writing N-bit data to each storage cell of the storage block, and the second program mode including writing M-bit data to each storage cell of the storage block, performing the program operation on the storage block including adjusting at least one voltage level of the program operation based on the first program mode or the second program mode. Here, N and M are positive integers, and M is less than N.

[0007] According to another aspect of at least one exemplary embodiment of the inventive concept, there is provided a storage system including: a non-volatile memory including a plurality of memory banks; and a memory controller configured to: measure an erase programming interval (EPI) of a first memory bank of the plurality of memory banks, the EPI being a time period from an erase time point of the memory bank to a program time point, determine a plurality of program modes based on a number of bits of data stored in each storage cell of the memory bank, select a program mode for the first memory bank from the plurality of program modes based on the measured EPI, and control a program operation to be performed on the first memory bank based on the selected program mode for the first memory bank, controlling the program operation including adjusting at least one voltage level associated with the program operation based on the selected program mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Various exemplary embodiments of the inventive concept will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0009] Figure 1 is a block diagram of a storage system according to at least one exemplary embodiment;

[0010] Figure 2 is a diagram illustrating an example of threshold voltage distribution characteristics due to Figure 1 an erase programming interval (EPI) of a non-volatile memory (NVM) according to at least one exemplary embodiment;

[0011] Figure 3 is a flowchart of a method of operating a storage system according to at least one exemplary embodiment;

[0012] Figures 4A to 4Dis an example diagram showing the distributions of threshold voltages of memory cells programmed to a single-level cell (SLC) mode, a multi-level cell (MLC) mode, a triple-level cell (TLC) mode, and a quad-level cell (QLC) mode, respectively, according to some example embodiments;

[0013] Figure 5 is according to at least one example embodiment Figure 1 of a memory controller;

[0014] Figure 6 is according to at least one example embodiment Figure 1 of a non-volatile memory (NVM);

[0015] Figure 7 shows an EPI table according to at least one example embodiment;

[0016] Figure 8 is a flowchart of a method for operating a storage system according to at least one example embodiment;

[0017] Figure 9 is according to at least one example embodiment in Figure 8 a conceptual diagram of a programming operation for a storage block in the operation method;

[0018] Figure 10 is a flowchart of a method for operating a storage system according to at least one example embodiment;

[0019] Figure 11 is according to at least one example embodiment in Figure 10 a conceptual diagram of a programming operation for a storage block in the operation method;

[0020] Figure 12 is a flowchart of a method for operating a storage system according to at least one example embodiment;

[0021] Figure 13 is according to at least one example embodiment in Figure 12 a conceptual diagram of a programming operation for a storage block in the operation method;

[0022] Figure 14 is a flowchart of a method for operating a storage system according to at least one example embodiment;

[0023] Figure 15 is according to at least one example embodiment in Figure 14 a conceptual diagram of a programming operation for a storage block in the operation method;

[0024] Figure 16A and Figure 16B shows a programming mode table according to some example embodiments;

[0025] Figure 17 shows a storage block configured to store EPI information according to at least one exemplary embodiment;

[0026] Figure 18A and Figure 18B respectively show an EPI table and a programming mode table according to some exemplary embodiments;

[0027] Figure 19 is a partial cross-sectional view of a storage block according to at least one exemplary embodiment;

[0028] Figure 20 is a conceptual diagram of a programming operation for a stack according to at least one exemplary embodiment;

[0029] Figure 21 is a conceptual diagram of a programming operation for a stack according to at least one exemplary embodiment;

[0030] Figure 22A and Figure 22B respectively show an EPI table and a programming mode table according to some exemplary embodiments;

[0031] Figure 23 is a conceptual diagram of a programming operation for a sub-block according to at least one exemplary embodiment;

[0032] Figure 24 is a conceptual diagram of a programming operation for a sub-block according to at least one exemplary embodiment;

[0033] Figure 25 is a flowchart of a data write operation between a host, a memory controller, and an NVM according to at least one exemplary embodiment;

[0034] Figure 26 is a flowchart of a data read operation between a host, a memory controller, and an NVM according to at least one exemplary embodiment;

[0035] Figure 27 is a flowchart of a garbage collection operation between a memory controller and an NVM according to at least one exemplary embodiment;

[0036] Figures 28 to 30 is according to some exemplary embodiments Figure 1 block diagram of a modified example of a storage system; and

[0037] Figure 31 is a block diagram of an example of applying a storage system according to at least one exemplary embodiment to a solid state drive (SSD) system. Detailed Description of Specific Embodiments

[0038] Hereinafter, various exemplary embodiments will be described in detail with reference to the accompanying drawings.

[0039] Figure 1 is a block diagram of a storage system 10 according to at least one exemplary embodiment.

[0040] Referring Figure 1 , the storage system 10 may include a memory controller 100 and / or a non-volatile memory (NVM) 200, etc., but the exemplary embodiment is not limited thereto, and more or fewer constituent elements may be included in the storage system 10. In at least one exemplary embodiment, the NVM 200 may be implemented as a storage chip, and the storage system 10 may include a plurality of storage chips, etc. In at least one exemplary embodiment, the memory controller 100 may be connected to a plurality of chips through a plurality of channels or a single channel, respectively. For example, the storage system 10 may be implemented as a storage device such as a solid state drive (SSD).

[0041] The memory controller 100 may control the NVM 200 to program data into the NVM 200, read data stored in the NVM 200, or erase data stored in the NVM 200 in response to a write / read request from the host HOST. For example, the memory controller 100 may provide a command CMD and an address ADDR to the NVM 200 and control the programming, reading, and erasing operations of the NVM 200. In addition, the data DATA to be programmed and the read data DATA may be sent and received between the memory controller 100 and the NVM 200. In at least one exemplary embodiment, the command CMD and the address ADDR may be sent from the memory controller 100 to the NVM 200 using the same input / output (I / O) channel as the data DATA. In at least one exemplary embodiment, the command CMD and the address ADDR may be sent from the memory controller 100 to the NVM 200 using a first I / O channel, while the data DATA may be sent from the memory controller 100 to the NVM 200 using a second I / O channel, but the exemplary embodiment is not limited thereto. In addition, the memory controller 100 may also provide a control signal CTRL to the NVM 200.

[0042] The NVM 200 may include, but is not limited to, a memory cell array 210 and / or a control circuit 220 (e.g., control logic, a controller, etc.). The memory cell array 210 may include a plurality of memory cells. For example, the plurality of memory cells may be flash memory cells. Hereinafter, example embodiments will be described in detail based on the assumption that the plurality of memory cells are NAND flash memory cells. However, the example embodiments of the inventive concept are not limited thereto, and the plurality of memory cells may be resistive memory cells such as resistive RAM (ReRAM) cells, phase change RAM (PRAM) cells, and / or magnetic RAM (MRAM), etc. The memory cell array 210 may include a plurality of blocks, and each block may include a plurality of pages. Each page may include a plurality of memory cells. In the memory cell array 210, a data erasure operation may be performed in units of blocks, and data write / read operations may be performed in units of pages, but they are not limited thereto.

[0043] The control circuit 220 may control the overall operation of the NVM 200 with respect to memory operations. The control circuit 220 may output various control signals for programming data into the memory cell array 210, reading data from the memory cell array 210, and / or erasing data stored in the memory cell array 210 based on a command CMD and an address ADD received from the memory controller 100. According to at least one example embodiment, the control circuit 220 may include: hardware including logic circuits; and a hardware / software combination (such as a processor executing software); or a combination thereof. For example, the control circuit may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc.

[0044] In a flash memory device, a period from a block erasure time point to a block programming time point may be defined as an erase program interval (EPI). Due to the characteristics of flash memory devices, especially vertical NAND (VNAND) flash memories including three-dimensional (3D) blocks, but not limited thereto, when the EPI is extended and / or prolonged, the reliability of data stored in the flash memory device may be reduced and / or decreased, etc. For example, during a period until another programming operation (e.g., a programming operation, a write operation, etc.) is performed after an erase operation, holes may diffuse into a space region between adjacent memory cells. When data is programmed in a state where the EPI is relatively long, electrons and holes may recombine after the programming operation is performed. Therefore, as described in detail with reference to Figure 2 the distribution of the threshold voltage of the memory cells may shift.

[0045] Figure 2 is an exemplary illustration of the fact that according to at least one example embodiment Figure 1 FIG. 2 is a graph of EPI-induced threshold voltage distribution characteristics of the NVM 200.

[0046] refer to Figure 2 , the abscissa represents the threshold voltage, and the ordinate represents the number of memory cells. In the first case 21, a programming operation (e.g., a programming operation, etc.) is performed immediately after erasing the block, that is, when the EPI is almost 0, the memory cell may have an erase state E and one of the first to nth programming states P1 to Pn according to (and / or based on) the threshold voltage. For example, the read voltage levels of the first programming state P1 and the second programming state P2 may be set to be desired, defined, and / or previously defined as Vr1 and Vr2, respectively.

[0047] In the second case 22, the program operation is performed during the first period after the erase block, that is, when the EPI is relatively short when compared to the first case 21, the distribution of the threshold voltage may generally shift to the left (or in the direction of decreasing the threshold voltage level). In the third case 23, the program operation is performed during the second period after the erase block, that is, when the EPI is relatively long when compared to the second case 22, the distribution of the threshold voltage may generally shift further to the left (or in the direction of decreasing the threshold voltage level). Here, the second period may be longer than the first period, but example embodiments are not limited thereto.

[0048] As described above, when data is programmed in a state where the EPI is relatively long (and / or longer than the expected or default EPI), the threshold voltage distribution characteristics may be degraded compared to a case where data is programmed in a state where the EPI is relatively short (and / or shorter than the expected or default EPI). In this case, when a read operation is performed on a memory cell using expected, defined, and / or previously defined read voltage levels Vr1, Vr2, ..., and Vrn, a read error may occur, and thus, the reliability of the data stored in the memory cell may be degraded and / or reduced. In addition, when a block detected as having a long EPI is not used to reduce and / or prevent reliability degradation due to the EPI, the storage space of the NVM 200 may not be effectively used, and may cause garbage collection operations to be frequently performed, expected, and / or required, and thus, the life of the NVM 200 may be shortened.

[0049] Return to reference Figure 1, To overcome the above disadvantages, the memory controller 100 may include an EPI checker circuit 110 and / or a programming mode control circuit 120, etc. The EPI checker circuit 110 may detect the EPI of the memory bank during an operation of writing data, such as user data or metadata, but is not limited thereto. For example, the EPI checker circuit 110 may detect the EPI of the memory bank during a garbage collection operation, a memory erase operation, etc. In addition, the memory bank may be a storage block, a storage stack, and / or a sub-storage block included in the memory cell array 210. However, the exemplary embodiments of the inventive concept are not limited thereto, and the EPI checker circuit 110 may detect the EPI of the memory bank in various cases where a programming operation for the memory bank is desired and / or required. According to at least one exemplary embodiment, the EPI checker circuit 110 may include: hardware including a logic circuit; and a hardware / software combination (such as a processor executing software); or a combination thereof. For example, the EPI checker circuit may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc.

[0050] The programming mode control circuit 120 may determine one of a plurality of programming modes as the programming mode of the memory bank based on the detected EPI. The plurality of programming modes may be set, defined, and / or predefined according to (and / or based on) the number of bits of data stored in each memory cell. For example, the plurality of programming modes may include at least one of a quad-level cell (QLC) mode, a triple-level cell (TLC) mode, a multi-level cell (MLC) mode, and a single-level cell (SLC) mode, etc., but is not limited thereto. The plurality of programming modes will be described below with reference to Figures 4A to 4D In addition, the programming mode control circuit 120 may control the programming operation for the memory bank in the determined programming mode. Thus, even when data is written into a memory bank having a long EPI, deterioration of data reliability may be reduced and / or prevented. According to at least one exemplary embodiment, the programming mode control circuit 120 may include: hardware including a logic circuit; and a hardware / software combination (such as a processor executing software); or a combination thereof. For example, the programming mode control circuit may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc. In addition, according to at least one exemplary embodiment, the EPI checker circuit 110 and the programming mode control circuit 120 may be implemented as and / or combined into a single circuit.

[0051] In some example embodiments, the storage system 10 may be an internal memory embedded in an electronic device. For example, the storage system 10 may be an SSD, an embedded universal flash storage (UFS) device, and / or an embedded multimedia card (eMMC), etc., but is not limited thereto. In some example embodiments, the storage system 10 is an external memory detachably attached to the electronic device. For example, the storage system 10 may include a UFS memory card, a compact flash (CF) memory, a secure digital (SD) memory, a micro SD memory, a mini SD memory, an extreme digital (xD) memory, and / or a memory stick, etc.

[0052] The storage system 10 and the host HOST may form a storage system, but the example embodiments are not limited thereto. The storage system may be implemented as, for example, a personal computer (PC), a data server, a network-coupled storage, an Internet of Things (IoT) device, and / or a portable electronic device, etc. The portable electronic device may be a laptop computer, a mobile phone, a smartphone, a tablet computer, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, a digital video camera, an audio device, a portable multimedia player (PMP), a personal navigation device (PND), an MPEG-1 audio layer 3 (MP3) player, a handheld game console, an e-book, a virtual reality device, an augmented reality device, an autonomous vehicle, and / or a wearable device, etc.

[0053] Figure 3 is a flowchart of a method of operating a storage system according to at least one example embodiment. Refer to Figure 3 , the operation method according to the present example embodiment may be a method of programming a storage system to improve threshold voltage distribution characteristics. For example, the operation method according to the present example embodiment may include operations performed in chronological order in the Figure 1 storage system 10.

[0054] In operation S110, the memory controller 100 may detect the EPI of the memory bank. For example, the EPI checker circuit 110 may include a timer (not shown), which may detect the time period (e.g., duration) from the time point when an erase operation or other operation is performed on the memory bank to the time point when a program operation is performed on the memory bank, as the EPI of the memory bank. In operation S120, the memory controller 100 may determine a program mode as one of a plurality of program modes based on the detected EPI, including, for example, a QLC mode, a TLC mode, an MLC mode, and / or an SLC mode, etc. For example, the program mode control circuit 120 may compare the detected EPI with a desired and / or (previously) defined reference time and select one of the plurality of program modes. In other words, the program mode may be selected based on the detected EPI and the desired reference time. In operation S130, the memory controller 100 may perform a program operation on the memory bank in the determined program mode, including adjusting at least one voltage level associated with the program operation (e.g., adjusting one or more write voltages associated with a write operation) based on the determined program mode.

[0055] Figures 4A to 4D is an example of a graph showing the distribution of threshold voltages of memory cells programmed to the SLC mode, the MLC mode, the TLC mode, and the QLC mode, respectively. However, the example embodiments are not limited thereto, and for example, the memory cells may operate in other NAND / flash memory programming modes. In Figures 4A to 4D the abscissa represents the threshold voltage, and the ordinate represents the number of memory cells.

[0056] Referring to Figure 4A , the single-level cell (SLC) mode may be a program mode in which 1 bit of data is stored in each memory cell, and each memory cell may be programmed to the SLC mode in which the memory cell may have one of two states depending on (e.g., based on) the distribution of the threshold voltage. For example, a memory cell configured to store the data "1" may be in the erased state E, and a memory cell configured to store the data "0" may be in the programmed state P. However, the example embodiments are not limited thereto, and the data values may correspond to other program modes.

[0057] Referring to Figure 4B, the multi-level cell (MLC) mode can be a programming mode in which 2 bits of data are stored in each memory cell, and each memory cell can be programmed to an MLC mode in which the memory cell can have one of four states depending on the distribution of threshold voltages. For example, a memory cell configured to store the data "11" can be in an erased state E, and memory cells configured to store the data "10", "01", and "00" can be in the first to third programming states P1 to P3, respectively. However, the example embodiments are not limited thereto, and the data values can correspond to other programming modes.

[0058] Referring to Figure 4C , the triple-level cell (TLC) mode can be a programming mode in which 3 bits of data are stored in each memory cell, and each memory cell can be programmed to a TLC mode in which the memory cell can have one of eight states depending on the distribution of threshold voltages. For example, a memory cell configured to store the data "111" can be in an erased state E, and memory cells configured to store the data "110", "101", "100", "011", "010", "001", and "000" can be in the first to seventh programming states P1 to P7, respectively. However, the example embodiments are not limited thereto, and the data values can correspond to other programming modes.

[0059] Referring to Figure 4D , the quad-level cell (QLC) mode can be a programming mode in which 4 bits of data are stored in each memory cell, and each memory cell can be programmed to a QLC mode in which the memory cell can have one of sixteen states depending on the distribution of threshold voltages. For example, a memory cell configured to store the data "1111" can be in an erased state E, and memory cells configured to store the data "1110", "1101", "1100", "1011", "1010", "1001", "1000", "0111", "0110", "0101", "0100", "0011", "0010", "0001", and "0000" can be in the first to fifteenth programming states P1 to P15. However, the example embodiments are not limited thereto, and the data values can correspond to other programming modes.

[0060] Referring to Figures 4A to 4D, the interval between two adjacent states (i.e., two valleys) can be defined as "valley margin". In a memory cell programmed in SLC mode, there can be a first valley margin VM1 between the erase state E and the programmed state P. In a memory cell programmed in MLC mode, there can be a second valley margin VM2 smaller than the first valley margin VM1 between the first programmed state P1 and the second programmed state P2, but not limited thereto. In a memory cell programmed in TLC mode, there can be a third valley margin VM3 smaller than the second valley margin VM2 between the first programmed state P1 and the second programmed state P2, but not limited thereto. In a memory cell programmed in QLC mode, there can be a fourth valley margin VM4 smaller than the third valley margin VM3 between the first programmed state P1 and the second programmed state P2, but not limited thereto. As described above, according to at least one example embodiment, the valley margin can gradually decrease from SLC mode to QLC mode. However, the exemplary embodiment is not limited thereto. For example, the valley margin can be equal to or greater than the previous valley margin.

[0061] As referred to above Figure 2 As described, according to at least one example embodiment, the distribution of the threshold voltage of the memory cell programmed due to EPI can shift to the left, or in other words, the distribution of the threshold voltage is reduced and / or adjusted based on EPI. Therefore, a programming operation can be performed on a block with short EPI in a programming mode (e.g., QLC mode, etc.) having a relatively small valley margin compared to the valley margins of other programming modes, while a programming operation can be performed on a block with long EPI in a programming mode (e.g., SLC mode, etc.) having a relatively large valley margin compared to the valley margins of other programming modes. This will be described below with reference to Figures 8 to 13 this.

[0062] Figure 5 is an example of Figure 1 the memory controller 100 according to at least one example embodiment.

[0063] Referring to Figure 5 , the memory controller 100a can include an EPI checker circuit 110, a programming mode control circuit 120, a processing circuit 130, a host interface 140, a buffer 150, and / or an NVM interface 160, etc., but not limited thereto. Additionally, the memory controller 100a can further include a bus 170, and the components of the memory controller 100a can communicate with each other through the bus 170. Referring to Figures 1 to 5 the above description presented can be applied to one or more other example embodiments, and its repeated description will be omitted. However, the example embodiment is not limited thereto, and the example embodiment can have other components in addition to Figure 1 and Figure 5Alternative hardware structures other than the hardware structure of

[0064] The EPI checker circuit 110 may include at least one timer and detect the EPI of each memory bank included in the memory cell array 210 of the NVM 200. In at least one example embodiment, at least one timer included in the EPI checker circuit 110 may be shared among multiple memory banks. In at least one example embodiment, the EPI checker circuit 110 may include timers corresponding to multiple memory banks, respectively. However, the inventive concept is not limited thereto, and the EPI checker circuit 110 may be defined to include various other circuits, components, and / or computer-readable instructions capable of measuring time. For example, when the EPI checker circuit 110 measures time based on counting the periods of clock signals generated by a clock generator (not shown), the EPI checker circuit 110 may also include a counter, etc.

[0065] The programming mode control circuit 120 may determine the programming mode of the memory bank as one of multiple programming modes, including at least one of a QLC mode, a TLC mode, an MLC mode, and an SLC mode, based on the detection result of the EPI checker circuit 110. In at least one example embodiment, the programming mode control circuit 120 may be implemented as software or firmware (e.g., computer-readable instructions, etc.), loaded into the memory of the memory controller 100a, and executed by the processing circuit 130. In at least one example embodiment, the programming mode control circuit 120 may be implemented as hardware.

[0066] The processing circuit 130 may include a central processing unit (CPU), a microprocessor (MP), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on chip (SoC), a programmable logic unit, an application specific integrated circuit (ASIC), etc., and / or may be a hardwired circuit including logic circuits, or a combination thereof, but the example embodiments are not limited thereto. The processing circuit 130 may control the overall operation of the memory controller 100a. In at least one example embodiment, the processing circuit 130 may be implemented as a multi-core processor, e.g., a dual-core processor, a quad-core processor, etc. According to at least one example embodiment, the processing circuit 130 may include, replace, and / or execute at least one of the functions of the EPI checker circuit 110 and the programming mode control circuit 120.

[0067] The host interface 140 can provide a physical connection between a host (e.g., an external device, a computing device, etc.) and the memory controller 100. For example, the host interface 140 can include various interface methods such as Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI), PCI Express (PCI-E), IEEE 1394, Universal Serial Bus (USB), Secure Digital (SD) card, Multimedia Card (MMC), Embedded Multimedia Card (eMMC), and / or Compact Flash (CF) card interface, but is not limited thereto.

[0068] The NVM interface 160 can provide a physical connection between the memory controller 100 and the NVM 200. For example, signals such as commands CMD, addresses ADDR, and / or data DATA can be sent and / or received between the memory controller 100 and the NVM 200 through the NVM interface 160. Data requested to be written from the host and data read from the NVM 200 can be temporarily stored in the buffer 150.

[0069] Figure 6 is according to at least one example embodiment Figure 1 a block diagram of an example of the NVM 200.

[0070] Referring to Figure 6 , the NVM 200a can include a memory cell array 210, a control circuit 220, a voltage generator 230, a row decoder 240, and / or a page buffer 250. Although not shown in Figure 6 , the NVM 200a can also include various other components related to the memory operation(s), such as a data I / O circuit, an I / O interface, etc.

[0071] The memory cell array 210 can include a plurality of blocks BLK1 to BLKz, and the memory cells of the blocks BLK1 to BLKz can be connected to word lines WL, string selection lines SSL, ground selection lines GSL, and / or bit lines BL, etc. The memory cell array 210 can be connected to the row decoder 240 through word lines WL, string selection lines SSL, and / or ground selection lines GSL, etc., and can be connected to the page buffer 250 through bit lines BL. Each memory cell can store at least one bit. In at least one example embodiment, each memory cell can correspond to SLC, MLC, TLC, or QLC.

[0072] In at least one example embodiment, the memory cell array 210 may include a two-dimensional (2D) memory cell array including a plurality of cell strings arranged in a row direction and a column direction. However, the example embodiment is not limited thereto, and for example, the memory cell array may have other arrangements, such as a three-dimensional (3D) memory cell array including a plurality of cell strings, etc. Each cell string may include memory cells stacked on a substrate in a vertical direction, for example, respectively connected to word lines. The following patent documents incorporated herein by reference disclose suitable configurations of 3D memory cell arrays, where the 3D memory cell arrays are configured in multiple levels and word lines and / or bit lines are shared between levels: U.S. Patent No. 7,679,133; No. 8,553,466; No. 8,654,587; No. 8,559,235; and U.S. Patent Publication 2011 / 0233648.

[0073] The control circuit 220 may output various internal control signals based on signals such as a command CMD, an address ADDR, and / or a control CTRL received from the memory controller 100 for programming data into the memory cell array 210 or reading data from the memory cell array 210. For example, the control circuit 220 may output a voltage control signal CTRL_vol to control the levels of various voltages generated by the voltage generator 230, provide a row address X-ADDR to the row decoder 240, and provide a column address Y-ADDR to the page buffer 250, etc.

[0074] The voltage generator 230 may generate various types of voltages for performing programming, reading, and / or erasing operations, etc. on the memory cell array 210 based on the voltage control signal CTRL_vol. For example, the voltage generator 230 may generate a word line voltage VWL, such as a programming voltage, a reading voltage, and a programming verification voltage, etc. In response to the row address X-ADDR, the row decoder 240 may select one of the plurality of word lines WL and one of the plurality of string selection lines SSL. The page buffer 250 may select some of the bit lines BL in response to the column address Y-ADDR. For example, depending on the operation mode, etc., the page buffer 250 may operate as a write driver and / or a sense amplifier.

[0075] In at least one example embodiment, the control circuit 220 may generate a voltage control signal CTRL_vol for performing a programming operation on a memory bank according to and / or based on a programming mode corresponding to the memory bank. For example, when the programming mode is the MLC mode, as Figure 4B shown, the control circuit 220 may generate a voltage control signal CTRL_vol for generating a programming voltage and a programming verification voltage such that the memory cell is programmed to one of, for example, the first to third programming states P1 to P3, but is not limited thereto. For example, when the programming mode is the QLC mode, asFigure 4D As shown, the control circuit 220 may generate a voltage control signal CTRL_vol for generating a programming voltage and a programming verification voltage, such that the memory cell is programmed to one of the first to fifteenth programming states P1 to P15, and so on.

[0076] In at least one exemplary embodiment, the control circuit 220 may generate a voltage control signal CTRL_vol for performing a read operation on the memory bank according to and / or based on a programming pattern corresponding to the memory bank. For example, when the programming pattern is the TLC pattern, as Figure 4C shown, the control circuit 220 may generate a voltage control signal CTRL_vol corresponding to a read voltage for reading the first to seventh programming states P1 to P7, but the exemplary embodiment is not limited thereto. For example, when the programming pattern is the QLC pattern, as Figure 4D shown, the control circuit 220 may generate a voltage control signal CTRL_vol corresponding to a read voltage for reading the first to fifteenth programming states P1 to P15, and so on.

[0077] Figure 7 Shows an EPI table ET1 according to at least one exemplary embodiment.

[0078] Referring to Figure 7 , the EPI table ET1 may store EPI information corresponding to each of a plurality of memory blocks. Hereinafter, for the sake of brevity, the memory block is referred to as a block. For example, the EPI information about the first block BLK1 may be stored as t1, and the EPI information about the second block BLK2 may be stored as t2, and so on. In at least one exemplary embodiment, the EPI table ET1 may be stored in the metadata area of the NVM 200, but is not limited thereto, and the memory cell may be stored in other storage areas and / or storage devices. In at least one exemplary embodiment, the EPI table ET1 may be stored in the dynamic random access memory (DRAM) of the storage system 10. In at least one exemplary embodiment, the EPI table ET1 may be stored in the static RAM of the storage system 10. Hereinafter, at least one exemplary embodiment of managing the EPI information for each block will be mainly described with reference to Figures 8 to 1 6.

[0079] Figure 8 Is a flowchart of a method of operating a storage system according to at least one exemplary embodiment. Figure 9 Is according to at least one exemplary embodiment in Figure 8 The conceptual diagram of the programming operation for the memory block in the operation method of.

[0080] Referring to Figure 1 , Figure 8 And Figure 9, in operation S200, the storage system 10 can detect the EPI of the storage block. For example, when a data write request for the first block BLK1 is received, the storage system 10 can detect the EPI of the first block BLK1. In operation S210, the storage system 10 can determine whether the detected EPI is equal to or shorter than the reference time tREF. If it is determined that the detected EPI is equal to or shorter than the reference time tREF, operation S240 can be executed; otherwise, operation S250 can be executed. In other words, the storage system 10 can determine whether to execute operation S240 based on the length of the detected EPI.

[0081] When the detected EPI is equal to or shorter than the reference time tREF, in operation S240, the storage system 10 can perform a programming operation in a first programming mode in which N bits of data are written into a storage cell (N is a positive integer). For example, N can be 4, and the first programming mode can be the QLC mode, but the example embodiment is not limited thereto. For example, when the EPI of the first block BLK1 is equal to or shorter than the reference time tREF, the storage system 10 can perform a programming operation on some pages of the first block BLK1 in the QLC mode, and so on.

[0082] Otherwise, if the detected EPI exceeds the reference time tREF, in operation S250, the storage system 10 can perform a programming operation in a second programming mode in which M bits of data are written into a storage cell (M is a positive integer less than N). For example, M can be 3, and the second programming mode can be the TLC mode, but the example embodiment is not limited thereto. For example, when the EPI of the first block BLK1 exceeds the reference time tREF, the storage system 10 can perform a programming operation on some pages of the remaining pages of the first block BLK1 in the TLC mode, and so on.

[0083] In at least one example embodiment, after the programming operation on some pages of the first block BLK1 in the QLC mode, a write request for the first block BLK1 can be requested again after a desired and / or predetermined time has elapsed. Therefore, the EPI of the first block BLK1 can be detected again, and the EPI may exceed the reference time tREF at the time point of detecting the EPI of the first block BLK1 again. In this case, a programming operation can be performed on some pages of the remaining pages of the first block BLK1 in the TLC mode.

[0084] Figure 10 is a flowchart of a method for operating the storage system 10 according to at least one example embodiment.

[0085] Figure 11 is according to at least one example embodiment in Figure 10 the operation method for a conceptual diagram of the programming operation for a storage block.

[0086] Reference Figure 1 , Figure 10 and Figure 11 , the operation method according to the exemplary embodiment may correspond to Figure 8 a modified example of the operation method shown, and its repeated description will be omitted. In operation S210a, the storage system 10 may determine whether the detected EPI is equal to or shorter than a first reference time tREF1. For example, the first reference time tREF1 may be about 25 minutes, but is not limited thereto, and the reference time may be set to any desired time. If it is determined that the detected EPI exceeds the first reference time tREF1, then in operation S220, the storage system 10 may determine whether the detected EPI is equal to or shorter than a second reference time tREF2. For example, the second reference time tREF2 may be three hours or the like. If it is determined that the detected EPI is equal to or shorter than the second reference time tREF2, operation S250 may be performed; otherwise, operation S260 may be performed.

[0087] In operation S250, the storage system 10 may perform a programming operation in a second programming mode in which M-bit data is written to a storage cell. In operation S260, the storage system 10 may perform a programming operation in a third programming mode in which L-bit data is written to a storage cell. (Here, L is a positive integer less than M). For example, L may be 2, and the third programming mode may be the MLC mode, but the exemplary embodiment is not limited thereto. For example, when the EPI of the first block BLK1 exceeds the second reference time tREF2, a programming operation may be performed on some of the remaining pages of the first block BLK1 in the MLC mode, and so on.

[0088] Figure 12 is a flowchart of a method for operating a storage system according to at least one exemplary embodiment. Figure 13 is according to at least one exemplary embodiment in Figure 12 the operation method of a conceptual diagram for the programming operation of a storage block.

[0089] Reference Figure 1 , Figure 12 and Figure 13 , according to Figure 1 , Figure 12 and Figure 13 the operation method of the exemplary embodiment may correspond to Figure 10Modified example embodiments of the operation method shown will omit their repeated description. In operation S220, the storage system 10 may determine whether the detected EPI is equal to or shorter than a second reference time tREF2. If it is determined that the detected EPI exceeds the second reference time tREF2, then in operation S230, the storage system 10 may determine whether the detected EPI is equal to or shorter than a third reference time tREF3. For example, the third reference time tREF3 may be 24 hours, but is not limited thereto. If it is determined that the detected EPI is equal to or shorter than the third reference time tREF3, operation S260 may be performed; otherwise, operation S270 may be performed.

[0090] In operation S260, the storage system 10 may perform a programming operation in a third programming mode in which L-bit data is written to a storage cell. In operation S270, the storage system 10 may perform a programming operation in a fourth programming mode in which K-bit data is written to a storage cell (K is a positive integer less than L). For example, K may be 1, and the fourth programming mode may be the SLC mode, but the example embodiments are not limited thereto. For example, when the EPI of the first block BLK1 exceeds the third reference time tREF3, the storage system 10 may perform a programming operation on some of the remaining pages of the first block BLK1 in the SLC mode, but the example embodiments are not limited thereto.

[0091] Figure 14 is a flowchart of a method for operating a storage system according to at least one example embodiment. Figure 15 is according to at least one example embodiment in Figure 14 the operation method for the programming operation of a storage block.

[0092] Referring to Figure 1 、 Figure 14 and Figure 15 , the operation method according to at least one example embodiment may correspond to Figure 8 a modified example of the operation method shown, and referring to Figure 8 and Figure 9 the descriptions presented may also be applied to the current example embodiment. For example, compared with the operation method of Figure 8 , according to Figure 1 、 Figure 14 and Figure 15 the operation method may further include operations S280 and S290. However, the example embodiments of the inventive concept are not limited thereto. In some example embodiments, compared with the operation method of Figure 10 or Figure 12 , the operation method may further include operations S280 and S290, and so on.

[0093] In operation S290, the storage system 10 may perform a programming operation in a default programming mode. For example, after a sudden power outage (SPO) event occurs during the programming operation of the first block BLK1, when power is restored again, the programming operation may be performed on some of the remaining pages of the first block BLK1 in the default programming mode (e.g., SLC mode, etc.).

[0094] Due to the occurrence of SPO, the timer for detecting the EPI of the memory bank may be reset and / or the information indicating the erasure time point of the memory bank may be deleted. For these reasons, the accuracy of the EPI information of the storage device may be reduced. Therefore, when performing a programming operation on the memory bank after SPO occurs, it may be assumed that a large amount of time has elapsed since the erasure time point of the corresponding storage block, and the programming operation may be performed on the corresponding storage block in the default programming mode. For example, the default programming mode may be an SLC mode or an MLC mode with a relatively large valley margin, but the example embodiments are not limited thereto.

[0095] Figure 16A and Figure 16B show a programming mode table PMT1 and PMT1' according to some example embodiments.

[0096] Referring to Figure 16A , the programming mode table PMT1 may store programming modes corresponding to a plurality of logical page numbers (LPNs) respectively. In some example embodiments, the programming mode table PMT1 may store the programming mode for each LPN group that describes the start LPN and the end LPN. For example, the programming mode for the first LPN LPN1 may be determined as the QLC mode, and the programming mode for the second LPN LPN2 may be determined as the MLC mode, but the example embodiments are not limited thereto.

[0097] Referring to Figure 16B , the programming mode table PMT1' may store programming modes corresponding to a plurality of physical page numbers (PPNs) respectively. In some example embodiments, the programming mode table PMT1' may store the programming mode for each PPN group that describes the start PPN and the end PPN. For example, the programming mode for the first PPN PPN1 may be determined as the QLC mode, and the programming mode for the second PPN PPN2 may be determined as the MLC mode, but the example embodiments are not limited thereto.

[0098] Referring to Figure 1 , Figure 16A and Figure 16B, after determining the programming mode based on EPI or after performing a programming operation on the NVM 200 in the determined programming mode, the memory controller 100 may update the programming mode tables PMT1 and / or PMT2. In at least one example embodiment, the memory controller 100 may store the programming mode tables PMT1 and / or PMT2 in the meta region of the NVM 200. In at least one example embodiment, the memory controller 100 may store the programming mode tables PMT1 and / or PMT2 in the memory of the memory controller 100 (e.g., SRAM) and / or the memory of the storage system 10 (e.g., DRAM), etc.

[0099] Figure 17 Shows a storage block BLKz configured to store EPI information according to at least one example embodiment.

[0100] Refer to Figure 17 , the EPI information and / or programming mode information regarding the first to third pages page1 to page3 of the block BLKz may be stored in the meta region related to the first to third pages page1 to page3 of the block BLKz, but the example embodiments are not limited thereto. In addition, the EPI information and / or programming mode information regarding the other pages page(k - 1) to page(k) of the block BLKz may be stored in the meta region related to the pages page(k - 1) to page(k) of the block BLKz, but the example embodiments are not limited thereto.

[0101] As a first example, when receiving a data write request, the memory controller 100 may read the EPI information stored in the meta region of the block BLKz and determine the programming mode of the block BLKz based on the read EPI information, etc. As a second example, when receiving a data read request, the memory controller 100 may read the programming mode information stored in the meta region of the block BLKz and adjust the read conditions (e.g., one or more read voltage levels) of the block BLKz based on the read programming mode information, etc.

[0102] Figure 18A and Figure 18B Show the EPI table ET2 and the programming mode table PMT2 according to some example embodiments, respectively.

[0103] Refer to Figure 18A , the EPI table ET2 may store the EPI information corresponding to each of the multiple memory stacks. Hereinafter, for simplicity, the sub - memory stack is referred to as a stack. For example, the EPI information of the first stack STK1 may be stored as t1', and the EPI information of the second stack STK2 may be stored as t2', etc.

[0104] Refer to Figure 18B, the programming mode table PMT2 can store programming modes corresponding to multiple stacks respectively. In some example embodiments, the programming mode table PMT2 can store the programming modes of each stack group that describes the start stack and the end stack. For example, the programming mode of the first stack STK1 can be determined as the QLC mode, and the programming mode of the second stack STK2 can be determined as the MLC mode, but the example embodiments are not limited thereto. Hereinafter, reference will be made to Figure 19 to describe the structure and definition of the stack.

[0105] Figure 19 is a partial cross-sectional view of the memory block BLK according to at least one example embodiment.

[0106] Referring to Figure 19 , in a vertical memory device according to at least one example embodiment, an etching process for forming a channel hole can be performed to form a channel structure in the memory block BLK having a 3D structure, and the diameter of the channel hole can vary according to the height of the memory block BLK. However, the example embodiments are not limited thereto. For example, from the upper part to the lower part of the memory block BLK having a 3D structure, the diameter of the channel hole can be reduced. In order to reduce the diameter of the channel hole and / or prevent the diameter of the channel hole from being reduced more than expected and / or being overly reduced in the memory block BLK having a 3D structure, the etching process for forming the channel hole can be performed at least twice. Specifically, after forming the first stack STK1 (i.e., the first stack structure) on the substrate, the etching process can be performed, and the second stack STK2 (i.e., the second stack structure) can be formed on the first stack SK1. In addition, the etching process etc. can be performed on the second stack STK2.

[0107] In at least one example embodiment, in the memory block BLK having a 3D structure, the first stack STK1 can include gate electrodes 310 and / or insulating films 320 etc. alternately arranged in the vertical direction, but the embodiments are not limited thereto. In addition, the second stack STK2 stacked on the first stack STK1 can include gate electrodes 340 and / or insulating films 350 etc. alternately arranged in the vertical direction, but the example embodiments are not limited thereto. According to at least one example embodiment, the inter-stack layer 330 can be located between the first stack STK1 and the second stack STK2. In addition, the channel structure 360 can include a channel 362, a dielectric film structure 363 surrounding the outer sidewall of the channel 362, and / or a channel buried film pattern 361 located inside the channel 362 etc. The above structures can be only at least one example embodiment, and the memory block BLK having a 3D structure according to one or more example embodiments can have various other structures in which the etching process is performed at least twice.

[0108] Figure 20It is a conceptual diagram for a programming operation of a stack according to at least one exemplary embodiment.

[0109] Referring to Figure 1 and Figures 18A to 20 , the memory bank may correspond to a stack, and the storage system 10 may manage the EPI in units of stacks and determine the programming mode. For example, the block BLK may include at least a first stack STK1 and a second stack STK2 stacked on a substrate in a vertical direction, but the exemplary embodiment is not limited thereto. For example, the first stack STK1 and the second stack STK2 may respectively have Figure 19 the simplified structures of the first stack STK1 and the second stack STK2 shown. Figures 8 to 15 The operation method shown may be applied to this exemplary embodiment.

[0110] In at least one exemplary embodiment, when a data write request to the block BLK is received, the storage system 10 may detect a first EPI t1' of the first stack STK1 based on the EPI table ET2. Thereafter, the storage system 10 may determine whether the detected first EPI t1' is equal to or shorter than a first reference time (e.g., Figure 12 tREF1). If it is determined that the detected first EPI t1' is equal to or shorter than the first reference time tREF1, the storage system 10 may perform a programming operation on the first stack STK1 in a first programming mode in which N-bit data is written into the storage cells. For example, N may be 4, and the first programming mode may be a QLC mode, but the exemplary embodiment is not limited thereto.

[0111] In at least one exemplary embodiment, the storage system 10 may detect a second EPI t2' of the second stack STK2 based on the EPI table ET2. Thereafter, the storage system 10 may compare the detected second EPI t2' with first to third reference times (e.g., Figure 12 tREF1, tREF2, and tREF3), but the exemplary embodiment is not limited thereto. When the detected second EPI t2' exceeds the second reference time tREF2, the storage system 10 may perform a programming operation on the second stack STK2 in a third programming mode in which L-bit data is written into the storage cells. For example, L may be 2, and the third programming mode may be an MLC mode, but the exemplary embodiment is not limited thereto.

[0112] Figure 21 It is a conceptual diagram for a programming operation of a stack according to at least one exemplary embodiment.

[0113] Referring to Figure 1 and Figure 21 , according to Figure 1 and Figure 21 the programming operation may correspond to Figure 20Example embodiments of modifications to the programming operations shown. In at least one example embodiment, when the first EPI t1' for the first stack STK1 is equal to or shorter than a first reference time (e.g., Figure 12 tREF1 of

[0114] ), the storage system 10 may perform a programming operation on some pages of the first stack STK1 in, for example, the QLC mode, but the example embodiments are not limited thereto. After performing a programming operation on some pages of the first stack STK1, when the first EPI t1' exceeds the first reference time tREF1, the storage system 10 may perform a dummy programming operation of writing dummy data on the remaining pages of the first stack STK1, but the example embodiments are not limited thereto. As described above, only one programming mode may be applied to one stack instead of multiple programming modes.

[0115] Figure 22A And Figure 22B respectively show an EPI table ET3 and a programming mode table PMT3 according to some example embodiments.

[0116] Referring to Figure 22A , the EPI table ET3 may store EPI information corresponding to each of a plurality of sub-storage blocks. Hereinafter, for simplicity, the sub-storage blocks are referred to as sub-blocks. For example, the EPI information about the first sub-block SBLK1 may be stored as t1", and the EPI information about the second sub-block SBLK2 may be stored as t2".

[0117] Referring to Figure 22B , the programming mode table PMT3 may store programming modes corresponding to a plurality of sub-blocks, respectively. In some example embodiments, the programming mode table PMT3 may store the programming mode for each sub-block group that describes the start sub-block and the end sub-block. For example, the programming mode of the first sub-block SBLK1 may be determined as the QLC mode, and the programming mode of the second sub-block SBLK2 may be determined as the MLC mode, but the example embodiments are not limited thereto. Hereinafter, at least one example embodiment of managing EPI information for each sub-block will be mainly described with reference to Figure 23 And Figure 24 .

[0118] Figure 23It is a conceptual diagram for the programming operation of sub - blocks according to at least one example embodiment.

[0119] Referring to Figure 1 and Figures 22A to 23 , the memory bank can correspond to a sub - block, and the storage system 10 can manage the EPI in units of sub - blocks and determine the programming mode. Here, the sub - block can be an independently erasable unit and can be referred to as a partial block. For example, the block BLK' can include at least a first sub - block SBLK1 and a second sub - block SBLK2, but is not limited thereto.

[0120] The first sub - block SBLK1 can include word lines WL0 to WLi, and the second sub - block SBLK2 can include word lines WLi + 1 to WLm. When the size of the block BLK' increases, the block BLK' can be divided into multiple sub - blocks including the first sub - block SBLK1 and the second sub - block SBLK2, etc., to facilitate the management of the block. In this case, an erase operation can be performed on each sub - block, and the storage block BLK' can be the desired and / or maximum storage unit that can be erased simultaneously.

[0121] In at least one example embodiment, when a data write request to the block BLK' is received, the storage system 10 can detect the first EPI t1" of the first sub - block SBLK1 based on the EPI table ET3. Thereafter, the storage system 10 can determine whether the detected first EPI t1" is equal to or shorter than a first reference time (e.g., Figure 12 tREF1, etc.). If it is determined that the detected first EPI t1" is equal to or shorter than the first reference time tREF1, the storage system 10 can perform a programming operation on the first sub - block SBLK1 in a first programming mode in which N - bit data is written into the storage unit. For example, N can be 4, and the first programming mode can be the QLC mode, but the example embodiment is not limited thereto.

[0122] In at least one example embodiment, the storage system 10 can detect the second EPI t2" of the second sub - block SBLK2 based on the EPI table ET3. Thereafter, the storage system 10 can compare the detected second EPI t2" with the first to third reference times (e.g., Figure 12 tREF1, tREF2, and tREF3, etc.). When the detected second EPI t2" exceeds the second reference time tREF2, the storage system 10 can perform a programming operation on the second sub - block SBLK2 in a third programming mode in which L - bit data is written into the storage unit. For example, L can be 2, and the third programming mode can be the MLC mode, but the example embodiment is not limited thereto.

[0123] Figure 24It is a conceptual diagram of a programming operation for a sub-block according to at least one example embodiment.

[0124] Referring to Figure 1 and Figure 24 , according to Figure 1 and Figure 24 , the programming operation can correspond to a modified example of the programming operation shown in Figure 23 . In at least one example embodiment, when the first EPI t1' of the first sub-block SBLK1 is equal to or shorter than the first reference time (e.g., Figure 12 's tREF1), the storage system 10 can perform a programming operation on some pages of the first sub-block SBLK1 in, for example, the QLC mode, but the example embodiment is not limited thereto. After performing a programming operation on some pages of the first sub-block SBLK1, when the first EPI t1' exceeds the first reference time tREF1, the storage system 10 can perform a dummy operation of writing dummy data on the remaining pages of the first sub-block SBLK1, but the example embodiment is not limited thereto. As described above, only one programming mode can be applied to a sub-block instead of multiple programming modes.

[0125] In addition, according to some example embodiments, when the EPI corresponding to the first sub-block SBLK1 exceeds the first reference time tREF1 during the programming operation of the first sub-block SBLK1, the programming mode of the second sub-block SBLK2 can be determined to be at least one of the QLC mode, TLC mode, MLC mode, SLC mode, etc. In this case, a dummy programming operation of writing dummy data is not performed on the second sub-block SBLK2. Therefore, a programming operation can be effectively performed on each sub-block, and a sub-block is a unit smaller than a storage block.

[0126] Figure 25 It is a flowchart of a data writing operation between the host 400, the memory controller 100, and / or the NVM 200, etc. according to at least one example embodiment.

[0127] Referring to Figure 25 , in operation S310, the host 400 can issue a data writing request. In operation S320, the host 400 can send the data writing request and the address ADDR to the memory controller 100. In operation S330, the memory controller 100 can detect the EPI of the memory bank corresponding to the received address ADDR. For example, the memory controller 100 can detect the EPI of the memory bank based on the EPI table (refer to Figure 7 's ET1, Figure 18A 's ET2, and Figure 22A 's ET3, but the example embodiment is not limited thereto)

[0128] In operation S340, the memory controller 100 may determine a programming mode of the memory bank based on the detected EPI. In operation S350, the memory controller 100 may issue a programming command (e.g., a programming command such as a write command, etc.) in the determined programming mode. In operation S360, the memory controller 100 may send the programming command together with the programming mode to the NVM 200. In this case, the memory controller 100 may also send user data and / or metadata to be written to the NVM 200. In operation S370, the NVM 200 may perform a programming operation on the memory bank in the programming mode, such as executing a write command using an adjusted write voltage level based on the detected EPI. In operation S380, the NVM 200 may send a response message indicating that the programming operation has been completed to the memory controller 100. In operation S390, the memory controller 100 may send a response message indicating that the data write operation has been completed to the host 400.

[0129] Figure 26 is a flowchart of a data read operation among the host 400, the memory controller 100, and / or the NVM 200, etc., according to at least one example embodiment.

[0130] Referring to Figure 26 , in operation S410, the host 400 may issue a data read request. In operation S420, the host 400 may send a data read request and / or an address ADDR to the memory controller 100. In operation S430, the memory controller 100 may detect the EPI and / or the programming mode corresponding to the received address ADDR. For example, the memory controller 100 may detect the EPI of the memory bank based on an EPI table (refer to ET1 of Figure 7 ), ET2 of Figure 18A , and ET3 of Figure 22A , but the example embodiment is not limited thereto). For example, the memory controller 100 may detect the EPI of the memory bank based on a programming mode table (refer to PMT1 of Figure 16A , PMT1' of Figure 16B , PMT2 of Figure 18B , and PMT3 of Figure 22B , but the example embodiment is not limited thereto).

[0131] In operation S440, the memory controller 100 may adjust read conditions for a memory bank based on the detected EPI and / or programming mode. For example, the read conditions may include a read voltage level and / or a read time. In operation S450, the memory controller 100 may issue a read command with adjusted read conditions by adjusting the read voltage based on the detected EPI and / or programming mode. In operation S460, the memory controller 100 may send the read command together with the read conditions to the NVM 200. In operation S470, the NVM 200 may perform a read operation on the memory bank under the adjusted read conditions. In operation S480, the NVM 200 may send the read data to the memory controller 100. In operation S490, the memory controller 100 may send the read data to the host 400.

[0132] Figure 27 is a flowchart of a garbage collection operation between the memory controller 100 and / or the NVM 200, etc. according to at least one example embodiment.

[0133] Referring Figure 27 , in operation S510, the memory controller 100 may start a garbage collection operation. The garbage collection operation may refer to an operation of making a source block an idle block by programming valid data included in the source block into a target block. For example, the memory controller 100 may perform the garbage collection operation as a background operation. In operation S520, the memory controller 100 may detect the EPI of the target block. In operation S530, the memory controller 100 may determine a programming mode for the target block based on the detected EPI. In operation S540, the memory controller 100 may issue a programming command in the determined programming mode.

[0134] In operation S550, the memory controller 100 may send the programming command together with the programming mode to the NVM 200, or in other words, the programming command may include programming mode information indicating the programming mode. In operation S560, the NVM 200 may perform a programming operation on the target block based on the programming mode information. In operation S570, the NVM 200 may send a response message indicating that the programming operation on the target block has been completed to the memory controller 100.

[0135] Figure 28 is a block diagram of a modified example of a Figure 1 storage system according to at least one example embodiment.

[0136] Referring Figure 28, the storage system 10a may include a memory controller 100a and / or an NVM 200, etc., and the memory controller 100a may include an EPI checker circuit 110a and / or a programming mode control circuit 120, etc. In addition, the NVM 200 may include a memory cell array 210, and the memory cell array 210 includes a plurality of blocks BLK1 to BLKz and / or a control circuit 220, etc. The storage system 10a according to at least one example embodiment may correspond to Figure 1 a modified example of the storage system 10, and with reference to Figures 1 to 27 the above description presented may be applied to the modified example embodiment.

[0137] The EPI checker circuit 110a may include a plurality of timers (e.g., a first timer 111 and a second timer 112, etc.), and the number of timers (e.g., the first timer 111 and the second timer 112, etc.) may correspond to the number of blocks BLK1 to BLKz. The memory controller 100a may determine the location of the block requested to write data from the host. The EPI checker circuit 110a may refer to the value of the timer corresponding to the determined block and detect the EPI of the block. Each of the first timer 111 and the second timer 112 may determine the period between the erasure time point and the write time point of its corresponding block, and detect and / or measure the EPI of the block. In an example, the first timer 111 corresponding to the first block BLK1 may determine the time elapsed from the erasure time point of the first block BLK1 to the programming time point of the first block BLK1, and detect and / or measure the EPI of the first block BLK1.

[0138] Figure 29 is a block diagram of a modified example of the Figure 1 storage system according to at least one example embodiment.

[0139] With reference to Figure 29 , the storage system 10b may include a memory controller 100b and / or an NVM 200, etc. The memory controller 100b may include an EPI checker circuit 110b, a programming mode control circuit 120, and / or an erasure time storage circuit 180, etc. The storage system 10b according to at least one example embodiment may correspond to Figure 1 a modified example of the storage system 10, and with reference to Figures 1 to 27 the above description presented may be applied to the example embodiment, but the example embodiment is not limited thereto.

[0140] The EPI checker circuit 110b may include a timer 111, which may be shared between at least two blocks. For example, the timer 111 included in the EPI checker circuit 110b may detect the EPI of a first block BLK1 and a second block BLK2, etc. The timer 111 may determine the time point at which an erase operation is performed on the first block BLK1, and the time point at which an erase operation is performed on the second block BLK2. In an example, the erase time point of the first block BLK1 may be different from the erase time point of the second block BLK2, and the determined erase time points may be stored in the erase time storage circuit 180 and / or the meta-region of the storage cell array 210, etc.

[0141] Subsequently, the timer 111 may continuously determine the passage of time, and determine the write time point of the first block BLK1 when a write request for the first block BLK1 is received. Based on the detected EPI, according to one or more of the above exemplary embodiments, the EPI checker circuit 110b may confirm the information indicating the previously stored erase time point of the first block BLK1, detect and / or measure the EPI indicating the period from the write time point to the erase time point, and perform a programming operation on the first block BLK1 in any of a plurality of programming modes. Similarly, the timer 111 may determine the write time point of the second block BLK2, and detect and / or measure the EPI of the second block BLK2 based on the information indicating the previously stored erase time point and the write time point of the second block BLK2.

[0142] Figure 30 is according to at least one example embodiment Figure 1 block diagram of a modified example of a storage system.

[0143] Referring to Figure 30 , the storage system 10c may include a memory controller 100c and / or an NVM 200c, etc. The NVM 200c may include a storage cell array 210, a control circuit 220, and / or an EPI checker circuit 260, etc. The NVM 200c may determine the block in which data is to be written based on the address ADDR provided together with and / or included in the programming command from the memory controller 100c. In one example, the address ADDR may include a block address indicating any one of a plurality of blocks BLK1 to BLKz of the storage cell array 210.

[0144] The EPI checker circuit 260 may detect the EPI of the block selected by the block address. As in the above exemplary embodiment, the EPI checker circuit 260 may include at least one timer 261. As an example, the EPI checker circuit 260 may include the same number of timers as the number of blocks BLK1 to BLKz included in the memory cell array 210, or a number of timers less than the number of blocks BLK1 to BLKz, and so on.

[0145] For example, the first block BLK1 may perform an erase operation in response to an erase command received from the memory controller 100c, or perform an erase operation due to an internal operation of the NVM 200c (e.g., a garbage collection operation). The EPI checker circuit 260 may determine the erase time point of the first block BLK1 and detect and / or measure the EPI of the first block BLK1 by determining the elapsed time from after the execution of the erase operation until the execution of the program operation.

[0146] The control circuit 220 may receive EPI information from the EPI checker circuit 260, determine a programming mode based on the received EPI information, and control the programming operation of the memory cell array 210 according to the determined programming mode. In addition, the control circuit 220 may receive EPI information from the EPI checker circuit 260, determine read conditions (e.g., read voltage levels, etc.) based on the received EPI information, and control the read operation of the memory cell array 210 under the determined read conditions.

[0147] Figure 31 is a block diagram of an example in which a storage system according to at least one exemplary embodiment is applied to an SSD system 1000.

[0148] Reference Figure 31 , the SSD system 1000 may include a host 1100 and / or an SSD 1200, etc. The SSD 1200 may send a signal SIG to the host 1100 and receive a signal SIG from the host 1100 through a signal connector, and receive power PWR through a power connector. The SSD 1200 may include an SSD controller 1210, an auxiliary power device 1220, and / or a plurality of storage devices 1230, 1240, and 1250, etc., but the exemplary embodiment is not limited thereto. The plurality of storage devices 1230, 1240, and 1250 may be respectively connected to the SSD controller 1210 through a plurality of channels Ch1, Ch2, and Chn.

[0149] The SSD controller 1210 may use the above reference Figures 1 to 30Implemented by multiple memory controllers 100, 100a, 100b, 100c, etc. described, but not limited thereto. For example, the SSD controller 1210 may determine a programming mode corresponding to the memory bank based on the EPI of the memory bank. In addition, the SSD controller 1210 may adjust read conditions corresponding to the memory bank based on the EPI information and / or programming mode corresponding to the memory bank, including adjusting at least one voltage level (e.g., read voltage threshold level, etc.) based on the EPI information and / or programming mode.

[0150] May be implemented using the multiple NVMs 200, 200a, 200b, 200c described above Figures 1 to 30 To implement the storage devices 1230, 1240, and 1250, but not limited thereto. For example, each of the storage devices 1230, 1240, and 1250 may perform a programming operation on the memory bank in a determined programming mode and / or perform a read operation on the memory bank under adjusted read conditions, including adjusting at least one voltage level associated with the programming operation and / or read operation based on the EPI information and / or programming mode.

[0151] Although various exemplary embodiments of the inventive concept have been specifically shown and described with reference to exemplary embodiments of the present invention, it should be understood that various changes may be made in form and detail without departing from the spirit and scope of the appended claims.

Claims

1. A method of operating a storage system, the storage system including a non-volatile memory, the method comprising: Measuring, by a processing circuit, an erase programming interval (EPI) of a memory bank, the EPI being a time period from an erase time point to a program time point of the memory bank, the memory bank being included in the non-volatile memory; Determining, by the processing circuit, a plurality of programming modes based on the number of bits of data stored in each memory cell of the memory bank; Selecting, by the processing circuit, a programming mode of the memory bank from the plurality of programming modes based on the measured EPI of the memory bank; And Performing, by the processing circuit, a programming operation on the memory bank corresponding to the selected programming mode, performing the programming operation on the memory bank including adjusting at least one voltage level of the programming operation based on the selected programming mode.

2. The method according to claim 1, wherein The plurality of programming modes includes at least one of the following: a quad-level cell (QLC) mode, a triple-level cell (TLC) mode, a multi-level cell (MLC) mode, and a single-level cell (SLC) mode or a combination thereof.

3. The method according to claim 1, wherein The memory bank includes at least one of a storage block, a memory stack, and a sub-storage block or a combination thereof.

4. The method according to claim 1, wherein The memory bank includes a storage block; and Selecting the programming mode includes: In response to the measured EPI being equal to or shorter than a reference time, selecting a first programming mode of the storage block in which N bits of data are written into each memory cell, and In response to the measured EPI exceeding the reference time, selecting a second programming mode of the storage block in which M bits of data are written into each memory cell, Wherein, N and M are positive integers, and M is less than N.

5. The method according to claim 1, wherein The non-volatile memory includes a plurality of storage blocks, each of the plurality of storage blocks including a plurality of memory stacks stacked on a substrate in a direction perpendicular to the substrate of the non-volatile memory; The memory bank includes a memory stack; Measuring the EPI of the memory bank includes: Measuring a first EPI of a first memory stack of the memory bank, and Measuring a second EPI of a second memory stack of the memory bank, the second memory stack being located on the first memory stack in a direction perpendicular to the first memory stack; and Selecting the programming mode includes: Based on the first EPI, selecting a programming mode of the first memory stack as at least one of a QLC mode, a TLC mode, an MLC mode, and an SLC mode, and Based on the second EPI, selecting a programming mode of the second memory stack as at least one of a QLC mode, a TLC mode, an MLC mode, and an SLC mode.

6. The method according to claim 5, further comprising: During the programming operation on the first memory stack, in response to the first EPI exceeding the reference time, selecting a programming mode of the second memory stack as at least one of a QLC mode, a TLC mode, an MLC mode, and an SLC mode.

7. The method according to claim 1, wherein The non - volatile memory includes a plurality of memory blocks, and each of the plurality of memory blocks includes a plurality of sub - memory blocks that can be independently erased; Measuring the EPI of a memory group includes: Measuring a first EPI of a first sub - memory block, and Measuring a second EPI of a second sub - memory block adjacent to the position of the first sub - memory block; and Selecting a programming mode includes: Based on the first EPI, selecting the programming mode of the first sub - memory block as at least one of a quad - level cell (QLC) mode, a triple - level cell (TLC) mode, a multi - level cell (MLC) mode, and a single - level cell (SLC) mode, and Based on the second EPI, selecting the programming mode of the second sub - memory block as at least one of a QLC mode, a TLC mode, a MLC mode, and a SLC mode.

8. The method according to claim 7, wherein, Selecting the programming mode of the second sub - memory block further includes: during the programming operation of the first sub - memory block, in response to the first EPI exceeding a reference time, selecting at least one of a QLC mode, a TLC mode, a MLC mode, and a SLC mode as the programming mode of the second sub - memory block.

9. The method according to claim 1, wherein, The non - volatile memory includes a metadata area configured to store an EPI table, wherein the EPI table stores EPI information, and the EPI information indicates the measured EPI corresponding to each memory group; and Measuring the EPI of a memory group includes measuring the EPI corresponding to the memory group based on the EPI table stored in the metadata area.

10. The method according to claim 1, further includes: Using a processing circuit to select the programming mode of a memory group, and selecting the programming mode of the memory group includes selecting a default programming mode after a sudden power - off (SPO) event, and the default programming mode is a multi - level cell (MLC) mode or a single - level cell (SLC) mode.

11. The method according to claim 1, wherein, Measuring the EPI of a memory group includes at least one of the following: In response to a write request received from a host, measuring the EPI of the memory group during a user data programming operation; Measuring the EPI of the memory group during a metadata programming operation; Measuring the EPI of the memory group during a garbage collection operation; or A combination thereof.

12. The method according to claim 1, further includes: In response to a read request for a memory group, selecting a programming mode corresponding to the memory blocks of the memory group based on a programming mode table, and the programming mode table includes a programming mode corresponding to each memory group; And Adjusting the read conditions for the memory group based on the programming mode of the selected memory blocks of the memory group, and the adjusting the read conditions includes adjusting at least one voltage level associated with the read conditions based on the programming mode of the selected memory blocks.

13. A method of operating a storage system, the storage system including a non - volatile memory, the method including: Using a processing circuit, in response to a write request received from a host, measuring the erase - programming interval (EPI) of a memory block of the non - volatile memory, and the EPI is a time period from the erase time point of the memory block to the programming time point; And Using a processing circuit, perform a programming operation on a storage block in a first programming mode or a second programming mode based on the duration of the EPI. The first programming mode includes writing N-bit data to each storage cell of the storage block, and the second programming mode includes writing M-bit data to each storage cell of the storage block. Performing the programming operation on the storage block includes adjusting at least one voltage level of the programming operation based on the first programming mode or the second programming mode. Wherein, N and M are positive integers, and M is less than N.

14. The method according to claim 13, further comprising: Using a processing circuit, in response to the EPI exceeding a first reference time and a second reference time, perform a programming operation on the storage block in a third programming mode. The third programming mode includes writing L-bit data to each storage cell of the storage block. The second reference time is longer than the first reference time. Wherein, L is a positive integer less than M.

15. The method according to claim 14, further comprising: Using a processing circuit, in response to the EPI exceeding a third reference time, perform a programming operation on the storage block in a fourth programming mode. The third reference time is longer than the second reference time. The fourth programming mode includes writing K-bit data to each storage cell of the storage block. Wherein, K is a positive integer less than L.

16. The method according to claim 13, wherein, Measuring the EPI of the storage block includes reading the EPI of the storage block from an EPI table stored in a meta-region of the non-volatile memory.

17. The method according to claim 13, further comprising: Using a processing circuit, in response to a read request for the storage block, select a programming mode corresponding to the storage block based on a programming mode table. The programming mode table includes programming modes corresponding to each storage block; And Using a processing circuit, adjust the read condition of the storage block based on the programming mode of the selected storage block. Adjusting the read condition includes adjusting at least one voltage level associated with the read condition based on the programming mode of the selected storage module.

18. A storage system, comprising: A non-volatile memory, including a plurality of memory groups; And A memory controller, configured to: Measure an erase programming interval (EPI) of a first memory group among the plurality of memory groups. The EPI is a time period from an erase time point to a programming time point of the first memory group. Determine a plurality of programming modes based on the number of bits of data stored in each storage cell of the plurality of memory groups. Based on the measured EPI, select a programming mode of the first memory group from the plurality of programming modes, and Control the programming operation of the first memory group based on the selected programming mode of the first memory group. Controlling the programming operation includes adjusting at least one voltage level associated with the programming operation based on the selected programming mode.

19. The storage system according to claim 18, wherein, The plurality of programming modes includes at least one of a quad-level cell (QLC) mode, a triple-level cell (TLC) mode, a multi-level cell (MLC) mode, and a single-level cell (SLC) mode.

20. The storage system according to claim 18, wherein, The plurality of memory groups includes storage blocks, memory stacks, sub-storage blocks, or a combination thereof.

Images