Integrated circuit and method for forming the same, method for forming semiconductor package

Abstract

An integrated circuit and a method for forming the same and a method for forming a semiconductor package. The integrated circuit includes: a first dielectric structure having a first inner sidewall located above an interlayer dielectric structure. A second dielectric structure is located above the first dielectric structure, wherein the first inner sidewall is located between the second inner sidewalls of the second dielectric structure. A sidewall barrier structure is located above the first dielectric structure and extends vertically along the second inner sidewall. A lower bump structure is located between the second inner sidewalls and extends vertically along the first inner sidewall and extends vertically along the third inner sidewall of the sidewall barrier structure. An upper bump structure is located above both the lower bump structure and the sidewall barrier structure and between the second inner sidewalls, wherein the uppermost point of the upper bump structure is located at the uppermost point of the second dielectric structure or below the uppermost point of the second dielectric structure.

Description

Technical Field

[0001] The embodiments of the present invention relate to an integrated circuit and a method for forming the same, and a method for forming a semiconductor package. Background Art

[0002] During batch manufacturing of integrated circuits (ICs), multiple IC dies are formed on a semiconductor wafer. After the IC dies are formed, the IC dies are separated and packaged. Wafer-level packaging (WLP) is a packaging process in which the IC dies are packaged before being separated. Some types of WLP may include, for example, flip chip packaging, chip scale package (CSP), etc. Summary of the invention

[0003] An embodiment of the present invention provides a method for forming an integrated circuit, which includes: receiving a workpiece, the workpiece including an interconnect structure embedded in an interlayer dielectric structure and including a first dielectric layer arranged on the interlayer dielectric structure and the interconnect structure; forming a first dielectric structure on the workpiece; forming a sidewall barrier structure on the first dielectric layer and along the inner sidewall of the first dielectric structure; forming a hard mask structure on the first dielectric layer and along the inner sidewall of the sidewall barrier structure, wherein the height of the hard mask structure is less than the height of the first dielectric structure; after forming the hard mask structure, removing an upper portion of the sidewall barrier structure so that the height of the sidewall barrier structure is less than or equal to the height of the hard mask structure; removing a portion of the first dielectric layer arranged between the inner sidewalls of the sidewall barrier structure to form a second dielectric structure; forming a lower bump structure on the interlayer dielectric structure, the lower bump structure extending vertically along the inner sidewall of the second dielectric structure and along the inner sidewall of the sidewall barrier structure; and forming an upper bump structure on both the lower bump structure and the sidewall barrier structure.

[0004] An embodiment of the present invention provides an integrated circuit, which includes an interlayer dielectric structure, a first dielectric structure, a second dielectric structure, a sidewall barrier structure, a lower bump structure and an upper bump structure. The interlayer dielectric structure is arranged on a semiconductor substrate, wherein an interconnect structure is embedded in the interlayer dielectric structure. The first dielectric structure is arranged on the interlayer dielectric structure and the interconnect structure, wherein a conductive pad of the interconnect structure is at least partially arranged between the first inner sidewalls of the first dielectric structure. The second dielectric structure is arranged on the first dielectric structure, wherein the first inner sidewall is arranged between the second inner sidewalls of the second dielectric structure. The sidewall barrier structure is arranged on the first dielectric structure and extends vertically along the second inner sidewall. The lower bump structure is arranged on the conductive pad and between the second inner sidewall, wherein the lower bump structure extends vertically along the first inner sidewall and along the third inner sidewall of the sidewall barrier structure. The upper bump structure is disposed over both the lower bump structure and the sidewall barrier structure, wherein the upper bump structure extends vertically along the second inner sidewall, and wherein an uppermost point of the upper bump structure is disposed at or below an uppermost point of the second dielectric structure.

[0005] An embodiment of the present invention provides a method, which includes: receiving a semiconductor wafer having a plurality of integrated circuits arranged on the semiconductor wafer, wherein: a first integrated circuit among the plurality of integrated circuits includes an interlayer dielectric (ILD) structure, a dielectric structure arranged on the interlayer dielectric structure, and a bump structure arranged on the interlayer dielectric structure and between inner sidewalls of the dielectric structure; the bump structure includes a lower bump structure and an upper bump structure; a sidewall barrier structure is arranged along the outer sidewall of the lower bump structure and at least partially separates the lower bump structure from the inner sidewall of the dielectric structure; the uppermost surface of the sidewall barrier structure is substantially coplanar with the uppermost surface of the lower bump structure; and the upper bump structure is arranged on both the lower bump structure and the sidewall barrier structure; bonding a carrier wafer to the semiconductor wafer, wherein the carrier wafer is bonded to the dielectric structure or the bump structure; and forming a first individualized die including the first integrated circuit by individualizing the first integrated circuit from the semiconductor wafer and the carrier wafer that are bonded together. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 Cross-sectional views of some embodiments of an integrated circuit (IC) having a bump structure are shown.

[0008] Figure 2 Show Figure 1An enlarged cross-sectional view of some embodiments of an area of ​​.

[0009] Figure 3 Show Figure 1 Magnified cross-sectional views of some other embodiments of an area of ​​.

[0010] Figure 4 Show Figure 1 Magnified cross-sectional views of some other embodiments of an area of ​​.

[0011] Figure 5 Show Figure 1 Magnified cross-sectional views of some other embodiments of an area of ​​.

[0012] Figure 6 Show Figure 1 Cross-sectional views of some other embodiments of ICs are shown.

[0013] Figure 7 Show Figure 1 Cross-sectional views of some other embodiments of ICs are shown.

[0014] Figure 8 Show Figure 1 Cross-sectional views of some other embodiments of ICs are shown.

[0015] Fig. 9 Shown including Figure 1 Cross-sectional views of some embodiments of display devices of some embodiments of the IC are shown.

[0016] FIG. 10A to FIG. 10B Show Fig. 9 Various views of some other embodiments of display devices are shown.

[0017] FIG. 11A to FIG. 11B to FIG. 24A to FIG. 24B Shown to form Figure 1 A series of cross-sectional views of some embodiments of methods of some embodiments of the IC are shown.

[0018] Fig.25 Shown to form Figure 1 Flowcharts of some embodiments of methods of some embodiments of the IC are shown.

[0019] Fig.26A , FIG. 26B to FIG. 28A , Fig.28B A series of various views showing some embodiments of a method of forming a first singulated die comprising Figure 1 Some embodiments of the IC are shown.

[0020] Fig.29 A cross-sectional view showing some embodiments of a method of forming a display device, the display device comprising FIG. 26A to FIG. 26B to FIG. 28A to FIG. 28B A first singulated die is formed in the process.

[0021] Fig.30 A flowchart showing some embodiments of a method for: (1) forming a Figure 1 singulated dies of some embodiments of the illustrated IC 100; and (2) forming a display device including the singulated dies. DETAILED DESCRIPTION

[0022] The present disclosure will now be described with reference to the drawings, wherein the same reference numerals are used throughout to refer to the same elements, and the structures illustrated therein are not necessarily drawn to scale. It should be understood that this detailed description and the corresponding drawings do not limit the scope of the present disclosure in any way, and that the detailed description and the drawings only provide several examples to illustrate some ways in which the concepts of the present invention can be apparent.

[0023] The present disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, the following description in which a first feature is formed on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than indicating the relationship between the various embodiments and / or configurations discussed.

[0024] Additionally, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature illustrated in a figure to another (other) element or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0025] According to some packaging processes using a nickel / gold (Ni / Au) bumping process, a first dielectric layer (e.g., silicon nitride (SiN)) is formed covering the copper pad, and a second dielectric layer (e.g., silicon dioxide (SiO2)) is formed covering the first dielectric layer. A first etch is performed on the second dielectric layer. The first etch stops on the first dielectric layer and forms a first opening overlying the copper pad. Thereafter, a metal including a sidewall barrier structure (e.g., titanium nitride (TiN)) is formed to line the sidewalls of the first opening. A second etch is then performed on the first dielectric layer. The second etch forms a second opening, which exposes the copper pad and is laterally spaced apart between the sidewalls of the first opening. A Ni / Au bump is formed on the copper pad and along the metal including the sidewall barrier structure. The Ni / Au bump includes a nickel layer on the copper pad and a gold layer overlying the nickel layer. The metal including the sidewall barrier structure blocks or otherwise slows the movement (e.g., diffusion) of copper from the copper pads to the gold layer along the sidewalls of the nickel layer. This prevents copper from contaminating the gold layer, which could negatively impact yield during batch manufacturing and / or packaging of ICs using a packaging process.

[0026] One challenge of the packaging process is that the Ni / Au bumps may extend vertically above the upper surface of the second dielectric layer. For example, due to over-plating of the gold layer on the metal containing the sidewall barrier structure, the Ni / Au bumps may extend vertically above the upper surface of the second dielectric layer. Due to the height of the metal containing the sidewall barrier structure, over-plating of the gold layer on the metal containing the barrier structure may cause the gold layer to extend vertically above the upper surface of the second dielectric layer. In some embodiments, the over-plating results in the formation of a "fence" structure (e.g., an outer ring portion) that extends vertically above the upper surface of the second dielectric layer and overlies the metal containing the sidewall barrier structure. Since the Ni / Au bumps extend vertically above the second dielectric layer, the bondability of the Ni / Au bumps and / or the second dielectric layer to a transparent screen panel (e.g., a glass screen panel) and / or a carrier substrate (e.g., a carrier wafer) may be negatively affected (e.g., due to a seam (e.g., a gap) between the carrier substrate and the Ni / Au bumps and / or the second dielectric layer). Therefore, during batch manufacturing and / or packaging of ICs using a packaging process, the Ni / Au bumps extending vertically above the upper surface of the second dielectric layer may result in low yield.

[0027] Various embodiments of the present application relate to a mask transfer method and related apparatus for a bump process (e.g., a Ni / Au bump process). In some embodiments, the method includes receiving a workpiece, the workpiece including a first dielectric layer covering a conductive pad and a second dielectric layer covering the first dielectric layer. A first opening is formed in the second dielectric layer and at least partially between the sidewalls of the conductive pad. A sidewall barrier structure is formed on the first dielectric layer and along the sidewalls of the first opening. A hard mask layer is formed to line the second dielectric layer, the sidewall barrier structure, and a portion of the first dielectric layer disposed between the inner sidewalls of the sidewall barrier structure. A mask layer is formed to line the hard mask layer and fill the first opening.

[0028] The upper portion of the mask layer is removed so that the lower portion of the mask layer is disposed in the first opening and has an upper surface disposed between an upper surface of the second dielectric layer and an upper surface of the first dielectric layer. Thereafter, the upper portion of the hard mask layer is removed so that the lower portion of the hard mask layer is disposed in the first opening and has an upper surface substantially aligned with an upper surface of the lower portion of the mask layer. The upper portion of the sidewall barrier structure is then removed so that the lower portion of the sidewall barrier structure has an upper surface disposed below and spaced apart from an upper surface of the second dielectric layer by a non-zero distance.

[0029] Thereafter, the lower portion of the hard mask layer and the lower portion of the mask layer are removed. A second opening is then formed in the first dielectric layer to expose the conductive pad. A second opening is formed between the sidewalls of the first opening. A lower bump structure is then formed on the conductive layer and at least partially along the inner sidewall of the lower portion of the sidewall barrier structure. An upper bump structure covering the lower bump structure and the sidewall barrier structure is then formed. Since the upper surface of the lower portion of the sidewall barrier structure is disposed below the upper surface of the second dielectric layer and is spaced apart from the upper surface of the second dielectric layer by a non-zero distance, the height of the lower portion of the sidewall barrier structure can prevent the upper bump structure from extending vertically above the upper surface of the second dielectric layer (for example, the height of the lower portion of the sidewall barrier structure is such that overplating of the lower portion of the sidewall barrier structure does not cause the upper bump structure to extend vertically above the upper surface of the second dielectric structure). Therefore, the upper bump structure may not be formed with a "fence" structure extending vertically above the upper surface of the second dielectric layer. Therefore, the mask transfer method for the bumping process may improve yield during batch manufacturing and / or packaging of ICs.

[0030] Figure 1 A cross-sectional view of some embodiments of an integrated circuit (IC) 100 having a bump structure is shown.

[0031] The IC 100 includes a semiconductor substrate 102. The semiconductor substrate 102 may include any type of semiconductor body (e.g., single crystal silicon / complementary metal-oxide-semiconductor (CMOS) block, silicon-germanium (SiGe), silicon on insulator (SOI), etc.). One or more semiconductor devices 104 may be disposed on / in the semiconductor substrate 102. The one or more semiconductor devices 104 may be or include, for example, a metal oxide semiconductor (MOS) field-effect transistor (FET), some other MOS device, or some other semiconductor device. For example, the one or more semiconductor devices 104 may be a MOSFET including a pair of source / drain regions 106 disposed in the semiconductor substrate 102, a gate dielectric 108 disposed on the semiconductor substrate 102 and located between the source / drain regions 106, and a gate electrode 110 disposed on the gate dielectric 108 and located between the source / drain regions 106.

[0032] An interlayer dielectric (ILD) structure 112 is disposed above the semiconductor substrate 102 and the one or more semiconductor devices 104. In some embodiments, the ILD structure 112 includes one or more stacked ILD layers, and the one or more stacked ILD layers may respectively include a low-k dielectric (e.g., a dielectric material having a dielectric constant less than about 3.9), an oxide (e.g., silicon dioxide (SiO2)), etc. An interconnect structure 114 (e.g., a copper interconnect) is embedded in the ILD structure 112. The interconnect structure 114 includes a plurality of first conductive features (e.g., metal lines, metal vias, metal contacts, etc.). The interconnect structure 114 is configured to electrically couple the one or more semiconductor devices 104 together. In some embodiments, the interconnect structure 114 may include, for example, copper (Cu), aluminum (Al), tungsten (W), some other conductive material, or a combination of the foregoing materials.

[0033] The interconnect structure 114 includes an upper conductive pad 114p. In some embodiments, the upper conductive pad 114p is the uppermost first conductive feature of the interconnect structure 114. In yet other embodiments, the upper conductive pad 114p is a copper pad. It should be understood that in some embodiments, the upper conductive pad 114p is one of a plurality of upper conductive pads having substantially coplanar upper surfaces. In such embodiments, the plurality of upper conductive pads may be the uppermost first conductive feature of the interconnect structure 114, and the upper conductive pad 114p is one of the uppermost first conductive features.

[0034] A first dielectric structure 116 is disposed over the interconnect structure 114 and the ILD structure 112. In some embodiments, the first dielectric structure 116 comprises a nitride (e.g., silicon nitride (SiN)), an oxide (e.g., SiO2), an oxynitride (e.g., silicon oxynitride (SiO X N Y )) etc. A second dielectric structure 118 is disposed on the first dielectric structure 116, the interconnect structure 114, and the ILD structure 112. In some embodiments, the second dielectric structure 118 comprises an oxide (e.g., SiO2), a nitride (e.g., SiN), an oxynitride (e.g., SiO X N Y ) etc. In some other embodiments, the second dielectric structure 118 comprises a different dielectric material than the first dielectric structure 116. In some other embodiments, the second dielectric structure 118 is SiO2 and the first dielectric structure 116 is SiN.

[0035] A bump structure 120 is disposed on the interconnect structure 114 and the ILD structure 112. The bump structure includes a lower bump structure 122 and an upper bump structure 124. In some embodiments, the bump structure 120 is directly disposed on the upper conductive pad 114p.

[0036] The lower bump structure 122 is vertically disposed between the upper bump structure 124 and the upper conductive pad 114p. The lower bump structure 122 is electrically coupled to the interconnect structure 114. The lower bump structure 122 extends vertically through the first dielectric structure 116. The lower bump structure 122 may extend vertically through the first dielectric structure 116 and contact the upper conductive pad 114p. The lower bump structure 122 is at least partially disposed in the second dielectric structure 118. In some embodiments, the outer sidewall of the lower bump structure 122 is disposed within the outer sidewall of the upper conductive pad 114p. The upper surface of the lower bump structure 122 is vertically disposed between the upper surface of the second dielectric structure 118 and the lower surface of the second dielectric structure 118. In some embodiments, the upper surface of the lower bump structure 122 is the uppermost surface of the lower bump structure 122. In yet other embodiments, the upper surface of the second dielectric structure 118 is the uppermost surface of the second dielectric structure 118 , and the lower surface of the second dielectric structure 118 is the lowermost surface of the second dielectric structure 118 .

[0037] A first sidewall barrier structure 126 is disposed in the second dielectric structure 118 and along the outer sidewall of the lower bump structure 122. The first sidewall barrier structure 126 is configured to block or otherwise slow down the movement (e.g., diffusion) of atoms from the upper conductive pad 114p to the upper bump structure 124 along the sidewall of the lower bump structure 122. In some embodiments, the first sidewall barrier structure 126 is disposed directly above the upper conductive pad 114p.

[0038] The first sidewall barrier structure 126 is vertically disposed between the upper bump structure 124 and the first dielectric structure 116. In some embodiments, the outer sidewall of the first sidewall barrier structure 126 is disposed inside the outer sidewall of the upper conductive pad 114p. In other embodiments, the inner sidewall of the first sidewall barrier structure 126 is substantially aligned with the inner sidewall of the first dielectric structure 116. The first dielectric structure 116 vertically separates the first sidewall barrier structure 126 from the upper conductive pad 114p. The upper surface of the first sidewall barrier structure 126 is vertically disposed between the upper surface of the second dielectric structure 118 and the lower surface of the second dielectric structure 118. In some embodiments, the upper surface of the first sidewall barrier structure 126 is substantially coplanar with the upper surface of the lower bump structure 122. In other embodiments, the upper surface of the first sidewall barrier structure 126 is the uppermost surface of the first sidewall barrier structure 126.

[0039] The upper bump structure 124 is disposed in the second dielectric structure 118 and above both the lower bump structure 122 and the first sidewall barrier structure 126. The upper bump structure 124 may cover the lower bump structure 122 and / or the first sidewall barrier structure 126. In some embodiments, the uppermost point of the upper bump structure 124 is disposed at the uppermost point of the second dielectric structure 118 or below the uppermost point of the second dielectric structure 118. In yet other embodiments, the upper bump structure 124 has a substantially flat upper surface. Since the uppermost point of the upper bump structure 124 is disposed at the uppermost point of the second dielectric structure 118 or below the uppermost point of the second dielectric structure 118, the upper surface of the upper bump structure 124 does not have a "fence" structure extending above the upper surface of the second dielectric structure 118. Therefore, the bump structure 120 may improve the ability (eg, bondability) of the IC 100 to be bonded to a transparent screen panel (eg, a glass screen panel) and / or a carrier substrate (eg, a carrier wafer).

[0040] Figure 2 exemplify Figure 1 The region 128 shown (see, for example, Figure 1 ) are enlarged cross-sectional views of some embodiments.

[0041] like Figure 2As shown in , the first sidewall barrier structure 126 extends vertically a first distance D1 from the upper surface of the first dielectric structure 116 toward the upper surface of the second dielectric structure 118. The upper surface of the second dielectric structure 118 is vertically spaced apart from the upper surface of the first dielectric structure 116 by a second distance D2. The first distance D1 is less than the second distance D2. In some embodiments, the first distance D1 is between ten percent and fifty percent of the second distance D2. If the first distance D1 is greater than fifty percent of the second distance D2, the uppermost point of the upper bump structure 124 may extend vertically above the uppermost point of the second dielectric structure 118, so that the upper bump structure 124 has a "fence" extending vertically above the upper surface of the second dielectric structure 118 (for example, due to over-plating on the upper surface of the first sidewall barrier structure 126 by the process used to form the upper bump structure 124). On the other hand, if the first distance D1 is less than ten percent of the second distance D2, the uppermost point of the upper bump structure 124 may be disposed too far below the uppermost point of the second dielectric structure 118, such that the upper bump structure 124 has a severe “hump” extending vertically above the upper surface of the second dielectric structure 118 (e.g., a protruding portion of the upper bump structure disposed directly above the lower bump structure 122). In some embodiments, the first sidewall barrier structure 126 contacts the first dielectric structure 116, the lower bump structure 122, the upper bump structure 124, and the second dielectric structure 118.

[0042] In some embodiments, the first sidewall barrier 126 has an arc-shaped inner sidewall. The arc-shaped inner sidewall of the first sidewall barrier 126 may be an arc from the lower surface of the first sidewall barrier 126 to the upper surface of the first sidewall barrier 126. The arc-shaped inner sidewall of the first sidewall barrier 126 may be curved (arc) toward the outer sidewall of the first sidewall barrier 126 from the lower surface of the first sidewall barrier 126 to the upper surface of the first sidewall barrier 126. In other embodiments, the inner sidewall of the first sidewall barrier 126 may be substantially vertical. In yet other embodiments, the lower surface of the first sidewall barrier 126 is the lowest surface of the first sidewall barrier 126.

[0043] The second dielectric structure 118 has an inner sidewall. In some embodiments, the inner sidewall of the second dielectric structure 118 is substantially vertical. The inner sidewall of the second dielectric structure 118 has a first lower portion and a first upper portion disposed above the first lower portion. In some embodiments, the outer sidewall of the first sidewall barrier structure 126 engages with the first lower portion of the inner sidewall of the second dielectric structure 118. The outer sidewall of the first sidewall barrier structure 126 extends vertically along the first lower portion of the inner sidewall of the second dielectric structure 118. In yet other embodiments, the outer sidewall of the first sidewall barrier structure 126 is substantially vertical. In yet other embodiments, the first lower portion is defined by a lower portion of the inner sidewall of the second dielectric structure 118 extending vertically from a lower surface of the second dielectric structure 118 to an upper surface of the first sidewall barrier structure 126. The first upper portion is defined by an upper portion of the inner sidewall of the second dielectric structure 118 that vertically extends from a lower portion of the inner sidewall of the second dielectric structure 118 to an upper surface of the second dielectric structure 118 .

[0044] There is an angle θ between one of the inner sidewalls of the first sidewall barrier 126 and the lower surface of the first sidewall barrier 126. In some embodiments, the angle θ is between twenty degrees and ninety degrees. In yet other embodiments, the angle θ between each of the inner sidewalls of the first sidewall barrier 126 and the lower surface of the first sidewall barrier 126 is substantially the same.

[0045] In some embodiments, the outermost periphery of the first sidewall barrier structure 126 is disposed within the outermost periphery of the upper conductive pad 114p. In other embodiments, the outermost periphery of the first sidewall barrier structure 126 may be at least partially disposed outside the outermost periphery of the upper conductive pad 114p. In such an embodiment, one or more outer sidewalls of the outer sidewalls of the upper conductive pad 114p are disposed within the outer sidewalls of the first sidewall barrier structure 126.

[0046] In some embodiments, the upper surface of the first sidewall barrier structure 126 is substantially flat. In some other embodiments, the upper surface of the first sidewall barrier structure 126 surrounds the lower bump structure 122 in the lateral direction. In such embodiments, the upper surface extends in a continuous closed path around the lower bump structure 122 in the lateral direction. In some other embodiments, the first sidewall barrier structure 126 includes, for example, titanium (Ti), titanium nitride (TiN), some other material sufficient to block atoms from diffusing from the upper conductive pad 114p to the upper bump structure 124, or a combination of the foregoing materials.

[0047] The lower bump structure 122 is disposed between the inner sidewalls of the first sidewall barrier structure 126 and between the inner sidewalls of the first dielectric structure 116. In some embodiments, the inner sidewalls of the first dielectric structure 116 are substantially vertical. In some other embodiments, the inner sidewalls of the first dielectric structure 116 are disposed between the inner sidewalls of the second dielectric structure 118. The upper conductive pad 114p is at least partially disposed between the inner sidewalls of the first dielectric structure 116.

[0048] In some embodiments, the lower bump structure 122 contacts both the first dielectric structure 116 and the first sidewall barrier structure 126. In yet other embodiments, the lower surface of the lower bump structure 122 is substantially coplanar with the lower surface of the first dielectric structure 116. In yet other embodiments, the lower bump structure 122 comprises, for example, pure nickel (Ni), a Ni alloy, some other suitable metal, or a combination of the foregoing materials. In yet other embodiments, the lower surface of the lower bump structure 122 is the lowest surface of the lower bump structure 122.

[0049] The outer sidewall of the lower bump structure 122 has a second lower portion and a second upper portion disposed above the second lower portion. In some embodiments, the second lower portion of the outer sidewall of the lower bump structure 122 is connected to the inner sidewall of the first dielectric structure 116. The second lower portion is defined by the lower portion of the outer sidewall of the lower bump structure 122 extending vertically from the lower surface of the lower bump structure 122 to the upper surface of the first dielectric structure 116. In some other embodiments, the lower portion of the outer sidewall of the lower bump structure 122 is substantially vertical.

[0050] The second upper portion of the outer sidewall of the lower bump structure 122 is connected to the inner sidewall of the first sidewall barrier structure 126. The second upper portion is defined by the upper portion of the outer sidewall of the lower bump structure 122 extending vertically from the lower portion of the outer sidewall of the lower bump structure 122 to the upper surface of the lower bump structure 122. In some embodiments, the upper portion of the outer sidewall of the lower bump structure 122 is arc-shaped. In some other embodiments, the arc-shaped upper portion of the outer sidewall of the lower bump structure 122 is an arc from the lower portion of the outer sidewall of the lower bump structure 122 to the upper surface of the lower bump structure 122 toward the outer sidewall of the first sidewall barrier structure 126. In some other embodiments, the arc-shaped outer sidewall of the lower bump structure 122 may be arc-shaped so that at least a portion of the arc-shaped outer sidewall of the lower bump structure 122 is disposed outside the inner sidewall of the first dielectric structure 116. In other embodiments, the upper portion of the outer sidewall of the lower bump structure 122 is substantially vertical.

[0051] In some embodiments, the outermost periphery of the lower bump structure 122 is disposed within the outermost periphery of the upper conductive pad 114p. In other embodiments, the outermost periphery of the lower bump structure 122 may be at least partially disposed outside the outermost periphery of the upper conductive pad 114p. In such an embodiment, one or more outer sidewalls of the outer sidewall of the upper conductive pad 114p are disposed within the outer sidewall of the lower bump structure 122.

[0052] In some embodiments, the upper bump structure 124 contacts both the lower bump structure 122 and the first sidewall barrier structure 126. The upper bump structure 124 may completely cover both the lower bump structure and the first sidewall barrier structure 126. In some other embodiments, the lower surface of the upper bump structure 124 may be substantially flat. In some other embodiments, the upper bump structure 124 may include, for example, gold (Au), platinum (Pt), some other suitable metal, or a combination of the foregoing materials. In some other embodiments, the lower surface of the upper bump structure 124 is the lowest surface of the upper bump structure 124.

[0053] In some embodiments, the outer sidewall of the upper bump structure 124 is connected to the first upper portion of the outer sidewall of the second dielectric structure 118. In some other embodiments, the outer sidewall of the upper bump structure 124 is disposed inside the outer sidewall of the upper conductive pad 114p. The outer sidewall of the upper bump structure 124 may be substantially vertical. In some other embodiments, the outer sidewall of the upper bump structure 124 is substantially aligned with the outer sidewall of the first sidewall barrier structure 126.

[0054] In some embodiments, the upper surface of the upper bump structure 124 is substantially coplanar with the upper surface of the second dielectric structure 118. In some other embodiments, the lower surface of the upper bump structure 124 is substantially flat. In some other embodiments, the height of the upper bump structure 124 (e.g., the distance between the upper surface of the upper bump structure 124 and the lower surface of the upper bump structure 124) is greater than or equal to the first distance D1.

[0055] In some embodiments, the outermost periphery of the upper bump structure 124 is disposed within the outermost periphery of the upper conductive pad 114p. In other embodiments, the outermost periphery of the upper bump structure 124 may be at least partially disposed outside the outermost periphery of the upper conductive pad 114p. In such an embodiment, one or more outer sidewalls of the upper conductive pad 114p are disposed within the outer sidewalls of the upper bump structure 124.

[0056] Figure 3 exemplify Figure 1 The region 128 shown (see, e.g. Figure 1 ) are enlarged cross-sectional views of some other embodiments.

[0057] like Figure 3 As shown in , the upper surface of the upper bump structure 124 may be disposed below the upper surface of the second dielectric structure 118. In such an embodiment, the upper surface of the upper bump structure 124 may be spaced apart from the upper surface of the second dielectric structure 118 by less than or equal to 1,000 angstroms. If the upper surface of the upper bump structure 124 is spaced apart from the upper surface of the second dielectric structure 118 by more than The electrical connection between the overlying second conductive feature (eg, conductive line) and the upper bump structure 124 may then be unsatisfactory (eg, the resistance between the upper bump structure 124 and the overlying second conductive feature is too high).

[0058] Figure 4 exemplify Figure 1 The region 128 shown (see, e.g. Figure 1 ) are enlarged cross-sectional views of some other embodiments.

[0059] like Figure 4 As shown in , the upper surface of the lower bump structure 122 may be disposed below the upper surface of the first sidewall barrier structure 126. In some embodiments, the upper bump structure 124 has a first outer sidewall that is connected to the first upper portion of the inner sidewall of the second dielectric structure 118 and a second outer sidewall that is connected to the inner sidewall of the first sidewall barrier structure 126. The second outer sidewall of the upper bump structure 124 partially extends vertically along the inner sidewall of the first sidewall barrier structure 126. The second outer sidewall of the upper bump structure 124 is disposed between the first outer sidewalls of the upper bump structure 124. In some further embodiments, the upper bump structure 124 has a first lower surface that is connected to the upper surface of the lower bump structure 122 and a second lower surface that is connected to the upper surface of the first sidewall barrier structure 126. The second lower surface of the upper bump structure 124 is disposed above the first lower surface of the upper bump structure 124. In still other embodiments, the second lower surface of the upper bump structure 124 extends in a continuous closed path in the lateral direction around the first lower surface of the upper bump structure 124 .

[0060] Figure 5 exemplify Figure 1 The region 128 shown (see, e.g. Figure 1 ) are enlarged cross-sectional views of some other embodiments.

[0061] like Figure 5As shown in , the lower bump structure 122 may be partially disposed on the first sidewall barrier structure 126. In some embodiments, the upper surface of the lower bump structure 122 has a first recessed portion and a first annular portion. The first annular portion extends around the first recessed portion in a continuous closed path in the lateral direction. In some embodiments, the first annular portion is directly disposed on the first sidewall barrier structure 126. In some other embodiments, the lowest point of the first recessed portion is disposed above the upper surface of the first sidewall barrier structure 126. In other embodiments, the lowest point of the first recessed portion is disposed below the upper surface of the first sidewall barrier structure 126.

[0062] In some embodiments, the lower surface of the upper bump structure 124 has a second recessed portion and a second annular portion. The second recessed portion is connected to the first recessed portion, and the second annular portion is connected to the first annular portion. The second annular portion extends around the second recessed portion in a continuous closed path in the lateral direction. In some embodiments, the second annular portion is directly disposed on the first annular portion. In some other embodiments, the lowest point of the second recessed portion is disposed above the upper surface of the first sidewall blocking structure 126. In other embodiments, the lowest point of the second recessed portion is disposed below the upper surface of the first sidewall blocking structure 126.

[0063] In some embodiments, the upper surface of the upper bump structure 124 has a third recessed portion and a third annular portion. The third annular portion extends around the third recessed portion in a continuous closed path in the lateral direction. In some embodiments, the third annular portion is disposed directly above the first annular portion and / or the second annular portion. The lowest point of the third recessed portion is disposed below the upper surface of the second dielectric structure 118.

[0064] The uppermost point of the third annular portion is disposed at the uppermost point of the second dielectric structure 118 or below the uppermost point of the second dielectric structure 118. Since the uppermost point of the third annular portion is disposed at the uppermost point of the second dielectric structure 118 or below the uppermost point of the second dielectric structure 118, the upper bump structure 124 does not have a "fence" structure 502 (illustrated in dashed lines to provide additional context) extending above the upper surface of the second dielectric structure 118. Therefore, the bump structure 120 can improve the bonding ability of the IC 100 with a transparent screen panel (e.g., a glass screen panel) and / or a carrier substrate (e.g., a carrier wafer). In other words, if the bump structure 120 has a "fence" structure 502, the "fence" structure 502 will be a high stress point, which will negatively affect the bonding ability of the IC 100 with the transparent screen panel and / or the carrier substrate (e.g., the transparent screen panel is cracked / broken / delaminated due to the high stress point). In some embodiments, the uppermost point of the third annular portion is not disposed above the uppermost point of the second dielectric structure 118. Since the uppermost point of the third annular portion is not disposed above the uppermost point of the second dielectric structure 118, the upper bump structure 124 does not have a “fence” structure 502 extending above the upper surface of the second dielectric structure 118. Therefore, the bump structure 120 can improve the bonding capability of the IC 100 with a transparent screen panel (e.g., a glass screen panel) and / or a carrier substrate (e.g., a carrier wafer).

[0065] Figure 6 exemplify Figure 1 Cross-sectional views of some other embodiments of IC 100 are shown.

[0066] like Figure 6 As shown in , IC 100 may include a plurality of bump structures disposed on an interconnect structure 114 and an ILD structure 112. A bump structure of the plurality of bump structures is electrically coupled to the interconnect structure 114. In some embodiments, the bump structures of the plurality of bump structures are electrically coupled to the interconnect structure 114 through a plurality of upper conductive pads, respectively. Each of the bump structures of the plurality of bump structures includes a lower bump structure 122, an upper bump structure 124, and a first sidewall barrier structure 126. It should be understood that in some embodiments, the bump structure 120 is the only bump structure disposed on the IC 100 (e.g., the IC 100 includes only one bump structure).

[0067] Figure 7 exemplify Figure 1 Cross-sectional views of some other embodiments of IC 100 are shown.

[0068] like Figure 7As shown in FIG, IC 100 includes a carrier substrate 702 disposed over the bump structure 120, the ILD structure 112, and the semiconductor substrate 102. The carrier substrate 702 may be bonded to the second dielectric structure 118 and / or the upper bump structure 124. In some embodiments, the carrier substrate 702 may be, for example, a polyimide substrate, a semiconductor substrate, etc. Since the IC 100 includes the bump structure 120, there is an improved bonding interface between the carrier substrate 702 and the IC 100, thereby improving yield (e.g., by preventing damage to the IC 100 during bonding of the IC 100 to the carrier substrate 702).

[0069] Figure 8 exemplify Figure 1 Cross-sectional views of some other embodiments of IC 100 are shown.

[0070] like Figure 8 As shown in , IC 100 includes a screen panel 802 disposed on a bump structure 120, an ILD structure 112, and a semiconductor substrate 102. The screen panel 802 is bonded to the IC 100. The screen panel includes a transparent bonding layer 804 (e.g., silicone gel, urethane, or some other suitable adhesive) and a transparent cover structure 806 (e.g., cover glass, touch screen, etc.). The transparent bonding layer 804 is disposed between the transparent cover structure 806 and the bump structure 120 and between the transparent cover structure 806 and the second dielectric structure 118. Since the IC 100 includes the bump structure 120, there is an improved bonding interface between the screen panel 802 and the IC 100, thereby improving the yield (e.g., by preventing damage to the IC 100 and / or the screen panel 802 during the bonding of the IC 100 to the screen panel 802).

[0071] Fig. 9 Examples include Figure 1 Some embodiments of IC 100 are shown in cross-sectional views of some embodiments of display device 900 .

[0072] like Fig. 9As shown in , the display device 900 includes the IC 100 and a plurality of light-emitting ICs 902a, 902b, 902c. For example, the display device includes a first light-emitting IC 902a, a second light-emitting IC 902b, and a third light-emitting IC 902c. The light-emitting ICs 902a-902c include one or more light-emitting structures 904a, 904b, 904c (e.g., light-emitting diodes (LEDs), micro-LEDs, etc.). For example, the first light-emitting IC 902a includes a first light-emitting structure 904a, the second light-emitting IC 902b includes a second light-emitting structure 904b, and the third light-emitting IC 902c includes a third light-emitting structure 904c. The light-emitting ICs 902a-902c may include one or more semiconductor devices (for ease of description, the light-emitting ICs 902a-902c are shown in FIG. 1 ). Fig. 9 The one or more semiconductor devices are arranged on a semiconductor substrate (for ease of description, Fig. 9 ) and electrically coupled to the one or more light emitting structures 904a-904c.

[0073] The one or more light emitting structures 904a-904c are configured to emit light having a specific wavelength, which passes through the screen panel 802 (e.g., by Fig. 9 ). In some embodiments, the light emitted by the one or more light emitting structures 904a-904c is colored light. For example, the first light emitting structure 904a is configured to emit red light, the second light emitting structure 904b is configured to emit green light, and the third light emitting structure 904c is configured to emit blue light.

[0074] IC 100 and the plurality of light emitting ICs 902a-902c are bonded to screen panel 802. Because IC 100 includes bump structure 120, there is an improved bonding interface between screen panel 802 and IC 100. For example, because upper bump structure 124 does not have a "fence" structure 502 extending above the upper surface of second dielectric structure 118 (see, e.g., Figure 5), so the bonding interface between IC 100 and screen panel 802 is improved. The improved bonding interface can improve the robustness of display device 900 (e.g., screen panel 802 resists cracking / shattering / delamination in response to a given mechanical force applied to transparent cover structure 806) and / or improve the yield of display device 900. For example, because bump structure 120 reduces high stress points that may cause cracking / shattering / delamination of screen panel 802 during manufacture of display device 900 (or during consumer use) (e.g., because the reduction of high stress points increases the amount of mechanical force that can be applied to transparent cover structure 806 before screen panel 802 cracks / shatters / delaminates), the improved bonding interface can improve the robustness of display device 900 and / or the yield of display device 900.

[0075] In some embodiments, one or more second conductive features 906 (e.g., wires) are disposed in the transparent cover structure 806. The one or more second conductive features 906 are configured to electrically couple the light-emitting ICs 902a-902c to the IC 100. In some embodiments, the transparent bonding layer 804 is configured to provide electrical connections (via the one or more second conductive features 906, the IC 100, and the light-emitting ICs 902a-902c) between the IC 100 and the light-emitting ICs 902a-902c. Fig. 9 In some other embodiments, the bump structure 120 is electrically coupled to the one or more second conductive features 906. In some other embodiments, the input / output (I / O) structure (for ease of illustration, in FIG. Fig. 9 ) is electrically coupled to the one or more second conductive features 906. It should be understood that in some embodiments, a filling material is disposed between the IC 100 and the light-emitting ICs 902a-902c to provide structural support between the IC 100 and the light-emitting ICs 902a-902c.

[0076] In some embodiments, IC 100 includes control circuitry for display device 900. For example, the control circuitry is configured to provide electrical signals (e.g., voltages) to light-emitting ICs 902a-902c so that display device 900 displays a desired image. In still other embodiments, IC 100 does not include any light-emitting structures. In such embodiments, IC 100 may include only circuitry for controlling light-emitting ICs 902a-902c.

[0077] FIG. 10A to FIG. 10B Show Fig. 9 Various views of some other embodiments of display device 900 are shown. Fig. 10A exemplify Fig. 9Isometric views of some other embodiments of display devices are shown. Fig. 10B Example of edge Fig. 10A The line AA intercepts Fig. 10A Cross-sectional views of some embodiments of display devices are shown.

[0078] like FIG. 10A to FIG. 10B As shown in FIG. 1 , IC 100 and light emitting ICs 902a-902c may be arranged in an array (e.g., a 5×5 array). In some embodiments, IC 100 may be arranged at the center of the array. It should be understood that in other embodiments, IC 100 may be arranged anywhere in the array (or outside the array). It should also be understood that display device 900 may include arrays of other sizes (e.g., a 4×4 array, a 7×7 array, etc.). IC 100 is electrically coupled to the light emitting ICs 902a-902c of the array (e.g., via one or more second conductive features 906 (for clarity, FIG. 10A to FIG. 10B ). IC 100 is configured to provide an electrical signal (eg, voltage) to each of light emitting ICs 902a-902c so that display device 900 displays a desired image.

[0079] The screen panel 802 extends continuously over the IC 100 and the light-emitting ICs 902a-902c. Each of the light-emitting ICs 902a-902c and the IC 100 are bonded to the screen panel 802. It should be understood that the display device 900 may include any number of arrays, each of which includes the IC 100 and the light-emitting ICs 902a-902c bonded to the screen panel 802. For example, the display device may include a first array and a second array, the first array including a first IC (e.g., IC 100) and a first plurality of light-emitting ICs (e.g., light-emitting ICs 902a-902c), the second array being disposed on one side of the first array and including a second IC (e.g., IC 100) and a second plurality of light-emitting ICs (e.g., light-emitting ICs 902a-902c). The first IC is configured to control the first plurality of light-emitting ICs, and the second IC is configured to control the second plurality of light-emitting ICs. Depending on the desired display size of the display device 900, the display device 900 includes a predetermined number of arrays arranged in a larger array so that the display device 900 has the desired display size (e.g., 1.5", 1.7", 5.8", 6.1", 6.5", 10.2", 10.5", 12.9", 15.4", 17", 35", 42", 48", 55", 65", 75", etc.).

[0080] FIG. 11A to FIG. 11B to FIG. 24A to FIG. 24B Shown to form Figure 1A series of cross-sectional views of some embodiments of methods of some embodiments of the illustrated IC 100. Figures suffixed with "A" (e.g., Fig.11A ) exemplifies the formation of Figure 1 A series of cross-sectional views of some embodiments of methods of some embodiments of the illustrated IC 100. Figures suffixed with "B" (e.g., Fig. 11B ) shows a series of enlarged cross-sectional views of the area of ​​the corresponding figure with the suffix "A". For example, Fig. 11B Show Fig.11A An enlarged cross-sectional view of region 128 is shown, Fig. 12B Show Fig. 12A An enlarged cross-sectional view of area 128 is shown, and so on.

[0081] like Fig.11A , Fig. 11B As shown in , a workpiece 1102 is received. The workpiece 1102 includes a semiconductor substrate 102. One or more semiconductor devices 104 are disposed on / in the semiconductor substrate 102. An ILD structure 112 is disposed above the semiconductor substrate and the one or more semiconductor devices 104. An interconnect structure 114 is embedded in the ILD structure 112, and the interconnect structure 114 is disposed above the semiconductor substrate 102. The interconnect structure 114 includes an upper conductive pad 114p.

[0082] In some embodiments, the method of forming the workpiece 1102 includes the following process. The one or more semiconductor devices 104 are formed by forming a pair of source / drain regions in the semiconductor substrate 102 (for example, by ion implantation). Thereafter, a gate dielectric and a gate electrode are formed on the semiconductor substrate 102 and between the pair of source / drain regions (for example, by a deposition / growth process and an etching process). A first ILD layer is then formed on the one or more semiconductor devices 104, and a contact opening is formed in the first ILD layer. A conductive material (for example, W) is formed on the first ILD layer and in the contact opening. Thereafter, a planarization process (for example, chemical-mechanical polishing (CMP)) is performed on the conductive material to form a conductive contact (for example, a metal contact) in the first ILD layer.

[0083] A second ILD layer is then formed over the first ILD layer and the conductive contacts, and a first conductive trench is formed in the second ILD layer. A conductive material (e.g., Cu) is formed on the second ILD layer and in the first conductive trench. Thereafter, a planarization process (e.g., CMP) is performed on the conductive material to form a conductive wire (e.g., Metal 1) in the second ILD. A third ILD layer is then formed over the second ILD layer and the conductive wire, and a via opening is formed in the third ILD layer. A conductive material (e.g., Cu) is formed on the third ILD layer and in the via opening. Thereafter, a planarization process (e.g., CMP) is performed on the conductive material to form a via (e.g., metal through hole) in the third ILD layer. The above process for forming the conductive wire and the via may be repeated any number of times to form the ILD structure 112 and the interconnect structure 114 embedded in the ILD structure 112.

[0084] Likewise FIG. 11A to FIG. 11B As shown in FIG. 1 , a first dielectric layer 1104 is formed on the semiconductor substrate 102, the ILD structure 112, and the interconnect structure 114. The first dielectric layer 1104 covers the upper conductive pad 114p. In some embodiments, the first dielectric layer 1104 includes a nitride (e.g., SiN), an oxide (e.g., SiO2), an oxynitride (e.g., SiO X N Y ), some other dielectric material, or a combination of the foregoing materials. In some other embodiments, the first dielectric layer 1104 is SiN. The first dielectric layer 1104 can be formed by depositing the first dielectric layer 1104 on the ILD structure 112 and the upper conductive pad 114p. In some embodiments, the first dielectric layer 1104 can be deposited by, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), some other deposition process, or a combination of the foregoing processes.

[0085] Likewise FIG. 11A to FIG. 11B As shown in FIG. 1 , a second dielectric layer 1106 is formed on the first dielectric layer 1104. In some embodiments, the second dielectric layer 1106 includes an oxide (e.g., SiO 2 ), a nitride (e.g., SiN), an oxynitride (e.g., SiO X N Y), some other dielectric material, or a combination of the foregoing materials. In yet other embodiments, the second dielectric layer 1106 is SiO2. The second dielectric layer 1106 can be formed by depositing the second dielectric layer 1106 on the first dielectric layer 1104. In some embodiments, the second dielectric layer 1106 can be deposited by, for example, CVD, PVD, ALD, some other deposition process, or a combination of the foregoing processes.

[0086] like FIG. 12A to FIG. 12B As shown in , a second dielectric structure 118 is formed on the first dielectric layer 1104. The second dielectric structure 118 is formed with inner sidewalls spaced apart in the lateral direction. In some embodiments, the inner sidewalls of the second dielectric structure 118 are disposed within the outermost periphery of the upper conductive pad 114p. In other embodiments, one or more inner sidewalls of the second dielectric structure 118 are disposed outside the outermost periphery of the upper conductive pad 114p. In still other embodiments, the inner sidewalls of the second dielectric structure are substantially vertical.

[0087] In some embodiments, the process for forming the second dielectric structure 118 includes forming a second dielectric layer 1106 (see, e.g., Fig.11A , Fig. 11B ) is formed on the first dielectric layer 1104. In some other embodiments, the patterned mask layer can be formed by: forming a mask layer (not shown) on the second dielectric layer 1106; exposing the mask layer to a pattern (e.g., by photolithography); and developing the mask layer to form a patterned mask layer. Thereafter, with the patterned mask layer in place, an etching process (e.g., wet / dry etching) is performed on the second dielectric layer 1106 to remove the unmasked portions of the second dielectric layer 1106, thereby forming a second dielectric structure 118. The second dielectric structure 118 corresponds to the portion of the second dielectric layer 1106 that remains on the first dielectric layer 1104 after the etching process is performed on the second dielectric layer 1106. Subsequently, the patterned mask layer can be stripped.

[0088] After forming the second dielectric structure 118, a third opening 1202 is disposed in the second dielectric structure 118 and above the upper conductive pad 114p. The third opening 1202 is defined by a first central portion of the upper surface of the first dielectric layer 1104 and the inner sidewalls of the second dielectric structure 118. The first central portion of the upper surface of the first dielectric layer 1104 is disposed directly between the inner sidewalls of the second dielectric structure 118. In some embodiments, the uppermost boundary of the third opening 1202 is disposed at (or below) the upper surface of the second dielectric structure 118. In yet other embodiments, the third opening 1202 is formed with an outermost periphery disposed within an outermost periphery of the upper conductive pad 114p. In other embodiments, the third opening 1202 is formed such that the outermost periphery of the third opening 1202 is at least partially formed outside the outermost periphery of the upper conductive pad 114p.

[0089] like Fig.13A , Fig. 13B As shown in , a barrier layer 1302 is formed over the second dielectric structure 118 and the first dielectric layer 1104. The barrier layer 1302 is formed to line the sidewalls of the third opening 1202, the first central portion of the upper surface of the first dielectric layer 1104, and the upper surface of the second dielectric structure 118. In some embodiments, the barrier layer 1302 may include, for example, Ti, TiN, some other material sufficient to block atoms from diffusing from the upper conductive pad 114p to the upper bump structure 124, or a combination of the foregoing materials. The barrier layer 1302 may be formed as a conformal layer. In yet other embodiments, the process for forming the barrier layer 1302 includes: depositing the barrier layer 1302, the barrier layer 1302 being located on the second dielectric structure 118, on the first dielectric layer 1104, and lining the sidewalls of the third opening 1202. The barrier layer 1302 may be deposited by, for example, CVD, PVD, ALD, sputtering, some other deposition process, or a combination of the foregoing processes.

[0090] like Fig.14A , Fig. 14B As shown in , a second sidewall barrier structure 1402 is formed along the sidewall of the third opening 1202. In some embodiments, the second sidewall barrier structure 1402 is formed to have a height substantially the same as that of the third opening 1202. In some other embodiments, the process for forming the second sidewall barrier structure 1402 includes: Fig.13A , Fig. 13B ) performs an etching process to remove the barrier layer 1302 from the horizontal surface, leaving the barrier layer 1302 along the sidewall of the third opening 1202 as a second sidewall barrier structure 1402.

[0091] like Fig.15A , Fig. 15BAs shown in FIG. 1 , a hard mask layer 1502 is formed over the second dielectric structure 118, the first dielectric layer 1104, and the second sidewall barrier structure 1402. The hard mask layer 1502 is at least partially formed in the third opening 1202 and lines the inner sidewalls of the second sidewall barrier structure 1402. The hard mask layer 1502 has a first density and the second dielectric structure 118 has a second density less than the first density. In some embodiments, the hard mask layer 1502 is a conformal layer. The hard mask layer 1502 may be or include, for example, an oxide (e.g., SiO2), a nitride (e.g., SiN), an oxynitride (e.g., SiO X N Y ) etc. In some other embodiments, the hard mask layer is SiO2. In some other embodiments, the hard mask layer 1502 is a high-temperature oxide (HTO) (e.g., SiO2 formed by a high-temperature deposition / growth process). The hard mask layer 1502 may be formed to a thickness of less than or equal to 100 angstroms.

[0092] In some embodiments, the process for forming the hard mask layer 1502 includes depositing the hard mask layer 1502 on the second dielectric structure 118, on the first dielectric layer 1104, and on the inner sidewalls of the second sidewall barrier structure 1402. The hard mask layer 1502 can be deposited by, for example, CVD, PVD, ALD, sputtering, some other deposition process, or a combination of the foregoing processes. In some other embodiments, the hard mask layer is formed in a process chamber at a temperature higher than 400° C.

[0093] like Fig.16A , Fig. 16B As shown in FIG. 1 , a first mask structure 1602 is formed over the hard mask layer 1502 and the second dielectric structure 118. The first mask structure 1602 is formed in the third opening 1202 (see, for example, Fig.15A , Fig. 15B ). In some embodiments, the first mask structure 1602 completely fills the third opening 1202. The first mask structure 1602 may be formed to have a substantially flat upper surface disposed above the upper surface of the hard mask layer 1502. In some embodiments, the first mask structure 1602 may include, for example, a positive photoresist, a negative photoresist, etc. In yet other embodiments, the upper surface of the first mask structure 1602 is the uppermost surface of the first mask structure 1602. In yet other embodiments, the upper surface of the hard mask layer 1502 is the uppermost surface of the hard mask layer 1502.

[0094] In some embodiments, the process for forming the first mask structure 1602 includes depositing a mask layer (not shown) (e.g., a positive photoresist, a negative photoresist, etc.) on the hard mask layer 1502 and filling the third opening 1202. The mask layer can be deposited by CVD, PVD, ALD, a spin coating process, a spray coating process, a roller coating process, a dip coating process, some other deposition process, or a combination of the foregoing processes. The mask layer is then exposed to electromagnetic radiation (e.g., ultraviolet (UV) light) to form the first mask structure 1602. In some embodiments, the mask layer can be exposed to a pattern of electromagnetic radiation (e.g., by photolithography) and then the mask layer is developed to form the first mask structure 1602 having a pattern.

[0095] like Fig.17A , Fig. 17B As shown in , a second mask structure 1702 is formed over the first dielectric layer 1104 and in the second dielectric structure 118. The second mask structure 1702 is formed directly between the inner sidewalls of the second sidewall barrier structure 1402. In some embodiments, the second mask structure 1702 is formed to have an upper surface disposed below the upper surface of the second dielectric structure 118. In still other embodiments, the second mask structure 1702 is formed directly above the upper conductive pad 114p. In still other embodiments, the upper surface of the second mask structure 1702 is the uppermost surface of the second mask structure 1702.

[0096] In some embodiments, the process for forming the second mask structure 1702 includes: Fig.16A , Fig. 16B ) performs a first etching process 1704 (e.g., a wet / dry etching process). The first etching process 1704 removes an upper portion of the first mask structure 1602, thereby leaving a lower portion of the first mask structure 1602 between the inner sidewalls of the second sidewall blocking structure 1402 as the second mask structure 1702. In some embodiments, the first etching process 1704 is a dry etching process (e.g., reactive ion etching). In some other embodiments, the first etching process 1704 may be a dry etching process (e.g., oxygen plasma etching, oxygen plasma ashing, etc.) using oxygen as a processing gas (and / or etchant).

[0097] like Fig.18A , Fig.18BAs shown in FIG. 1 , a hard mask structure 1802 is formed over the first dielectric layer 1104 and in the second dielectric structure 118. The hard mask structure 1802 is formed directly between the inner sidewalls of the second sidewall barrier structure 1402 and separates the second mask structure 1702 from the second sidewall barrier structure 1402. In some embodiments, the hard mask structure 1802 is formed to have an upper surface that is substantially coplanar with an upper surface of the second mask structure 1702. In other embodiments, the hard mask structure 1802 is formed such that the upper surface of the hard mask structure 1802 is disposed above (or below) the upper surface of the second mask structure 1702. In yet other embodiments, the upper surface of the hard mask structure 1802 is the uppermost surface of the hard mask structure 1802.

[0098] In some embodiments, the process for forming the hard mask structure 1802 includes: Fig.17A , Fig. 17B ) performs a second etching process 1804 (e.g., a wet / dry etching process). The second etching process 1804 removes an upper portion of the hard mask layer 1502, thereby leaving a lower portion of the hard mask layer 1502 that separates the second mask structure 1702 from the second sidewall blocking structure 1402 as the hard mask structure 1802.

[0099] In some embodiments, the second etching process 1804 is a wet etching process. In some other embodiments, the second etching process 1804 is a wet etching process using hydrofluoric acid (HF) as an etchant. In such an embodiment, the wet etching process includes exposing the hard mask layer 1502 to a first solution containing HF. The first solution may have a concentration of about one percent HF. It should be understood that the first solution may have a different HF concentration (e.g., HF greater than / less than about one percent). In some other such embodiments, the hard mask layer 1502 is exposed to the first solution for a first time interval. In some other such embodiments, the first time interval may be about 60 seconds. If the first time interval is about 60 seconds, the height of the hard mask structure 1802 may be controlled so that the upper surface of the hard mask structure 1802 is substantially coplanar with the upper surface of the second mask structure 1702; if the first time interval is greater than / less than about 60 seconds, the height of the hard mask structure 1802 may be reduced / increased so that the upper surface of the hard mask structure 1802 is disposed below / above the upper surface of the second mask structure 1702. It should be understood that the first time interval may be any time interval sufficient to form the hard mask structure 1802 having a predetermined height (e.g., greater than 60 seconds).

[0100] like Fig.19A , Fig.19BAs shown in FIG. 1 , a first sidewall barrier structure 126 is formed over the first dielectric layer 1104 and in the second dielectric structure 118. The first sidewall barrier structure 126 is formed directly between the inner sidewalls of the second dielectric structure 118 and separates the hard mask structure 1802 from the inner sidewalls of the second dielectric structure 118. In some embodiments, the first sidewall barrier structure 126 is formed to have a substantially flat upper surface.

[0101] The first sidewall barrier structure 126 is formed to vertically extend a first distance D1 from the upper surface of the first dielectric layer 1104 toward the upper surface of the second dielectric structure 118. The upper surface of the second dielectric structure 118 is vertically spaced apart from the upper surface of the first dielectric layer 1104 by a second distance D2. The first distance D1 is less than the second distance D2. In some embodiments, the first distance D1 is between ten percent and fifty percent of the second distance D2.

[0102] In some embodiments, the process for forming the first sidewall barrier structure 126 includes forming the second sidewall barrier structure 1402 (see, for example, Fig.18A , Fig.18B ) performs a third etching process 1903 (e.g., a dry / wet etching process). The third etching process 1903 removes an upper portion of the second sidewall blocking structure 1402, thereby forming a first sidewall blocking structure 126. In some embodiments, the third etching process reduces the height of the second sidewall blocking structure 1402 by between fifty percent and ninety percent, thereby forming the first sidewall blocking structure 126. The height of the hard mask structure 1802 and / or the height of the second mask structure 1702 provide a way to control the third etching process 1903, thereby allowing the first sidewall blocking structure 126 to be formed to extend vertically from the upper surface of the first dielectric layer 1104 toward the upper surface of the second dielectric structure 118 by a first distance D1.

[0103] In some embodiments, the third etching process 1903 is a wet etching process. In some other embodiments, the third etching process 1903 is a wet etching process using hydrogen peroxide (H2O2) as an etchant. In such an embodiment, the wet etching process includes exposing the second sidewall blocking structure 1402 to a second solution containing H2O2. The second solution has a different chemical composition from the first solution. The second solution may have a concentration of about thirty percent H2O2. It should be understood that the second solution may contain different concentrations of H2O2 (e.g., greater than / less than about thirty percent H2O2). In some other such embodiments, the second sidewall blocking structure 1402 is exposed to the second solution for a second time interval. In some other such embodiments, the second time interval may be about thirty seconds. If the second time interval is about 30 seconds, the first sidewall barrier structure 126 is formed to vertically extend the first distance D1 from the upper surface of the first dielectric layer 1104 toward the upper surface of the second dielectric structure 118; if the second time interval is greater than / less than about thirty seconds, the first sidewall barrier structure 126 is formed to vertically extend a third distance not equal to the first distance D1 from the upper surface of the first dielectric layer 1104 toward the upper surface of the second dielectric structure 118. It should be understood that the second time interval may be any time interval sufficient to form the first sidewall barrier structure 126 vertically extending the first distance D1 from the upper surface of the first dielectric layer 1104 toward the upper surface of the second dielectric structure 118 (e.g., greater than / less than thirty seconds).

[0104] Likewise Fig.19A , Fig.19B , the third mask structure 1904 is formed directly between the inner sidewalls of the hard mask structure 1802. In some embodiments, the third mask structure 1904 is formed to have an upper surface disposed below the upper surface of the hard mask structure 1802. In yet other embodiments, the upper surface of the third mask structure 1904 is the uppermost surface of the third mask structure 1904.

[0105] Likewise Fig.19A , Fig.19B As shown in FIG. 1 , a crevice 1906 is formed between the third mask structure 1904 and the hard mask structure 1802. The crevice 1906 is a void of material disposed between the third mask structure 1904 and the hard mask structure 1802. In some embodiments, the sidewalls of the crevice 1906 are defined by the outer sidewalls of the third mask structure 1904 and the inner sidewalls of the hard mask structure 1802. In still other embodiments, the crevice 1906 at least partially extends from the upper surface of the third mask structure 1904 to the lower surface of the third mask structure 1904. In other embodiments, the crevice 1906 completely extends from the upper surface of the third mask structure 1904 to the lower surface of the third mask structure 1904. In still other embodiments, the crevice 1906 laterally surrounds the third mask structure 1904.

[0106] In some embodiments, the process for forming the third mask structure 1904 and the slit 1906 includes performing a third etching process on the second mask structure 1702. The third etching process 1903 removes an upper portion of the second mask structure 1702 and an outer portion of the second mask structure 1702, thereby forming the third mask structure 1904. Since the third etching process 1903 removes the outer portion of the second mask structure 1702, the slit 1906 is formed between the third mask structure 1904 and the hard mask structure 1802.

[0107] Furthermore, because the third etching process 1903 is performed with the hard mask structure 1802 and the second mask structure 1702 in place over the first dielectric layer 1104, a gap 1906 is formed between the hard mask structure 1802 and the third mask structure 1904. If the hard mask structure 1802 is not in place, the gap 1906 may be formed between the second mask structure 1702 and the first sidewall barrier structure 126. If the gap 1906 is between the second mask structure 1702 and the first sidewall barrier structure 126, a portion of the first dielectric layer 1104 may be unintentionally removed, thereby increasing manufacturing costs without adding benefits.

[0108] like Fig. 20A , Fig. 20B As shown in , the third mask structure 1904 is removed (see, e.g. Fig.19A , Fig.19B ). The third mask structure 1904 is removed from the hard mask structure 1802. In some embodiments, the process for removing the third mask structure 1904 includes performing a fourth etching process 2002 (e.g., a wet / dry etching process) on the third mask structure 1904. In some further embodiments, the fourth etching process 2002 is a dry etching process (e.g., reactive ion etching). In some further embodiments, the fourth etching process 2002 may be a dry etching process (e.g., oxygen plasma etching, oxygen plasma ashing, etc.) using oxygen as a processing gas (and / or etchant).

[0109] like Fig.21A , Fig.21B As shown in , the hard mask structure 1802 is removed (see, e.g. Fig. 20A , Fig. 20B ). The hard mask structure 1802 is removed from the first sidewall blocking structure 126 and the first dielectric layer 1104. In some embodiments, the process for removing the hard mask structure 1802 includes performing a fifth etching process 2102 (eg, a wet / dry etching process) on the hard mask structure 1802.

[0110] In some embodiments, the fifth etching process 2102 is a wet etching process. In some other embodiments, the fifth etching process 2102 is a wet etching process using HF as an etchant. In such an embodiment, the wet etching process includes exposing the third mask structure 1904 to a third solution containing HF. The third solution may have a concentration of about one percent HF. It should be understood that the third solution may have a different HF concentration (e.g., HF is greater than / less than about one percent). The third solution may have the same chemical composition as the first solution. In other embodiments, the third solution may have a different chemical composition from the first solution (e.g., different concentrations of HF). In some other such embodiments, the third mask structure 1904 is exposed to the third solution for a third time interval. In some other such embodiments, the third time interval is substantially the same as the first time interval. In other embodiments, the third time interval may be greater than (or less than) the first time interval. It should be understood that in some embodiments, the third mask structure 1904 and the hard mask structure 1802 can be removed by the same etching process.

[0111] After removing the third mask structure 1904 and the hard mask structure 1802, a fourth opening 2104 is provided in the second dielectric structure 118 and on the upper conductive pad 114p. The fourth opening 2104 is defined by a first upper portion of the inner sidewall of the second dielectric structure 118, an upper surface of the first sidewall barrier structure 126, an inner sidewall of the first sidewall barrier structure 126, and a second central portion of the upper surface of the first dielectric layer 1104. The second central portion of the upper surface of the first dielectric layer 1104 is directly disposed between the inner sidewalls of the first sidewall barrier structure 126. The fourth opening 2104 has a lower region and an upper region disposed above the lower region. In some embodiments, the lower region of the fourth opening 2104 is defined by the inner sidewall of the first sidewall barrier structure 126 and the second central portion of the upper surface of the first dielectric layer 1104. In some other embodiments, the upper region of the fourth opening 2104 is defined by the first upper portion of the inner sidewall of the second dielectric structure 118 and the upper surface of the first sidewall barrier structure 126. In some other embodiments, the uppermost boundary of the upper region of the fourth opening 2104 is disposed at (or below) the upper surface of the second dielectric structure 118. In some other embodiments, the uppermost boundary of the lower region of the fourth opening 2104 is disposed at (or below) the upper surface of the first sidewall barrier structure 126.

[0112] like Fig.22A , Fig. 22BAs shown in FIG. 1 , a first dielectric structure 116 is formed between the second dielectric structure 118 and the ILD structure 112. The first dielectric structure 116 is also formed between the first sidewall barrier structure 126 and the upper conductive pad 114p. The first dielectric structure 116 is formed to have inner sidewalls spaced apart in the lateral direction. In some embodiments, the inner sidewalls of the first dielectric structure 116 are substantially aligned with the inner sidewalls of the first sidewall barrier structure 126. In still other embodiments, the inner sidewalls of the first dielectric structure 116 are substantially vertical.

[0113] In some embodiments, the process for forming the first dielectric structure 116 includes: Fig.21A , Fig.21B ) is performed an etching process (e.g., a dry / wet etching process). The process for forming the first dielectric structure 116 removes a central region of the first dielectric layer 1104, thereby forming the first dielectric structure 116. The central region of the first dielectric layer 1104 is at least partially disposed between the inner sidewalls of the first sidewall barrier structure 126. In yet other embodiments, during the etching process, the second dielectric structure 118 and the first sidewall barrier structure 126 are used as mask structures so that the etching process removes the central region of the first dielectric layer 1104, thereby leaving the masked portion of the first dielectric layer 1104 in place as the first dielectric structure 116.

[0114] After forming the first dielectric structure 116, a fifth opening 2202 is disposed in the first dielectric structure 116 and between the fourth opening 2104 and the upper conductive pad 114p. The fifth opening 2202 is defined by a third central portion of the upper surface of the upper conductive pad 114p and an inner sidewall of the first dielectric structure 116. In some embodiments, the uppermost boundary of the fifth opening 2202 is disposed at (or below) the upper surface of the first dielectric structure 116. In some embodiments, the outer periphery of the fifth opening 2202 is disposed within the outer periphery of the fourth opening 2104.

[0115] like Fig.23A , Fig. 23BAs shown in , a lower bump structure 122 is formed on the ILD structure 112 and the upper conductive pad 114p. In some embodiments, the lower bump structure 122 is formed on the upper conductive pad 114p. The lower bump structure 122 is formed between the inner sidewalls of the first dielectric structure 116 and between the inner sidewalls of the first sidewall barrier structure 126. In some embodiments, the lower bump structure 122 is formed to have an upper surface that is substantially coplanar with the upper surface of the first sidewall barrier structure 126. In other embodiments, the lower bump structure 122 is formed so that the upper surface of the lower bump structure 122 is disposed above (or below) the upper surface of the first sidewall barrier structure 126. In still other embodiments, the lower bump structure 122 is formed to contact the upper surface of the upper conductive pad 114p, the inner sidewall of the first dielectric structure 116, and the inner sidewall of the first sidewall barrier structure 126. In yet other embodiments, the lower bump structure 122 is formed to contact an inner sidewall of the second dielectric structure 118 .

[0116] In some embodiments, the process for forming the lower bump structure 122 includes forming a first portion of the lower bump structure 122 on the upper conductive pad 114p in the fifth opening 2202 (see, for example, FIG. 22A to FIG. 22B ) and partially depositing the first conductive material in the fourth opening 2104 (e.g., the lower area of ​​the fourth opening 2104), thereby forming a lower bump structure 122 extending vertically above the upper conductive pad 114p and toward the upper surface of the second dielectric structure 118. In some embodiments, the first conductive material may be or include, for example, Ni, Ni alloy, some other suitable metal, or a combination of the foregoing materials. The first conductive material may be deposited by, for example, CVD, PVD, ALD, sputtering, electrochemical plating, electroless plating, some other deposition process, or a combination of the foregoing processes. In some further embodiments, the first conductive material is deposited by an electroplating process.

[0117] like Fig.24A , Fig. 24BAs shown in , an upper bump structure 124 is formed over the lower bump structure 122 and the first sidewall barrier structure 126. In some embodiments, the upper bump structure 124 is formed on the lower bump structure 122 and on the first sidewall barrier structure 126. The upper bump structure 124 is formed between the inner sidewalls of the second dielectric structure 118. The upper bump structure 124 is formed to have an upper surface that is substantially coplanar with the upper surface of the second dielectric structure 118 (or disposed below the upper surface of the second dielectric structure 118). In some embodiments, the upper bump structure 124 is formed so that the upper surface of the upper bump structure 124 does not extend above the upper surface of the second dielectric structure 118. In yet other embodiments, the upper bump structure 124 is formed to contact the upper surface of the lower bump structure 122 and the inner sidewall of the second dielectric structure 118. In yet other embodiments, the upper bump structure 124 is formed to contact the upper surface of the first sidewall barrier structure 126. In still other embodiments, the upper bump structure 124 is formed to contact the inner sidewall of the first sidewall barrier 126 .

[0118] In some embodiments, the process for forming the upper bump structure 124 includes forming a first sidewall barrier structure 126 on the lower bump structure 122 and locally in the fourth opening 2104 (eg, an upper region of the fourth opening 2104 (see, for example, Fig.23A , Fig. 23B )) deposits a second conductive material to form an upper bump structure 124 located above both the lower bump structure 122 and the first sidewall barrier structure 126 and extending vertically toward the upper surface of the second dielectric structure 118. The second conductive material is different from the first conductive material. In some embodiments, the second conductive material may be or include, for example, Au, Pt, some other suitable metal, or a combination of the foregoing materials. In some further embodiments, the first conductive material is Ni and the second conductive material is Au. The second conductive material may be deposited by, for example, CVD, PVD, ALD, sputtering, electrochemical plating, electroless plating, some other deposition process, or a combination of the foregoing processes. In some further embodiments, the second conductive material is deposited by an electroplating process.

[0119] In some embodiments, the formation of the bump structure 120 is completed after the upper bump structure 124 is formed. The bump structure 120 includes a lower bump structure 122 and an upper bump structure 124. In yet other embodiments, the formation of the IC 100 is completed after the upper bump structure 124 is formed.

[0120] Fig.25 Shown to form Figure 1 Flowchart 2500 of some embodiments of methods of some embodiments of IC 100 is shown. Fig.25Flowchart 2500 is illustrated and described herein as a series of actions or events, but it should be understood that the illustrated order of these actions or events should not be interpreted as having a limiting meaning. For example, certain actions may occur in different orders and / or may occur simultaneously with other actions or events other than those illustrated and / or described herein. In addition, not all illustrated actions may be required when implementing one or more aspects or embodiments described herein, and one or more of the actions illustrated herein may be performed in one or more separate actions and / or stages.

[0121] At action 2502, a first dielectric structure is formed over a first dielectric layer and over a workpiece, wherein the workpiece includes an upper conductive pad, wherein the first dielectric layer is disposed between the first dielectric structure and the workpiece, and wherein inner sidewalls of the first dielectric structure define sidewalls of an opening disposed in the first dielectric structure and over the upper conductive pad. FIG. 11A to FIG. 11B to FIG. 12A to FIG. 12B A series of various cross-sectional views of some embodiments corresponding to act 2502 are shown.

[0122] At act 2504, a first sidewall blocking structure is formed over the first dielectric layer and along sidewalls of the opening. FIG. 13A to FIG. 13B to FIG. 14A to FIG. 14B A series of various cross-sectional views of some embodiments corresponding to act 2504 are shown.

[0123] At act 2506, a mask structure is formed over the first dielectric layer and between inner sidewalls of the first sidewall barrier structure. FIG. 15A to FIG. 15B to FIG. 17A to FIG. 17B A series of various cross-sectional views of some embodiments corresponding to act 2506 are shown.

[0124] At act 2508, a hard mask structure is formed over the first dielectric layer and between inner sidewalls of the first sidewall barrier structure, wherein the hard mask structure separates the mask structure from both the first sidewall barrier structure and the first dielectric structure. FIG. 15A to FIG. 15B to FIG. 18A to FIG. 18B A series of various cross-sectional views of some embodiments corresponding to act 2508 are shown.

[0125] At act 2510 , a second sidewall barrier structure is formed between inner sidewalls of the first dielectric structure and over the first dielectric layer by removing an upper portion of the first sidewall barrier structure. FIG. 19A to FIG. 19B Various cross-sectional views of some embodiments corresponding to act 2510 are illustrated.

[0126] At act 2512, a second dielectric structure is formed between the workpiece and the first dielectric structure and between the workpiece and the second sidewall blocking structure. FIG. 20A to FIG. 20B to FIG. 22A to FIG. 22BA series of various cross-sectional views of some embodiments corresponding to act 2512 are shown.

[0127] At act 2514, a lower bump structure is formed over the upper conductive pad, wherein the lower bump structure is electrically coupled to the upper conductive pad, and wherein the lower bump structure vertically passes through the second dielectric structure and vertically extends along an inner sidewall of the second sidewall barrier structure. FIG. 23A to FIG. 23B Various cross-sectional views of some embodiments corresponding to act 2514 are illustrated.

[0128] At activity 2516 , an upper bump structure is formed over the lower bump structure, over the second sidewall barrier structure, and between the inner sidewalls of the first dielectric structure. FIG. 24A to FIG. 24B Various cross-sectional views of some embodiments corresponding to act 2516 are shown.

[0129] FIG. 26A to FIG. 26B to FIG. 28A to FIG. 28B A series of various views showing some embodiments of a method of forming a first singulated die comprising Figure 1 Some embodiments of the IC shown. Figures with a suffix of "A" (e.g., Fig.26A ) shows a series of layout diagrams of some embodiments of a method of forming a first individualized die, the first individualized die comprising Figure 1 Some embodiments of IC 100 are shown. Figures with a suffix of "B" (e.g., Fig.26B ) shows a series of cross-sectional views of the corresponding figures with the suffix "A" taken along the line BB of the corresponding figures. For example, Fig.26B Shown along Fig.26A The line BB shown is taken Fig.26A A cross-sectional view of IC 100 is shown, Fig.27B Shown along Fig.27A The line BB shown is taken Fig.27A A cross-sectional view of IC 100 is shown, and so on.

[0130] like Fig.26A , Fig.26BAs shown in , a plurality of ICs (not labeled for ease of illustration) are disposed on a semiconductor wafer 2602. The plurality of ICs are disposed in an array on the semiconductor wafer 2602. IC 100 is one of the plurality of ICs. In some embodiments, each of the ICs in the plurality of ICs includes a bump structure (e.g., bump structure 120) at least partially disposed in a second dielectric structure (e.g., second dielectric structure 118), the bump structure including a lower bump structure (e.g., lower bump structure 122) and an upper bump structure (e.g., upper bump structure 124). The semiconductor wafer 2602 includes any type of semiconductor body (e.g., single crystal silicon / CMOS block, silicon germanium (SiGe), silicon on insulator (SOI), etc.). In some embodiments, the semiconductor wafer 2602 is disk-shaped.

[0131] like Fig.27A , Fig.27B As shown in , a carrier wafer 2702 is bonded to a semiconductor wafer 2602. In some embodiments, the carrier wafer 2702 is disk-shaped. The carrier wafer 2702 may be, for example, a polyimide wafer, a semiconductor wafer, etc. In some embodiments, a process for bonding the carrier wafer 2702 to the semiconductor wafer 2602 includes bonding the carrier wafer 2702 to the second dielectric structure of the plurality of ICs and / or the upper bump structure of the plurality of ICs (e.g., by a temporary bonding process). Since the ICs in the plurality of ICs include bump structures, the process of bonding the carrier wafer 2702 to the semiconductor wafer 2602 (e.g., by bonding the carrier wafer 2702 to the second dielectric structure of the plurality of ICs and / or the upper bump structure of the plurality of ICs) may be improved because the uppermost point of the upper bump structure is disposed at the uppermost point of the second dielectric structure or below the uppermost point of the second dielectric structure, thereby improving yield (e.g., by preventing damage to the ICs during bonding, preventing unintentional peeling of the carrier wafer, etc.).

[0132] like Fig.28A , Fig.28B As shown in FIG. 2 , in the case where the carrier wafer 2702 is bonded to the semiconductor wafer 2602, the carrier wafer 2702 and the semiconductor wafer 2602 bonded together (see, for example, Fig.27A , Fig.27B) performs a wafer cutting process to singulate ICs of the plurality of ICs from the carrier wafer 2702 and the semiconductor wafer 2602 bonded together to form a first plurality of singulated dies. The first plurality of singulated dies respectively include the plurality of ICs. For example, IC 100 is singulated from the carrier wafer 2702 and the semiconductor wafer 2602 bonded together to form a first singulated die 2802 including IC 100. In some embodiments, the wafer cutting process includes performing a series of cuts into the carrier wafer 2702 and the semiconductor wafer 2602 bonded together to form a plurality of cut lanes 2804, each of the plurality of cut lanes 2804 being disposed on one side of an IC of the plurality of ICs. Subsequently, a mechanical force is applied to the carrier wafer 2702 and the semiconductor wafer 2602 bonded together to singulate the ICs of the plurality of ICs to form a first plurality of singulated dies. In still other embodiments, the cuts may be performed by, for example, mechanical sawing, laser cutting, etc.

[0133] In some embodiments, after forming the plurality of singulated dies, each of the singulated dies in the plurality of singulated dies includes a semiconductor substrate and a carrier substrate. For example, the first singulated die 2802 includes the semiconductor substrate 102 and the carrier substrate 702 (see, e.g., Figure 7 ). In some embodiments, semiconductor substrate 102 is a portion of semiconductor wafer 2602 that has been singulated from semiconductor wafer 2602 by a wafer cutting process. In still other embodiments, carrier substrate 702 is a portion of carrier wafer 2702 that has been singulated from carrier wafer 2702 by a wafer cutting process. First singulated die 2802 may have a square (or rectangular) layout. Semiconductor substrate 102 may have a square (or rectangular) layout. Carrier substrate 702 may have a square (or rectangular) layout. In some embodiments, the layout of semiconductor substrate 102 is substantially the same as the layout of carrier substrate 702 (e.g., having substantially the same area and layout shape). After forming first singulated die 2802, carrier substrate 702 may be removed (e.g., stripped) from IC 100 by a subsequent removal process. It should be understood that in some embodiments, carrier wafer 2702 may be removed (e.g., stripped) before performing a wafer cutting process. In such an embodiment, after forming the plurality of singulated dies, singulated dies in the plurality of singulated dies do not include a carrier substrate.

[0134] Fig.29 A cross-sectional view showing some embodiments of a method of forming a display device (or a semiconductor package) 900, wherein the display device 900 includes FIG. 26A to FIG. 26B to FIG. 28A to FIG. 28B A first singulated die 2802 is formed in FIG.

[0135] like Fig.29 As shown in FIG. 8 , the first singulated die 2802 is bonded to the screen panel 802 (see, for example, Figure 8 It should be understood that the first individualized die 2802 is not limited to include FIG. 26A to FIG. 26B to FIG. 28A to FIG. 28B , but the first individualized die 2802 may include other embodiments of IC 100 (see, for example, Figures 1 to 6 ). In some embodiments, before the first individualized die 2802 is bonded to the screen panel 802, the carrier substrate 702 is removed from the first individualized die 2802 (e.g., by a suitable stripping process, such as a laser stripping process). In some embodiments, the screen panel 802 includes a transparent bonding layer 804 and a transparent cover structure 806. In some further embodiments, one or more second conductive features 906 (e.g., wires) are provided in the transparent cover structure 806. In addition, a second plurality of individualized dies 2902a-2902b are bonded to the screen panel 802. The second plurality of individualized dies 2902a-2902b include the plurality of light-emitting ICs 902a-902c, respectively. For example, the second individualized die 2902a includes a first light-emitting IC 902a, and the third individualized die 2902b includes a second light-emitting IC 902b. It should be appreciated that in other embodiments, one or more of the plurality of light emitting ICs 902a-902c can be disposed on one of the second plurality of singulated dies.

[0136] In some embodiments, the process for bonding the first individualized die 2802 and the second plurality of individualized dies 2902a-2902b to the screen panel 802 includes transferring the first individualized die 2802 and the second plurality of individualized dies 2902a-2902b to the screen panel 802 through a transfer process, thereby bonding the first individualized die 2802 and the second plurality of individualized dies 2902a-2902b to the screen panel 802. For example, the transfer process includes picking up the first individualized die 2802, the second individualized die 2902, and the third individualized die 2902b from the first position, and transferring the first individualized die 2802, the second individualized die 2902, and the third individualized die 2902b to the transparent bonding layer 804, thereby bonding the first individualized die 2802, the second individualized die 2902a, and the third individualized die 2902b to the screen panel 802. Since the first individualized die 2802 , the second individualized die 2902 a , and the third individualized die 2902 b are bonded to the screen panel 802 , the IC 100 , the first light-emitting IC 902 a , and the second light-emitting IC 902 b are also bonded to the screen panel 802 .

[0137] In some embodiments, the transfer process may be, for example, a pick-and-place transfer process, an elastomer stamp (or roller) process, an electrostatic stamp process, some other suitable transfer process, or a combination of the foregoing processes. It should be understood that the first individualized die 2802, the second individualized die 2902a, and the third individualized die 2902b may be bonded to the screen panel 802 by a plurality of transfer processes. The first individualized die 2802, the second individualized die 2902a, and the third individualized die 2902b are bonded to the screen panel 802 in a predetermined pattern (e.g., a 5×5 array) such that the one or more second conductive features 906 electrically couple the light emitting ICs 902a-902c to the IC 100.

[0138] Because IC 100 includes bump structure 120, there is an improved bonding interface between first singulated die 2802 and screen panel 802. For example, because upper bump structure 124 does not have a "fence" structure 502 extending above the upper surface of second dielectric structure 118 (see, e.g., Figure 5 ), so the bonding interface between the first individualized tube core 2802 and the screen panel 802 is improved. The improved bonding interface can improve the robustness of the display device 900 (for example, the screen panel 802 is resistant to cracking / shattering / delamination in response to a given mechanical force applied to the transparent cover structure 806) and / or increase the yield of the display device 900. For example, because the bump structure 120 reduces high stress points that may cause the screen panel 802 to crack / shatter / delaminate during the manufacture of the display device 900 (or during consumer use) (for example, the amount of mechanical force that can be applied to the transparent cover structure 806 before the screen panel 802 cracks / shatters / delaminates due to the reduction of high stress points), the improved bonding interface can improve the robustness of the display device 900 and / or the yield of the display device 900.

[0139] Fig.30 Flowchart 3000 illustrates some embodiments of a method for (e.g., forming a semiconductor package) of: (1) forming a semiconductor package including: Figure 1 Some embodiments of the IC 100 are shown as singulated dies; and (2) forming a display device including the singulated dies. Fig.30Flowchart 3000 is illustrated and described herein as a series of actions or events, but it should be understood that the illustrated order of these actions or events should not be interpreted as having a limiting meaning. For example, certain actions can occur in different orders, and / or can occur simultaneously with other actions or events other than the actions or events illustrated and / or described herein. In addition, all illustrated actions may not be required when implementing one or more aspects or embodiments described herein, and one or more of the actions illustrated herein may be implemented in one or more separate actions and / or stages.

[0140] At act 3002, a semiconductor wafer including a plurality of integrated circuits (ICs) disposed on the semiconductor wafer is received. FIG. 26A to FIG. 26B Various views of some embodiments corresponding to act 3002 are shown.

[0141] At act 3004, a carrier wafer is bonded to the semiconductor wafer. FIG. 27A to FIG. 27B Various views of some embodiments corresponding to action 3004 are illustrated.

[0142] At act 3006, a first singulated die including a first IC of the plurality of ICs is formed by singulating the first IC of the plurality of ICs from the semiconductor wafer and the carrier wafer bonded together. FIG. 28A to FIG. 28B Various views of some embodiments corresponding to action 3006 are illustrated. In some embodiments, the method for forming a Figure 1 Method 3007 of singulating dies for some embodiments of the illustrated IC includes act 3002 , act 3004 , and act 3006 .

[0143] At act 3008, the first singulated die is bonded to the screen panel. Fig.29 Cross-sectional views of some embodiments corresponding to action 3008 are illustrated.

[0144] At act 3010, a second singulated die including a light emitting IC is bonded to a screen panel. Fig.29 A cross-sectional view of some embodiments corresponding to act 3010 is illustrated. In some embodiments, method 3011 for forming a display device including a singulated die includes act 3008 and act 3010.

[0145] In some embodiments, the present application provides a method for forming an integrated circuit (IC). The method includes: receiving a workpiece, the workpiece including an interconnect structure embedded in an interlayer dielectric (ILD) structure and including a first dielectric layer disposed on the ILD structure and the interconnect structure. A first dielectric structure is formed on the workpiece. A sidewall barrier structure is formed on the first dielectric layer and along the inner sidewall of the first dielectric structure. A hard mask structure is formed on the first dielectric layer and along the inner sidewall of the sidewall barrier structure, wherein the height of the hard mask structure is less than the height of the first dielectric structure. After forming the hard mask structure, an upper portion of the sidewall barrier structure is removed so that the height of the sidewall barrier structure is less than or equal to the height of the hard mask structure. A portion of the first dielectric layer disposed between the inner sidewalls of the sidewall barrier structure is removed to form a second dielectric structure. A lower bump structure is formed on the ILD structure, and the lower bump structure extends vertically along the inner sidewall of the second dielectric structure and along the inner sidewall of the sidewall barrier structure. An upper bump structure is formed over both the lower bump structure and the sidewall barrier structure.

[0146] In the above method of forming an integrated circuit, removing the portion of the first dielectric layer exposes an upper conductive pad of the interconnect structure; and the lower bump structure is formed to extend vertically from the upper conductive pad.

[0147] In the above method of forming an integrated circuit, the method further includes: removing the hard mask structure after removing the upper portion of the sidewall barrier structure and before removing the portion of the first dielectric layer.

[0148] In the above-mentioned method for forming an integrated circuit, forming the hard mask structure includes: forming a hard mask layer that pads the upper surface of the first dielectric structure, the inner sidewall of the sidewall barrier structure, and the upper surface of the portion of the first dielectric layer; forming a mask structure on the hard mask layer; removing the upper portion of the mask structure so that the lower portion of the mask structure remains on the hard mask layer, wherein the upper surface of the lower portion of the mask structure is arranged below both the uppermost surface of the first dielectric structure and the uppermost surface of the hard mask layer; and removing the upper portion of the hard mask layer to form the hard mask structure.

[0149] In the above-mentioned method of forming an integrated circuit, the upper portion of the sidewall blocking structure is removed by a first etching process; and the first etching process removes the outer area of ​​the lower portion of the mask structure, thereby forming a gap between the lower portion of the mask structure and the hard mask layer.

[0150] In the above-mentioned method of forming an integrated circuit, after removing the upper portion of the sidewall blocking structure and before forming the lower bump structure, both the lower portion of the mask structure and the hard mask structure are removed; and the upper portion of the hard mask layer is removed by a second etching process; the first etching process includes exposing the upper portion of the sidewall blocking structure, the lower portion of the mask structure and the hard mask structure to a first etchant; and the second etching process includes exposing the hard mask layer and the lower portion of the mask structure to a second etchant different from the first etchant.

[0151] In some embodiments, the present application provides an integrated circuit (IC). The IC includes: an interlayer dielectric (ILD) structure disposed on a semiconductor substrate, wherein an interconnect structure is embedded in the ILD structure. A first dielectric structure is disposed on the ILD structure and the interconnect structure, wherein a conductive pad of the interconnect structure is at least partially disposed between a first inner sidewall of the first dielectric structure. A second dielectric structure is disposed on the first dielectric structure, wherein the first inner sidewall is disposed between a second inner sidewall of the second dielectric structure. A sidewall barrier structure is disposed on the first dielectric structure and extends vertically along the second inner sidewall. A lower bump structure is disposed on the conductive pad and between the second inner sidewalls, wherein the lower bump structure extends vertically along the first inner sidewall and along a third inner sidewall of the sidewall barrier structure. An upper bump structure is disposed on both the lower bump structure and the sidewall barrier structure, wherein the upper bump structure extends vertically along the second inner sidewall, and wherein the uppermost point of the upper bump structure is disposed at the uppermost point of the second dielectric structure or below the uppermost point of the second dielectric structure.

[0152] In the above integrated circuit, the sidewall barrier structure is titanium nitride; the lower bump structure is nickel; and the upper bump structure is gold.

[0153] In the above integrated circuit, the uppermost surface of the upper bump structure is not disposed above the uppermost surface of the second dielectric structure.

[0154] In the above integrated circuit, the uppermost surface of the sidewall barrier structure is substantially flat.

[0155] In the above-mentioned integrated circuit, the third inner sidewall is arc-shaped; one of the third inner sidewalls is bent from the lowermost surface of the sidewall barrier structure to the uppermost surface of the sidewall barrier structure toward the outer sidewall of the sidewall barrier structure; and the one of the third inner sidewalls and the outer sidewall of the sidewall barrier structure are both arranged on the same side of the lower bump structure.

[0156] In the above integrated circuit, the uppermost surface of the sidewall barrier structure is disposed between the uppermost surface of the second dielectric structure and the lowermost surface of the second dielectric structure.

[0157] In the above integrated circuit, the uppermost surface of the lower bump structure is substantially coplanar with the uppermost surface of the sidewall barrier structure; and the uppermost surface of the upper bump structure is disposed below the uppermost surface of the second dielectric structure.

[0158] In the above integrated circuit, the uppermost surface of the lower bump structure is disposed below the uppermost surface of the sidewall barrier structure; and the uppermost surface of the upper bump structure is substantially coplanar with the uppermost surface of the second dielectric structure.

[0159] In the above integrated circuit, the uppermost point of the lower bump structure is arranged above the uppermost surface of the sidewall barrier structure.

[0160] In the above integrated circuit, the uppermost surface of the lower bump structure has a first recessed portion and a first annular portion; and the first annular portion extends around the first recessed portion in a first continuous path in a lateral direction.

[0161] In the above integrated circuit, the uppermost surface of the upper bump structure has a second recessed portion and a second annular portion; and the second annular portion extends around the second recessed portion in a second continuous path in a lateral direction.

[0162] In some embodiments, the present application provides a method. The method includes: receiving a semiconductor wafer having a plurality of integrated circuits (ICs) disposed on the semiconductor wafer, wherein: a first IC of the plurality of ICs includes an interlayer dielectric (ILD) structure, a dielectric structure disposed on the ILD structure, and a bump structure disposed on the ILD structure and between inner sidewalls of the dielectric structure; the bump structure includes a lower bump structure and an upper bump structure; a sidewall barrier structure is disposed along an outer sidewall of the lower bump structure and at least partially separates the lower bump structure from the inner sidewall of the dielectric structure; the uppermost surface of the sidewall barrier structure is substantially coplanar with the uppermost surface of the lower bump structure; and the upper bump structure is disposed on both the lower bump structure and the sidewall barrier structure. The carrier wafer is bonded to the semiconductor wafer by bonding the carrier wafer to the dielectric structure or the bump structure. A first individualized die including the first IC is formed by singulating the first IC from the bonded semiconductor wafer and the carrier wafer.

[0163] In the above method, after forming the first individualized die, the first individualized die includes a semiconductor substrate disposed below the interlayer dielectric structure and a carrier substrate disposed above both the dielectric structure and the bump structure.

[0164] In the above method, after forming the first individualized tube core, the carrier substrate is removed from the first individualized tube core; after removing the carrier substrate from the first individualized tube core, the first individualized tube core is bonded to the screen panel; and a second individualized tube core including a light-emitting integrated circuit is bonded to the screen panel, wherein the light-emitting integrated circuit includes one or more light-emitting structures.

[0165] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method of forming an integrated circuit, the method comprising: receiving a workpiece, the workpiece comprising an interconnect structure embedded in an interlayer dielectric structure and comprising a first dielectric layer disposed over the interlayer dielectric structure and the interconnect structure; forming a first dielectric structure over the workpiece; forming a sidewall barrier structure on the first dielectric layer and along the inner sidewalls of the first dielectric structure; forming a hard mask structure on the first dielectric layer and along the inner sidewalls of the sidewall barrier structure, wherein the height of the hard mask structure is less than the height of the first dielectric structure; After forming the hard mask structure, removing an upper portion of the sidewall barrier structure so that a height of the sidewall barrier structure is less than or equal to the height of the hard mask structure; removing a portion of the first dielectric layer disposed between the inner sidewalls of the sidewall barrier structure to form a second dielectric structure; forming a lower bump structure over the interlayer dielectric structure, the lower bump structure extending vertically along an inner sidewall of the second dielectric structure and along the inner sidewall of the sidewall barrier structure; as well as An upper bump structure is formed over both the lower bump structure and the sidewall barrier structure.

2. The method of forming an integrated circuit according to claim 1, wherein: Removing the portion of the first dielectric layer exposes the upper conductive pads of the interconnect structure; and The lower bump structure is formed to vertically extend from the upper conductive pad.

3. The method of forming an integrated circuit according to claim 2, further comprising: The hard mask structure is removed after removing the upper portion of the sidewall blocking structure and before removing the portion of the first dielectric layer.

4. The method of forming an integrated circuit according to claim 3, wherein forming the hard mask structure comprises: forming a hard mask layer lining an upper surface of the first dielectric structure, the inner sidewalls of the sidewall barrier structure, and an upper surface of the portion of the first dielectric layer; forming a mask structure over the hard mask layer; removing an upper portion of the mask structure so that a lower portion of the mask structure remains over the hard mask layer, wherein an upper surface of the lower portion of the mask structure is disposed below both an uppermost surface of the first dielectric structure and an uppermost surface of the hard mask layer; and An upper portion of the hard mask layer is removed to form the hard mask structure.

5. The method of forming an integrated circuit according to claim 4, wherein: The upper portion of the sidewall barrier structure is removed by a first etching process; as well as The first etching process removes an outer region of the lower portion of the mask structure, thereby forming a gap between the lower portion of the mask structure and the hard mask layer.

6. The method of forming an integrated circuit according to claim 5, wherein: removing both the lower portion of the mask structure and the hard mask structure after removing the upper portion of the sidewall barrier structure and before forming the lower bump structure; as well as The upper portion of the hard mask layer is removed by a second etching process; The first etching process includes exposing the upper portion of the sidewall barrier structure, the lower portion of the mask structure, and the hard mask structure to a first etchant; and The second etching process includes exposing the hard mask layer and the lower portion of the mask structure to a second etchant different from the first etchant.

7. An integrated circuit comprising: An interlayer dielectric structure is disposed on the semiconductor substrate, wherein the interconnect structure is embedded in the interlayer dielectric structure; A first dielectric structure disposed on the interlayer dielectric structure and the interconnect structure, wherein the conductive pad of the interconnect structure is at least partially disposed between first inner sidewalls of the first dielectric structure; a second dielectric structure disposed on the first dielectric structure, wherein the first inner sidewall is disposed between second inner sidewalls of the second dielectric structure; a sidewall blocking structure disposed on the first dielectric structure and extending vertically along the second inner sidewall; a lower bump structure disposed above the conductive pad and between the second inner sidewalls, wherein the lower bump structure vertically extends along the first inner sidewall and along the third inner sidewall of the sidewall barrier structure; as well as an upper bump structure disposed on both the lower bump structure and the sidewall barrier structure, wherein the upper bump structure extends vertically along the second inner sidewall, and wherein the uppermost point of the upper bump structure is disposed at the uppermost point of the second dielectric structure or below the uppermost point of the second dielectric structure, The third inner side wall is arc-shaped; One of the third inner sidewalls is formed to bend from the lowermost surface of the sidewall barrier structure to the uppermost surface of the sidewall barrier structure toward the outer sidewall of the sidewall barrier structure; as well as The one of the third inner sidewalls and the outer sidewall of the sidewall barrier structure are both disposed on a same side of the lower bump structure.

8. The integrated circuit of claim 7, wherein: The sidewall barrier structure is titanium nitride; The lower bump structure is nickel; and The upper bump structure is gold. 9 . The integrated circuit of claim 7 , wherein an uppermost surface of the upper bump structure is not disposed above an uppermost surface of the second dielectric structure.

10. The integrated circuit of claim 7, wherein: The uppermost surface of the sidewall barrier structure is flat.

11. The integrated circuit of claim 7, wherein: The uppermost surface of the sidewall barrier structure is disposed between the uppermost surface of the second dielectric structure and the lowermost surface of the second dielectric structure.

12. The integrated circuit of claim 11, wherein: The uppermost surface of the lower bump structure is coplanar with the uppermost surface of the sidewall barrier structure; and An uppermost surface of the upper bump structure is disposed below the uppermost surface of the second dielectric structure.

13. The integrated circuit of claim 11, wherein: The uppermost surface of the lower bump structure is disposed below the uppermost surface of the sidewall barrier structure; and An uppermost surface of the upper bump structure is coplanar with the uppermost surface of the second dielectric structure.

14. The integrated circuit of claim 11, wherein: An uppermost point of the lower bump structure is disposed above the uppermost surface of the sidewall barrier structure.

15. The integrated circuit of claim 14, wherein: The uppermost surface of the lower bump structure has a first recessed portion and a first annular portion; as well as The first annular portion extends laterally around the first recessed portion in a first continuous path.

16. The integrated circuit of claim 15, wherein: The uppermost surface of the upper bump structure has a second recessed portion and a second annular portion; as well as The second annular portion extends laterally around the second recessed portion in a second continuous path.

17. A method of forming a semiconductor package, comprising: receiving a semiconductor wafer having a plurality of integrated circuits disposed on the semiconductor wafer, wherein: A first integrated circuit among the plurality of integrated circuits comprises an interlayer dielectric (ILD) structure, a first dielectric layer disposed on the interlayer dielectric structure, a dielectric structure, and a bump structure and a sidewall barrier structure disposed on the interlayer dielectric structure and between inner sidewalls of the dielectric structure, wherein a method for forming the bump structure and the sidewall barrier structure comprises: forming the sidewall barrier structure on the first dielectric layer and along the inner sidewall of the first dielectric structure; forming a hard mask structure on the first dielectric layer and along the inner sidewalls of the sidewall barrier structure, wherein the height of the hard mask structure is less than the height of the first dielectric structure; After forming the hard mask structure, removing an upper portion of the sidewall barrier structure so that a height of the sidewall barrier structure is less than or equal to the height of the hard mask structure; removing a portion of the first dielectric layer disposed between the inner sidewalls of the sidewall barrier structure to form a second dielectric structure; forming a lower bump structure over the interlayer dielectric structure, the lower bump structure extending vertically along an inner sidewall of the second dielectric structure and along the inner sidewall of the sidewall barrier structure; and forming an upper bump structure on both the lower bump structure and the sidewall barrier structure; bonding a carrier wafer to the semiconductor wafer, wherein the carrier wafer is bonded to the dielectric structure or the bump structure; and A first singulated die including the first integrated circuit is formed by singulating the first integrated circuit from the semiconductor wafer and the carrier wafer bonded together.

18. The method of forming a semiconductor package according to claim 17, wherein: After forming the first singulated die, the first singulated die includes a semiconductor substrate disposed below the interlayer dielectric structure and a carrier substrate disposed above both the dielectric structure and the bump structure.

19. The method according to claim 18, further comprising: After forming the first singulated die, removing the carrier substrate from the first singulated die; bonding the first singulated die to a screen panel after removing the carrier substrate from the first singulated die; as well as A second singulated die including a light emitting integrated circuit is bonded to the screen panel, wherein the light emitting integrated circuit includes one or more light emitting structures.

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