Method for manufacturing semiconductor device
By defining source contact holes using self-alignment back-etching and side wall processes in semiconductor device manufacturing, the problem of increased stepping and high on-resistance caused by photolithography definition is solved, and smaller steps and lower On-resistance.
Patent Information
- Application Number
- CN201910825434.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2019-09-03
- Publication Date
- 2024-12-27
- Estimated Expiration
- 2039-09-03
AI Technical Summary
In the existing semiconductor device manufacturing method, the contact hole size and trench gate spacing at the top of the photolithography defines the source region are difficult to reduce, resulting in an increase in stepping of the device and an increase in on-resistance.
The self-alignment re-engraving process is used to form a first self-alignment re-engraving trench on the top of the gate conductive material layer, and self-alignment etching is performed in the semiconductor platform area to form a second self-alignment re-engraving trench, passing through the side wall The process defines the source contact hole, which reduces the width of the source contact hole and the spacing of the trench gate.
It effectively reduces the step of the device, reduces the specific on-resistance, and improves the performance of the device.
Smart Images
Figure CN112447844B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a method for manufacturing a semiconductor integrated circuit, and in particular to a method for manufacturing a semiconductor device. Background Art
[0002] like Figure 1 As shown, it is a schematic diagram of the structure of an existing trench gate MOSFET device, including: a highly doped semiconductor substrate such as a silicon substrate 1, the resistivity of the silicon substrate 1 is usually between 0.001Ω*cm and 0.002Ω*cm, and the thickness of the silicon substrate 1 is also expected to be as thin as possible to reduce the substrate resistance.
[0003] An epitaxial layer such as a silicon epitaxial layer 2 is formed on the surface of the silicon substrate 1. The thickness and doping concentration of the silicon epitaxial layer 2 determine the device voltage of the device. The higher the breakdown voltage of the device, the thicker the silicon epitaxial layer 2 needs to be and the lower the doping concentration. Usually, the thickness of the silicon epitaxial layer 2 is between 2μm and 15μm, and the resistivity of the silicon epitaxial layer 2 is between 0.1Ω*cm and 2Ω*cm. The silicon epitaxial layer 2 can be a single-layer structure, and the resistivity is consistent throughout the epitaxial layer; the silicon epitaxial layer 2 can also be a two-layer structure with a buffer layer (Buffer), which is located in the contact area between the silicon epitaxial layer 2 and the silicon substrate 1, and the resistivity of the buffer layer is usually relatively low. The silicon epitaxial layer 2 can also be a multi-layer structure.
[0004] The trench gate includes a gate dielectric layer such as a gate oxide layer 3 and a gate conductive material layer such as a polysilicon gate 9 formed in the gate trench. The lower the breakdown voltage of the device, the thinner the thickness of the gate oxide layer 3. For an N-type trench gate MOSFET, its polysilicon gate 9 is usually heavily doped with N-type; for a P-type trench gate MOSFET, its polysilicon gate 9 is usually heavily doped with P-type.
[0005] The channel region 4 is formed on the surface of the silicon epitaxial layer 2 , and the doping concentration of the channel region 4 determines the threshold voltage of the device. In practice, the depth of the gate trench is usually deeper than the depth of the channel region 4 by 0.1 μm to 0.2 μm.
[0006] A heavily doped source region 5 is formed on the surface of the channel region 4 .
[0007] Interlayer film 6 and front metal layer 7, interlayer film 6 is usually an oxide layer. In order to reduce the on-resistance of power MOSFET, the thickness of top metal layer 7 is usually relatively thick, which is currently above 4 μm.
[0008] Through hole or contact hole 8, usually, the front metal layer 7 includes multiple layers, the connection between the first layer of the front metal layer 7 and the doped regions at the bottom, such as the source region 5 and the channel region 4, is connected through the contact hole; the connection between the front metal layers 7 is connected through the through hole, Figure 1Only one front metal layer 7 is shown schematically, and the mark 8 corresponds to the contact hole. The front metal layer 7 will form a source and a gate after patterning, and the source is connected to the source region 5 and the channel region 4 through the corresponding contact hole 8.
[0009] The current flow region of the trench gate MOSFET device is composed of a plurality of periodically arranged unit cells. The trench gate usually extends to a gate lead-out region outside the current flow region and is connected to a gate composed of a front metal layer 7 through a contact hole 8 formed on top of a polysilicon gate 9 in the gate lead-out region.
[0010] The on-resistance of trench gate MOSFET is closely related to the density of the trench, i.e. the gate trench. The greater the trench density, the lower the on-resistance of the trench gate MOSFET. Therefore, in terms of technology, it is hoped that the trench density can be increased as much as possible. The trench density is determined by:
[0011] The width of the groove is mainly related to the accuracy of photolithography and the etching depth of the groove.
[0012] The distance between the grooves is also called the width of the platform area (Mesa). The width of Mesa is determined by the size of the contact hole and the distance between the contact hole and the groove. The size of the contact hole is determined by the accuracy of the photolithography. Figure 1 The top width d1 of the trench in the contact hole is the distance between the contact hole and the trench. Figure 1 The distance d2 in the contact hole needs to be kept at a certain distance. In addition, the position of the contact hole is also affected by the photolithography alignment accuracy. This leads to the need for a wider Mesa width.
[0013] For a typical trench gate MOSFET, the minimum trench width can be 0.2μm, the Mesa width is 0.6μm, the contact hole width is 0.2μm, and the corresponding step (Pitch) can be 0.8μm, where Pitch is the sum of the width of a trench and the trench spacing. Summary of the invention
[0014] The technical problem to be solved by the present invention is to provide a method for manufacturing a semiconductor device, which can self-align and define a contact hole at the top of a source region, thereby reducing the step size of the device and thus reducing the specific on-resistance of the device.
[0015] In order to solve the above technical problems, the present invention provides a method for manufacturing a semiconductor device, comprising the following steps:
[0016] Step 1, providing a semiconductor substrate, the top surface of the semiconductor substrate is a first surface; using a photolithography definition plus etching process to form a plurality of gate trenches in the semiconductor substrate, the area between each adjacent gate trench is a semiconductor platform area; in a current flow area of the semiconductor device, a unit cell formation area is formed by one gate trench and an adjacent semiconductor platform area, and the current flow area is composed of a plurality of unit cells arranged periodically.
[0017] Step 2: forming a gate dielectric layer, wherein the gate dielectric layer is formed on the bottom surface and side surfaces of the gate trench and extends to the surface outside the gate trench.
[0018] Step three: forming a gate conductive material layer, wherein the gate conductive material layer completely fills the gate trench and extends to a surface outside the gate trench.
[0019] Step 4: Perform a first self-aligned backetch on the gate conductive material layer, wherein the first self-aligned backetch removes all of the gate conductive material layer on the outer surface of the gate groove and backetches the top surface of the gate conductive material layer in the gate groove area to below the first surface to form a first self-aligned backetch groove.
[0020] Step five: forming a channel region in the semiconductor platform region.
[0021] Step six: forming a source region on the surface of the channel region, wherein the channel region at the bottom of the source region is covered by the side of the gate conductive material layer, and the surface of the channel region covered by the side of the gate conductive material layer is used to form a channel.
[0022] Step seven: filling the first self-aligned back groove with a first dielectric layer.
[0023] Step eight, using the first dielectric layer as a self-aligned condition, the semiconductor material of the semiconductor platform area is etched back to form a second self-aligned etched back groove, the bottom surface of the second self-aligned etched back groove is lower than the first surface and the source region is located below the bottom surface of the second self-aligned etched back groove.
[0024] Step nine: forming a sidewall composed of the second dielectric layer on the inner side surface of the second self-aligned back-etched groove, and defining a source contact hole at the top of the source region by self-alignment of the sidewall.
[0025] Step 10: forming an interlayer film, contact holes and a front metal layer, and patterning the front metal layer to form a gate and a source; the gate is connected to the gate conductive material layer through a gate contact hole, and the source is connected to the source region through a source contact hole.
[0026] A further improvement is that in step one, the semiconductor material constituting the semiconductor substrate includes silicon and silicon carbide.
[0027] A further improvement is that in step 2, the gate dielectric layer is a gate oxide layer; and the gate dielectric layer is grown by a thermal oxidation process.
[0028] The gate conductive material layer is a polysilicon gate.
[0029] A further improvement is that the steps of forming the gate trench include:
[0030] A hard mask layer is formed on the surface of the semiconductor substrate.
[0031] The formation area of the gate trench is defined by photolithography.
[0032] The hard mask layer and the semiconductor substrate are anisotropically etched in sequence to form the gate trench.
[0033] A further improvement is that after forming the gate trench, the gate trench is processed by isotropic etching to make the corners of the gate trench smooth; or, after forming the gate trench, a sacrificial oxide layer is formed and then the sacrificial oxide layer is removed to make the corners of the gate trench smooth.
[0034] A further improvement is that the material of the hard mask layer includes an oxide layer, a nitride layer or a nitride oxide layer; and the hard mask layer is removed after forming the gate trench and before forming the channel region in step five.
[0035] A further improvement is that in step five, a channel implantation plus annealing drive process is used to form the channel region.
[0036] A further improvement is that the material of the first dielectric layer includes an oxide layer, a nitride layer or a nitride oxide layer.
[0037] A further improvement is that in step nine, the material of the second dielectric layer and the material of the interlayer film have an etching rate difference and meet the conditions of selective etching; the sub-steps of forming the sidewalls in step nine include:
[0038] The second dielectric layer is fully deposited.
[0039] The second dielectric layer is fully etched to form the sidewall on the inner side of the second self-aligned back-etched groove.
[0040] A further improvement is that the material of the interlayer film is an oxide layer; and the material of the second dielectric layer includes a nitride layer.
[0041] A further improvement is that the trench gate MOSFET further comprises a shielding layer, and the steps of forming the shielding layer are further comprised before forming the gate dielectric layer and the gate conductive material layer, which are respectively:
[0042] A shielding dielectric layer is formed.
[0043] The shielding layer is formed by a deposition and back etching process.
[0044] An inter-gate isolation dielectric layer is formed on the top surface of the shielding layer.
[0045] The shielding layer is formed in the gate groove at the bottom of the gate conductive material layer. The material of the shielding layer is the same as that of the gate conductive material layer. The shielding layer and the bottom surface and side of the gate groove are separated by a shielding dielectric layer. The shielding layer and the gate conductive material layer are separated by an inter-gate isolation dielectric layer.
[0046] A further improvement is that in step nine, after forming the side wall, the step also includes etching the semiconductor substrate at the bottom of the source contact hole with the side wall as a self-alignment condition so that the bottom of the source contact hole passes through the source region and is connected to the channel region, and the source region and the channel region are simultaneously connected to the source through the source contact hole.
[0047] A further improvement is that a gate lead-out region is formed outside the current flow region, the trench gate in the current flow region also extends into the gate lead-out region, a gate contact hole is formed on the top of the gate conductive material layer in the gate lead-out region, and the gate conductive material layer and the gate composed of the front metal layer are connected through the gate contact hole.
[0048] A further improvement is that the semiconductor device is a MOSFET device, and after step ten is completed, the following backside process is also included:
[0049] Step 11: thinning the back side of the semiconductor substrate and forming a drain region on the back side of the semiconductor substrate, wherein the semiconductor substrate between the drain region and the channel region constitutes a drift region.
[0050] Step 12: forming a back metal layer on the back side of the drain region and forming a drain electrode with the back metal layer.
[0051] A further improvement is that the semiconductor device is an N-type device, the channel region is P-type doped, and the source region is heavily N-type doped; the semiconductor device is a P-type device, the channel region is N-type doped, and the source region is heavily P-type doped.
[0052] In view of the defects that the size of the contact hole, i.e., the source contact hole, can be reduced and the reduction of the spacing between the source contact hole and the adjacent trench gate when the contact hole at the top of the source region is defined by photolithography in the existing process, the present invention utilizes that the top of the gate conductive material layer of the trench gate can be self-aligned and etched back to form a first self-aligned and etched back groove on the top of the gate conductive material layer, and conversely, after the first dielectric layer is filled in the first self-aligned and etched back groove, the semiconductor platform region can be self-aligned and etched to form a second self-aligned and etched back groove; and the sidewall process can be used to form a sidewall on the inner side of the second self-aligned and etched back groove, and the sidewall can self-align to open the middle part of the source region to achieve the self-aligned definition of the source contact hole, that is, the width of the source contact hole is self-aligned and defined by the width of the sidewalls on the two inner sides of the second self-aligned and etched back groove, and at the same time, the spacing between the source contact hole and the trench gate is self-aligned and defined by the width of the sidewall; because the width of the source contact hole and the spacing with the trench gate are both defined by self-alignment, the present invention can reduce the stepping of the device and thus reduce the specific on-resistance of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0053] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:
[0054] Figure 1 It is a schematic diagram of the structure of an existing trench gate MOSFET device;
[0055] Figure 2 is a flow chart of a method for manufacturing a semiconductor device according to a first embodiment of the present invention;
[0056] Figure 3A-Figure 3I It is a schematic diagram of the device structure in each step of the method for manufacturing a semiconductor device according to the first embodiment of the present invention. DETAILED DESCRIPTION
[0057] like Figure 2 FIG. 1 is a flow chart of a method for manufacturing a semiconductor device according to a first embodiment of the present invention; FIG. 3A to FIG. 3I FIG. 1 is a schematic diagram of the device structure in each step of the method for manufacturing a semiconductor device according to the first embodiment of the present invention. The method for manufacturing a semiconductor device according to the first embodiment of the present invention comprises the following steps:
[0058] Step 1: Figure 3A As shown, a semiconductor substrate 101 is provided, and the top surface of the semiconductor substrate 101 is a first surface; a plurality of gate trenches 201 are formed in the semiconductor substrate 101 by using a photolithography definition plus etching process, and the area between each adjacent gate trench 201 is a semiconductor platform area; in the current flow area of the semiconductor device, a unit cell formation area is composed of one gate trench 201 and an adjacent semiconductor platform area, and the current flow area is composed of a plurality of unit cells arranged periodically.
[0059] The semiconductor material constituting the semiconductor substrate 101 includes silicon and silicon carbide.
[0060] The steps of forming the gate trench 201 include:
[0061] A hard mask layer is formed on the surface of the semiconductor substrate 101 .
[0062] The formation area of the gate trench 201 is defined by photolithography.
[0063] The hard mask layer and the semiconductor substrate 101 are anisotropically etched in sequence to form the gate trench 201 .
[0064] After forming the gate trench 201, the method further includes performing isotropic etching on the gate trench 201 to make the corners of the gate trench 201 smooth; or, after forming the gate trench 201, the method further includes forming a sacrificial oxide layer and then removing the sacrificial oxide layer to make the corners of the gate trench 201 smooth.
[0065] The material of the hard mask layer includes an oxide layer, a nitride layer or a nitride oxide layer; the hard mask layer is removed after forming the gate trench 201 and before forming the channel region 105 in the subsequent step five.
[0066] Step 2: Figure 3B As shown, a gate dielectric layer 102 is formed. The gate dielectric layer 102 is formed on the bottom surface and side surfaces of the gate trench 201 and extends to the surface outside the gate trench 201 .
[0067] The gate dielectric layer 102 is a gate oxide layer; the gate dielectric layer 102 is grown by a thermal oxidation process.
[0068] Step 3: Figure 3B As shown, a gate conductive material layer 103 is formed, and the gate conductive material layer 103 completely fills the gate trench 201 and extends to the surface outside the gate trench 201 .
[0069] The gate conductive material layer 103 is a polysilicon gate.
[0070] Step 4: Figure 3B As shown, the gate conductive material layer 103 is subjected to a first self-aligned backetching, and the first self-aligned backetching removes all the gate conductive material layer 103 on the outer surface of the gate trench 201 and backetches the top surface of the gate conductive material layer 103 in the gate trench 201 area to below the first surface and forms a first self-aligned backetching groove 202.
[0071] Step 5: Figure 3CAs shown, a channel region 105 is formed in the semiconductor platform region.
[0072] The channel region 105 is formed by using a channel implantation plus annealing drive-in process.
[0073] Step 6: Figure 3D As shown, a source region 106 is formed on the surface of the channel region 105, the channel region 105 located at the bottom of the source region 106 is covered by the side of the gate conductive material layer 103, and the surface of the channel region 105 covered by the side of the gate conductive material layer 103 is used to form a channel.
[0074] Step 7: Figure 3E As shown, the first dielectric layer 104 is filled in the first self-aligned back groove 202 .
[0075] The material of the first dielectric layer 104 includes an oxide layer, a nitride layer or a nitride oxide layer.
[0076] Step 8: Figure 3F As shown, the semiconductor material of the semiconductor platform area is etched back with the first dielectric layer 104 as a self-aligned condition to form a second self-aligned etched back groove 203, wherein the bottom surface of the second self-aligned etched back groove 203 is lower than the first surface and the source region 106 is located below the bottom surface of the second self-aligned etched back groove 203.
[0077] Step 9: Figure 3G As shown, a sidewall 107 composed of the second dielectric layer is formed on the inner side of the second self-aligned back groove 203 , and a source contact hole 109 at the top of the source region 106 is defined by the sidewall 107 in a self-aligned manner.
[0078] The steps of forming the sidewall 107 include:
[0079] The second dielectric layer is fully deposited.
[0080] The second dielectric layer is fully etched to form the sidewall 107 on the inner side of the second self-aligned back-etched groove 203 .
[0081] In step 9, the material of the second dielectric layer and the material of the subsequently formed interlayer film 108 have an etching rate difference and meet the conditions of selective etching. Preferably, the material of the interlayer film 108 is an oxide layer; the material of the second dielectric layer includes a nitride layer.
[0082] In the first embodiment of the present invention, after forming the side wall 107, the semiconductor substrate 101 at the bottom of the source contact hole 109 is etched with the side wall 107 as a self-alignment condition so that the bottom of the source contact hole 109 passes through the source region 106 and is connected to the channel region 105, and the source region 106 and the channel region 105 are simultaneously connected to the source through the source contact hole 109.
[0083] Step 10: Figure 3H As shown, an interlayer film 108, a contact hole 109 and a front metal layer 110 are formed, and the front metal layer 110 is patterned to form a gate and a source; the gate is connected to the gate conductive material layer 103 through the gate contact hole 109, and the source is connected to the source region 106 through the source contact hole 109.
[0084] A gate lead-out region is also formed outside the current flow region, and the trench gate in the current flow region also extends into the gate lead-out region. A gate contact hole is formed on the top of the gate conductive material layer 103 in the gate lead-out region, and the gate conductive material layer 103 and the gate composed of the front metal layer 110 are connected through the gate contact hole.
[0085] In the method of the first embodiment of the present invention, the contact hole formed in step 10 includes forming the top portion of the source contact hole 109 and the gate contact hole. The bottom portion of the source contact hole 109 is defined by the self-alignment of the sidewall spacer formed in step 9, the top portion of the source contact hole 109 passes through the interlayer film 108, and the gate contact hole also passes through the interlayer film 108.
[0086] The semiconductor device is a MOSFET device, and after step 10 is completed, the following back surface processes are also included:
[0087] Step 11: Fig. 3I As shown, the semiconductor substrate 101 is thinned on the back side and a drain region 111 is formed on the back side of the semiconductor substrate 101 . The semiconductor substrate 101 between the drain region 111 and the channel region 105 forms a drift region.
[0088] Step twelve: forming a back metal layer 112 on the back side of the drain region 111 and forming a drain electrode with the back metal layer 112 .
[0089] In the first embodiment of the present invention, the semiconductor device is an N-type device, the channel region 105 is P-type doped, the source region 106 and the drain region 111 are both N-type heavily doped, and the drift region is N-type doped. In other embodiments, the semiconductor device is a P-type device, the channel region 105 is N-type doped, the source region 106 and the drain region 111 are both P-type heavily doped, and the drift region is P-doped.
[0090] In view of the defects that the contact hole 109, i.e., the source contact hole 109, which is defined at the top of the source region 106 by photolithography in the prior art will reduce the size of the source contact hole 109 and the reduction of the spacing between the source contact hole 109 and the adjacent trench gate is limited, the first embodiment of the present invention utilizes that the top of the gate conductive material layer 103 of the trench gate can be self-aligned and etched back to form a first self-aligned etched back groove 202 at the top of the gate conductive material layer 103, and conversely, after the first dielectric layer 104 is filled in the first self-aligned etched back groove 202, the semiconductor platform region can be self-aligned and etched to form a second self-aligned etched back groove 203; and the sidewall 107 is used to process The process can form a side wall 107 on the inner side surface of the second self-aligned back-etched groove 203, and the side wall 107 can self-align to open the middle part of the source area 106 to achieve self-alignment definition of the source contact hole 109, that is, the width of the source contact hole 109 is self-aligned and defined by the width of the side walls 107 on the two inner sides of the second self-aligned back-etched groove 203, and at the same time, the spacing between the source contact hole 109 and the trench gate is self-aligned and defined by the width of the side wall 107; since the width of the source contact hole 109 and the spacing with the trench gate are both defined by self-alignment, the first embodiment of the present invention can reduce the stepping of the device and thereby reduce the specific on-resistance of the device.
[0091] In order to more clearly illustrate the method of the first embodiment of the present invention, the method of the first embodiment of the present invention is further illustrated in combination with specific parameters:
[0092] Take a semiconductor device with a breakdown voltage of 20V and a unit cell step of 0.5 microns, i.e., the corresponding MOSFET device in the first embodiment of the present invention, as an example: for low-voltage MOSFET, a highly phosphorus-doped semiconductor substrate 101 is usually used instead of a highly arsenic-doped semiconductor substrate. This is because the phosphorus-doped semiconductor substrate can achieve a lower minimum resistivity than the arsenic-doped semiconductor substrate. At present, the lowest resistivity of phosphorus-doped semiconductor substrates can be 0.7mΩ*cm to 0.9mΩ*cm, while for arsenic substrates, the lowest resistivity is 1.0mΩ*cm to 1.5mΩ*cm. Because low-voltage devices have a low on-resistance and the substrate accounts for a large proportion of the total on-resistance, lower substrate resistance becomes more important.
[0093] The epitaxial layer is on the semiconductor substrate 101. In order to reduce the back diffusion of the high-concentration phosphorus substrate, an epitaxial layer is sometimes added. The thickness of the epitaxial layer is usually between 1μm and 2μm, and the corresponding resistivity is usually between 0.02Ω*cm and 0.05Ω*cm. The resistivity and thickness of the epitaxial layer are related to the required breakdown voltage of the device. The higher the breakdown voltage of the device, the lower the doping concentration of the epitaxial layer, and the thicker the epitaxial layer. For a MOSFET with a breakdown voltage of 20V, the thickness of the epitaxial layer is usually between 2μm and 4μm, and the corresponding doping concentration, that is, the corresponding resistivity, is around 0.15Ω*cm.
[0094] The width of the gate trench 201 of the semiconductor device is 0.2 μm, the distance between the gate trenches 201 is 0.3 μm, and the corresponding pitch is 0.5 μm. The side inclination angle of the gate trench 201 is usually between 88 and 89 degrees, and the depth of the gate trench 201 is usually about 1 μm.
[0095] The gate trench 201 is formed by photolithography and etching process, and anisotropic etching is used. In order to ensure that the bottom of the trench is as smooth as possible (because it has to withstand a large electric field), the etching is adjusted to isotropic etching when the anisotropic etching is about to end. Or after the etching is completed, a relatively thick sacrificial oxidation is grown to make the top as smooth as possible. Therefore, the opening of the gate trench 201 formed at the end is usually greater than 0.2μm.
[0096] Before growing the gate dielectric layer 102, a sacrificial oxidation is usually required to repair the sidewall defects caused by etching the gate trench 201. The thickness of the sacrificial oxidation is usually The growth temperature is usually between 900°C and 950°C. For a 20V device, the thickness of the gate dielectric layer 102 is usually between arrive between.
[0097] The gate conductive material layer 103 is N-type polysilicon. For a P-type device, the gate conductive material layer 103 is usually P-type polysilicon.
[0098] The channel region 105 is formed by channel ion implantation, which usually requires passing through a shielding oxide layer, so as to prevent the tunneling effect of the ion implantation and thus prevent the implantation depth from being too deep. The thickness of the shielding oxide layer is usually This shielding oxide layer can be deposited or grown by thermal oxidation.
[0099] The injection voltage of the channel ion implantation of the channel region 105 is usually 60keV to 150keV, the implantation dose is between 5e12cm-2 and 2e13cm-2, and the implanted impurity is boron. After the channel ion implantation, the channel region 105 is driven-in by thermal annealing. The drive-in condition is usually between 1000°C and 1100°C, and the time is between 30 minutes and 100 minutes.
[0100] The injection voltage of the source region 106 is usually 40keV to 80keV, the injection dose is usually between 2e15cm-2 and 6e15cm-2, and the injected ions are usually arsenic.
[0101] In step nine, the thickness of the second dielectric layer deposited completely is
[0102] In step nine, the semiconductor substrate 101 at the bottom of the source contact hole 109 is etched with the sidewall 107 as a self-alignment condition. The etching angle is usually 87 degrees to 89 degrees, and the etching depth is greater than 0.3 microns and is ensured to pass through the source region 106.
[0103] In step 10, the thickness of the interlayer film 108 is
[0104] The source contact hole 109 and the gate contact hole are usually implemented by filling Ti, TiN and W in the openings of the contact holes; the front metal layer 110 is usually implemented by depositing Al, and the thickness of the front metal layer 110 is usually 4 microns.
[0105] Whether a passivation layer and an opening of the passivation layer are needed on the topmost front metal layer 110 depends on the breakdown voltage. Generally, for a power MOSFET device with a breakdown voltage less than 40V, a passivation layer may not be needed.
[0106] A method for manufacturing a semiconductor device according to a second embodiment of the present invention:
[0107] The difference between the method of the first embodiment of the present invention and the method of manufacturing a semiconductor device of the second embodiment of the present invention is that the method further has the following features:
[0108] The semiconductor device further has a shielding layer, that is, the semiconductor device is an SGT MOSFET, and before forming the gate dielectric layer 102 and the gate conductive material layer 103, the steps of forming the shielding layer are also included, which are:
[0109] A shielding dielectric layer is formed.
[0110] The shielding layer is formed by a deposition and back etching process.
[0111] An inter-gate isolation dielectric layer is formed on the top surface of the shielding layer.
[0112] The shielding layer is formed in the gate groove 201 at the bottom of the gate conductive material layer 103. The material of the shielding layer is the same as that of the gate conductive material layer 103. The shielding layer and the bottom surface and side of the gate groove 201 are separated by a shielding dielectric layer. The shielding layer and the gate conductive material layer 103 are separated by an inter-gate isolation dielectric layer.
[0113] In fact, for SGT MOSFET, reducing the width of Mesa is more meaningful. This is because for SGT, the shielding layer as the source field plate will laterally deplete the drift region. The smaller the width of Mesa, the higher the doping concentration of the drift region can be, and the lower the device's specific on-resistance.
[0114] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.
Claims
1. A method for manufacturing a semiconductor device, characterized in that: The steps include: Step 1, providing a semiconductor substrate, wherein the top surface of the semiconductor substrate is a first surface; forming a plurality of gate trenches in the semiconductor substrate by using a photolithography definition and etching process, wherein the area between each adjacent gate trench is a semiconductor platform area; In the current flow region of the semiconductor device, a formation region of a primitive cell is formed by one of the gate trenches and one of the adjacent semiconductor platform regions, and the current flow region is composed of a plurality of primitive cells arranged periodically; Step 2: forming a gate dielectric layer, wherein the gate dielectric layer is formed on the bottom surface and side surfaces of the gate trench and extends to the surface outside the gate trench; Step 3: forming a gate conductive material layer, wherein the gate conductive material layer completely fills the gate trench and extends to a surface outside the gate trench; Step 4: performing a first self-aligned etching back on the gate conductive material layer, wherein the first self-aligned etching back completely removes the gate conductive material layer on the outer surface of the gate trench and etches back the top surface of the gate conductive material layer in the gate trench region to below the first surface to form a first self-aligned etching back trench; Step 5: forming a channel region in the semiconductor platform region; Step 6: forming a source region on the surface of the channel region, wherein the channel region at the bottom of the source region is covered by the side of the gate conductive material layer, and the surface of the channel region covered by the side of the gate conductive material layer is used to form a channel; Step 7: filling the first dielectric layer in the first self-aligned back-etched groove; Step eight, using the first dielectric layer as a self-aligned condition, back-etching the semiconductor material of the semiconductor platform region to form a second self-aligned back-etched groove, wherein the bottom surface of the second self-aligned back-etched groove is lower than the first surface and the source region is located below the bottom surface of the second self-aligned back-etched groove; Step nine, forming a sidewall composed of a second dielectric layer on the inner side surface of the second self-aligned back-etched groove, and defining a source contact hole at the top of the source region by self-alignment of the sidewall; Step 10: forming an interlayer film, a contact hole and a front metal layer, and patterning the front metal layer to form a gate and a source; The gate is connected to the gate conductive material layer through a gate contact hole, and the source is connected to the source region through a source contact hole.
2. The method for manufacturing a semiconductor device according to claim 1, wherein: In step 1, the semiconductor material constituting the semiconductor substrate includes silicon and silicon carbide.
3. The method for manufacturing a semiconductor device according to claim 2, wherein: In step 2, the gate dielectric layer is a gate oxide layer; the gate dielectric layer is grown by a thermal oxidation process; The gate conductive material layer is a polysilicon gate.
4. The method for manufacturing a semiconductor device according to claim 1, wherein: The steps of forming the gate trench include: forming a hard mask layer on the surface of the semiconductor substrate; Photolithography defines a formation region of the gate trench; The hard mask layer and the semiconductor substrate are anisotropically etched in sequence to form the gate trench.
5. The method for manufacturing a semiconductor device according to claim 4, wherein: After forming the gate trench, the method further includes performing isotropic etching to process the gate trench to make the corners of the gate trench smooth; or, after forming the gate trench, the method further includes forming a sacrificial oxide layer and then removing the sacrificial oxide layer to make the corners of the gate trench smooth.
6. The method for manufacturing a semiconductor device according to claim 4, wherein: The material of the hard mask layer includes an oxide layer, a nitride layer or a nitride oxide layer; the hard mask layer is removed after forming the gate trench and before forming the channel region in step five.
7. The method for manufacturing a semiconductor device according to claim 1, wherein: In step five, a channel implantation plus annealing drive process is used to form the channel region.
8. The method for manufacturing a semiconductor device according to claim 1, wherein: The material of the first dielectric layer includes an oxide layer, a nitride layer or a nitride oxide layer.
9. The method for manufacturing a semiconductor device according to claim 8, wherein: In step nine, the material of the second dielectric layer and the material of the interlayer film have an etching rate difference and meet the selective etching condition; The sub-steps of forming the sidewall in step nine include: Fully depositing to form a second dielectric layer; The second dielectric layer is fully etched to form the sidewall on the inner side of the second self-aligned back-etched groove.
10. The method for manufacturing a semiconductor device according to claim 9, wherein: The material of the interlayer film is an oxide layer; the material of the second dielectric layer includes a nitride layer.
11. The method for manufacturing a semiconductor device according to claim 1, wherein: The semiconductor device is a trench gate MOSFET, and the trench gate MOSFET also has a shielding layer. Before forming the gate dielectric layer and the gate conductive material layer, the steps of forming the shielding layer are also included, which are: forming a shielding dielectric layer; The shielding layer is formed by a deposition and back etching process; forming an inter-gate isolation dielectric layer on the top surface of the shielding layer; The shielding layer is formed in the gate groove at the bottom of the gate conductive material layer. The material of the shielding layer is the same as that of the gate conductive material layer. The shielding layer and the bottom surface and side of the gate groove are separated by a shielding dielectric layer. The shielding layer and the gate conductive material layer are separated by an inter-gate isolation dielectric layer.
12. The method for manufacturing a semiconductor device according to claim 1, wherein: In step nine, after forming the side wall, the step also includes etching the semiconductor substrate at the bottom of the source contact hole with the side wall as a self-alignment condition so that the bottom of the source contact hole passes through the source region and is connected to the channel region, and the source region and the channel region are simultaneously connected to the source through the source contact hole.
13. The method for manufacturing a semiconductor device according to claim 1, wherein: A gate lead-out region is also formed outside the current flow region, and the gate groove of the current flow region also extends into the gate lead-out region. A gate contact hole is formed on the top of the gate conductive material layer in the gate lead-out region, and the gate conductive material layer and the gate composed of the front metal layer are connected through the gate contact hole.
14. The method for manufacturing a semiconductor device according to claim 1, wherein: The semiconductor device is a MOSFET device, and after step 10 is completed, the following back surface processes are also included: Step 11, thinning the back side of the semiconductor substrate and forming a drain region on the back side of the semiconductor substrate, wherein the semiconductor substrate between the drain region and the channel region constitutes a drift region; Step 12: forming a back metal layer on the back side of the drain region and forming a drain electrode with the back metal layer.
15. The method for manufacturing a semiconductor device according to any one of claims 1 to 14, characterized in that: The semiconductor device is an N-type device, the channel region is P-type doped, and the source region is N-type heavily doped; the semiconductor device is a P-type device, the channel region is N-type doped, and the source region is P-type heavily doped.