AD conversion circuit, photoelectric conversion device, photoelectric conversion system, and mobile object

Abstract

The present invention provides an AD conversion circuit, a photoelectric conversion device, a photoelectric conversion system, and a mobile object. The AD conversion circuit includes a comparator configured to compare an analog signal with a ramp signal and output a comparison result signal indicating the comparison result, and performs AD conversion using the comparison result signal. During the comparison, the potential of the ramp signal changes from a first potential to a second potential over time. Before the comparison, the potential of the ramp signal changes at a first rate of change, and then changes at a second rate of change that is less than the first rate of change, changing from the first potential to a third potential between the first and second potentials. When the third potential is input to the comparator, the comparator is reset.

Description

Technical Field

[0001] Aspects of the embodiments relate to an analog-to-digital (AD) conversion circuit, a photoelectric conversion device, a photoelectric conversion system, and a moving object. Background Art

[0002] There is known an analog-to-digital (AD) conversion circuit that converts an analog signal into a digital signal using a reference signal (ramp signal) whose potential changes with the passage of time.

[0003] Japanese Patent Application Laid-Open No. 2013-150121 discusses a technique for resetting a comparator by inputting a potential (offset potential) obtained by shifting a reference signal from its initial potential. This technique sets an operating point at which the signal output from the comparator changes during AD conversion. Furthermore, the reference signal is reset to its initial potential, and this potential is changed over time from the initial potential (generating a ramp signal), thereby performing AD conversion. Summary of the Invention

[0004] According to one aspect of the embodiment, there is provided an analog-to-digital (AD) conversion circuit, which includes a comparator configured to compare an analog signal with a ramp signal and output a comparison result signal indicating a comparison result, and performs AD conversion using the comparison result signal to convert the analog signal into a digital signal, wherein, in the comparison, the potential of the ramp signal changes from a first potential to a second potential over time, and wherein, before the comparison, the potential of the ramp signal changes at a first change rate and then changes at a second change rate that is smaller than the first change rate, the potential of the ramp signal changes from the first potential to a third potential between the first potential and the second potential, and in a state where the third potential is input to the comparator, the comparator is reset.

[0005] According to another aspect of the embodiment, an AD conversion circuit is provided, which includes a comparator configured to compare an analog signal with a ramp signal and output a comparison result signal indicating a comparison result, and performs AD conversion using the comparison result signal to convert the analog signal into a digital signal, wherein, in the comparison, the potential of the ramp signal changes from a first potential to a second potential over time, wherein, before the comparison, the comparator is reset in a state where a third potential is input to the comparator, the third potential being a voltage between the first potential and the second potential, and wherein, in the comparison, during a period in which the potential of the ramp signal changes from the first potential to the third potential, the potential of the ramp signal changes at a first change rate and then changes at a second change rate that is smaller than the first change rate.

[0006] Further features of the present disclosure will become apparent from the following description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a block diagram showing the configuration of an image pickup device as an example of a photoelectric conversion device.

[0008] Figure 2 is a block diagram showing a configuration including an analog-to-digital (AD) conversion circuit.

[0009] Figure 3 is a circuit diagram showing the configuration of a ramp signal generating circuit.

[0010] Figure 4 is a timing chart showing the operation of the AD conversion circuit.

[0011] Figure 5 is a block diagram showing the configuration of an AD conversion circuit.

[0012] Figure 6 : is a circuit diagram showing the configuration of a control circuit that controls the AD conversion circuit.

[0013] Figure 7 is a circuit diagram showing the configuration of a synchronization circuit.

[0014] Figure 8 is a timing diagram showing the operation of the synchronization circuit.

[0015] Figure 9 is a circuit diagram showing the configuration of a ramp signal generating circuit.

[0016] Figure 10 is a circuit diagram showing the configuration of a ramp signal generating circuit.

[0017] Figure 11 is a timing chart showing the operation of the AD conversion circuit.

[0018] Figure 12 This is a table showing the relationship among the count value of the counter, the control signal, and the value of the current flowing through the resistance element.

[0019] Figure 13 is a block diagram showing the configuration of a photoelectric conversion system.

[0020] Figure 14A and Figure 14B The configuration and operation of the photoelectric conversion system and the moving body are shown. DETAILED DESCRIPTION

[0021] In the technology discussed in Japanese Patent Application Laid-Open No. 2013-150121, the voltage range of the reference signal from a predetermined potential to the potential at which the comparator is reset is an area in which the signal output from the comparator does not change during analog-to-digital (AD) conversion. Therefore, there is room for shortening the AD conversion period or the period for resetting the comparator. The following exemplary embodiments relate to a technology for shortening the AD conversion period or the period for resetting the comparator.

[0022] Exemplary embodiments will be described below with reference to the accompanying drawings.

[0023] In the following exemplary embodiments, an imaging device is primarily described as an example of a photoelectric conversion device according to the present disclosure. However, the exemplary embodiments are not limited to imaging devices and may also be applied to other examples of photoelectric conversion devices. Examples of photoelectric conversion devices include distance measuring devices (e.g., devices for measuring distance using focus detection or time-of-flight (TOF)) and photometric devices (e.g., devices for measuring the amount of incident light).

[0024] (First exemplary embodiment)

[0025] Figure 1 is a block diagram illustrating a configuration of an image pickup apparatus according to a first exemplary embodiment.

[0026] The imaging device includes a pixel array unit 100. In the pixel array unit 100, a plurality of pixels 101 are arranged in a plurality of rows and columns. As described below, each of the plurality of unit pixels 101 is equipped with a photoelectric conversion unit that receives incident light and generates signal charge. The pixel array unit 100 is equipped with a plurality of signal lines arranged corresponding to the columns of unit pixels 101. A vertical scanning circuit 110 selects unit pixels 101 for each row. Each unit pixel 101 in the row selected by the vertical scanning circuit 110 outputs a pixel signal based on the signal charge to the corresponding signal line.

[0027] The imaging device further includes a readout circuit 102. The readout circuit 102 supplies current to each signal line to read out a signal from the unit pixel 101. Furthermore, the readout circuit 102 supplies current to each signal line and performs signal processing on the pixel signal output from each unit pixel 101 via the corresponding signal line. Examples of signal processing performed by the readout circuit 102 include signal amplification, noise reduction in the signal (correlated double sampling), and sampling and holding.

[0028] The imaging device further includes a first bias supply circuit 103. The first bias supply circuit 103 supplies the readout circuit 102 with a voltage and a current.

[0029] The imaging device further includes a comparison circuit 104, a second bias supply circuit 105, a column memory 106, a horizontal scanning circuit 107, a ramp signal generation circuit 108, and a counter 109. The second bias supply circuit 105 supplies voltage and current to the comparison circuit 104. The ramp signal generation circuit 108 generates a ramp signal whose potential changes with the passage of time, and outputs the ramp signal to the comparison circuit 104. The comparison circuit 104 outputs a comparison result signal indicating a comparison result between the ramp signal and the pixel signal output from the readout circuit 102 to the column memory 106. The readout circuit 102 is an analog signal output unit that outputs the pixel signal as an analog signal to the comparison circuit 104.

[0030] The counter 109 generates a count signal indicating the passage of time using a pulse signal output from a phase-locked loop (PLL) circuit 113 , and outputs the count signal to the column memory 106 .

[0031] The column memory 106 holds the count signal output from the counter 109 based on the change in the signal level indicated by the comparison result signal output from the comparison circuit 104. Therefore, the column memory 106 holds the count signal indicating the signal value corresponding to the value of the pixel signal as a digital signal corresponding to the pixel signal.

[0032] The horizontal scanning circuit 107 scans each column of the column memory 106 and reads digital signals from the column memory arranged corresponding to each column of the unit pixels 101 to the digital front end (DFE) 114. The DFE 114 performs various digital signal processing on the read digital signals, such as amplification, noise reduction, addition, and correction. The DFE 114 outputs the processed digital signals to the signal output circuit 112. The signal output circuit 112 outputs the digital signals to the outside of the imaging device.

[0033] The image pickup apparatus further includes a timing generator (TG) 111. The TG 111 outputs a control signal for controlling operation to each of the vertical scanning circuit 110, the first bias supply circuit 103, the second bias supply circuit 105, the ramp signal generating circuit 108, and the PLL circuit 113.

[0034] Figure 2 2 is a block diagram showing a configuration including an AD conversion circuit 200. The AD conversion circuit 200 includes Figure 1 The comparison circuit 104, the column memory 106 and the ramp signal generation circuit 108 are shown. Figure 2 Not only the AD conversion circuit 200 but also the TG 111 and the PLL circuit 113 are shown.

[0035] Control signals P_RAMP_EN1, P_RAMP_EN2, and P_RAMP_RES are supplied from the TG 111 to the ramp signal generation circuit 108. The ramp signal generation circuit 108 supplies the reference signal RAMP_O to the comparison circuit 104. The comparison circuit 104 includes a comparator 201, capacitance elements 202 and 203, and switches 204 and 205. An inverting input terminal (first input terminal), which is one of the input nodes of the comparator 201, receives a pixel signal from the readout circuit 102 in the corresponding column through the capacitance element 202 (first capacitance element). A non-inverting input terminal (second input terminal), which is the other of the input nodes of the comparator 201, receives the reference signal RAMP_O through the capacitance element 203 (second capacitance element).

[0036] The comparator 201 compares the pixel signal with the reference signal RAMP_O and outputs a comparison result signal indicating the comparison result to the corresponding column memory 106 - 1 .

[0037] The switches 204 and 205 are controlled by the signal P_COMP_FB input from the TG 111. When the switches 204 and 205 are turned on, the charges of the capacitive elements 202 and 203 are reset, thereby resetting the comparator 201.

[0038] Despite Figure 2 The non-inverting input terminal and the inverting input terminal of the comparator 201 are not shown in the drawing, but it is assumed that the pixel signal is input to one of the non-inverting input terminal and the inverting input terminal, and the ramp signal is input to the other of the non-inverting input terminal and the inverting input terminal.

[0039] The TG 111 and the PLL circuit 113 receive a clock signal CLK as a reference clock. The TG 111 supplies a control signal P_CNT_EN to the PLL circuit 113. The PLL circuit 113 supplies a pulse signal, which serves as a counter clock signal for operating the counter 109, to the counter 109. The counter 109 counts the pulse signal, which serves as the counter clock signal, to generate a count signal. The counter 109 supplies the count signal to each of the column memories 106-1 to 106-n in each column.

[0040] Figure 3 is a circuit diagram showing details of the ramp signal generating circuit 108 .

[0041] Each of the first current source 301 and the second current source 302 is a variable current source, wherein the amount of current to be supplied is variable. The on / off of switches 303 and 304 is controlled by control signals P_RAMP_EN1 and P_RAMP_EN2 supplied from TG 111. Capacitive element 306 is charged by turning on one or both of switches 303 and 304. Reference signal RAMP_O is generated by charging capacitor element 306 with current. The on / off of switch 305 is controlled by control signal P_RAMP_RES supplied from TG 111. When switch 305 is turned on, the charge of capacitor element 306 is discharged to ground electrode GND. Therefore, the charge from capacitor element 306 is reset, thereby resetting reference signal RAMP_O.

[0042] Figure 4 It shows Figure 3 FIG. 1 is a timing diagram of the operation of the ramp signal generating circuit 108 .

[0043] In the period from time t1 to time t12, the readout circuit 102 outputs a reset level signal from each unit pixel 101 to the comparison circuit 104. In the period from time t12 to time t18, the readout circuit 102 outputs a photoelectric conversion signal from each unit pixel 101.

[0044] The reset level signal and photoelectric conversion signal output from each unit pixel 101 will now be described. Typically, each unit pixel 101 includes a photodiode serving as a photoelectric conversion unit, a transfer transistor, a floating diffusion unit, an amplifier transistor, a selection transistor, and a reset transistor. The main node of one of the source and drain of the transfer transistor corresponds to the photoelectric conversion unit, and the main node of the other of the source and drain of the transfer transistor is connected to the floating diffusion unit. The floating diffusion unit is connected to the gate of the amplifier transistor. The drain of the amplifier transistor is supplied with a power supply voltage. The source of the amplifier transistor is connected to the main node of one of the source and drain of the selection transistor. The main node of the other of the source and drain of the selection transistor is connected to a signal line provided for each column of the unit pixel 101. The main node of one of the source and drain of the reset transistor is supplied with a power supply voltage, and the main node of the other of the source and drain of the reset transistor is connected to the floating diffusion unit. The gates of each of the transfer transistor, reset transistor, and selection transistor are controlled by the vertical scanning circuit 110.

[0045] When the reset transistor is turned on, the floating diffusion unit is reset to a potential based on the power supply voltage. By turning off the reset transistor, the floating diffusion unit's reset state is released. The reset level signal output from each unit pixel 101 is a signal output from the amplifier transistor and corresponds to the potential of the floating diffusion unit after the reset state is released. The reset level signal includes noise components from the unit pixel 101.

[0046] Then, when the transfer transistor is turned on, the photodiode performs photoelectric conversion on incident light, generating signal charge, which is then transferred to the floating diffusion. Here, the signal charge is assumed to be electrons. The amplifier transistor outputs a signal corresponding to the potential of the floating diffusion to which the signal charge was transferred, as a photoelectric conversion signal. The pixel signal output from each unit pixel 101 includes a reset level signal and a photoelectric conversion signal.

[0047] This exemplary embodiment is described assuming that the readout circuit 102 has a function for inverting and amplifying the pixel signal. Specifically, as the amount of light incident on the photodiode increases, the potential of the photoelectric conversion signal decreases. Since the signal output from the readout circuit 102 is a signal obtained by inverting and amplifying the photoelectric conversion signal, the potential of the signal increases as the amount of light increases. The reset level signal output from each unit pixel 101 is referred to as an N signal, and the photoelectric conversion signal output from each unit pixel 101 is referred to as an S signal. The signal obtained by inverting and amplifying the N signal output from the readout circuit 102 is referred to as an amplified N signal, and the signal obtained by inverting and amplifying the S signal output from the readout circuit 102 is referred to as an amplified S signal.

[0048] At time t1, the signal P_RAMP_RES becomes high level (hereinafter referred to as "Hi"), and the switch 305 is turned on. As a result, the potential of the reference signal RAMP_O is reset to the ground potential GND.

[0049] At time t2, signals P_RAMP_EN2 and P_RAMP_EN1 become "Hi." Consequently, switches 303 and 304 are turned on. Accordingly, first current source 301 and second current source 302 supply current to capacitor 306. However, since switch 305 is turned on, capacitor 306 is not charged, and reference signal RAMP_O is maintained at ground potential GND.

[0050] At time t3, the signal P_RAMP_RES changes to a low level (hereinafter referred to as "Lo"), and the switch 305 is turned off. Thus, the capacitance element 306 starts to be charged with the current supplied from each of the first current source 301 and the second current source 302.

[0051] Furthermore, the signal P_COMP_FB becomes “Hi.” Therefore, the switches 204 and 205 of the comparison circuit 104 are turned on and the comparator 201 is reset.

[0052] At time t4, signal P_RAMP_EN2 becomes "Lo." Consequently, switch 304 is turned off. Then, at time t5, signal P_RAMP_EN1 becomes "Lo," and switch 303 is turned off. Specifically, during the period from time t3 to time t4, capacitor 306 is charged with current supplied from both first current source 301 and second current source 302. Furthermore, during the period from time t4 to time t5, capacitor 306 is charged with current supplied from first current source 301.

[0053] Here, assuming that the slope of the reference signal RAMP_O when the capacitor 306 is charged by both the first current source 301 and the second current source 302 is represented by d12, and the slope of the reference signal RAMP_O when the capacitor 306 is charged by the first current source 301 is represented by d1, the following equation (1) holds.

[0054] d12>d1···(1)

[0055] During the period from time t3 to time t4, the capacitor 306 is quickly charged, and during the period from time t4 to time t5, the capacitor 306 is slowly charged. Therefore, during the period from time t3 to time t4, the potential of the reference signal RAMP_O changes with the passage of time at a first rate of change. It can be said that during the period from time t4 to time t5, the reference signal RAMP_O changes with the passage of time at a second rate of change that is less than the first rate of change. In this exemplary embodiment, the potential of the reference signal RAMP_O (ground potential GND) during the period from time t1 to time t3 corresponds to the initial potential (first potential).

[0056] At time t6, signal P_COMP_FB becomes "Lo." At time t6, reference signal RAMP_O (Voffset) and the output from readout circuit 102 are clamped to capacitor element 203 and capacitor element 202, respectively. Thus, comparator 201 is reset. The potential Voffset of reference signal RAMP_O used to reset comparator 201 corresponds to the third potential.

[0057] Thereafter, the reference signal RAMP_O is reset to the ground potential GND corresponding to the first potential.

[0058] The signal output from the readout circuit 102 moves forward based on the input of the S signal. Therefore, unless the amplitude of the reference signal RAMP_O is greater than or equal to the potential Voffset, the signal level of the comparison result signal output from the comparator 201 will not change. Therefore, when the reset of the comparator 201 is completed, the reference signal RAMP_O (Voffset) clamped to the capacitor 203 is added with an offset until the comparison result signal is changed to the ground potential GND corresponding to the first potential. Therefore, the offset added to the comparator 201 is called the comparator offset. The period from time t3 to time t6 to which the comparator offset is added is called the offset addition period. The change in the potential of the reference signal RAMP_O over time may have low linearity at the beginning of the change. The accuracy of the AD conversion in the area where the linearity of the reference signal RAMP_O is low deteriorates. Therefore, by adding an offset, the beneficial effect of using the area where the linearity of the reference signal RAMP_O is excellent can be obtained.

[0059] Furthermore, by increasing the rate of change of the reference signal RAMP_O during the period from time t3 to time t4, the potential of the reference signal RAMP_O can be quickly brought to the third potential.

[0060] At time t7, the signal P_RAMP_RES becomes “Hi.” Therefore, the switch 305 is turned on, and the charge of the capacitor 306 is discharged to the ground electrode GND. As a result, the reference signal RAMP_O is reset to the ground potential GND (first potential).

[0061] At time t8, each of signals P_RAMP_EN2 and P_RAMP_EN1 becomes "Hi." Therefore, first current source 301 and second current source 302 supply current to capacitor 306. However, since switch 305 is turned on, capacitor 306 is not charged, and thus reference signal RAMP_O is maintained at ground potential GND.

[0062] At time t9, signal P_RAMP_RES becomes "Lo," and switch 305 is turned off. Consequently, capacitor 306 begins to be charged with current supplied from each of first current source 301 and second current source 302. As a result, the potential of reference signal RAMP_O changes over time. In other words, a ramp signal is generated.

[0063] At time t10, signal P_RAMP_EN2 becomes "Lo" and switch 304 is turned off. Then, at time t11, signal P_RAMP_EN1 becomes "Lo" and switch 303 is turned off. Specifically, during the period from time t9 to time t10, capacitor 306 is charged with current supplied from both first current source 301 and second current source 302. Furthermore, during the period from time t10 to time t11, capacitor 306 is charged with current supplied from first current source 301.

[0064] In other words, during the period from time t9 to time t10, the reference signal RAMP_O changes at a first change rate d12. Then, during the period from time t10 to time t11, the reference signal RAMP_O changes at a second change rate d1.

[0065] During the period from time t9 to time t11, the readout circuit 102 outputs the amplified N signal. The period from time t9 to time t11 during which the amplified N signal is AD-converted is referred to as an NAD period.

[0066] The reference signal RAMP_O at time t10 is represented by V1, and V1 <Voffset···(2)。

[0067] Therefore, the AD conversion gain in the NAD period is determined by the slope d1.

[0068] During the period from time t12 to time t14 , the signal P_RAMP_RES becomes “Hi”, and the reference signal RAMP_O is reset to the ground potential GND (first potential) again.

[0069] At time t13, each of signals P_RAMP_EN2 and P_RAMP_EN1 becomes "Hi." Accordingly, first current source 301 and second current source 302 supply current to capacitor 306. However, since switch 305 is turned on, capacitor 306 is not charged, and reference signal RAMP_O is thus maintained at ground potential GND.

[0070] At time t14, the signal P_RAMP_RES becomes "Lo," and the switch 305 is turned off. Consequently, the capacitance element 306 begins to be charged with the current supplied from each of the first current source 301 and the second current source 302. That is, a ramp signal is generated.

[0071] At time t15, signal P_RAMP_EN2 becomes "Lo," and switch 304 is turned off. Then, at time t16, signal P_RAMP_EN1 becomes "Lo." Consequently, switch 303 is turned off. Specifically, during the period from time t14 to time t15, capacitor 306 is charged with current supplied from both first current source 301 and second current source 302. Then, during the period from time t15 to time t16, capacitor 306 is charged with current supplied from first current source 301.

[0072] In other words, during the period from time t14 to time t15, the reference signal RAMP_O changes at the first change rate d12. Then, during the period from time t15 to time t16, the reference signal RAMP_O changes at the second change rate d1.

[0073] The period from time t14 to time t16 is a period for AD conversion of the amplified S signal, which is referred to as a SAD period.

[0074] As in the NAD period, the reference signal RAMP_O at time t15 is represented by V1, and the same conditions as those of the above equation (2) are set, so the AD conversion gain in the SAD period is determined by the slope d1.

[0075] During the period from time t17 to time t18, the signal P_RAMP_RES becomes “Hi.” As a result, the reference signal RAMP_O is reset to the ground potential GND.

[0076] As in this exemplary embodiment, when the reference signal RAMP_O changes from the first potential to the second potential in each of the offset addition period, the NAD period, and the SAD period, a first rate of change is used. Furthermore, when the reference signal RAMP_O changes from the second potential to the third potential (the potential at any of time t5, time t11, and time t16), a second rate of change that is smaller than the first rate of change is used. Therefore, compared to the case where the reference signal RAMP_O changes from the first potential to the third potential at the second rate of change, the offset addition period (the period for resetting the comparator 201) and the AD conversion period can be further reduced.

[0077] According to this exemplary embodiment, the reference signal RAMP_O also changes at two slopes during the offset addition period, as in the NAD period and the SAD period. During the offset addition period, for example, the reference signal RAMP_O can change at one type of slope, namely, slope d12. During at least one of the NAD period and / or the SAD period, the potential of the ramp signal can be changed using both the first change rate and the second change rate. However, as in this exemplary embodiment, the beneficial effect of reducing horizontal shading as described above can be achieved by changing the potential of the reference signal RAMP_O during the offset addition period in the same manner as in both the NAD period and the SAD period.

[0078] For example, when the AD conversion gain is low, that is, when the reference signal RAMP_O changes with a large slope, unlike in the present exemplary embodiment, the reference signal RAMP_O does not need to be controlled with multiple slopes in the NAD period and the SAD period.

[0079] As described above, according to this exemplary embodiment, the increase in the comparator offset period, NAD period, and SAD period can be suppressed by changing the AD conversion gain, thereby achieving high-speed AD conversion. Therefore, it is possible to acquire an image with excellent quality without reducing the frame rate.

[0080] In the present exemplary embodiment, the ramp signal is generated by charging the capacitance element 306 with current, and the ramp signal may be generated by discharging the capacitance element 306 .

[0081] (Second exemplary embodiment)

[0082] The differences between the first exemplary embodiment and the second exemplary embodiment will be mainly described.

[0083] If the offset component and the noise component included in the digital signal obtained during the NAD period and the digital signal obtained during the SAD period vary in each line, horizontal stripe noise may occur in an image generated using the digital signals.

[0084] The second exemplary embodiment shows a configuration in which the timing of starting to charge the capacitance element 306, the timing of changing the slope of the reference signal RAMP_O, and the timing of starting the counter operation are synchronized. This configuration makes it possible to prevent the above-mentioned horizontal stripe noise from appearing in the image.

[0085] Figure 5 is a block diagram showing the configuration of an AD conversion circuit 500 according to the second exemplary embodiment.

[0086] The AD conversion circuit 500 includes a control circuit 501 that controls the comparison circuit 104 and the counter 109 in each column. As described below, the control circuit 501 includes Figure 1 TG 111 shown.

[0087] Figure 6 is a circuit diagram showing the configuration of the control circuit 501 .

[0088] A signal CLK, which is a reference clock signal, is input to each of the TG 111 and the synchronization circuit 601. The TG 111 outputs the signals P_RAMP_EN2, P_RAMP_RES, and P_CNT_EN to the synchronization circuit 601. Furthermore, the TG 111 outputs the signal P_RAMP_EN1 to the ramp signal generation circuit 108. The synchronization circuit 601 outputs the signals P_RAMP_EN2_O and P_RAMP_RES_O to the ramp signal generation circuit 108. The synchronization circuit 601 also outputs a counter clock signal to the counter 109.

[0089] The synchronization circuit 601 includes a PLL circuit 701 and a ramp control signal circuit 702 . The ramp control signal circuit 702 generates a signal for controlling the ramp signal generation circuit 108 .

[0090] Will be in Figure 7 The configuration of the synchronization circuit 601 is described in .

[0091] The synchronization circuit 601 includes a PLL circuit 701. A signal CLK, which is a reference clock signal, is input from outside the imaging device to a phase comparator 705. The output from the phase comparator 705 is input to a filter circuit 704 including a charge pump and a loop filter. Furthermore, the output from the filter circuit 704 is input to a voltage-controlled oscillator (VCO) 703. The signal PLLCLK output from the VCO 703 is input to an AND circuit 710.

[0092] The signal PLLCLK is input to the frequency divider 706. The frequency divider 706 divides the frequency of the signal PLLCLK by N. Therefore, the signal DIVCLK output from the frequency divider 706 is expressed by the following equation (3).

[0093] DIVCLK = PLLCLK / N ··· (3)

[0094] When the PLL circuit 701 is locked, the following equation (4) holds true.

[0095] CLK = DIVCLK = PLLCLK / N ··· (4)

[0096] The signal P_CNT_EN will be described. This signal P_CNT_EN is a signal for allowing the counter clock signal to be output to the counter 109. Figure 4 The signal P_CNT_EN is not shown in FIG, but the signal P_CNT_EN is a signal that becomes “Hi” during a period from the time when the potential of the reference signal RAMP_O starts to change to the time when the change ends in each of the NAD period and the SAD period.

[0097] Flip-flop (FF) 707 synchronizes the signal change timing of signal P_CNT_EN with the signal change timing of signal CLK. FF 708 synchronizes the signal change timing of A signal P_CNT_EN_1 output from FF 707 with the signal change timing of signal DIVCLK. FF 709 synchronizes the signal change timing of A signal P_CNT_EN_2 output from FF 708 with the signal change timing of signal PLLCLK. Signal P_CNT_EN_3 output from FF 709 is input to one input terminal of AND circuit 710, and signal PLLCLK is input to the other input terminal. During the period when signal P_CNT_EN_3 is "Hi", signal PLLCLK is supplied to counter 109 as a counter clock signal.

[0098] Next, the ramp control signal circuit 702 will be described.

[0099] The signal P_RAMP_EN2 is input to the FF 714. The FF 714 synchronizes the signal change timing of the input signal P_RAMP_EN2 with the signal change timing of the signal CLK, thereby outputting the signal P_RAMP_EN2_1.

[0100] The FF 715 synchronizes the signal change timing of the input signal P_RAMP_EN2_1 with the signal change timing of the signal PLLCLK, thereby outputting the signal P_RAMP_EN2_2.

[0101] The FF 716 synchronizes the signal change timing of the input signal P_RAMP_EN2_2 with the signal change timing of the signal PLLCLK, thereby outputting the signal P_RAMP_EN2_O. The signal P_RAMP_EN2_O is input to the ramp signal generating circuit 108.

[0102] The FF 711 synchronizes the signal change timing of the input signal P_RAMP_RES with the signal change timing of the signal CLK, thereby outputting the signal P_RAMP_RES_1.

[0103] The FF 712 outputs a signal P_RAMP_RES_2 obtained by synchronizing the signal change timing of the input signal P_RAMP_RES_1 with the signal DIVCLK.

[0104] The FF 713 outputs a signal P_RAMP_RES_O obtained by synchronizing the signal change timing of the signal P_RAMP_RES_2 with the signal PLLCLK. The signal P_RAMP_RES_O is input to the ramp signal generating circuit 108.

[0105] Will refer to Figure 8 In this exemplary embodiment, the method of generating the above-mentioned control signal is described in the same manner as described in the first exemplary embodiment. Figure 8 Operations other than those shown.

[0106] Figure 8 Only how to synchronize the signals P_RAMP_EN2, CLK, DIVCLK, and PLLCLK is shown. The other signals P_RAMP_RES and P_CNT_EN can be generated in the same manner as the method of synchronizing the signal P_RAMP_EN2.

[0107] Now I will explain Figure 8 The operations of FFs 714, 715, and 716 were described previously.

[0108] During the period when the input to the FF's clock terminal is "Hi," FF 714 receives input data to the D terminal. Then, when the input to the clock terminal goes "Lo," it outputs a signal from the Q terminal. Meanwhile, FF 715 and FF 716 receive input data to the D terminal during the period when the clock terminal is "Lo." Then, when the input from the clock terminal goes "Hi," they output a signal from the Q terminal.

[0109] The FF 714 synchronizes with the falling edge of the signal CLK at time t1 and outputs the signal P_RAMP_EN2 obtained when the signal CLK is “Hi” before time t1 as the signal P_RAMP_EN2_1. In this case, the signal P_RAMP_EN2_1 changes from “Lo” to “Hi”.

[0110] FF 714 synchronizes with the falling edge of signal CLK at time t4 and outputs signal P_RAMP_EN2 obtained when signal CLK is "Hi" before time t4 as signal P_RAMP_EN2_1. In this case, signal P_RAMP_EN2_1 changes from "Hi" to "Lo." Therefore, signal P_RAMP_EN2_1 is generated by FF 714 in synchronization with signal CLK.

[0111] FF 715 synchronizes with the rising edge of the DIVCLK signal at time t2 and outputs the signal P_RAMP_EN2_1 obtained when the DIVCLK signal is "Lo" as the signal P_RAMP_EN2_2 before time t2. In this case, the signal P_RAMP_EN2_2 changes from "Lo" to "Hi". FF 715 synchronizes with the rising edge of the DIVCLK signal at time t5 and outputs the signal P_RAMP_EN2_1 obtained during the period when the DIVCLK signal is "Lo" as the signal P_RAMP_EN2_2 before time t5. In this case, the signal P_RAMP_EN2_2 changes from "Hi" to "Lo". Therefore, the signal P_RAMP_EN2_2 synchronized with the DIVCLK signal is generated by FF 715.

[0112] The FF 716 synchronizes with the rising edge of the signal PLLCLK at time t3 and outputs the signal P_RAMP_EN2_2 obtained when the signal PLLCLK is “Lo” before time t3 as the signal P_RAMP_EN2_O.

[0113] In this case, the signal P_RAMP_EN2_O changes from "Lo" to "Hi." FF 716 synchronizes with the rising edge of signal PLLCLK at time t6 and outputs signal P_RAMP_EN2_2 obtained during the period when signal PLLCLK is "Lo" before time t6 as signal P_RAMP_EN2_O. In this case, signal P_RAMP_EN2_O changes from "Hi" to "Lo." Therefore, signal P_RAMP_EN_O is generated by FF 716 in synchronization with signal PLLCLK.

[0114] In this exemplary embodiment, a common signal PLL_CLK is input to the respective clock terminals of FF 709, FF 713, and FF 716. Therefore, signals P_CNT_EN3, P_RAMP_RES_O, and PRAMP_EN2_O are synchronized by the common signal PLLCLK. Signal P_CNT_EN3 is a signal for enabling the output of a counter clock to counter 109. Signal P_RAMP_RES_O is a signal for controlling the timing of starting a potential change of reference signal RAMP_O. Signal PRAMP_EN2_O is a signal for changing the rate of potential change of reference signal RAMP_O.

[0115] In this exemplary embodiment, signals P_CNT_EN3, P_RAMP_RES_O, and PRAMP_EN2_O are synchronized. Therefore, the count signal output from counter 109 is synchronized with both the timing of the start of a potential change in reference signal RAMP_O and the timing of a change in the rate of change in the potential of reference signal RAMP_O. This configuration prevents degradation in AD conversion accuracy caused by the count signal deviating from the timing of the start of a potential change in reference signal RAMP_O or the timing of a change in the rate of change in the potential of reference signal RAMP_O. Consequently, horizontal streak noise that appears in images can be reduced.

[0116] This exemplary embodiment shows a configuration in which each of the signals P_CNT_EN3, P_RAMP_RES_O, and PRAMP_EN2_O is synchronized three times with the signals CLK, DIVCLK, and PLLCLK. However, this exemplary embodiment is not limited to this configuration. The signals P_CNT_EN3, P_RAMP_RES_O, and PRAMP_EN2_O can be synchronized with a common signal and can be synchronized at least once.

[0117] (Third exemplary embodiment)

[0118] The differences between the first exemplary embodiment and the third exemplary embodiment will be mainly described.

[0119] Figure 9 : is a circuit diagram showing the configuration of the ramp signal generating circuit 908 according to the third exemplary embodiment. The configuration of the imaging device according to the third exemplary embodiment has the following configuration: Figure 1 In the structure shown, Figure 9 The ramp signal generating circuit 908 is shown in place of the ramp signal generating circuit 108 .

[0120] The ramp signal generating circuit 908 according to the present exemplary embodiment is different from the ramp signal generating circuit 108 according to the first exemplary embodiment in that the ramp signal generating circuit 908 includes a voltage source 901 and a switch 902. The on / off state of the switch 902 is controlled by a signal P_OFFSET supplied from the TG 111. When the switch 902 is turned on, the potential Voffset is output from the voltage source 901 as the potential of the reference signal RAMP_O.

[0121] In the ramp signal generating circuit 908 according to the present exemplary embodiment, the voltage source 901 outputs the potential Voffset. Figure 4In the illustrated operation, during the period from time t3 to time t4, the capacitor 306 is charged with current from the current source, thereby changing the reference signal RAMP_O to the potential Voffset. In this exemplary embodiment, the ramp signal generating circuit 908 includes a voltage source 901 that outputs the potential Voffset. With this configuration, the period for changing the reference signal RAMP_O to the potential Voffset can be reduced.

[0122] The operation in each of the NAD period and the SAD period can be performed in the same manner as in the first exemplary embodiment.

[0123] (Fourth Exemplary Embodiment)

[0124] The differences between the first exemplary embodiment and the fourth exemplary embodiment will be mainly described.

[0125] In the first exemplary embodiment, the ramp signal generating circuit 108 generates a ramp signal by charging a capacitance element with a current supplied from a current source. In the fourth exemplary embodiment, a digital-to-analog conversion (DAC) circuit is used as the ramp signal generating circuit.

[0126] Figure 10 1111 is a circuit diagram showing a configuration of a ramp signal generating circuit 1111 according to the present exemplary embodiment. The imaging apparatus according to the present exemplary embodiment has a ramp signal generating circuit 1111 instead of Figure 1 The configuration of the ramp signal generating circuit 108 is shown.

[0127] The ramp signal generating circuit 1111 according to the present exemplary embodiment includes an AND circuit 1201 , a counter 1202 , a switch 1203 , a current source 1204 , a switch 1205 , a resistance element 1213 , and a current source group 1214 .

[0128] The current source group 1214 includes current sources 1206, 1208, 1210, and 1212 and switches 1205, 1207, 1209, and 1211. The counter 1202 outputs signals P1 to Pn to the switches 1205, 1207, 1209, and 1211, respectively. Figure 10 The current source group 1214 is shown as including four current sources and four switches. However, in reality, the current source group 1214 includes a larger number of current sources and switches. The number of current sources and the number of switches are each set to a value obtained by adding "1" to the number of bits of the digital signal generated by AD conversion. In the case of 12-bit AD conversion, "n" is 13, and therefore, 13 current sources and 13 switches are controlled by the counter 1202.

[0129] The relationship between the current amounts supplied from the current sources 1206, 1208, 1210, and 1212 is set to correspond to the nth power of 2. Specifically, the current amounts supplied from the current sources 1206, 1208, 1210, and 1212 are 1b, 2·Ib, 4·Ib, and 2·Ib, respectively. n ·Ib indicates.

[0130] Figure 12 12 is a table showing the relationship between the count value of the counter 1202, the control signal, and the current value flowing through the resistor element 1213. Figure 12 As shown in the table, every time the count value output from counter 1202 increases by "1", signal P1 repeatedly changes between "Hi" and "Lo". Every time the count value increases by "2", signal P2 repeatedly changes between "Hi" and "Lo". Every time the count value increases by "4", signal P3 repeatedly changes between "Hi" and "Lo". Figure 12 The table shows only the signals P1 to P3. The signals P1 to Pn correspond to the low bit to the high bit. The current value of each current source corresponding to the signals P1 to Pn corresponds to the n-th power of 2 of the current amount Ib set as the reference.

[0131] like Figure 12 As shown, every time the count value of the counter 1202 increases by "1", the current value flowing through the resistor element 1213 increases by Ib.

[0132] AND circuit 1201 outputs a logical AND of input signals PLLCLK and P_RAMP_E2 to counter 1202 .

[0133] The switch 1203 receives the signal P_RAMP_EN1 from the TG 111. In addition, the switch 1215 receives the signal P_RAMP_RES from the TG 111.

[0134] Figure 11 It is shown that Figure 10 The ramp signal generating circuit 1111 is shown as a timing chart of the operation of the imaging device.

[0135] During the period from time t1 to time t2, the signal P_RAMP_RES becomes “Hi.” Accordingly, the counter 1202 is reset. In addition, the switch 1215 is turned on, and the reference signal RAMP_O is reset to the ground potential GND.

[0136] During the period from time t2 to time t5, the signal P_COMP_FB becomes “Hi.” This period corresponds to the offset addition period described in the first exemplary embodiment.

[0137] During the period from time t3 to time t4, the signal P_RAMP_EN2 becomes “Hi.” During this period, the signal PLLCLK is supplied to the counter 1202. The counter 1202 supplies signals P1 to Pn to switches 1205, 1207, 1209, and 1211, respectively.

[0138] During the period from time t3 to time t6 , the signal P_RAMP_EN1 becomes “Hi.” The switch 1203 is turned on, and the current source 1204 supplies the current value Ia to the resistance element 1213 .

[0139] Assuming that the resistance value of the resistor element 1213 is represented by R1, the reference signal RAMP_O at time t3 is expressed by the following equation (5).

[0140] RAMP_O = R1 × Ia = V1 ··· (5)

[0141] During the period from time t3 to time t4 , based on the count value of the counter 1202 , the following equation (6) holds true.

[0142] RAMP_O=R1×Ia+R1×(Pn×2 n +P(n-1)×2 (n-1) +···+P3×2 2 +

[0143] P2×2 1 +P1×2 0 )×Ib···(6)

[0144] The signals Pn to P1 in the formula (6) indicate “1” when each of the signals Pn to P1 is “Hi”, and indicate “0” when each of the signals Pn to P1 is “Lo”.

[0145] At time t4, signal P_RAMP_EN2 becomes "Lo." Consequently, the supply of signal PLLCLK to counter 1202 stops, and the counting operation of counter 1202 stops. Accordingly, the total amount of current from current source group 1214 is fixed to the current value obtained at that time. The reference signal RAMP_O used in this case corresponds to the potential Voffset.

[0146] During the period from time t4 to time t6, the value of the current flowing through the resistive element 1213 does not change, so the reference signal RAMP_O is maintained at the potential Voffset. As shown in equations (5) and (6), R1×Ia does not contribute to the slope of the reference signal RAMP_O, but acts as an offset. Therefore, if the current Ia is variable, any offset can be added to the reference signal RAMP_O.

[0147] During the period from time t6 to time t7, the signal P_RAMP_RES becomes “Hi.” Therefore, the count value of the counter 1202 is reset. In addition, the switch 1215 is turned on, so the reference signal RAMP_O is reset to the ground potential GND.

[0148] During the period from time t8 to time t10, the signal P_RAMP_EN1 becomes “Hi.” During the period from time t8 to time t9, the signal P_RAMP_EN2 becomes “Hi.”

[0149] The reference signal RAMP_O obtained at time t8 is the same as the reference signal in equation (5). During the period from time t8 to time t9, based on the count value of the counter 1202, the reference signal RAMP_O gradually increases according to equation (6).

[0150] In the present exemplary embodiment, the period from time t8 to time t9 corresponds to the NAD period described in the first exemplary embodiment.

[0151] At time t9, signal P_RAMP_EN2 becomes "Lo." Consequently, the counting operation of counter 1202 stops. The total amount of current from current source group 1214 is fixed to the current value obtained at that time. During the period from time t9 to time t10, the value of the current flowing through resistor element 1213 does not change, so reference signal RAMP_O obtained at time t9 is held until time t10.

[0152] During the period from time t10 to time t11, the signal P_RAMP_RES becomes “Hi.” Therefore, the count value of the counter 1202 is reset. In addition, the switch 1215 is turned on, and the reference signal RAMP_O is reset to the ground potential GND.

[0153] During the period from time t12 to time t14, the signal P_RAMP_EN1 becomes “Hi.” During the period from time t12 to time t13, the signal P_RAMP_EN2 becomes “Hi.”

[0154] The reference signal RAMP_O obtained at time t12 is the same as the reference signal in equation (5). During the period from time t12 to time t13, based on the count value of the counter 1202, the reference signal RAMP_O gradually increases according to equation (6).

[0155] In the present exemplary embodiment, the period from time t12 to time t13 corresponds to the SAD period described in the first exemplary embodiment.

[0156] At time t13, signal P_RAMP_EN2 becomes "Lo." Thus, the counting operation of counter 1202 stops. Accordingly, the total amount of current from current source group 1214 is fixed to the current value obtained at that time. During the period from time t13 to time t14, the value of the current flowing through resistor element 1213 does not change, so reference signal RAMP_O obtained at time t13 is held until time t14.

[0157] During the period from time t14 to time t15, the signal P_RAMP_RES becomes "Hi", and the counter 1202 is reset. In addition, the switch 1215 is turned on, and the reference signal RAMP_O is reset to the ground potential GND.

[0158] As described above, any offset is added to the reference signal RAMP_0 in each of the offset addition period, the NAD period, and the SAD period. Therefore, a desired offset can be added in a short time.

[0159] Therefore, even if the slope of the reference signal RAMP_O in each of the NAD period and the SAD period is made gentle to increase the AD conversion gain, AD conversion can be started from a state where a desired offset is added to the reference signal RAMP_O while suppressing an increase in the AD conversion period. Therefore, when the AD conversion gain is high, a decrease in the frame rate can be prevented.

[0160] In addition, in the present exemplary embodiment, the signals P_RAMP_EN2 and P_CNT_EN can be synchronized using the same signal by the same method as the second exemplary embodiment.

[0161] The current value Ia obtained in the offset addition period, the current value Ia obtained in the NAD period, and the current value Ia obtained in the SAD period may be different values, respectively.

[0162] For example, assuming that the current value Ia obtained in the offset addition period is represented by Iao, and the current value Ia obtained in the other periods (at least one of the NAD period and / or the SAD period) is represented by Iaad, the following equation (7) holds.

[0163] Iao>Iaad···(7)

[0164] Therefore, even in Figure 11 During the period from time t3 to time t4 shown, the signal P_RAMP_EN2 is fixed to "Lo", and the following equation (8) also holds.

[0165] At t8, Voffset>V1···(8)

[0166] Therefore, there is no need to set the signal P_RAMP_EN2 to "Hi" in the offset addition period, and there is no need to add an offset using the current source group 1214. Therefore, the offset addition period can be shortened, and a decrease in the frame rate can be prevented.

[0167] (Fifth Exemplary Embodiment)

[0168] Will refer to Figure 13 A photoelectric conversion system according to a fifth exemplary embodiment is described. Figure 13 is a block diagram showing a schematic configuration of a photoelectric conversion system according to a fifth exemplary embodiment.

[0169] The imaging devices described in the first to fourth exemplary embodiments can be applied to various photoelectric conversion systems. Examples of applicable photoelectric conversion systems include digital still cameras, digital camcorders, surveillance cameras, copiers, fax machines, mobile phones, vehicle-mounted cameras, and satellites. Examples of photoelectric conversion systems also include camera modules and imaging devices that include optical systems (e.g., lenses). Figure 13 is a block diagram illustrating a digital camera as an example of a photoelectric conversion system.

[0170] Figure 13 The photoelectric conversion system shown includes an image pickup device 1004, a lens 1002 for focusing an optical image of a subject on the image pickup device 1004, a stop 1003 for changing the amount of light passing through the lens 1002, and a barrier 1001 for protecting the lens 1002. The lens 1002 and the stop 1003 are an optical system for focusing light on the image pickup device 1004. The image pickup device 1004 corresponds to the photoelectric conversion device (image pickup device) according to any of the above-described exemplary embodiments, and converts the optical image formed by the lens 1002 into an electrical signal.

[0171] The photoelectric conversion system also includes a signal processing unit 1007 as an image generation unit that generates an image by processing the output signal from the imaging device 1004. The signal processing unit 1007 performs various correction and compression processing as needed and outputs image data. The signal processing unit 1007 can be formed on the semiconductor substrate on which the imaging device 1004 is mounted, or on a semiconductor substrate different from the semiconductor substrate on which the imaging device 1004 is mounted. The imaging device 1004 and the signal processing unit 1007 can also be formed on the same semiconductor substrate.

[0172] The photoelectric conversion system also includes a storage unit 1010 for temporarily storing image data and an external interface unit (external I / F unit) 1013 for communicating with an external computer, etc. The photoelectric conversion system also includes a recording medium 1012, such as a semiconductor memory, for recording or reading captured image data, and a recording medium control interface unit (recording medium control I / F unit) 1011 for recording or reading data on or from the recording medium 1012. The recording medium 1012 may be incorporated into the photoelectric conversion system or may be detachably attached to the photoelectric conversion system.

[0173] The photoelectric conversion system includes: an overall control / calculation unit 1009 that controls various calculations and controls the overall operation of the digital still camera; and a timing generation unit 1008 that outputs various timing signals to each of the image pickup device 1004 and the signal processing unit 1007. In this case, the timing signal and the like may be input from the outside, and the photoelectric conversion system may include at least the image pickup device 1004 and the signal processing unit 1007 that processes the output signal output from the image pickup device 1004.

[0174] The imaging device 1004 outputs an imaging signal to the signal processing unit 1007. The signal processing unit 1007 performs predetermined signal processing on the imaging signal output from the imaging device 1004 and outputs image data. The signal processing unit 1007 generates an image using the imaging signal.

[0175] As described above, according to the present exemplary embodiment, a photoelectric conversion system to which the photoelectric conversion device (imaging device) according to any of the above-described exemplary embodiments is applied can be realized.

[0176] (Sixth Exemplary Embodiment)

[0177] Will refer to Figure 14A and Figure 14B A photoelectric conversion system and a moving object according to a sixth exemplary embodiment are described. Figure 14A and Figure 14B The configurations of a photoelectric conversion system and a moving body according to the present exemplary embodiment are shown.

[0178] Figure 14AAn example of a photoelectric conversion system for an on-vehicle camera is shown. Photoelectric conversion system 300 includes an imaging device 310. Imaging device 310 functions as a photoelectric conversion device (imaging device) according to any of the above-described exemplary embodiments. Photoelectric conversion system 300 also includes an image processing unit 312 that performs image processing on a plurality of image data acquired by imaging device 310, and a parallax acquisition unit 314 that calculates parallax (phase difference between parallax images) based on the plurality of image data acquired by photoelectric conversion system 300. Photoelectric conversion system 300 also includes a distance measurement unit 316 that calculates the distance to a target object based on the calculated parallax, and a collision determination unit 318 that determines whether a collision is likely to occur based on the calculated distance. In this case, parallax acquisition unit 314 and distance measurement unit 316 are examples of distance information acquisition units that acquire distance information regarding the distance to a target object. The term "distance information" refers to information regarding, for example, parallax, defocus amount, and distance to a target object. Collision determination unit 318 can determine the likelihood of a collision by using any of the distance information. The distance information acquisition unit can be implemented by specially designed hardware, or can be implemented by a software module. In addition, the distance information acquisition unit can be implemented by a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc. or a combination thereof.

[0179] Photoelectric conversion system 300 is connected to vehicle information acquisition device 320 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. Photoelectric conversion system 300 is also connected to an electronic control unit (ECU) 330, which outputs a control signal for generating vehicle braking force based on the determination result from collision determination unit 318. Photoelectric conversion system 300 is also connected to an alarm device 340, which issues an alarm to the driver based on the determination result from collision determination unit 318. For example, if a collision is likely to occur based on the determination result from collision determination unit 318, ECU 330 controls the vehicle to avoid the collision or minimize damage by, for example, applying the brakes, releasing the accelerator, or suppressing engine output. Alarm device 340 issues an alarm to the user by, for example, emitting an audible alarm, displaying an alarm message on a screen of a car navigation system, or vibrating the seatbelt or steering wheel.

[0180] In the present exemplary embodiment, the photoelectric conversion system 300 captures an image of the periphery of the vehicle, for example, the front or rear of the vehicle. Figure 14B The photoelectric conversion system 300 is shown when capturing an image of the front of the vehicle (imaging range 350). The vehicle information acquisition device 320 sends an instruction to the photoelectric conversion system 300 or the imaging device 310. With this configuration, the accuracy of distance measurement can be further improved.

[0181] While the exemplary embodiment described above illustrates an example of a control operation for preventing a vehicle from colliding with another vehicle, the exemplary embodiment can also be applied to control operations for autonomous driving, such as following another vehicle, and control operations for autonomous driving to prevent the vehicle from deviating from its lane. Furthermore, the photoelectric conversion system is not limited to vehicles such as those equipped with the photoelectric conversion system 300, but can be applied to mobile objects (mobile devices) such as ships, aircraft, or industrial robots. Furthermore, the exemplary embodiment is not limited to mobile objects, but can be applied to devices that widely utilize object recognition, such as intelligent transportation systems (ITS).

[0182] [Modified exemplary embodiment]

[0183] The present disclosure is not limited to the above-described exemplary embodiments and may be modified in various ways.

[0184] For example, examples in which some configurations according to any one of the above exemplary embodiments are added to other exemplary embodiments, and examples in which some configurations according to any one of the above exemplary embodiments are replaced by some configurations according to other exemplary embodiments are also included in the exemplary embodiments of the present disclosure.

[0185] The photoelectric conversion systems described above in the fifth and sixth exemplary embodiments are examples of photoelectric conversion systems to which the photoelectric conversion apparatus according to the present disclosure can be applied, and the photoelectric conversion systems to which the photoelectric conversion apparatus according to the present disclosure can be applied are not limited to Figure 13 、 Figure 14A and Figure 14B The structure shown.

[0186] The above exemplary embodiments are merely specific examples for implementing the present disclosure, and the technical scope of the present disclosure should not be interpreted restrictively by the exemplary embodiments. That is, the embodiments may be implemented in various forms without departing from the technical ideas or main features of the embodiments.

[0187] According to the present disclosure, the AD conversion period or the period for resetting the comparator can be further reduced.

[0188] While the present disclosure has been described with reference to exemplary embodiments, it is to be understood that the present disclosure is not limited to the disclosed exemplary embodiments.The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions.

Claims

1. An analog-to-digital (AD) conversion circuit, comprising a comparator configured to compare an analog signal with a ramp signal and output a comparison result signal indicating a comparison result, and performing AD conversion using the comparison result signal to convert the analog signal into a digital signal; a first capacitive element; and The second capacitive element, in, In the comparison, the potential of the ramp signal changes from a first potential to a second potential over time. Before the comparison, the potential of the ramp signal changes at a first rate of change, then changes at a second rate of change that is smaller than the first rate of change, the potential of the ramp signal changes from the first potential to a third potential between the first potential and the second potential, and the comparator is reset when the third potential is input to the comparator. The comparator includes a first input terminal and a second input terminal, The analog signal is input to the first input terminal through the first capacitive element. The ramp signal is input to the second input terminal through the second capacitive element. The comparator reset is an operation for resetting the charges of the first capacitance element and the second capacitance element. The analog signal includes a reset level signal and a photoelectric conversion signal, and In the comparison, the reset level signal is compared with the ramp signal, and the photoelectric conversion signal is compared with the ramp signal.

2. The AD conversion circuit according to claim 1, wherein In the comparison, the potential of the ramp signal changes from the first potential to a fourth potential between the first potential and the third potential at a first change rate, and changes from the fourth potential at a second change rate.

3. The AD conversion circuit according to claim 1, wherein The period length from when the potential of the ramp signal starts changing from the first potential to when the rate of change of the potential of the ramp signal changes from the first rate of change to the second rate of change in the comparison is equal to the period length in resetting of the comparator.

4. The AD conversion circuit according to claim 2, wherein: The period length from when the potential of the ramp signal starts changing from the first potential to when the rate of change of the potential of the ramp signal changes from the first rate of change to the second rate of change in the comparison is equal to the period length in resetting of the comparator.

5. The AD conversion circuit according to claim 1, wherein The potential of the ramp signal that changes from the first potential to the second potential in the comparison is equal to the potential of the ramp signal in the resetting of the comparator.

6. The AD conversion circuit according to claim 1, in, The AD conversion circuit performs multiple AD conversions and In the comparison for each of the plurality of AD conversions, while the potential of the ramp signal changes from the first potential to the third potential, the potential of the ramp signal changes at the first change rate and then changes at the second change rate.

7. The AD conversion circuit according to claim 6, wherein: The multiple AD conversions convert analog signals having different values ​​into corresponding digital signals.

8. The AD conversion circuit according to claim 6, wherein: In the plurality of AD conversions, a period from when the potential of the ramp signal starts changing from the first potential to when the rate of change of the potential of the ramp signal changes from the first rate to the second rate is the same length.

9. The AD conversion circuit according to claim 7, wherein: In the plurality of AD conversions, a period from when the potential of the ramp signal starts changing from the first potential to when the rate of change of the potential of the ramp signal changes from the first rate to the second rate is the same length.

10. The AD conversion circuit according to claim 6, wherein: In the plurality of AD conversions, the potential of the ramp signal that changes from the first potential to the second potential is the same potential.

11. The AD conversion circuit according to claim 1 , further comprising: a ramp signal generating circuit configured to generate a ramp signal; a counter configured to count the pulse signal to generate a count signal; as well as Synchronous circuits, The synchronization circuit outputs a control signal to the ramp signal generation circuit and outputs a pulse signal to the counter.

12. The AD conversion circuit according to claim 11, wherein: The control signal is a signal for changing the rate of change of the potential of the ramp signal from a first rate of change to a second rate of change.

13. The AD conversion circuit according to claim 11, in, The synchronization circuit includes a first flip-flop circuit configured to generate a control signal and including a first clock terminal, and a second flip-flop circuit configured to generate a pulse signal and including a second clock terminal, and The common signal is input to each of the first clock terminal and the second clock terminal.

14. The AD conversion circuit according to claim 1, in, The potential of the ramp signal is changed by charging or discharging the capacitive element with current, and The first change rate and the second change rate are changed by changing the current value.

15. A photoelectric conversion device comprising: The AD conversion circuit according to any one of claims 1 to 14; as well as The analog signal output unit is configured to generate electric charges based on incident light and output a signal based on the electric charges as an analog signal.

16. A photoelectric conversion system comprising: The photoelectric conversion device according to claim 15; as well as An image generating unit is configured to generate an image using the digital signal output from the photoelectric conversion device.

17. A mobile object, comprising: The photoelectric conversion device according to claim 15; as well as a distance information acquisition unit configured to acquire distance information about the distance to the target object from the parallax image based on the signal output from the photoelectric conversion device, The moving object further includes a control unit configured to control the moving object based on the distance information.

18. An analog-to-digital (AD) conversion circuit, comprising a comparator configured to compare an analog signal with a ramp signal and output a comparison result signal indicating a comparison result, and performing AD conversion using the comparison result signal to convert the analog signal into a digital signal; a first capacitive element; and The second capacitive element, in, In the comparison, the potential of the ramp signal changes from a first potential to a second potential over time. Before the comparison, the comparator is reset in a state where a third potential is input to the comparator, the third potential being a voltage between the first potential and the second potential. wherein, in the comparison, during a period in which the potential of the ramp signal changes from the first potential to the third potential, the potential of the ramp signal changes at a first change rate and then changes at a second change rate that is smaller than the first change rate; The comparator includes a first input terminal and a second input terminal, The analog signal is input to the first input terminal through the first capacitive element. The ramp signal is input to the second input terminal through the second capacitive element. The comparator reset is an operation for resetting the charges of the first capacitance element and the second capacitance element. The analog signal includes a reset level signal and a photoelectric conversion signal, and In the comparison, the reset level signal is compared with the ramp signal, and the photoelectric conversion signal is compared with the ramp signal.

19. The AD conversion circuit according to claim 18, wherein: In the comparison, the ramp signal changes from the third potential to the second potential at a second change rate.

20. The AD conversion circuit according to claim 18, wherein During resetting of the comparator, the potential of the ramp signal changes from a first potential at a first change rate and then changes to a second potential at a second change rate.

21. The AD conversion circuit according to claim 20, wherein: The period length from when the potential of the ramp signal starts changing from the first potential to when the rate of change of the potential of the ramp signal changes from the first rate of change to the second rate of change in the comparison is equal to the period length in resetting of the comparator.

22. The AD conversion circuit according to claim 20, wherein: The potential of the ramp signal that changes from the first potential to the second potential in the comparison is equal to the potential of the ramp signal in the resetting of the comparator.

23. The AD conversion circuit according to claim 18, in, The AD conversion circuit performs multiple AD conversions and In the comparison for each of the plurality of AD conversions, while the potential of the ramp signal changes from the first potential to the third potential, the potential of the ramp signal changes at the first change rate and then changes at the second change rate.

24. The AD conversion circuit according to claim 23, wherein: The multiple AD conversions convert analog signals having different values ​​into corresponding digital signals.

25. The AD conversion circuit according to claim 23, wherein: In the plurality of AD conversions, a period from when the potential of the ramp signal starts changing from the first potential to when the rate of change of the potential of the ramp signal changes from the first rate to the second rate is the same length.

26. The AD conversion circuit according to claim 24, wherein: In the plurality of AD conversions, a period from when the potential of the ramp signal starts changing from the first potential to when the rate of change of the potential of the ramp signal changes from the first rate to the second rate is the same length.

27. The AD conversion circuit according to claim 23, wherein: In the plurality of AD conversions, the potential of the ramp signal that changes from the first potential to the second potential is the same potential.

28. The AD conversion circuit according to claim 18, further comprising: a ramp signal generating circuit configured to generate a ramp signal; a counter configured to count the pulse signal to generate a count signal; as well as Synchronous circuits, The synchronization circuit outputs a control signal to the ramp signal generation circuit and outputs a pulse signal to the counter.

29. The AD conversion circuit according to claim 28, wherein: The control signal is a signal for changing the rate of change of the potential of the ramp signal from a first rate of change to a second rate of change.

30. The AD conversion circuit according to claim 28, in, The synchronization circuit includes a first flip-flop circuit configured to generate a control signal and including a first clock terminal, and a second flip-flop circuit configured to generate a pulse signal and including a second clock terminal, and The common signal is input to each of the first clock terminal and the second clock terminal.

31. The AD conversion circuit according to claim 18, in, The potential of the ramp signal is changed by charging or discharging the capacitive element with current, and The first change rate and the second change rate are changed by changing the current value.

32. A photoelectric conversion device comprising: The AD conversion circuit according to any one of claims 18 to 31; as well as The analog signal output unit is configured to generate electric charges based on incident light and output a signal based on the electric charges as an analog signal.

33. A photoelectric conversion system comprising: The photoelectric conversion device according to claim 32; as well as An image generating unit is configured to generate an image using the digital signal output from the photoelectric conversion device.

34. A mobile object comprising: The photoelectric conversion device according to claim 32; as well as a distance information acquisition unit configured to acquire distance information about the distance to the target object from the parallax image based on the signal output from the photoelectric conversion device, The moving object further includes a control unit configured to control the moving object based on the distance information.

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