Electronic device, chip, panel, decoder, and operating method

Abstract

The present invention provides a chip, an electronic device, a panel, a decoder, and an operating method of the chip and an operating method of the electronic device. The chip can control the panel to perform fingerprint sensing. The fingerprint sensing pixels of the panel are divided into a plurality of fingerprint areas along the column direction. The chip includes a selection circuit and a control circuit. The selection circuit obtains information about a selected fingerprint area among the fingerprint areas. The control circuit provides a plurality of control signals for controlling the panel to perform fingerprint sensing. The control signal includes a plurality of start pulse signals. The start pulse signals collectively indicate the selected fingerprint area. The number of fingerprint areas is greater than the number of start pulse signals.

Description

Technical Field

[0001] The present invention relates to an electronic device, a chip, a panel, a decoder, an operating method of the chip and an operating method of the electronic device. Background Art

[0002] In the current full-screen fingerprint technology, all fingerprint sensing pixels of the panel are divided into a first number of fingerprint areas along the column direction of the panel. Based on the number of fingerprint areas, a plurality of wires and a plurality of conductors having a corresponding number (equal to or greater than the first number) must be placed on the panel. These wires are used to connect between these fingerprint areas and these conductors. These conductors occupy the area of ​​the panel.

[0003] For example, if the fingerprint sensing pixels of the panel are divided into 10 fingerprint areas Zone1 to Zone10 along the column direction, each of the left and right sides of the panel requires 10 wires for driving the 10 fingerprint areas Zone1 to Zone10, respectively. The 10 wires of the conventional fingerprint sensing control chip output 10 signals (start pulse signals) to the 10 wires on one side of the panel, thereby resetting the fingerprint sensing pixels corresponding to the fingerprint area. The other 10 wires of the conventional fingerprint sensing control chip output 10 signals (start pulse signals) to the 10 wires on the other side of the panel, thereby selecting the fingerprint sensing pixels corresponding to the fingerprint area. Using the start pulse signal, the conventional fingerprint sensing control chip can notify the panel which of the fingerprint areas among the fingerprint areas Zone1 to Zone10 needs to perform scanning on the fingerprint sensing pixel.

[0004] It is conceivable that the larger the panel (ie, the greater the number of fingerprint areas), the greater the number of wires and conductors disposed on the panel. A greater number of wires and / or conductors may result in a larger bezel of the panel.

[0005] It should be noted that the contents of the "background technology" section are used to facilitate understanding of the present invention. Some (or all) of the contents disclosed in the "background technology" section may not be related to conventional technologies known to ordinary technicians in the field. The contents disclosed in the "background technology" section do not mean that the contents are already known to ordinary technicians in the field before the present application is submitted. Summary of the invention

[0006] The present invention provides a chip, an electronic device, a panel, a decoder, and an operating method of the chip and an operating method of the electronic device, which can reduce the number of start pulse signals output from the chip to the panel as much as possible.

[0007] The present invention provides a chip capable of controlling a panel to perform fingerprint sensing. The panel includes a plurality of fingerprint sensing pixels and a plurality of gate lines. The gate lines are arranged along the row direction of the panel for controlling the fingerprint sensing pixels. The fingerprint sensing pixels are divided into a first number of fingerprint regions along the column direction of the panel. Each of the fingerprint regions is coupled to a corresponding one or more gate lines among the gate lines of the panel. The chip includes a selection circuit and a control circuit. The selection circuit is configured to obtain information about a selected fingerprint region among the first number of fingerprint regions of the panel. The control circuit is coupled to the selection circuit to receive information about the selected fingerprint region. The control circuit is configured to provide a plurality of control signals to the panel for controlling the panel to perform fingerprint sensing. The control signal includes a second number of start pulse signals. The second number of start pulse signals collectively indicate the selected fingerprint region. The first number is greater than the second number.

[0008] The operating method of the chip of the present invention comprises: obtaining information about a selected fingerprint area among a first number of fingerprint areas of a panel through a selection circuit; and providing a plurality of control signals to the panel through a control circuit for controlling the panel to perform fingerprint sensing, wherein the control signal comprises a second number of start pulse signals, and the second number of start pulse signals collectively indicate the selected fingerprint area. The first number is greater than the second number.

[0009] The chip of the present invention includes a selection circuit and a control circuit. The selection circuit is configured to obtain information about a selected fingerprint area among a first number of fingerprint areas of a panel. The control circuit is coupled to the selection circuit to receive information about the selected fingerprint area. The control circuit is configured to provide a plurality of control signals to the panel for controlling the panel to perform fingerprint sensing. The control signal includes a plurality of start pulse signals. The start pulse signal is used to be provided to a decoder disposed on the panel so that the decoder obtains information about the selected fingerprint area according to a plurality of logic values ​​of the start pulse signal.

[0010] The operating method of the chip of the present invention includes: obtaining information about a selected fingerprint area among a first number of fingerprint areas of a panel through a selection circuit; and providing multiple control signals to the panel through a control circuit for controlling the panel to perform fingerprint sensing, wherein the control signal includes multiple start pulse signals, and the start pulse signals are used to be provided to a decoder disposed on the panel so that the decoder obtains information about the selected fingerprint area according to multiple logic values ​​of the start pulse signals.

[0011] The electronic device of the present invention includes a panel and a chip. The panel includes a plurality of fingerprint sensing pixels and a plurality of first gate lines, and the plurality of first gate lines are arranged along the row direction of the panel for controlling the fingerprint sensing pixels. The fingerprint sensing pixels are divided into a first number of fingerprint areas along the column direction of the panel. Each of the fingerprint areas is coupled to a corresponding one or more first gate lines among the first gate lines of the panel. The chip is capable of controlling the panel to perform fingerprint sensing. The chip is configured to obtain information about a selected fingerprint area among the first number of fingerprint areas of the panel and provide a plurality of first control signals to the panel for controlling the panel to perform fingerprint sensing. The first control signal includes a second number of start pulse signals. The second number of start pulse signals collectively indicate the selected fingerprint area. The first number is greater than the second number.

[0012] The operating method of the electronic device of the present invention includes: dividing a plurality of fingerprint sensing pixels of a panel into a first number of fingerprint areas along the column direction of the panel, wherein each of the fingerprint areas is coupled to a corresponding one or more gate lines among a plurality of gate lines of the panel, and the gate lines are arranged along the row direction of the panel for controlling the fingerprint sensing pixels; and controlling the panel through a chip to perform fingerprint sensing so as to obtain information about a selected fingerprint area among the first number of fingerprint areas of the panel and provide a plurality of control signals to the panel for controlling the panel to perform fingerprint sensing, wherein the control signal includes a second number of start pulse signals, the second number of start pulse signals collectively indicate the selected fingerprint area, and the first number is greater than the second number.

[0013] The electronic device of the present invention includes a panel and a chip. The panel includes a plurality of fingerprint sensing pixels and a plurality of first gate lines, and the plurality of first gate lines are arranged along the row direction of the panel for controlling the fingerprint sensing pixels. The fingerprint sensing pixels are divided into a first number of fingerprint areas along the column direction of the panel. Each of the fingerprint areas is coupled to a corresponding one or more first gate lines among the first gate lines of the panel. The chip is capable of controlling the panel to perform fingerprint sensing. The chip is configured to obtain information about a selected fingerprint area among the first number of fingerprint areas of the panel and provide a plurality of first control signals to the panel for controlling the panel to perform fingerprint sensing. The first control signal includes a plurality of start pulse signals. The start pulse signal is used to provide to a decoder disposed on the panel so that the decoder obtains information about the selected fingerprint area according to a plurality of logic values ​​of the start pulse signal.

[0014] The operating method of the electronic device of the present invention includes: arranging a plurality of gate lines of the panel along the row direction of the panel for controlling a plurality of fingerprint sensing pixels of the panel; dividing the fingerprint sensing pixels into a first number of fingerprint areas along the column direction of the panel, wherein each of the fingerprint areas is coupled to a corresponding one or more gate lines among the gate lines of the panel; and controlling the panel through a chip to perform fingerprint sensing so as to obtain information about a selected fingerprint area among the first number of fingerprint areas of the panel and provide a plurality of control signals to the panel for the control panel to perform fingerprint sensing, wherein the control signals include a plurality of start pulse signals, and the start pulse signals are used to provide to a decoder disposed on the panel so that the decoder obtains information about the selected fingerprint area according to a plurality of logic values ​​of the start pulse signals.

[0015] The panel of the present invention includes a plurality of fingerprint sensing pixels, a plurality of first gate lines, and a first gate-on-array (GOA) circuit. The first gate lines are arranged along the row direction of the panel for controlling the fingerprint sensing pixels. The fingerprint sensing pixels are divided into a first number of fingerprint regions along the column direction of the panel. Each of the fingerprint regions is coupled to a corresponding one or more first gate lines among the first gate lines of the panel. The GOA circuit is disposed on the panel. The GOA circuit is configured to receive a control signal from a chip and generate a plurality of first scanning signals to control the first gate lines respectively to perform fingerprint sensing, wherein the control signal includes a plurality of start pulse signals. The GOA circuit includes a decoder. The decoder is configured to decode the start pulse signal to obtain information about the selected fingerprint region for performing fingerprint sensing.

[0016] The decoder of the present invention is applicable to a panel including a plurality of fingerprint sensing pixels. The decoder includes a plurality of decoder units. The plurality of input terminals of each of the decoder units are configured to receive all of the first plurality of start pulse signals. Each of the decoder units is configured to decode the first plurality of start pulse signals into a corresponding one of the second plurality of start pulse signals.

[0017] In summary, the chip provided by the embodiment of the present invention can output a start pulse signal to the panel, wherein the start pulse signal relates to a selected fingerprint area among the first number of fingerprint areas of the panel. The panel can generate multiple scanning signals according to the start pulse signal to be provided to the selected fingerprint area. The number of start pulse signals is less than the number of fingerprint areas. Therefore, the electronic device can achieve the goal of reducing the number of start pulse signals provided by the chip to the panel as much as possible.

[0018] In order to better understand the above features and advantages of the present invention, embodiments are described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and together with the description serve to explain the principles of the present invention.

[0020] Figure 1 is a schematic circuit block diagram illustrating an electronic device according to an embodiment of the present invention.

[0021] Figure 2 This is to explain the Figure 1 Schematic diagram of the layout of the panel and fingerprint sensor depicted in FIG.

[0022] Figure 3 This is to explain the Figure 2 Schematic diagram of a partial layout of the panel shown in FIG.

[0023] Figure 4 This is to explain the Figure 3 FIG. 4 is a circuit diagram of a fingerprint sensing pixel shown in FIG.

[0024] Figure 5 This is to explain the Figure 3 Schematic diagram of signal timing of an integrated circuit shown in FIG.

[0025] Figure 6 This is to explain the Figure 1 Schematic circuit block diagram of the fingerprint sensing control circuit depicted in .

[0026] Fig. 7A This is a description of an embodiment of the present invention Figure 1 Schematic circuit block diagram of the fingerprint sensing control circuit depicted in .

[0027] Figure 7B This is a diagram illustrating another embodiment of the present invention. Figure 1 Schematic circuit block diagram of the fingerprint sensing control circuit depicted in .

[0028] Figure 8 is a flow chart illustrating a method of operation according to an embodiment of the present invention.

[0029] Fig. 9 is a flow chart illustrating an operating method according to another embodiment of the present invention.

[0030] Fig.10 This is a description of an embodiment of the present invention Fig. 7A Schematic circuit block diagram of the control circuit depicted in .

[0031] Fig.11 This is a diagram illustrating another embodiment of the present invention. Fig. 7ASchematic circuit block diagram of the control circuit depicted in .

[0032] Fig.12 This is a description of an embodiment of the present invention Fig. 7A Schematic circuit block diagram of the decoder depicted in .

[0033] Figures 13 to 26 The invention is described in detail according to different embodiments of the present invention. Fig.12 Schematic circuit block diagram of the decoder depicted in .

[0034] Description of Figure Numbers

[0035] 20: touch area;

[0036] 100: electronic device 100;

[0037] 110: processor 110;

[0038] 120: fingerprint sensing control circuit;

[0039] 121, 124: control circuit;

[0040] 122: Select circuit;

[0041] 123: fingerprint reading circuit;

[0042] 130: touch control circuit;

[0043] 135: TDDI circuit;

[0044] 140: display driving circuit;

[0045] 150: Panel;

[0046] 151: Multiplexer circuit;

[0047] 152, 152a, 152b: decoder;

[0048] 160: fingerprint sensor;

[0049] 200: Integrated circuit 200;

[0050] 201: Flexible circuit board;

[0051] 610, 710, 720: start pulse generating circuit;

[0052] 730: switch circuit;

[0053] C1: capacitor;

[0054] CK: clock signal;

[0055] D_SELCT: selected area information;

[0056] D1: photodiode;

[0057] DGL, FPR_GL1, FPR_GL2: gate lines;

[0058] DP, FP, TP: Operation;

[0059] DPix: display pixels;

[0060] DU_1, DU_2, DU_3, DU_31, DU_n-1, DU_n: decoder unit;

[0061] FPR_GLi_RESET, FPR_GL1_RESET, FPR_GL2_RESET, FPR_GL3_RESET, FPR_GLi_SEL / WRITE, FPR_GL1_SEL / WRITE, FPR_GL2_SEL / WRITE, FPR_GL3_SEL / WRITE: scan signal;

[0062] FSU: fingerprint sensing pixel;

[0063] GOA1, GOA2, GOA2_1, GOA2_2: GOA circuit;

[0064] S_1, S_5, S_m, S_n, S1_1, S1_m, S2_1, S2_m, SP_1, SP_2, SP_3, SP_4, SP_5, SP_6, SP_30, SP_31, SP_n-1, SP_n, SP_i, SP1_i, SP1_1, SP1_2, SP1_3, SP1_4, SP1_5, SP1_6, SP1_n, SP2_i, SP2_1, SP2_2, SP2_3, SP2_4, SP2_5, SP2_6, SP2_n: start pulse signal;

[0065] S410, S420, S510, S520, S530: steps;

[0066] SPB: blue sub-pixel;

[0067] SPG: green sub-pixel;

[0068] SPR: red sub-pixel;

[0069] SG_1, SG_2, SG_3, SG_4, SG_n: fingerprint area;

[0070] SL: sensing line;

[0071] SN_1, SN_2: sensing groups;

[0072] SR_1, SR_2, SR_3, SR_4, SR_n-1, SR_n, SR1_1, SR1_2, SR1_3, SR1_4, SR1_n, SR2_1, SR2_2, SR2_3, SR2_4, SR2_n: shift register group;

[0073] SW_FP, SWB, SWG, SWR, T1, T2: switch;

[0074] T3: transistor;

[0075] TDDI_GCK1, TDDI_GCK2, TDDI_STV, TDDI_SW_FP, TDDI_SWB, TDDI_SWG, TDDI_SWR: signals;

[0076] Vbias1, Vbias2: reference voltage;

[0077] VDD: system voltage;

[0078] Vout: output voltage;

[0079] Vout1: sensing result;

[0080] Vout2: reset result;

[0081] Z1, Z2, Z3, Z4: fingerprint sensing blocks. DETAILED DESCRIPTION

[0082] The term "coupling (or connection)" throughout the specification (including claims) of the present application is widely used, and covers direct and indirect connections or coupling members. For example, if the present disclosure describes that the first device is coupled (or connected) to the second device, it should be interpreted that the first device can be directly connected to the second device, or the first device can be indirectly connected to the second device via other devices or by a coupling member. The terms such as "first" and "second" mentioned throughout the specification (including claims) of the present application are only used to name the name of the element or distinguish different embodiments or scopes, and are not intended to limit the upper or lower limit of the number of elements, and are not intended to limit the order of the elements. In addition, the elements / components / steps with the same reference numerals represent the same or similar parts in the drawings and embodiments. The elements / components / symbols with the same reference numerals in different embodiments can refer to the relevant description.

[0083] Figure 1 1 is a schematic circuit block diagram of an electronic device 100 according to an embodiment of the present invention. The electronic device 100 may be a mobile device or other non-mobile devices. Figure 1The electronic device 100 described in the figure includes a processor 110, a fingerprint sensing control circuit 120, a touch control circuit 130, a display driver circuit 140, and a panel 150. It should be noted that even though the fingerprint sensing control circuit 120, the touch control circuit 130, and the display driver circuit 140 are described as different circuit blocks, part or all of each block may be integrated with another (or two) or all blocks. Based on design requirements, in some embodiments, part or all of the fingerprint sensing control circuit 120, the touch control circuit 130, and the display driver circuit 140 may be embedded in a single chip or separated into different chips. The chip can communicate with the processor 110 and control the panel 150.

[0084] Based on design requirements, in some embodiments, the processor 110 includes an application processor (AP), a central processing unit (CPU), a microcontroller or other processor (processing circuit). The processor 110 can be coupled to the display driver circuit 140 to provide image frames. The display driver circuit 140 can be coupled (directly or indirectly) to the panel 150. The display driver circuit 140 can drive / control the display panel 150 to display an image in the display area of ​​the panel 150.

[0085] Based on design requirements, the panel 150 may be a touch display panel. For example, the panel 150 may include a touch detector (not shown). The touch control circuit 130 is coupled to (and controls) the touch detector of the panel 150. The touch control circuit 130 may control the touch detection on the panel 150 to obtain a touch area corresponding to an object (e.g., a finger) on the panel 150. The processor 110 is coupled to the touch control circuit 130 to receive the result of the touch sensing (touch area).

[0086] The panel 150 may be any panel having a fingerprint sensing function. The specific structure of the panel 150 is not limited in the present embodiment. Based on design requirements, the panel 150 may be a display panel having an in-display fingerprint recognition function. For example, in some embodiments, the panel 150 further includes a fingerprint sensor 160, and the fingerprint sensor 160 includes a plurality of fingerprint sensing pixels. Based on design requirements, the fingerprint sensor 160 may be an optical fingerprint sensor or other fingerprint sensors, such as a capacitive fingerprint sensor.

[0087] The fingerprint sensor 160 may be placed under the panel 150. Alternatively, the fingerprint sensor 160 may be embedded in the panel 150. The implementation details of the panel 150 may be determined based on design requirements. For example, the fingerprint sensor 160 may be arranged in one of an on-display configuration, a below-display configuration, a local in-display configuration, and a global in-display configuration. Alternatively, the fingerprint sensor 160 may be arranged in another configuration.

[0088] Part (or all) of the display area of ​​the panel 150 may serve as a sensing area of ​​the fingerprint sensor 160 for sensing fingerprints. Generally speaking, as the area of ​​the sensing area increases, the user's degree of freedom in operation may increase. The sensing area (fingerprint sensor 160) may have a plurality of sensing units (fingerprint sensing pixels). When the user presses a finger on any orientation of the sensing area of ​​the panel 150, the fingerprint sensor 160 may sense / recognize the fingerprint of the user's finger. Based on design requirements, in some embodiments, the panel 150 may perform optical fingerprint sensing, and the fingerprint sensor 160 of the panel 150 includes a plurality of optical fingerprint sensing pixels capable of sensing light.

[0089] The fingerprint sensing control circuit 120 may be coupled to the fingerprint sensor 160 of the panel 150 to control the fingerprint sensing of the panel 150 and read the result of the fingerprint sensing. The processor 110 is coupled to the fingerprint sensing control circuit 120 to receive the sensing result (i.e., the sensing signal). Based on the design requirements, in some embodiments, the fingerprint sensing control circuit 120, the touch control circuit 130, and the display driver circuit 140 may be different integrated circuits. In some other embodiments, the touch control circuit 130 and the display driver circuit 140 may be integrated in a touch with display driver integration (TDDI) chip (or TDDI circuit 135), and the fingerprint sensing control circuit 120 is implemented in another chip (or integrated circuit). The TDDI circuit 135 may control the touch operation and display operation on the panel 150. In some other embodiments, the fingerprint sensing control circuit 120 and the TDDI circuit 135 may be integrated in a single integrated circuit (chip) 200. The integrated circuit 200 may control the fingerprint sensing of the panel 150, and the touch operation and display operation on the panel 150.

[0090] Figure 2 This is to explain the Figure 1Schematic diagram of the layout of the panel 150 and the fingerprint sensor 160 depicted in FIG. The fingerprint sensor 160 has a plurality of fingerprint sensing circuits, and these fingerprint sensing circuits form an array. The flexible circuit board 201 is electrically connected to the panel 150, and the integrated circuit 200 is disposed on the flexible circuit board 201. According to design requirements, one or more of the fingerprint sensing control circuit 120, the touch control circuit 130, and the display driving circuit 140 can be configured in the integrated circuit 200. Figure 2 In the embodiment shown in FIG. 1 , the fingerprint sensor 160 is divided into 20 fingerprint regions in the Y direction and one fingerprint region in the X direction. Each fingerprint region has a plurality of display rows, each display row has a plurality of display pixels, and each (or a plurality of) display pixels is equipped with a fingerprint sensing circuit.

[0091] For example, Figure 3 This is to explain the Figure 2 FIG. 1 is a schematic diagram of a partial layout of the panel 150 shown in FIG. Figure 3 In the embodiment shown in FIG. 1 , the panel 150 has a plurality of display rows, and each display row has a plurality of display pixels DPix, and one display pixel DPix has a plurality of sub-pixels, such as a red sub-pixel SPR, a green sub-pixel SPG, and a blue sub-pixel SPB (not limited thereto). One or more gate on array (GOA) circuits, such as a GOA circuit GOA1 of the panel 150, may be coupled to the display pixel DPix via a plurality of gate lines DGL. The GOA circuit GOA1 scans the gate line DGL of the display pixel DPix according to the control of the TDDI circuit 135. The GOA circuit GOA1 may be implemented as one or more GOA circuit blocks. In addition, the GOA circuit GOA1 may be disposed on one side or both sides of the display panel.

[0092] Each (or more) display pixel DPix may be equipped with a fingerprint sensing pixel FSU or arranged together with the fingerprint sensing pixel FSU. One or more GOA circuits, for example, the GOA circuit GOA2 of the panel 150 may be coupled to the fingerprint sensing pixel FSU via multiple gate lines (e.g., FPR_GL1 and FPR_GL2). The GOA circuit GOA2 scans the gate line FPR_GL1 and the gate line FPR_GL2 of the fingerprint sensing pixel FSU according to the control of the fingerprint sensing control circuit 120. According to design requirements, each of the gate line FPR_GL1 and the gate line FPR_GL2 may be a single wire or include multiple wires. In addition, the GOA circuit GOA2 may be implemented as one or more GOA circuit blocks. In addition, the GOA circuit GOA2 may be disposed on one or both sides of the display panel. Therefore, each of the gate line FPR_GL1 and the gate line FPR_GL2 may include a circuit for transmitting a scan signal FPR_GLi_RESET ( Figure 4) and / or for transmitting the scan signal FPR_GLi_SEL / WRITE ( Figure 4 ) of the selected wires.

[0093] As an example, a GOA circuit GOA2 including one or more GOA circuit blocks is implemented on one side of the display panel, and each of the gate lines FPR_GL1 and FPR_GL2 may include a gate line for transmitting a scan signal FPR_GLi_RESET ( Figure 4 ) and a reset wire for transmitting a scan signal FPR_GLi_SEL / WRITE ( Figure 4 As another example, a GOA circuit GOA2_1 (not shown) including one or more GOA circuit blocks is implemented on one side of the display panel, and each of the gate lines may include a gate line for transmitting a scan signal FPR_GLi_RESET ( Figure 4 and another GOA circuit GOA2_2 including one or more GOA circuit blocks is implemented on the other side of the display panel, and each of the gate lines may include a reset wire for transmitting a scan signal FPR_GLi_SEL / WRITE ( Figure 4 Different circuit arrangements of the GOA circuits for scanning display pixels and fingerprint pixels can be made according to design requirements and are not limited in the present disclosure.

[0094] Figure 4 FIG. 1 is a circuit diagram illustrating a fingerprint sensing pixel according to an embodiment. The fingerprint sensing pixel may be Figure 3 The fingerprint sensing pixel FSU shown in FIG. 1 is not limited thereto. Figure 4 In the embodiment shown in FIG. 1 , the fingerprint sensing pixel FSU includes a switch T1, a switch T2, a transistor T3, a capacitor C1, and a photodiode D1. The switch T1 is controlled by a scan signal FPR_GLi_RESET. The scan signal FPR_GLi_RESET is configured to control the corresponding fingerprint sensing pixel FSU to perform a reset operation. The scan signal FPR_GLi_RESET can be Figure 5 The switch T2 is controlled by the scan signal FPR_GLi_SEL / WRITE. The scan signal FPR_GLi_SEL / WRITE is configured to control the corresponding fingerprint sensing pixel FSU to perform a selection / write operation. The scan signal FPR_GLi_SEL / WRITE can be Figure 5The cathode of the photodiode D1 is coupled to the system voltage VDD via the switch T1. The anode of the photodiode D1 is coupled to the reference voltage Vbias1. Figure 4 Vbias2 shown in FIG. 2 is another reference voltage. For example, a bias circuit including an N-type metal oxide semiconductor (NMOS) transistor controlled by the reference voltage Vbias2 can be coupled to the fingerprint pixel to draw current from the sensing line SL. According to design requirements, the NMOS transistor controlled by the reference voltage Vbias2 can be implemented in the integrated circuit 200 or outside. Different structures of the fingerprint sensing pixel can be implemented and are not limited in the present disclosure.

[0095] Figure 5 is a schematic diagram illustrating the signal timing of a chip capable of controlling a panel to perform fingerprint sensing according to an embodiment. The chip may be implemented as Figure 3 The integrated circuit 200 shown in FIG. 1 is not limited thereto. Figure 5 In the embodiment shown in FIG. 1 , the signal TDDI_STV represents a start pulse for display driving operation. The signals TDDI_GCK1 and TDDI_GCK2 represent clock signals for display driving operation. The signal TDDI_SWR represents Figure 3 The signal TDDI_SWG represents the control signal of the switch SWR shown in FIG. Figure 3 The signal TDDI_SWB represents the control signal of the switch SWG shown in FIG. Figure 3 The signal TDDI_SW_FP represents the control signal of the switch SWB shown in FIG. Figure 3 . The operation DP represents a display driving operation performed by the integrated circuit 200. The operation TP represents a touch sensing driving operation performed by the integrated circuit 200. The operation FP represents a fingerprint sensing driving operation performed by the integrated circuit 200. The start pulse signal SP_4, the start pulse signal SP_5 and the start pulse signal SP_6 represent start pulses for the fingerprint sensing driving operation FP. The scan signal FPR_GL1_RESET, the scan signal FPR_GL2_RESET and the scan signal FPR_GL3_RESET represent reset signals for the fingerprint sensing driving operation FP. The scan signal FPR_GL1_SEL / WRITE, the scan signal FPR_GL2_SEL / WRITE and the scan signal FPR_GL3_SEL / WRITE represent selection signals for the fingerprint sensing driving operation FP.

[0096] In the first step, the integrated circuit 200 performs a fingerprint sensing driving operation FP to Figure 5 The start pulse signal SP_4, the start pulse signal SP_5, and the start pulse signal SP_6 shown in FIG. 1 are sequentially output to the panel 150. The start pulse signal SP_4 may include one or more start pulses, such as the start pulse signal SP1_4 and the start pulse signal SP2_4, the start pulse signal SP_5 may include one or more start pulse signals, such as the start pulse SP1_5 and the start pulse SP2_5, and the start pulse signal SP_6 may include start pulse signals, such as the start pulse SP1_6 and the start pulse SP2_6. In some embodiments, the start pulse signal SP_i (e.g., the start pulse signal SP_4, the start pulse signal SP_5, and the start pulse signal SP_6) can be used to generate the scan signal FPR_GLi_RESET (e.g., the scan signal FPR_GL1_RESET, the scan signal FPR_GL2_RESET, and the scan signal FPR_GL3_RESET) and to generate the scan signal FPR_GLi_SEL / WRITE (e.g., the scan signal FPR_GL1_SEL / WRITE, the scan signal FPR_GL2_SEL / WRITE, and the scan signal FPR_GL3_SEL / WRITE). The start pulse signal SP_i can be generated by a GOA circuit on one side of the display panel, as will be described in Fig. 7A . Additionally or alternatively, the start pulse signal SP1_i (e.g., the start pulse signal SP1_4, the start pulse signal SP1_5, and the start pulse signal SP1_6) may be used to generate the scan signal FPR_GLi_RESET (e.g., the scan signal FPR_GL1_RESET, the scan signal FPR_GL2_RESET, and the scan signal FPR_GL3_RESET), and the start pulse signal SP2_i (e.g., the start pulse signal SP2_4, the start pulse signal SP2_5, and the start pulse signal SP2_6) may be used to generate the scan signal FPR_GLi_SEL / WRITE (e.g., the scan signal FPR_GL1_SEL / WRITE, the scan signal FPR_GL2_SEL / WRITE, and the scan signal FPR_GL3_SEL / WRITE). The scan signal FPR_GLi_RESET sequentially turns on the reset switch T1 of each fingerprint sensing pixel FSU, so that the cathode of the photodiode D1 is reset to VDD (e.g., 5 volts). The start pulse signal SP1_i may be generated by a GOA circuit on one side of the display panel, and the start pulse signal SP2_i may be generated by another GOA circuit on the other side of the display panel, as will be described in Figure 7B More explanation in .

[0097] In the second step, the scan signal FPR_GLi_RESET (for example, the scan signal FPR_GL1_RESET, the scan signal FPR_GL2_RESET, or the scan signal FPR_GL3_RESET) disconnects the reset switch T1, and the voltage on the photodiode D1 is 5 volts. When light is irradiated on the fingerprint, it can generate reflected light. The reflected light illuminates the photodiode D1, which speeds up the discharge speed of the photodiode D1. The reflected light of the fingerprint peak is brighter, which makes the resistance of the photodiode D1 smaller, and the cathode discharge speed is faster, thereby obtaining a lower cathode voltage (for example, about 2 volts). The reflected light of the fingerprint valley is darker, which makes the resistance of the photodiode D1 larger. At this time, the cathode discharge speed is slow, thereby obtaining a large cathode voltage (for example, about 3 volts).

[0098] In the third step, the scan signal FPR_GLi_SEL / WRITE (e.g., the scan signal FPR_GL1_SEL / WRITE, the scan signal FPR_GL2_SEL / WRITE, or the scan signal FPR_GL3_SEL / WRITE) sequentially turns on the switch T2 of each fingerprint sensing pixel FSU, and transmits the cathode voltage of the photodiode D1 to the fingerprint sensing line as the output voltage Vout. In the fingerprint sensing driving operation FP, the control signal TDDI_SW_FP is a high logic level (the control signal TDDI_SWR, the control signal TDDI_SWG, and the control signal TDDI_SWB are low logic levels) to select (implement) the fingerprint sensing driving operation FP. At this time, the analog front end (AFE) circuit of the fingerprint sensing control circuit 120 can read the sensing result Vout1 (output voltage Vout) of the fingerprint sensing pixel FSU.

[0099] In the fourth step, the scan signal FPR_GLi_RESET turns on the reset switch T1, and the cathode of the photodiode D1 is reset to the system voltage VDD (e.g., 5 volts) again. The system voltage VDD is transmitted to the fingerprint sensing line as the output voltage Vout. At this time, the AFE circuit of the fingerprint sensing control circuit 120 can read the reset result Vout2 (output voltage Vout). In the fifth step, the fingerprint sensing control circuit 120 can subtract the reset result Vout2 and the sensing result Vout1 to obtain the fingerprint information.

[0100] Figure 6 is a schematic circuit block diagram illustrating a fingerprint sensing control circuit according to an embodiment. The fingerprint sensing control circuit may be implemented as Figure 1 The fingerprint sensing control circuit 120 depicted in FIG. 1 is not limited thereto in the present disclosure. Figure 6 In the example illustrated in FIG. 1 , all fingerprint sensing pixels in the sensing area of ​​the panel 150 are divided into a plurality of fingerprint sensing blocks (ie, Figure 6 Multiple small blocks described in Figure 6 The fingerprint sensing block Z1, the fingerprint sensing block Z2, the fingerprint sensing block Z3 ​​and the fingerprint sensing block Z4 described in FIG. Figure 1 and Figure 6 , the touch control circuit 130 can perform touch detection on the panel 150 to obtain the touch area 20 corresponding to the finger on the display panel 150 .

[0101] The panel 150 further includes a plurality of gate lines arranged along the row direction of the panel 150 , for example Figure 6 , and the gate lines FPR_GL1 and FPR_GL2 described in the figure. According to design requirements, each of the gate lines (such as the gate lines FPR_GL1 and the gate lines FPR_GL2) can be a single wire or include multiple wires. For example, the gate line FPR_GL1 can include a signal for transmitting the scan signal FPR_GL1_RESET ( Figure 5 ) and a reset wire for transmitting a scan signal FPR_GL1_SEL / WRITE ( Figure 5 The gate line FPR_GL2 may include a selection line for transmitting a scan signal FPR_GL2_RESET ( Figure 5 ) and a reset wire for transmitting a scan signal FPR_GL2_SEL / WRITE ( Figure 5 The gate lines are used to control the fingerprint sensing pixels of the panel 150. The fingerprint sensing pixels of the panel 150 are divided into a first number of fingerprint regions along the column direction of the panel 150, for example Figure 6 Each of the fingerprint regions SG_1 to SG_n is coupled to a corresponding one or more gate lines among the gate lines of the panel 150.

[0102] The gate-on-array (GOA) circuit of the panel 150 includes one or more shift register groups, such as Figure 6 The shift register group SR_1, shift register group SR_2, shift register group SR_3, shift register group SR_4, ... and shift register group SR_n described in the above description, wherein n may be any integer determined based on design requirements. Each of the fingerprint regions SG_1 to SG_n may be coupled to a corresponding one of the shift register groups SR_1 to SR_n, such as Figure 6As described in . Each of the shift register groups SR_1 to SR_n can receive one of the start pulse signal SP_1, start pulse signal SP_2, start pulse signal SP_3, start pulse signal SP_4, ... start pulse signal SP_n of the fingerprint sensing control circuit 120. One or more clock signals CK can trigger the shift register groups SR_1 to SR_n. The implementation details of the shift register groups SR_1 to SR_n are not limited in this embodiment. Based on design requirements, in some embodiments, any of the shift register groups SR_1 to SR_n can include a conventional shift register or other shift register circuits.

[0103] exist Figure 6 In the embodiment described in , the fingerprint sensing control circuit 120 (chip) may control the panel 150 to perform fingerprint sensing. Based on the touch sensing of the touch control circuit 130, the fingerprint sensing control circuit 120 (chip) may further obtain the touch area 20 corresponding to the object (e.g., finger) on the panel 150. According to the touch area 20, the fingerprint sensing control circuit 120 (chip) may select one or more fingerprint areas (e.g., fingerprint area SG_2 and fingerprint area SG_3) covering the touch area 20 from the fingerprint area SG_1 to the fingerprint area SG_n. That is, the fingerprint sensing control circuit 120 (chip) may obtain information about the selected fingerprint area SG_2 and the selected fingerprint area SG_3 (touch area 20).

[0104] exist Figure 6 In the embodiment illustrated in , the fingerprint sensing control circuit 120 (chip) includes a control circuit 121, a selection circuit 122, and a fingerprint reading circuit 123. The selection circuit 122 can obtain information about the touch area 20. Based on design requirements, in some embodiments, the processor 110 can provide information to the selection circuit 122. According to the touch information from the touch control circuit 130, the processor 110 can determine the selected fingerprint area. In some other embodiments, the touch control circuit 130 can provide information to the selection circuit 122. According to the information of the touch area 20, the selection circuit 122 can select a selected fingerprint area (e.g., fingerprint area SG_2 and fingerprint area SG_3) covering the touch area 20 from the fingerprint area SG_1 to the fingerprint area SG_n. The selection circuit 122 can provide information about the selected fingerprint area SG_2 and the selected fingerprint area SG_3 to the control circuit 121.

[0105] The control circuit 121 is coupled to the selection circuit 122 to receive information about the selected fingerprint area SG_2 and the selected fingerprint area SG_3. The control circuit 121 can provide a plurality of control signals (including the start pulse signal SP_1 to the start pulse signal SP_n) to the panel 150 for controlling the panel 150 to perform fingerprint sensing. Figure 6 In the embodiment described in , the start pulse signal and the selected fingerprint sensing area have a simple one-to-one mapping relationship. More specifically, when the fingerprint area SG_1 is selected for scanning, the fingerprint sensing control circuit 120 applies a pulse to the start pulse signal SP_1. When the fingerprint area SG_2 is selected for scanning, the fingerprint sensing control circuit 120 applies a pulse to the start pulse signal SP_2. When the fingerprint area SG_3 is selected for scanning, the fingerprint sensing control circuit 120 applies a pulse to the start pulse signal SP_3. When the fingerprint area SG_4 is selected for scanning, the fingerprint sensing control circuit 120 applies a pulse to the start pulse signal SP_4. When the fingerprint area SG_n is selected for scanning, the fingerprint sensing control circuit 120 applies a pulse to the start pulse signal SP_n. Therefore, the number of the start pulse signal SP_1 to the start pulse signal SP_n is equal to the number of the fingerprint area SG_1 to the fingerprint area SG_n. Based on the information about the selected fingerprint area SG_2 and the selected fingerprint area SG_3 (determined based on the touch area 20), the control circuit 121 applies pulses to the start pulse signal SP_2 and the start pulse signal SP_3 of the target shift register group SR_2 and the target shift register group SR_3 and does not apply pulses to the start pulse signal SP_1 and the start pulse signal SP_4 to the start pulse signal SP_n of other shift register groups SR_1 and shift register groups SR_4 to shift register groups SR_n.

[0106] In the row direction of the display panel 150, the fingerprint sensing blocks (eg, Figure 6 The fingerprint sensing blocks Z1, Z2, Z3 and Z4 described in the figure are divided into a plurality of sensing groups, for example, Figure 61 and 2. Each of the sensing groups includes one or more sensing lines. A multiplexer circuit 151 is coupled to the sensing groups of the panel 150. The fingerprint reading circuit 123 is coupled to the multiplexer circuit 151. Based on design requirements, the multiplexer circuit 151 can be disposed on the panel 150 or within the fingerprint sensing control circuit 120. The control circuit 121 can control the multiplexer circuit 151 to connect multiple signal paths from the target sensing group SN_1 and the target sensing group SN_2 to the fingerprint reading circuit 123 and disconnect multiple signal paths from the sensing groups other than the target sensing group SN_1 and the target sensing group SN_2 among the sensing groups to the fingerprint reading circuit 123.

[0107] Generally speaking, the larger the panel 150 is, the higher the total number n of the fingerprint area SG_1 to the fingerprint area SG_n is. The higher the total number n of the fingerprint area SG_1 to the fingerprint area SG_n is, the higher the number of wires and conductors used to transmit the start pulse signal SP_1 and the start pulse signal SP_4 to the start pulse signal SP_n is. The wires and conductors occupy the border area of ​​the panel 150.

[0108] Fig. 7A This is a description of an embodiment of the present invention Figure 1 Schematic circuit block diagram of the fingerprint sensing control circuit 120 depicted in FIG. Fig. 7A The panel 150, the multiplexer circuit 151, the plurality of gate lines including the gate lines FPR_GL1 to the gate lines FPR_GL2, the fingerprint regions SG_1 to the fingerprint regions SG_n, the sensing groups including the sensing groups SN_1 to the sensing groups SN_2, the shift register groups SR_1 to the shift register groups SR_n, and the fingerprint sensing blocks including the fingerprint sensing blocks Z1 to the fingerprint sensing blocks Z4 described in the foregoing can refer to the Figure 6 The relevant descriptions are inferred from those described in , and therefore will not be repeated.

[0109] exist Fig. 7A In the example illustrated in FIG. 1 , the fingerprint sensing control circuit 120 (chip) includes a control circuit 124 , a selection circuit 122 , and a fingerprint reading circuit 123 . Fig. 7A The control circuit 124, the selection circuit 122 and the fingerprint reading circuit 123 described in Figure 6 The descriptions related to the control circuit 121, the selection circuit 122, and the fingerprint reading circuit 123 described in the foregoing description can be inferred, and therefore the description will not be repeated.

[0110] exist Fig. 7AIn the example illustrated in FIG. 1 , the control circuit 124 is coupled to the selection circuit 122 to receive information about the selected fingerprint region SG_2 and the selected fingerprint region SG_3. The control circuit 124 may provide a plurality of control signals (including the start pulse signal S_1 to the start pulse signal S_m) to the panel 150 for controlling the panel 150 to perform fingerprint sensing. The start pulse signal S_1 to the start pulse signal S_m are used to control a plurality of gate lines (e.g., Fig. 7A The gate lines FPR_GL1 and FPR_GL2 described in FIG. 1 ). The start pulse signals S_1 to S_m may collectively indicate the selected fingerprint region (eg, the fingerprint region SG_2 and the fingerprint region SG_3). Compared to Figure 6 The selection for each of the fingerprint regions SG_1 to SG_n depends on a corresponding one of the start pulse signals S_1 to S_n, Fig. 7A The selection for each of the fingerprint regions SG_1 to SG_n may depend on more than one (eg, all) of the start pulse signals S_1 to S_m.

[0111] For example, the start pulse signals S_1 to S_m are provided to the GOA circuit (eg, Figure 2 The decoder 152 of the GOA circuit GOA2 is provided. The decoder 152 is disposed on the panel 150. The decoder 152 obtains information about the selected fingerprint area SG_2 and the selected fingerprint area SG_3 according to multiple logic values ​​of the start pulse signal S_1 to the start pulse signal S_m. That is, the decoder 152 can generate the start pulse signal SP_1 to the start pulse signal SP_n according to the start pulse signal S_1 to the start pulse signal S_m and provide the start pulse signal SP_1 to the start pulse signal SP_n to the shift register group SR_1 to the shift register group SR_n of the GOA circuit GOA2 respectively. The GOA circuit GOA2 includes the shift register group SR_1 to the shift register group SR_n, each of which can be coupled to a corresponding one of the fingerprint area SG_1 to the fingerprint area SG_n and operate according to more than one (for example, all) of the start pulse signal S_1 to the start pulse signal S_m. That is, after receiving the signal, the panel 150 can decode the signal to know which area should be operated. Fig. 7A The start pulse signal SP_1 to the start pulse signal SP_n described in the Figure 6The description of the start pulse signal SP_1 to the start pulse signal SP_n described in the above description is inferred, and therefore will not be repeated. The shift register group SR_1 to the shift register group SR_n of the GOA circuit GOA2 are configured to generate a plurality of scan signals. The scan signals are respectively used to control a plurality of gate lines (e.g., Fig. 7A The gate line FPR_GL1 and the gate line FPR_GL2 described in FIG.

[0112] exist Fig. 7A In the embodiment described in , the number n of fingerprint regions SG_1 to fingerprint regions SG_n is greater than the number m of start pulse signals S_1 to start pulse signals S_m. By reducing the number of start pulse signals between the fingerprint sensing control circuit 120 (chip) and the panel 150, the number of wires and conductors used to transmit the start pulse signals can be effectively reduced. The reduced wires and conductors can help reduce the border area of ​​the panel 150.

[0113] Figure 7B This is a diagram illustrating another embodiment of the present invention. Figure 1 Schematic circuit block diagram of the fingerprint sensing control circuit 120 depicted in FIG. Figure 7B The panel 150, the multiplexer circuit 151, the sensing groups SN_1 to SN_2, and the fingerprint sensing blocks Z1 to Z4 described in Figure 6 The shift register group SR1_1, the shift register group SR1_2, the shift register group SR1_3, the shift register group SR1_4, ... the shift register group SR1_n can refer to Fig. 7A , and Figure 7B The shift register group SR2_1, shift register group SR2_2, shift register group SR2_3, shift register group SR2_4, ... shift register group SR2_n described in Fig. 7A It can be inferred from the shift register group SR_1 to the shift register group SR_n described in the specification.

[0114] exist Figure 7B In the example illustrated in FIG. 1 , the fingerprint sensing control circuit 120 (chip) includes a control circuit 124 , a selection circuit 122 , and a fingerprint reading circuit 123 . Figure 7B The control circuit 124, the selection circuit 122 and the fingerprint reading circuit 123 described in Fig. 7A The descriptions related to the control circuit 121, the selection circuit 122, and the fingerprint reading circuit 123 described in the foregoing description can be inferred, and therefore the description will not be repeated.

[0115] exist Figure 7B In the example illustrated in FIG. 1 , the control circuit 124 is coupled to the selection circuit 122 to receive information about the selected fingerprint region SG_2 and the selected fingerprint region SG_3. The control circuit 124 may provide a plurality of control signals (including the start pulse signal S1_1 to the start pulse signal S1_m) to the panel 150 for controlling the panel 150 to perform fingerprint sensing. The start pulse signal S1_1 to the start pulse signal S1_m are used to control a plurality of gate lines (e.g., Figure 7B ). The start pulse signals S1_1 to S1_m may collectively indicate a selected fingerprint region (eg, fingerprint region SG_2 and fingerprint region SG_3). Figure 7B The start pulse signal S1_1 to the start pulse signal S1_m described in Fig. 7A It can be inferred from the description related to the start pulse signal S_1 to the start pulse signal S_m described in the text.

[0116] For example, the start pulse signals S1_1 to S1_m are provided to the decoder 152a of the GOA circuit GOA2 on the panel 150. The decoder 152a is disposed on the panel 150. The decoder 152a obtains information about the selected fingerprint area SG_2 and the selected fingerprint area SG_3 according to a plurality of logic values ​​of the start pulse signals S1_1 to S1_m. That is, the decoder 152a can generate the start pulse signal SP1_1, the start pulse signal SP1_2, the start pulse signal SP1_3, the start pulse signal SP1_4, ... the start pulse signal SP1_n according to the start pulse signals S1_1 to S1_m and provide the start pulse signal SP1_1, the start pulse signal SP1_2, the start pulse signal SP1_3, the start pulse signal SP1_4, ... the start pulse signal SP1_n to the shift register group SR1_1 to the shift register group SR1_n of the GOA circuit GOA2. Figure 7B The decoder 152a described in Fig. 7A The decoder 152 described in the above description can be used to infer. Figure 7B The start pulse signals SP1_1 to SP1_n described in the specification can refer to Figure 6 The description of the start pulse signal SP_1 to the start pulse signal SP_n described in the above description is inferred, and therefore will not be repeated. The shift register group SR1_1 to the shift register group SR1_n of the GOA circuit GOA2 are configured to generate a plurality of scan signals. The scan signals are respectively used to control a plurality of gate lines (e.g., Figure 7BA reset wire for transmitting the scan signal FPR_GL1_RESET and the scan signal FPR_GL2_RESET as described in the specification).

[0117] exist Figure 7B In the example illustrated in FIG. 1 , the control circuit 124 may provide a plurality of control signals (including the start pulse signal S2_1 to the start pulse signal S2_m) to the panel 150 for controlling the panel 150 to perform fingerprint sensing. The start pulse signal S2_1 to the start pulse signal S2_m are used to control a plurality of gate lines (e.g., Figure 7B The start pulse signals S2_1 to S2_m may collectively indicate a selected fingerprint region (eg, fingerprint region SG_2 and fingerprint region SG_3). Figure 7B The start pulse signal S2_1 to the start pulse signal S2_m described in the Fig. 7A It can be inferred from the description related to the start pulse signal S_1 to the start pulse signal S_m described in the text.

[0118] For example, the start pulse signals S2_1 to S2_m are provided to the decoder 152b of the GOA circuit GOA2 on the panel 150. The decoder 152b is disposed on the panel 150. The decoder 152b obtains information about the selected fingerprint area SG_2 and the selected fingerprint area SG_3 according to a plurality of logic values ​​of the start pulse signals S2_1 to S2_m. That is, the decoder 152b can generate the start pulse signal SP2_1, the start pulse signal SP2_2, the start pulse signal SP2_3, the start pulse signal SP2_4, ... the start pulse signal SP2_n according to the start pulse signal S2_1 to S2_m and provide the start pulse signal SP2_1, the start pulse signal SP2_2, the start pulse signal SP2_3, the start pulse signal SP2_4, ... the start pulse signal SP2_n to the shift register group SR2_1 to the shift register group SR2_n of the GOA circuit GOA2. Figure 7B The decoder 152b described in Fig. 7A The decoder 152 described in the above description can be used to infer. Figure 7B The start pulse signals SP2_1 to SP2_n described in the specification can refer to Figure 6The description of the start pulse signal SP_1 to the start pulse signal SP_n described in the above description is inferred, and therefore will not be repeated. The shift register group SR2_1 to the shift register group SR2_n of the GOA circuit GOA2 are configured to generate a plurality of scan signals. The scan signals are respectively used to control a plurality of gate lines (e.g., Figure 7B Selection wires for transmitting scan signal FPR_GL1_SEL / WRITE and scan signal FPR_GL2_SEL / WRITE as described in the specification).

[0119] It should be noted that although Figure 7B Two decoders are described in the figure, but in different embodiments, one decoder can be used to provide the start pulse signal SP_1 to the start pulse signal SP_n to the shift register group SR_1 to the shift register group SR_n, respectively, and provide the start pulse signal SP2_1, the start pulse signal SP2_2, the start pulse signal SP2_3, the start pulse signal SP2_4, ... the start pulse signal SP2_n to the shift register group SR2_1 to the shift register group SR2_n.

[0120] Figure 8 is a flow chart illustrating an operating method according to an embodiment of the present invention. Figure 1 , Fig. 7A as well as Figure 8 In step S410, a plurality of fingerprint sensing pixels of the panel 150 are divided into a first number n of fingerprint regions SG_1 to SG_n along a column direction of the panel 150. Each of the fingerprint regions SG_1 to SG_n is coupled to a corresponding one or more gate lines (e.g., Fig. 7A In step S410, the gate lines are arranged along the row direction of the panel 150 for the fingerprint sensing pixels of the panel 150. In step S410, the decoder 152 is disposed on the panel 150, wherein the decoder can obtain information about the selected fingerprint area according to a plurality of logic values ​​of the second number m of the start pulse signals S_1 to the start pulse signals S_m. Fig. 7A In the embodiment illustrated in , the selected fingerprint region may include fingerprint region SG_2 and fingerprint region SG_3.

[0121] In step S420, the chip (fingerprint sensing control circuit 120) controls the panel 150 to perform fingerprint sensing so as to obtain information about one (or more) selected fingerprint regions (e.g., fingerprint region SG_2 and fingerprint region SG_3) among the first number n fingerprint regions SG_1 to fingerprint regions SG_n of the panel 150. In step S420, the chip (fingerprint sensing control circuit 120) may further provide a plurality of control signals to the panel 150 for controlling the panel 150 to perform fingerprint sensing. The control signal includes a second number m of start pulse signals S_1 to start pulse signals S_m, and the start pulse signals S_1 to start pulse signals S_m collectively indicate the selected fingerprint region SG_2 and the selected fingerprint region SG_3. The first number n is greater than the second number m. The start pulse signals S_1 to start pulse signals S_m may be provided to a decoder 152 disposed on the panel 150 so that the decoder 152 obtains information about the selected fingerprint region SG_2 and the selected fingerprint region SG_3 according to the logic values ​​of the start pulse signals S_1 to start pulse signals S_m.

[0122] Fig. 9 is a flow chart illustrating an operating method according to another embodiment of the present invention. Figure 8 The step S420 described in Fig. 9 Related descriptions to speculate. Figure 1 , Fig. 7A as well as Fig. 9 In step S510, the selection circuit 122 may obtain information about the selected fingerprint region of the panel 150. Fig. 7A In the embodiment illustrated in , the selected fingerprint area may include the fingerprint area SG_2 and the fingerprint area SG_3 covering the touch area 20. That is, the fingerprint sensing control circuit 122 may select the corresponding fingerprint area (e.g., the fingerprint area SG_2 and the fingerprint area SG_3) from the fingerprint area SG_1 to the fingerprint area SG_n according to the touch area 20, and then provide information about the selected fingerprint area SG_2 and the selected fingerprint area SG_3 to the control circuit 124.

[0123] In step S520, the control circuit 124 may provide a control signal to the panel 150 for controlling the panel 150 to perform fingerprint sensing. The control signal includes a plurality of start pulse signals S_1 to start pulse signals S_m. That is, the control circuit 124 may generate corresponding start pulse signals S_1 to start pulse signals S_m according to information about the selected fingerprint region SG_2 and the selected fingerprint region SG_3. Each of the start pulse signals S_1 to start pulse signals S_m has a corresponding logic state, and a set of logic states of the start pulse signals S_1 to start pulse signals S_m has a first mapping relationship with the selected fingerprint region (e.g., fingerprint region SG_2 and fingerprint region SG_3). For example (but not limited to), the corresponding logic state of each of the start pulse signals S_1 to start pulse signals S_m may have a plurality of logic values. The selected fingerprint region is indicated according to a mathematical formula of the logic values ​​of the logic states of the start pulse signals S_1 to start pulse signals S_m.

[0124] The logic value and the mathematical formula may be determined based on the design requirements. For example, in some embodiments, the logic value includes 0 and 1, and the mathematical formula is NF is the index number of the selected fingerprint area (that is, when the fingerprint area SG_i is selected, NF=i), S_(i+1) also represents the logical value of the (i+1)th start pulse signal S_(i+1), i is 0 to N 2 -1 integer, and N 2 is the second number m. In this embodiment, NF is presented as a power of 2. In other embodiments, NF may be presented as a power of any other number, or NF may have any functional relationship (or mapping relationship) with the logic value of the above plurality of pulse signals. As long as the total number of pulse signals (and related signal lines) provided by the IC to the panel can be reduced, it can be used according to design or application requirements.

[0125] For example, assume that the first number n is 30 and the second number m is 5. A first mapping relationship exists between the logic state set of the start pulse signal S_1 to the start pulse signal S_5 and the selected fingerprint region (represented by the index number NF) among the fingerprint region SG_1 to the fingerprint region SG_30, and the first mapping relationship may be based on the formula The mapping relationship is defined by the following Table 1. When the logic state set of the start pulse signal S_1 to the start pulse signal S_5 is "00000", each of the start pulse signal S_1 to the start pulse signal S_5 is 0, and therefore NF=0, so this means that there is no fingerprint area that needs to be scanned. When the logic state set of the start pulse signal S_1 to the start pulse signal S_5 is "00001", the start pulse signal S_1 to the start pulse signal S_5 are 1, 0, 0, 0 and 0 respectively, and therefore NF=1, so this means that the first fingerprint area SG_1 needs to be scanned. Other logic state sets of the start pulse signal S_1 to the start pulse signal S_5 may be similar to the selected fingerprint area and are omitted here for brevity.

[0126] The mapping relationship between the input and output of the decoder 152 may be a mapping relationship defined by the following Table 2. When the logic state set of the start pulse signal S_1 to the start pulse signal S_5 (the input of the decoder 152) is "00000", the start pulse signal SP_1 to the start pulse signal SP_30 (the output of the decoder 152) are all 0. When the logic state set of the start pulse signal S_1 to the start pulse signal S_5 is "00001", the start pulse signal SP_1 is 1, and the rest of the start pulse signal SP_1 to the start pulse signal SP_n are 0. Other logic state sets of the start pulse signal S_1 to the start pulse signal S_5 and the start pulse signal SP_1 to the start pulse signal SP_30 may be similar and are omitted here for the sake of brevity.

[0127] More specifically, when the logic state set of the start pulse signal SP_1 to the start pulse signal SP_n is "100...0", the first fingerprint area SG_1 needs to be scanned. When the logic state set of the start pulse signal SP_1 to the start pulse signal SP_n is "010...0", the second fingerprint area SG_2 needs to be scanned. Other logic state sets of the start pulse signal SP_1 to the start pulse signal SP_n may be similar to the selected fingerprint area and are omitted here for brevity.

[0128] Therefore, only five wires are disposed between the fingerprint sensing control circuit 120 and the panel 150, and thus, the start pulse signals SP_1 to SP_5 can be transmitted to the panel 150. Figure 6 In the example described in FIG. 1 , thirty wires must be placed between the fingerprint sensing control circuit 120 and the panel 150 for transmitting the start pulse signal SP_1 to the start pulse signal SP_30. Therefore, since the total number of wires coupled between the fingerprint sensing control circuit 120 and the panel 150 is reduced from 30 to 5, Fig. 7A The frame area of ​​the panel 150 described in the figure can be reduced.

[0129] Table 1: Mapping relationship between the start pulse signal S_1 to the start pulse signal S_5 and the selected fingerprint area (from SG_1 to SG_30)

[0130]

[0131]

[0132] Table 2: Mapping relationship between start pulse signal S_1 to start pulse signal S_5 and start pulse signal SP_1 to start pulse signal SP_30

[0133]

[0134]

[0135] refer to Figure 1 , Fig. 7A as well as Fig. 9 , the start pulse signals S_1 to S_m are used to provide to the decoder 152 disposed on the panel 150. In step S530, the decoder 152 may obtain information about the selected fingerprint region (e.g., fingerprint region SG_2 and fingerprint region SG_3) according to the logic values ​​of the start pulse signals S_1 to S_m. Therefore, the start pulse signals S_1 to S_m may collectively indicate the selected fingerprint region SG_2 and the selected fingerprint region SG_3. For example, using Table 1 as an example to illustrate, when the start pulse signals S_1 to S_5 are "00010", the fingerprint region SG_2 is the selected fingerprint region, and therefore, the decoder 152 applies a pulse to the start pulse signal SP_2 and does not apply a pulse to the other start pulse signals SP_1 and the start pulse signals SP_3 to SP_30. When the start pulse signal S_1 to the start pulse signal S_5 are "00011", the fingerprint area SG_3 is the selected fingerprint area, and therefore, the decoder 152 applies a pulse to the start pulse signal SP_3 and does not apply a pulse to the other start pulse signals SP_1, SP_2, and SP_4 to SP_30.

[0136] Fig.10 This is a description of an embodiment of the present invention Fig. 7A A schematic circuit block diagram of the control circuit 124 is depicted in FIG. Fig.10In the embodiment illustrated in , the control circuit 124 includes a start pulse generating circuit 610 (e.g., an encoder, an encoding circuit, or any other conversion circuit that can be used to implement the functions described). The start pulse generating circuit 610 can convert the selected area information D_SELCT in digital form into the start pulse signals S_1 to S_m. The start pulse generating circuit 610 can provide the start pulse signals S_1 to S_m to the decoder 152 of the panel 150 according to the information about the selected fingerprint area (e.g., fingerprint area SG_2 and fingerprint area SG_3). The implementation details of the start pulse generating circuit 610 (start pulse generating circuit) are not limited in the present embodiment. For example, in some embodiments, the start pulse generating circuit 610 may include a binary start pulse generating circuit.

[0137] The fingerprint sensing control circuit 122 may select a corresponding fingerprint region (e.g., fingerprint region SG_2 and fingerprint region SG_3) from the fingerprint region SG_1 to the fingerprint region SG_n according to the touch area 20, and then provide information about the selected fingerprint region SG_2 and the selected fingerprint region SG_3 to the start pulse generating circuit 610 (start pulse generating circuit). The start pulse generating circuit 610 may generate corresponding start pulse signals S_1 to start pulse signals S_m according to the information about the selected fingerprint region SG_2 and the selected fingerprint region SG_3. For example, the start pulse generating circuit 610 (start pulse generating circuit) may encode or convert the index number of the selected fingerprint region into a logic value of the start pulse signal S_1 to the start pulse signal S_m. The logic state set of the start pulse signal S_1 to the start pulse signal S_m has a first mapping relationship with the selected fingerprint region from the fingerprint region SG_1 to the fingerprint region SG_n. Based on the design requirements, the first mapping relationship may be a mapping relationship defined by Table 1 or other mapping relationships.

[0138] It should be noted that Fig.10 The control circuit 124 described in FIG. 1 is an example of various implementations. Fig. 7A The specific implementation of the control circuit 124 described in the embodiment may be determined based on design requirements. In some other embodiments, the control circuit 124 may provide different numbers of start pulse signals according to different settings (operation modes). For example, when the fingerprint sensing control circuit 120 is applied to a panel 150 (i.e., Fig. 7A When the panel 150 described in FIG. 1 is used, the control circuit 124 may operate in the first operation mode to provide m start pulse signals S_1 to start pulse signals S_m to the Fig. 7A When the fingerprint sensing control circuit 120 is applied to a panel without a decoder 152 (ie, Figure 6When the panel 150 described in FIG. 1 is used, the control circuit 124 may operate in the second operation mode to provide n start pulse signals SP_1 to start pulse signals SP_n to the Figure 6 Shift register group SR_1 to shift register group SR_n of panel 150 illustrated in FIG.

[0139] Fig.11 This is a diagram illustrating another embodiment of the present invention. Fig. 7A A schematic circuit block diagram of the control circuit 124 is depicted in FIG. Fig.11 In the embodiment described in , the control circuit 124 includes a first start pulse generating circuit 710 , a second start pulse generating circuit 720 and a switch circuit 730 . Fig.11 The first start pulse generating circuit 710 described in Fig.10 1 and 12 , and thus will not be described repeatedly. In some embodiments, the first start pulse generating circuit 710 may include a binary start pulse generating circuit. The first start pulse generating circuit 710 may generate corresponding start pulse signals S_1 to S_m according to information about the selected fingerprint region, and the information is provided to the switch circuit 730 by the selection circuit 122. The start pulse signals S_1 to S_m are used to provide to the decoder 152 disposed on the panel 150 so that the decoder 152 obtains information about the selected fingerprint region according to the logic values ​​of the start pulse signals S_1 to S_m.

[0140] According to the information about the selected fingerprint area provided by the selection circuit 122, the second start pulse generation circuit 720 may provide a third number of start pulse signals, wherein the third number is not equal to the second number m. For example, the first second start pulse generation circuit 720 may provide n start pulse signals SP_1 to start pulse signals SP_n to the switch circuit 730 (i.e., the third number is equal to the first number n). The implementation details of the second start pulse generation circuit 720 are not limited in this embodiment. For example, in some embodiments, the second start pulse generation circuit 720 may include a thermometer code start pulse generation circuit or a one-hot code pulse generation circuit.

[0141] The switch circuit 730 is coupled to the first start pulse generating circuit 710 and the second start pulse generating circuit 720. Depending on the type of the panel (e.g., whether the panel has a decoder), the switch circuit 730 may select the start pulse signal S_1 to the start pulse signal S_m of the first start pulse generating circuit 710 or the start pulse signal SP_1 to the start pulse signal SP_n of the second start pulse generating circuit 720 as a control signal and output the control signal to the panel 150. There is a first mapping relationship between the logic state set of the start pulse signal S_1 to the start pulse signal S_m and the selected fingerprint area, and there is a second mapping relationship between the logic state set of the start pulse signal SP_1 to the start pulse signal SP_n and the selected fingerprint area. The first mapping relationship is different from the second mapping relationship.

[0142] Fig.12 This is a description of an embodiment of the present invention Fig. 7A A schematic circuit block diagram of the decoder 152 is depicted in FIG. Fig.12 In the embodiment illustrated in , the decoder 152 includes a decoder unit DU_1, a decoder unit DU_2, ..., a decoder unit DU_n-1, and a decoder unit DU_n. Each of the decoder units DU_1 to DU_n corresponds to one of the fingerprint areas SG_1 to the fingerprint areas SG_n. All start pulse signals S_1 to the start pulse signals S_m are provided to each of the decoder units DU_1 to the decoder units DU_n. The input terminal of each of the decoder units DU_1 to the decoder units DU_n can be coupled to the control circuit 124 to receive all start pulse signals S_1 to the start pulse signals S_m. Each of the decoder units DU_1 to the decoder units DU_n can be configured to decode the start pulse signals S_1 to the start pulse signals S_m to obtain a corresponding one of the start pulse signals SP_1 to the start pulse signals SP_n. The output terminals of the decoder units DU_1 to the decoder units DU_n are coupled to the shift register groups SR_1 to the shift register groups SR_n to provide the start pulse signals SP_1 to the start pulse signals SP_n. For example, decoder unit DU_1 can provide the start pulse signal SP_1 to the shift register group SR_1, decoder unit DU_2 can provide the start pulse signal SP_2 to the shift register group SR_2, decoder unit DU_n-1 can provide the start pulse signal SP_n-1 to the shift register group SR_n-1, and decoder unit DU_n can provide the start pulse signal SP_n to the shift register group SR_n.

[0143] Decoder unit DU_1 to decoder unit DU_n may have the same circuit structure. Input terminals of decoder unit DU_1 to decoder unit DU_n may have different coupling relationships with start pulse signal S_1 to start pulse signal S_m. Each of decoder unit DU_1 to decoder unit DU_n is configured to decode start pulse signal S_1 to start pulse signal S_m into a corresponding one of start pulse signal SP_1 to start pulse signal SP_n. Each of start pulse signal SP_1 to start pulse signal SP_n may correspond to one of fingerprint area SG_1 to fingerprint area SG_n. Each of start pulse signal SP_1 to start pulse signal SP_n is provided to a corresponding one of shift register group SR_1 to shift register group SR_n. Each of start pulse signal SP_1 to start pulse signal SP_n is used by one of shift register group SR_1 to shift register group SR_n (GOA circuit) to generate multiple scan signals (for example, Figure 7B The scan signal FPR_GL1_SEL / WRITE and / or the scan signal FPR_GL2_SEL / WRITE described in the embodiment of the present invention are used to control the gate lines (eg, Fig. 7A The gate line FPR_GL1 to the gate line FPR_GL2 described in FIG.

[0144] For example, Figures 13 to 26 The invention is described in detail according to different embodiments of the present invention. Fig.12 Schematic circuit block diagram of decoder unit DU_1 to decoder unit DU_n depicted in FIG. Figures 13 to 26 In the exemplary embodiment illustrated in , it is assumed that the first number n is 31, and it is assumed that the second number m is 5. That is, the decoder 152 includes a decoder unit DU_1, a decoder unit DU_2, ..., and a decoder unit DU_31. The control circuit 124 may provide a start pulse signal S_1 to a start pulse signal S_5 to the decoder unit DU_1 to the decoder unit DU_31. The output terminals of the decoder unit DU_1 to the decoder unit DU_31 may be coupled to the shift register group to provide the start pulse signal SP_1 to the start pulse signal SP_31. For example, the decoder unit DU_1 may provide the start pulse signal SP_1, the decoder unit DU_2 may provide the start pulse signal SP_2, the decoder unit DU_3 may provide the start pulse signal SP_3, and the decoder unit DU_31 may provide the start pulse signal SP_31.

[0145] exist Fig.13In the exemplary embodiment described in , each of the decoder units DU_1 to DU_31 includes a plurality of input terminals, an output terminal, and a plurality of first logic units. Here, the decoder unit DU_1 will be used as an example. Fig.13 The other decoder units DU_2 to DU_31 described in Fig.13 The decoder unit DU_1 can be inferred from the description related to the decoder unit DU_1 described in the text, and therefore the description will not be repeated. The decoder unit DU_1 includes a plurality of input terminals, which are respectively configured to be coupled to the start pulse signal S_1 to the start pulse signal S_5. This means that these input terminals can respectively receive the start pulse signal S_1 to the start pulse signal S_5 (or the inverted signals of the start pulse signal S_1 to the start pulse signal S_5). The decoder unit DU_1 includes an output terminal configured to provide a corresponding one of the start pulse signals SP_1 to the start pulse signal SP_31 (i.e., the start pulse signal SP_1). The decoder unit DU_1 includes a plurality of first logic units, such as Fig.13 The total number of the first logic units may be the same as the total number of the start pulse signals S_1 to S_5.

[0146] Each of the first logic units comprises an input terminal coupled to an input terminal of the decoder unit DU_1. Fig.13 In the exemplary embodiment illustrated in , the first logic units are cascade-connected, and a specific one of the first logic units has an output terminal coupled to an output terminal of the decoder unit DU_1. For example, each of the PMOS transistors includes a gate terminal coupled to an input terminal of the decoder unit DU_1. The PMOS transistors in the decoder unit DU_1 are cascade-connected, and a specific one of the PMOS transistors (i.e., the rightmost one) has an output terminal coupled to the output terminal of the decoder unit DU_1.

[0147] exist Fig.13 In the exemplary embodiment described in , the decoder unit DU_1 further comprises a plurality of second logic units, such as Fig.13The n-channel metal oxide semiconductor (NMOS) transistor described in the second logic unit. Each of the second logic units includes an input terminal (e.g., a gate terminal) coupled to a corresponding one of the start pulse signals S_1 to the start pulse signal S_5 (or an inverted signal of the start pulse signal S_1 to the start pulse signal S_5). The total number of second logic units can be the same as the total number of the start pulse signals S_1 to the start pulse signal S_5. All output terminals of the second logic units of the decoder unit DU_1 (e.g., all drain terminals of the NMOS transistors in the decoder unit DU_1) are coupled together to the output terminal of the decoder unit DU_1.

[0148] exist Fig.14 In the exemplary embodiment illustrated in , each of the decoder units DU_1 to DU_31 includes a plurality of input terminals, an output terminal, and a plurality of first logic units. Fig.14 The decoder units DU_1 to DU_31 described in the Fig.13 The description of the decoder units described in the previous section can be inferred, and therefore will not be repeated. Fig.14 In the exemplary embodiment illustrated in , the first logic unit may be an NMOS transistor in the decoder unit DU_1. Each of the first logic units includes an input terminal (e.g., a gate terminal) coupled to a corresponding one of the start pulse signal S_1 to the start pulse signal S_5. This means that each input terminal can receive one of the corresponding start pulse signal S_1 to the start pulse signal S_5 (or the inverted signals of the start pulse signal S_1 to the start pulse signal S_5). All output terminals of the first logic unit of the decoder unit DU_1 (e.g., all drain terminals of the NMOS transistors in the decoder unit DU_1) are coupled together to the output terminal of the decoder unit DU_1. In Fig.14 In the exemplary embodiment illustrated in , the decoder unit DU_1 further includes a PMOS transistor coupled to the NMOS transistor and the output terminal of the decoder unit DU_1.

[0149] exist Fig.15 In the exemplary embodiment illustrated in , each of the decoder units DU_1 to DU_31 includes a plurality of input terminals, an output terminal, and a plurality of first logic units. Fig.15 The decoder units DU_1 to DU_31 described in the Fig.13 The description of the decoder units described in the previous section can be inferred, and therefore will not be repeated. Fig.15In the exemplary embodiment described in, the first logic unit can be an NMOS transistor in the decoder unit DU_1. Each of the first logic units includes an input terminal (e.g., a gate terminal) coupled to a corresponding one of the start pulse signal S_1 to the start pulse signal S_5. This means that these input terminals can receive one of the corresponding start pulse signal S_1 to the start pulse signal S_5 (or the inverted signal of the start pulse signal S_1 to the start pulse signal S_5). The first logic units are cascade connected. For example, the NMOS transistors in the decoder unit DU_1 are cascade connected.

[0150] exist Fig.15 In the exemplary embodiment illustrated in , the decoder unit DU_1 further includes a PMOS transistor in the decoder unit DU_1. The PMOS transistor in the decoder unit DU_1 is coupled to an output terminal (eg, drain terminal) of a specific one of the NMOS transistors in the decoder unit DU_1. Fig.15 In the exemplary embodiment illustrated in , the decoder unit DU_1 further includes an inverter coupled between an output terminal of a specific one of the NMOS transistors (the first logic unit) and an output terminal of the decoder unit DU_1.

[0151] exist Fig.16 In the exemplary embodiment described in , each of the decoder units DU_1 to DU_31 includes a plurality of input terminals, an output terminal, a plurality of first logic units, and a plurality of second logic units. Fig.16 In the exemplary embodiment illustrated in , the first logic unit may be a PMOS transistor in each of the decoder units DU_1 to DU_31 , and the second logic unit may be an NMOS transistor in each of the decoder units DU_1 to DU_31 . Fig.16 The decoder units DU_1 to DU_31 described in the Fig.13 The descriptions related to those decoder units described in are inferred from the descriptions above and therefore will not be repeated.

[0152] exist Fig.16 In the exemplary embodiment described in , each of the decoder units DU_1 to DU_31 further includes a plurality of inverters. Here, the decoder unit DU_1 will be used as an example. Fig.16 The other decoder units DU_2 to DU_31 described in Fig.16The description of the decoder unit DU_1 described in the above description can be inferred, and therefore the description will not be repeated. Each of the inverters in the decoder unit DU_1 is coupled between one of the input terminals of the decoder unit DU_1 and an input terminal of one of the first logic units. It can be omitted according to design requirements. Fig.16 In the inverter described above, the input terminal of the inverter is floating.

[0153] exist Fig.17 In the exemplary embodiment described in , each of the decoder units DU_1 to DU_31 includes a plurality of input terminals, an output terminal, and a plurality of first logic units. Fig.17 In the exemplary embodiment illustrated in , the first logic unit may be an NMOS transistor in each of the decoder units DU_1 to DU_31, and each of the decoder units DU_1 to DU_31 may also include a PMOS transistor in each of the decoder units DU_1 to DU_31. Fig.17 The decoder units DU_1 to DU_31 described in the Fig.14 The descriptions related to those decoder units described in are inferred from the descriptions above and therefore will not be repeated.

[0154] exist Fig.17 In the exemplary embodiment described in , each of the decoder units DU_1 to DU_31 further includes a plurality of inverters. The inverters in each of the decoder units DU_1 to DU_31 can refer to Fig.16 The descriptions related to those inverters described in are inferred and therefore will not be repeated.

[0155] exist Fig.18 In the exemplary embodiment described in , each of the decoder units DU_1 to DU_31 includes a plurality of input terminals, an output terminal, and a plurality of first logic units. Fig.18 In the exemplary embodiment illustrated in , the first logic unit may be an NMOS transistor in each of the decoder units DU_1 to DU_31 , and each of the decoder units DU_1 to DU_31 may further include a PMOS transistor and an inverter coupled thereto. Fig.18 The decoder units DU_1 to DU_31 described in the Fig.15 The descriptions related to those decoder units described in are inferred from the descriptions above and therefore will not be repeated.

[0156] exist Fig.18In the exemplary embodiment described in , each of the decoder units DU_1 to DU_31 further includes a plurality of inverters. The inverters in each of the decoder units DU_1 to DU_31 can refer to Fig.16 The descriptions related to those inverters described in are inferred and therefore will not be repeated.

[0157] exist Fig.19 In the exemplary embodiment described in , each of the decoder units DU_1 to DU_31 includes a plurality of input terminals, an output terminal, and a plurality of first logic units. Fig.19 In the exemplary embodiment illustrated in , the first logic unit may be an NMOS transistor in each of the decoder units DU_1 to DU_31. Fig.19 The decoder units DU_1 to DU_31 described in the Fig.14 The description of the decoder units described in the previous section can be inferred, and therefore will not be repeated. Fig.19 In the exemplary embodiment described in Fig.14 The PMOS transistor in is replaced with a diode-connected NMOS transistor in each of the decoder units DU_1 to DU_31.

[0158] exist Fig. 20 In the exemplary embodiment described in , each of the decoder units DU_1 to DU_31 includes a plurality of input terminals, an output terminal, and a plurality of first logic units. Fig. 20 In the exemplary embodiment illustrated in , the first logic unit may be an NMOS transistor in each of the decoder units DU_1 to DU_31. Fig. 20 In the illustrated exemplary embodiment, the decoder unit DU_1 further includes an inverter coupled between an output terminal of a specific one of the NMOS transistors (first logic unit) and an output terminal of the decoder unit DU_1. Fig. 20 The decoder units DU_1 to DU_31 described in the Fig.15 The description of the decoder units described in the previous section can be inferred, and therefore will not be repeated. Fig. 20 In the exemplary embodiment described in Fig.15 The PMOS transistor in is replaced with a diode-connected NMOS transistor in each of the decoder units DU_1 to DU_31.

[0159] exist Fig.21In the exemplary embodiment described in , each of the decoder units DU_1 to DU_31 includes a plurality of input terminals, an output terminal, and a plurality of first logic units. Fig.21 In the exemplary embodiment illustrated in , the first logic unit may be an NMOS transistor in each of the decoder units DU_1 to DU_31. Fig.21 The decoder units DU_1 to DU_31 described in the Fig.17 The description of the decoder units described in the previous section can be inferred, and therefore will not be repeated. Fig.21 In the exemplary embodiment described in Fig.17 The PMOS transistor in is replaced with a diode-connected NMOS transistor in each of the decoder units DU_1 to DU_31.

[0160] exist Fig. 22 In the exemplary embodiment described in , each of the decoder units DU_1 to DU_31 includes a plurality of input terminals, an output terminal, and a plurality of first logic units. Fig. 22 In the exemplary embodiment illustrated in , the first logic unit may be an NMOS transistor in each of the decoder units DU_1 to DU_31. Fig. 22 In the illustrated exemplary embodiment, the decoder unit DU_1 further includes an inverter coupled between an output terminal of a specific one of the NMOS transistors (first logic unit) and an output terminal of the decoder unit DU_1. Fig. 22 The decoder units DU_1 to DU_31 described in the Fig.18 The description of the decoder units described in the previous section can be inferred, and therefore will not be repeated. Fig. 22 In the exemplary embodiment described in Fig.18 The PMOS transistor in is replaced with a diode-connected NMOS transistor in each of the decoder units DU_1 to DU_31.

[0161] exist Fig.23 In the exemplary embodiment described in , each of the decoder units DU_1 to DU_31 includes a plurality of input terminals, an output terminal, and a plurality of first logic units. Fig.23 In the exemplary embodiment illustrated in , the first logic unit may be an NMOS transistor in each of the decoder units DU_1 to DU_31. Fig.23 The decoder units DU_1 to DU_31 described in the Fig.14The description of the decoder units described in the previous section can be inferred, and therefore will not be repeated. Fig.23 In the exemplary embodiment described in Fig.14 The PMOS transistor in is replaced by a pull-up resistor in each of the decoder units DU_1 to DU_31.

[0162] exist Fig.24 In the exemplary embodiment described in , each of the decoder units DU_1 to DU_31 includes a plurality of input terminals, an output terminal, and a plurality of first logic units. Fig.24 In the exemplary embodiment illustrated in , the first logic unit may be an NMOS transistor in each of the decoder units DU_1 to DU_31. Fig.24 In the illustrated exemplary embodiment, the decoder unit DU_1 further includes an inverter coupled between an output terminal of a specific one of the NMOS transistors (first logic unit) and an output terminal of the decoder unit DU_1. Fig.24 The decoder units DU_1 to DU_31 described in the Fig.15 The description of the decoder units described in the previous section can be inferred, and therefore will not be repeated. Fig.24 In the exemplary embodiment described in Fig.15 The PMOS transistor in is replaced by a pull-up resistor in each of the decoder units DU_1 to DU_31.

[0163] exist Fig.25 In the exemplary embodiment described in , each of the decoder units DU_1 to DU_31 includes a plurality of input terminals, an output terminal, and a plurality of first logic units. Fig.25 In the exemplary embodiment illustrated in , the first logic unit may be an NMOS transistor in each of the decoder units DU_1 to DU_31. Fig.25 In the exemplary embodiment shown, each of the decoder units DU_1 to DU_31 further includes a plurality of inverters. Fig.25 The decoder units DU_1 to DU_31 described in the Fig.17 The description of the decoder units described in the previous section can be inferred, and therefore will not be repeated. Fig.25 In the exemplary embodiment described in Fig.17 The PMOS transistor in is replaced by a pull-up resistor in each of the decoder units DU_1 to DU_31.

[0164] exist Fig.26In the exemplary embodiment described in , each of the decoder units DU_1 to DU_31 includes a plurality of input terminals, an output terminal, and a plurality of first logic units. Fig.26 In the exemplary embodiment illustrated in , the first logic unit may be an NMOS transistor in each of the decoder units DU_1 to DU_31. Fig.26 In the exemplary embodiment shown, each of the decoder units DU_1 to DU_31 further includes a plurality of inverters. Fig.26 The decoder units DU_1 to DU_31 described in the Fig.18 The description of the decoder units described in the previous section can be inferred, and therefore will not be repeated. Fig.26 In the exemplary embodiment described in Fig.18 The PMOS transistor in is replaced by a pull-up resistor in each of the decoder units DU_1 to DU_31.

[0165] According to different design requirements, the blocks of the fingerprint sensing control circuit 120, the selection circuit 122, the fingerprint reading circuit 123 and / or the control circuit 124 can be implemented in the form of hardware, firmware, software (ie, program) or a combination of the above three forms.

[0166] In terms of hardware form, the blocks of the fingerprint sensing control circuit 120, the selection circuit 122, the fingerprint reading circuit 123, and / or the control circuit 124 may be implemented in logic circuits on an integrated circuit. The related functions of the fingerprint sensing control circuit 120, the selection circuit 122, the fingerprint reading circuit 123, and / or the control circuit 124 may be implemented in hardware form by utilizing a hardware description language (e.g., Verilog HDL or VHDL) or other suitable programming languages. For example, the related functions of the fingerprint sensing control circuit 120, the selection circuit 122, the fingerprint reading circuit 123, and / or the control circuit 124 may be implemented in various logic blocks, modules, and circuits in one or more controllers, microcontrollers, microprocessors, application-specific integrated circuits (ASICs), digital signal processors (DSPs), field programmable gate arrays (FPGAs), and / or other processing units.

[0167] In terms of software form and / or firmware form, the relevant functions of the fingerprint sensing control circuit 120, the selection circuit 122, the fingerprint reading circuit 123 and / or the control circuit 124 can be implemented in a logic circuit on an integrated circuit. For example, the fingerprint sensing control circuit 120, the selection circuit 122, the fingerprint reading circuit 123 and / or the control circuit 124 can be implemented by using a general programming language (e.g., C or C++) or other suitable programming languages. The programming code can be recorded / stored in a recording medium, and the aforementioned recording medium includes, for example, a read only memory (ROM), a storage device and / or a random access memory (RAM). The programming code can be accessed from the recording medium and executed by a computer, a central processing unit (CPU), a controller, a microcontroller or a microprocessor to complete the relevant functions. For the recording medium, a "non-transitory computer-readable medium" such as a tape, a disk, a card, a semiconductor memory or a programming logic circuit can be used. In addition, the program can be provided to the computer (or CPU) via any transmission medium (e.g., a communication network or radio waves). The communication network is, for example, the Internet, wired communication, wireless communication or other communication media.

[0168] In view of the foregoing, the fingerprint sensing control circuit (chip) provided by an embodiment of the present invention may output a start pulse signal to the panel. The start pulse signal relates to a selected fingerprint area among the fingerprint areas of the panel. The panel may generate a plurality of scan signals according to the start pulse signal, and the scan signals are provided to the selected fingerprint area. The number of start pulse signals is less than the number of fingerprint areas. The start pulse signal may be decoded to indicate the selected fingerprint area. The start pulse signal may be decoded to be provided to the shift register groups respectively. Therefore, the electronic device may realize minimizing the number of start pulse signals output by the fingerprint sensing control circuit (chip) to the panel.

[0169] Those skilled in the art will appreciate that various modifications and changes may be made to the structure of the disclosed embodiments without departing from the scope or spirit of the present disclosure. In view of the foregoing, it is intended that the present disclosure covers modifications and changes of the present disclosure within the scope of the appended claims and their equivalents.

Claims

1. A chip capable of controlling a panel to perform fingerprint sensing, It is characterized in that The panel includes a plurality of fingerprint sensing pixels and a plurality of gate lines, the plurality of gate lines are arranged along a row direction of the panel for controlling the fingerprint sensing pixels, the fingerprint sensing pixels are divided into a first number of fingerprint regions along a column direction of the panel, and each of the fingerprint regions is coupled to a corresponding one or more gate lines among the gate lines of the panel, and the chip includes: A selection circuit configured to obtain information about a selected fingerprint region among the first number of fingerprint regions of the panel; and a control circuit coupled to the selection circuit to receive the information about the selected fingerprint area, and configured to provide a plurality of control signals to the panel for controlling the panel to perform fingerprint sensing, wherein the control signals include a second number of start pulse signals collectively indicating the selected fingerprint area, wherein the first number is greater than the second number, the control circuit comprising: The first start pulse generating circuit is configured to provide the second number of start pulse signals according to the information about the selected fingerprint area.

2. The chip according to claim 1, It is characterized in that The start pulse signal is used to control the gate line of the panel.

3. The chip according to claim 2, It is characterized in that The start pulse signal is provided to an array gate circuit of the panel, and the array gate circuit is configured to generate a plurality of scan signals for respectively controlling the gate lines of the panel.

4. The chip according to claim 3, It is characterized in that The array-on-gate circuit includes a plurality of shift register groups, each of which is connected to a corresponding one of the fingerprint regions and operates according to all of the second number of start pulse signals.

5. The chip according to claim 3, It is characterized in that The scan signal is configured to control the corresponding fingerprint sensing pixel to perform a reset operation and / or a select / write operation.

6. The chip according to claim 1, It is characterized in that The selection circuit is configured to receive the information about the selected fingerprint area from a processor, and the processor is configured to determine the selected fingerprint area based on touch information.

7. The chip according to claim 6, It is characterized in that The processor is configured to receive the touch information from a touch control circuit configured to control touch sensing on the panel.

8. The chip according to claim 1, It is characterized in that The first start pulse generating circuit is a binary start pulse generating circuit.

9. The chip according to claim 1, It is characterized in that Each of the second number of start pulse signals has a corresponding logic state, the corresponding logic state has multiple logic values, and the control circuit further includes an encoding circuit configured to encode the index number of the selected fingerprint area into the logic value of the start pulse signal of the second number of start pulse signals.

10. The chip according to claim 1, It is characterized in that The control circuit is configured to provide different numbers of start pulse signals according to different settings.

11. The chip according to claim 10, It is characterized in that The control circuit further comprises: a second start pulse generating circuit configured to provide a third number of start pulse signals according to the information about the selected fingerprint area, wherein the third number is not equal to the second number; and A switch circuit is coupled to the first start pulse generating circuit and the second start pulse generating circuit and is configured to select the second number of start pulse signals or the third number of start pulse signals as the control signal.

12. The chip according to claim 11, It is characterized in that The second start pulse generating circuit is a thermometer code start pulse generating circuit or a one-hot code pulse generating circuit.

13. The chip according to claim 11, It is characterized in that The third number is equal to the first number.

14. The chip according to claim 11, It is characterized in that There is a first mapping relationship between the logic state set of the second number of start pulse signals and the selected fingerprint area, and there is a second mapping relationship between the logic state set of the third number of start pulse signals and the selected fingerprint area, wherein the first mapping relationship is different from the second mapping relationship.

15. The chip according to claim 1, It is characterized in that The second number of start pulse signals are used to provide to a decoder disposed on the panel so that the decoder obtains the information about the selected fingerprint area according to logic values ​​of the second number of start pulse signals.

16. The chip according to claim 15, It is characterized in that The second number of start pulse signals are used to be provided to the decoder to provide a fourth number of start pulses each for selecting a corresponding one of the first number of fingerprint regions, wherein the fourth number is equal to the first number.

17. The chip according to claim 15, It is characterized in that The decoder includes a plurality of decoder units each corresponding to one of the fingerprint regions.

18. The chip according to claim 17, It is characterized in that All of the second number of start pulse signals are provided to each of the decoder units.

19. The chip according to claim 1, It is characterized in that Each of the second number of start pulse signals has a corresponding logic state, and a first mapping relationship exists between the logic state sets of the second number of start pulse signals and the selected fingerprint region.

20. The chip according to claim 19, It is characterized in that The corresponding logic state of each of the second number of start pulse signals has a plurality of logic values, and the selected fingerprint region is indicated according to a mathematical formula of the logic values ​​of the logic states of the second number of start pulse signals.

21. The chip according to claim 20, It is characterized in that The plurality of logical values ​​include 0 and 1, and the mathematical formula is Where NF is the index number of the selected fingerprint area, S_(i+1) is the logic value of the (i+1)th start pulse signal S_(i+1), and i is 0 to N. 2 -1 integer, and N 2 is the second number.

22. The chip according to claim 1, It is characterized in that The fingerprint sensing pixel is an optical fingerprint sensing pixel capable of sensing light.

23. The chip according to claim 1, It is characterized in that The selection for each of the fingerprint regions depends on all of the second number of start pulse signals.

24. A method for operating a chip capable of controlling a panel to perform fingerprint sensing, It is characterized in that The panel includes a plurality of fingerprint sensing pixels and a plurality of gate lines, the plurality of gate lines are arranged along a row direction of the panel for controlling the fingerprint sensing pixels, the fingerprint sensing pixels are divided into a first number of fingerprint regions along a column direction of the panel, and each of the fingerprint regions is coupled to a corresponding one or more gate lines among the gate lines of the panel, and the operating method includes: obtaining, by a selection circuit, information about a selected fingerprint region among the first number of fingerprint regions of the panel; and A plurality of control signals are provided to the panel through a control circuit for controlling the panel to perform fingerprint sensing, wherein the control signals include a second number of start pulse signals collectively indicating the selected fingerprint area, the first number is greater than the second number, and the control circuit includes a first start pulse generating circuit configured to provide the second number of start pulse signals according to the information about the selected fingerprint area.

25. A chip capable of controlling a panel to perform fingerprint sensing, It is characterized in that The panel includes a plurality of fingerprint sensing pixels and a plurality of gate lines, the plurality of gate lines are arranged along a row direction of the panel for controlling the fingerprint sensing pixels, the fingerprint sensing pixels are divided into a first number of fingerprint regions along a column direction of the panel, and each of the fingerprint regions is coupled to a corresponding one or more gate lines among the gate lines of the panel, and the chip includes: A selection circuit configured to obtain information about a selected fingerprint region among the first number of fingerprint regions of the panel; and A control circuit is coupled to the selection circuit to receive the information about the selected fingerprint area, and is configured to provide a plurality of control signals to the panel for controlling the panel to perform fingerprint sensing, wherein the control signals include a plurality of start pulse signals, and the start pulse signals are used to be provided to a decoder disposed on the panel so that the decoder obtains the information about the selected fingerprint area according to logic values ​​of the start pulse signals.

26. The chip according to claim 25, It is characterized in that The decoder includes a plurality of decoder units each corresponding to one of the fingerprint regions.

27. The chip according to claim 26, It is characterized in that All of the start pulse signals are provided to each of the decoder units.

28. The chip according to claim 25, It is characterized in that The start pulse signal is used to control the gate line of the panel.

29. The chip according to claim 28, It is characterized in that The start pulse signal is provided to an array gate circuit of the panel, and the array gate circuit is configured to generate a plurality of scan signals for respectively controlling the gate lines of the panel.

30. The chip according to claim 29, It is characterized in that The array-on-gate circuit includes a plurality of shift register groups, each of which is connected to a corresponding one of the fingerprint regions and operates according to all of the start pulse signals.

31. The chip according to claim 29, It is characterized in that The scan signal is configured to control the corresponding fingerprint sensing pixel to perform a reset operation and / or a select / write operation.

32. The chip according to claim 25, It is characterized in that The selection circuit is configured to receive the information about the selected fingerprint area from a processor, and the processor is configured to determine the selected fingerprint area based on touch information.

33. The chip according to claim 32, It is characterized in that The processor is configured to receive the touch information from a touch control circuit configured to control touch sensing on the panel.

34. The chip according to claim 25, It is characterized in that The control circuit comprises: The first start pulse generating circuit is configured to provide the start pulse signal according to the information about the selected fingerprint area.

35. The chip according to claim 34, It is characterized in that The first start pulse generating circuit is a binary start pulse generating circuit.

36. The chip according to claim 34, It is characterized in that Each of the start pulse signals has a corresponding logic state having a plurality of logic values, and the control circuit further comprises an encoding circuit configured to encode the index number of the selected fingerprint region into the logic value of the start pulse signal.

37. The chip according to claim 34, It is characterized in that The control circuit is configured to provide different numbers of start pulse signals according to different settings.

38. The chip according to claim 37, It is characterized in that The control circuit further comprises: a second start pulse generating circuit configured to provide a third number of start pulse signals according to the information about the selected fingerprint region, wherein a total number of the start pulse signals generated by the second start pulse generating circuit is equal to a second number, and the third number is not equal to the second number; and A switch circuit is coupled to the first start pulse generating circuit and the second start pulse generating circuit and is configured to select the second number of start pulse signals or the third number of start pulse signals as the control signal.

39. The chip according to claim 38, It is characterized in that The second start pulse generating circuit is a thermometer code start pulse generating circuit or a one-hot code pulse generating circuit.

40. The chip according to claim 38, It is characterized in that The third number is equal to the first number.

41. The chip according to claim 38, It is characterized in that There is a first mapping relationship between the logic state set of the second number of start pulse signals and the selected fingerprint area, and there is a second mapping relationship between the logic state set of the third number of start pulse signals and the selected fingerprint area, wherein the first mapping relationship is different from the second mapping relationship.

42. The chip according to claim 38, It is characterized in that The second number of start pulse signals are used to be provided to the decoder disposed on the panel so that the decoder obtains the information about the selected fingerprint area according to logic values ​​of the second number of start pulse signals.

43. The chip according to claim 42, It is characterized in that The second number of start pulse signals is for being provided to the decoder to provide a fourth number of start pulses each for selecting a corresponding one of the first number of fingerprint regions, wherein the fourth number is equal to the first number.

44. The chip according to claim 25, It is characterized in that Each of the start pulse signals has a corresponding logic state, and a first mapping relationship exists between a set of logic states of the start pulse signals and the selected fingerprint region.

45. The chip according to claim 44, It is characterized in that The corresponding logic state of each of the start pulse signals has a plurality of logic values, and the selected fingerprint region is indicated according to a mathematical formula of the logic values ​​of the logic states of the start pulse signals.

46. ​​The chip according to claim 45, It is characterized in that The total number of the start pulse signals is equal to a second number, and the first number is greater than the second number.

47. The chip according to claim 46, It is characterized in that The plurality of logical values ​​include 0 and 1, and the mathematical formula is Where NF is the index number of the selected fingerprint area, S_(i+1) is the logic value of the (i+1)th start pulse signal S_(i+1), and i is 0 to N. 2 -1 integer, and N 2 is the second number.

48. The chip according to claim 25, It is characterized in that The fingerprint sensing pixel is an optical fingerprint sensing pixel capable of sensing light.

49. The chip according to claim 25, It is characterized in that The selection for each of the fingerprint regions depends on all of the start pulse signals.

50. A method for operating a chip capable of controlling a panel to perform fingerprint sensing, It is characterized in that The panel includes a plurality of fingerprint sensing pixels and a plurality of gate lines, the plurality of gate lines are arranged along a row direction of the panel for controlling the fingerprint sensing pixels, the fingerprint sensing pixels are divided into a first number of fingerprint regions along a column direction of the panel, and each of the fingerprint regions is coupled to a corresponding one or more gate lines among the gate lines of the panel, and the operating method includes: obtaining, by a selection circuit, information about a selected fingerprint region among the first number of fingerprint regions of the panel; and A plurality of control signals are provided to the panel through a control circuit for controlling the panel to perform fingerprint sensing, wherein the control signals include a plurality of start pulse signals, and the start pulse signals are provided to a decoder disposed on the panel so that the decoder obtains the information about the selected fingerprint area according to the logic values ​​of the start pulse signals.

51. An electronic device capable of performing fingerprint sensing, It is characterized in that The electronic device comprises: Panel, including: multiple fingerprint sensing pixels; a plurality of first gate lines arranged along a row direction of the panel for controlling the fingerprint sensing pixels, wherein the fingerprint sensing pixels are divided into a first number of fingerprint regions along a column direction of the panel, and each of the fingerprint regions is coupled to a corresponding one or more first gate lines among the first gate lines of the panel; and A first array upper gate circuit coupled to the gate line; and A chip capable of controlling the panel to perform fingerprint sensing, configured to obtain information about a selected fingerprint area among the first number of fingerprint areas of the panel and provide a plurality of first control signals to the first array on-gate circuit for controlling the fingerprint sensing pixels to perform fingerprint sensing, wherein the first control signals include a second number of start pulse signals collectively indicating the selected fingerprint area, wherein the first number is greater than the second number, the chip comprising: A selection circuit configured to obtain said information about said selected fingerprint region; and a control circuit coupled to the selection circuit to receive the information about the selected fingerprint area and configured to provide the first control signal to the panel, wherein the control circuit comprises: The first start pulse generating circuit is configured to provide the second number of start pulse signals according to the information about the selected fingerprint area.

52. The electronic device according to claim 51, It is characterized in that The first array-on-gate circuit includes a plurality of shift register groups, each of which is connected to a corresponding one of the fingerprint regions and operates according to all of the second number of start pulse signals.

53. The electronic device according to claim 51, It is characterized in that The start pulse signal is used to control the first gate line of the panel.

54. The electronic device according to claim 53, It is characterized in that The start pulse signal is provided to the first array upper gate circuit of the panel, and the first array upper gate circuit is configured to generate a plurality of scan signals for respectively controlling the first gate lines of the panel.

55. The electronic device according to claim 54, It is characterized in that The scan signal is configured to control the corresponding fingerprint sensing pixel to perform a reset operation and / or a select / write operation.

56. The electronic device according to claim 51, It is characterized in that The selection circuit is configured to receive the information about the selected fingerprint area from a processor, and the processor is configured to determine the selected fingerprint area based on touch information.

57. The electronic device according to claim 56, It is characterized in that The processor is configured to receive the touch information from a touch control circuit configured to control touch sensing on the panel.

58. The electronic device according to claim 51, It is characterized in that The first start pulse generating circuit is a binary start pulse generating circuit.

59. The electronic device according to claim 51, It is characterized in that Each of the second number of start pulse signals has a corresponding logic state, the corresponding logic state has multiple logic values, and the control circuit further includes an encoding circuit configured to encode the index number of the selected fingerprint area into the logic value of the start pulse signal of the second number of start pulse signals.

60. The electronic device according to claim 51, It is characterized in that The control circuit is configured to provide different numbers of start pulse signals according to different settings.

61. The electronic device according to claim 60, It is characterized in that The control circuit further comprises: a second start pulse generating circuit configured to provide a third number of start pulse signals according to the information about the selected fingerprint area, wherein the third number is not equal to the second number; and A switch circuit is coupled to the first start pulse generating circuit and the second start pulse generating circuit and is configured to select the second number of start pulse signals or the third number of start pulse signals as the first control signal.

62. The electronic device according to claim 61, It is characterized in that The second start pulse generating circuit is a thermometer code start pulse generating circuit or a one-hot code pulse generating circuit.

63. The electronic device according to claim 61, It is characterized in that The third number is equal to the first number.

64. The electronic device according to claim 61, It is characterized in that There is a first mapping relationship between the logic state set of the second number of start pulse signals and the selected fingerprint area, and there is a second mapping relationship between the logic state set of the third number of start pulse signals and the selected fingerprint area, wherein the first mapping relationship is different from the second mapping relationship.

65. The electronic device according to claim 61, It is characterized in that The first array gate circuit includes a decoder, and the second number of start pulse signals are used to be provided to the decoder disposed on the panel so that the decoder obtains the information about the selected fingerprint area according to logic values ​​of the second number of start pulse signals.

66. The electronic device according to claim 65, It is characterized in that The second number of start pulse signals is for being provided to the decoder to provide a fourth number of start pulses each for selecting a corresponding one of the first number of fingerprint regions, wherein the fourth number is equal to the first number.

67. The electronic device according to claim 66, It is characterized in that The first array-on-gate circuit also includes a plurality of shift registers coupled between the decoder and the fingerprint region.

68. The electronic device according to claim 65, It is characterized in that The decoder includes a plurality of decoder units each corresponding to one of the fingerprint regions.

69. The electronic device according to claim 68, It is characterized in that All of the second number of start pulse signals are provided to each of the decoder units.

70. The electronic device according to claim 51, It is characterized in that Each of the second number of start pulse signals has a corresponding logic state, and a first mapping relationship exists between the logic state sets of the second number of start pulse signals and the selected fingerprint region.

71. The electronic device according to claim 70, It is characterized in that The corresponding logic state of each of the second number of start pulse signals has a plurality of logic values, and the selected fingerprint region is indicated according to a mathematical formula of the logic values ​​of the logic states of the second number of start pulse signals.

72. The electronic device according to claim 71, It is characterized in that The plurality of logical values ​​include 0 and 1, and the mathematical formula is Where NF is the index number of the selected fingerprint area, S_(i+1) is the logic value of the (i+1)th start pulse signal S_(i+1), and i is 0 to N. 2 -1 integer, and N 2 is the second number.

73. The electronic device according to claim 51, It is characterized in that The fingerprint sensing pixel is an optical fingerprint sensing pixel capable of sensing light.

74. The electronic device according to claim 51, It is characterized in that The first array upper gate circuit is configured to receive the first control signal from the chip and generate a plurality of first scanning signals for respectively controlling the first gate lines of the panel.

75. The electronic device according to claim 74, It is characterized in that The first array upper gate circuit includes a decoder configured to decode the start pulse signal to obtain the information about the selected fingerprint region.

76. The electronic device according to claim 51, It is characterized in that The panel also includes: multiple display pixels; a plurality of second gate lines arranged along a row direction of the panel for controlling the plurality of display pixels; and The second array upper gate circuit is disposed on the panel and configured to receive a second control signal and generate a plurality of second scanning signals for respectively controlling the plurality of second gate lines to perform display.

77. The electronic device according to claim 76, It is characterized in that The chip also includes a display control circuit configured to generate the second control signal.

78. The electronic device according to claim 51, It is characterized in that The selection for each of the fingerprint regions depends on all of the second number of start pulse signals.

79. A method for operating an electronic device capable of performing fingerprint sensing, It is characterized in that The operation method comprises: Dividing a plurality of fingerprint sensing pixels of a panel into a first number of fingerprint regions along a column direction of the panel, wherein each of the fingerprint regions is coupled to a corresponding one or more gate lines among a plurality of gate lines of the panel, and the gate lines are arranged along a row direction of the panel for controlling the fingerprint sensing pixels; and The panel is controlled by a chip to perform fingerprint sensing so as to obtain information about a selected fingerprint area among the first number of fingerprint areas of the panel and provide multiple control signals to the panel for controlling the panel to perform fingerprint sensing, wherein the control signal includes a second number of start pulse signals collectively indicating the selected fingerprint area, wherein the first number is greater than the second number, the chip includes a selection circuit and a control circuit, the selection circuit is configured to obtain the information about the selected fingerprint area, the control circuit is coupled to the selection circuit to receive the information about the selected fingerprint area, the control circuit is configured to provide the control signal to the panel, and the control circuit includes a first start pulse generating circuit, the first start pulse generating circuit is configured to provide the second number of start pulse signals according to the information about the selected fingerprint area.

80. An electronic device capable of performing fingerprint sensing, It is characterized in that The electronic device comprises: Panel, including: multiple fingerprint sensing pixels; a plurality of first gate lines arranged along a row direction of the panel for controlling the fingerprint sensing pixels, wherein the fingerprint sensing pixels are divided into a first number of fingerprint regions along a column direction of the panel, and each of the fingerprint regions is coupled to a corresponding one or more first gate lines among the first gate lines of the panel; and A first array upper gate circuit coupled to the gate line; and A chip capable of controlling the panel to perform fingerprint sensing, configured to obtain information about a selected fingerprint area among the first number of fingerprint areas of the panel and provide a plurality of first control signals to the first array gate circuit for controlling the fingerprint sensing pixels to perform fingerprint sensing, wherein the first control signals include a plurality of start pulse signals, and the start pulse signals are used to be provided to a decoder disposed on the panel so that the decoder obtains the information about the selected fingerprint area according to the logic values ​​of the start pulse signals.

81. The electronic device according to claim 80, It is characterized in that The first array upper gate circuit includes a plurality of shift register groups, each of which is connected to a corresponding one of the fingerprint regions and operates according to all of the start pulse signals.

82. The electronic device according to claim 80, It is characterized in that The decoder includes a plurality of decoder units each corresponding to one of the fingerprint regions.

83. The electronic device according to claim 82, It is characterized in that All of the start pulse signals are provided to each of the decoder units.

84. The electronic device according to claim 80, It is characterized in that The start pulse signal is used to control the first gate line of the panel.

85. The electronic device according to claim 84, It is characterized in that The start pulse signal is provided to the first array upper gate circuit of the panel, and the first array upper gate circuit is configured to generate a plurality of scan signals for respectively controlling the first gate lines of the panel.

86. The electronic device according to claim 85, It is characterized in that The scan signal is configured to control the corresponding fingerprint sensing pixel to perform a reset operation and / or a select / write operation.

87. The electronic device according to claim 80, It is characterized in that The chip comprises: A selection circuit configured to obtain the information about the selected fingerprint region among the first number of fingerprint regions of the panel; and A control circuit is coupled to the selection circuit to receive the information about the selected fingerprint area and is configured to provide the plurality of first control signals to the panel for controlling the panel to perform fingerprint sensing.

88. The electronic device according to claim 87, It is characterized in that The selection circuit is configured to receive the information about the selected fingerprint area from a processor, and the processor is configured to determine the selected fingerprint area based on touch information.

89. The electronic device according to claim 88, It is characterized in that The processor is configured to receive the touch information from a touch control circuit configured to control touch sensing on the panel.

90. The electronic device according to claim 87, It is characterized in that The control circuit comprises: The first start pulse generating circuit is configured to provide the start pulse signal according to the information about the selected fingerprint area.

91. The electronic device according to claim 90, It is characterized in that The first start pulse generating circuit is a binary start pulse generating circuit.

92. The electronic device according to claim 90, It is characterized in that Each of the start pulse signals has a corresponding logic state having a plurality of logic values, and the control circuit further comprises an encoding circuit configured to encode the index number of the selected fingerprint region into the logic value of the start pulse signal.

93. The electronic device according to claim 90, It is characterized in that The control circuit is configured to provide different numbers of start pulse signals according to different settings.

94. The electronic device according to claim 93, It is characterized in that The control circuit further comprises: a second start pulse generating circuit configured to provide a third number of start pulse signals according to the information about the selected fingerprint region, wherein a total number of the start pulse signals generated by the second start pulse generating circuit is equal to a second number, and the third number is not equal to the second number; and A switch circuit is coupled to the first start pulse generating circuit and the second start pulse generating circuit and is configured to select the second number of start pulse signals or the third number of start pulse signals as the first control signal.

95. The electronic device according to claim 94, It is characterized in that The second start pulse generating circuit is a thermometer code start pulse generating circuit or a one-hot code pulse generating circuit.

96. The electronic device according to claim 94, It is characterized in that The third number is equal to the first number.

97. The electronic device according to claim 94, It is characterized in that There is a first mapping relationship between the logic state set of the second number of start pulse signals and the selected fingerprint area, and there is a second mapping relationship between the logic state set of the third number of start pulse signals and the selected fingerprint area, wherein the first mapping relationship is different from the second mapping relationship.

98. The electronic device according to claim 94, It is characterized in that The first array gate circuit further includes the decoder, and the second number of start pulse signals are used to be provided to the decoder disposed on the panel so that the decoder obtains the information about the selected fingerprint area according to the logic values ​​of the second number of start pulse signals.

99. The electronic device according to claim 98, It is characterized in that The second number of start pulse signals is for being provided to the decoder to provide a fourth number of start pulses each for selecting a corresponding one of the first number of fingerprint regions, wherein the fourth number is equal to the first number.

100. The electronic device according to claim 99, It is characterized in that The first array-on-gate circuit also includes a plurality of shift registers coupled between the decoder and the fingerprint region.

101. The electronic device according to claim 80, It is characterized in that Each of the start pulse signals has a corresponding logic state, and a first mapping relationship exists between a set of logic states of the start pulse signals and the selected fingerprint region.

102. The electronic device according to claim 101, It is characterized in that The corresponding logic state of each of the start pulse signals has a plurality of logic values, and the selected fingerprint region is indicated according to a mathematical formula of the logic values ​​of the logic states of the start pulse signals.

103. The electronic device according to claim 102, It is characterized in that The total number of the start pulse signals is equal to a second number, wherein the first number is greater than the second number.

104. The electronic device according to claim 102, It is characterized in that The plurality of logical values ​​include 0 and 1, and the mathematical formula is Where NF is the index number of the selected fingerprint area, S_(i+1) is the logic value of the (i+1)th start pulse signal S_(i+1), and i is 0 to N. 2 -1 integer, and N 2 is the second number.

105. The electronic device according to claim 80, It is characterized in that The fingerprint sensing pixel is an optical fingerprint sensing pixel capable of sensing light.

106. The electronic device according to claim 80, It is characterized in that The first array upper gate circuit is configured to receive the first control signal from the chip and generate a plurality of first scanning signals for respectively controlling the first gate lines.

107. The electronic device according to claim 106, It is characterized in that The first array upper gate circuit includes a decoder configured to decode the start pulse signal to obtain the information about the selected fingerprint region.

108. The electronic device according to claim 80, It is characterized in that The panel also includes: multiple display pixels; a plurality of second gate lines arranged along a row direction of the panel for controlling the plurality of display pixels; and The second array upper gate circuit is disposed on the panel and configured to receive a second control signal and generate a plurality of second scanning signals for respectively controlling the plurality of second gate lines.

109. The electronic device according to claim 108, It is characterized in that The chip also includes a display control circuit configured to generate the second control signal.

110. The electronic device according to claim 80, It is characterized in that The selection for each of the fingerprint regions depends on all of the start pulse signals.

111. A method for operating an electronic device capable of performing fingerprint sensing, It is characterized in that The operation method comprises: Arranging a plurality of gate lines of the panel along a row direction of the panel for controlling a plurality of fingerprint sensing pixels of the panel; dividing the fingerprint sensing pixels into a first number of fingerprint regions along a column direction of the panel, wherein each of the fingerprint regions is coupled to a corresponding one or more gate lines among the gate lines of the panel; and The panel is controlled by a chip to perform fingerprint sensing so as to obtain information about a selected fingerprint area among the first number of fingerprint areas of the panel and multiple control signals are provided to the panel for controlling the panel to perform fingerprint sensing, wherein the control signals include multiple start pulse signals, and the start pulse signals are used to be provided to a decoder disposed on the panel so that the decoder obtains the information about the selected fingerprint area according to the logic value of the start pulse signal.

112. A panel capable of performing fingerprint sensing, It is characterized in that The panel comprises: multiple fingerprint sensing pixels; a plurality of first gate lines arranged along a row direction of the panel for controlling the fingerprint sensing pixels, wherein the fingerprint sensing pixels are divided into a first number of fingerprint regions along a column direction of the panel, and each of the fingerprint regions is coupled to a corresponding one or more first gate lines among the first gate lines of the panel; and The first array gate circuit is disposed on the panel and configured to receive a control signal from the chip and generate a plurality of first scanning signals for controlling the first gate lines respectively to perform fingerprint sensing, wherein the control signal includes a plurality of start pulse signals, The first array upper gate circuit includes a decoder configured to decode the start pulse signal to obtain information about a selected fingerprint region for performing the fingerprint sensing.

113. The panel according to claim 112, It is characterized in that The scan signal is configured to control the corresponding fingerprint sensing pixel to perform a reset operation and / or a select / write operation.

114. The panel according to claim 112, It is characterized in that The first array upper gate circuit includes a plurality of shift register groups, each of which is connected to a corresponding one of the fingerprint regions and operates according to all of the start pulse signals.

115. The panel according to claim 112, It is characterized in that The panel also includes: multiple display pixels; a plurality of second gate lines arranged along a row direction of the panel for controlling the plurality of display pixels; and The second array upper gate circuit is disposed on the panel and configured to receive a control signal from the chip and generate a plurality of second scanning signals for respectively controlling the plurality of second gate lines.

116. The panel according to claim 112, It is characterized in that The fingerprint sensing pixel is an optical fingerprint sensing pixel capable of sensing light.

117. The panel according to claim 112, It is characterized in that The decoder is configured to receive a second number of start pulse signals and provide a third number of start pulses each for selecting a corresponding one of the first number of fingerprint regions, wherein the second number is greater than the first number and the third number is equal to the first number.

118. The panel according to claim 117, It is characterized in that The first array-on-gate circuit also includes a plurality of shift registers coupled between the decoder and the fingerprint region.

119. The panel according to claim 117, It is characterized in that The decoder includes a plurality of decoder units each corresponding to one of the fingerprint regions.

120. The panel according to claim 119, It is characterized in that All of the start pulse signals are provided to each of the decoder units.

121. The panel according to claim 112, It is characterized in that The selection for each of the fingerprint regions depends on all of the start pulse signals.

122. A decoder for a panel comprising a plurality of fingerprint sensing pixels, It is characterized in that The decoder comprises: A plurality of decoder units each comprising a plurality of input terminals configured to receive all of the first plurality of start pulse signals, wherein each of the decoder units is configured to decode the first plurality of start pulse signals into a corresponding one of the second plurality of start pulse signals.

123. The decoder according to claim 122, It is characterized in that The decoder units have the same circuit structure and the input terminals of the decoder units have different coupling relationships with the first plurality of start pulse signals.

124. The decoder according to claim 122, It is characterized in that Each of the second plurality of start pulse signals is used by an array on-gate circuit to generate a plurality of scan signals for controlling the fingerprint sensing pixels.

125. The decoder according to claim 122, It is characterized in that The panel further includes a plurality of gate lines coupled to the fingerprint sensing pixels, and each of the start pulse signals is used to generate a plurality of scan signals for controlling the gate lines coupled to the fingerprint sensing pixels.

126. The decoder according to claim 122, It is characterized in that The panel also includes a plurality of shift register groups coupled to corresponding fingerprint sensing pixels, and each of the second plurality of start pulse signals is provided to a corresponding one of the shift register groups.

127. The decoder according to claim 122, It is characterized in that The fingerprint sensing pixels are divided into a plurality of fingerprint regions and each of the second plurality of start pulse signals corresponds to one of the fingerprint regions.

128. The decoder according to claim 122, It is characterized in that The total number of the first plurality of start pulse signals is less than the total number of the second plurality of start pulse signals.

129. The decoder according to claim 122, It is characterized in that Each of the decoder units comprises: a plurality of input terminals configured to be coupled to the first plurality of start pulse signals; an output terminal configured to provide a corresponding one of the second plurality of start pulse signals; and a plurality of first logic units, wherein each of the first logic units comprises an input terminal configured to be coupled to the input terminal of the decoder unit, The total number of the first logic units is the same as the total number of the first plurality of start pulse signals.

130. The decoder according to claim 129, It is characterized in that The plurality of first logic units are connected in cascade, and a specific one of the first logic units has an output terminal coupled to the output terminal of the decoder unit.

131. The decoder according to claim 129, It is characterized in that Each of the decoder units further comprises: An inverter is coupled between the output terminal of the specific one of the first logic units and the output terminal of the decoder unit.

132. The decoder according to claim 129, It is characterized in that Each of the decoder units further comprises: A plurality of inverters are each coupled between one of the input terminals of the decoder unit and the input terminal of one of the first logic units.

133. The decoder according to claim 129, It is characterized in that All output terminals of the first logic unit are coupled together to the output terminal of the decoder unit.

134. The decoder according to claim 129, It is characterized in that Each of the decoder units further comprises: A plurality of inverters are each coupled between one of the input terminals of the decoder unit and the input terminal of one of the first logic units.

135. The decoder according to claim 129, It is characterized in that Each of the decoder units further comprises: a plurality of second logic units, each of the second logic units comprising an input terminal configured to be coupled to a corresponding one of the first plurality of start pulse signals, and a total number of the second logic units is the same as a total number of the first plurality of start pulse signals, wherein all output terminals of the second logic unit of one of the decoder units are coupled together to the output terminal of the one of the decoder units.

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