Semiconductor device and method for forming the same

Abstract

The present disclosure relates to a semiconductor device and a method for forming the same, and an improved work function layer and a method for forming the same are disclosed herein. In one embodiment, the method includes forming a semiconductor fin extending from a substrate; depositing a dielectric layer on the semiconductor fin; depositing a first work function layer on the dielectric layer; and exposing the first work function layer to a metastable plasma of a first reactant gas, a metastable plasma of a generated gas, and a metastable plasma of a second reactant gas, wherein the first reactant gas is different from the second reactant gas.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices, and more particularly to methods for improving work function layers. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are generally made by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and using lithography to pattern the layers of various materials to form electronic components and units on the semiconductor substrate.

[0003] The semiconductor industry continues to reduce the minimum feature size to continuously improve the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, or the like) so that more components can be integrated into a given area. However, as the minimum feature size is reduced, additional problems that need to be solved are also generated. Summary of the invention

[0004] One embodiment of the present invention provides a method for forming a semiconductor device, including forming a semiconductor fin extending from a substrate; depositing a dielectric layer on the semiconductor fin; depositing a first work function layer on the dielectric layer; and exposing the first work function layer to a metastable plasma of a first reaction gas, a metastable plasma of a generated gas, and a metastable plasma of a second reaction gas, wherein the first reaction gas is different from the second reaction gas.

[0005] Another embodiment of the present invention provides a method for forming a semiconductor device, comprising generating a first plasma from a first precursor gas, wherein the first precursor gas includes helium; separating a plurality of metastable species in the first plasma and a plurality of charged species in the first plasma; mixing the metastable species with a second precursor gas, wherein the second precursor gas includes hydrogen, wherein the step of mixing the first plasma and the second precursor gas generates a second plasma; and exposing a work function layer on a substrate to the second plasma.

[0006] Another embodiment of the present invention provides a semiconductor device, including a fin extending from a substrate; a dielectric layer located on the fin; a first work function layer located on the dielectric layer, the first work function layer including tungsten, nitrogen, and helium, wherein the carbon atom concentration of the first work function layer is less than 0.1% and is non-zero; a second work function layer located on the dielectric layer and the first work function layer, the second work function layer in the first region contacts the dielectric layer, and the second work function layer in the second region contacts the first work function layer; and a gate located on the first work function layer and the second work function layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a three-dimensional diagram of a fin field effect transistor in some embodiments.

[0008] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Fig. 8A , Figure 8B , Fig.9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig. 10C , Fig. 10D , Fig.11A , Fig. 11B , Fig. 12A , Fig. 12B , Fig.13A , Fig. 13B , Fig.14 and Fig.15 is a cross-sectional view of an intermediate stage of forming a fin field effect transistor in some embodiments.

[0009] Fig.16A is a cross-sectional view of a plasma manufacturing tool used to process a FinFET in some embodiments.

[0010] Fig. 16B is a graph of work function compositions after exposure to plasma generated at various gas flow rates for some embodiments.

[0011] Fig.17 , Fig.18 , Fig.19A , Fig.19B , Fig.19C , Fig. 20 , Fig.21A , Fig. 21B , Fig. 21C , Fig.22A , Fig. 22B , Fig.23A and Fig. 23B is a cross-sectional view of an intermediate stage of forming a fin field effect transistor in some embodiments.

[0012] Description of reference numerals:

[0013] AA, BB, CC: Reference profile

[0014] e - :electronic

[0015] He*: metastable helium

[0016] N*: metastable nitrogen

[0017] W1, W2: channel length

[0018] 50: Substrate

[0019] 50N,50P,300,400: Area

[0020] 51: Divider

[0021] 52: Fins

[0022] 54: Insulation material

[0023] 56: Shallow Trench Isolation Area

[0024] 58: Channel Area

[0025] 60: Virtual dielectric layer

[0026] 62: Virtual gate layer

[0027] 64: Mask layer

[0028] 72: Virtual gate

[0029] 74: Mask

[0030] 80: Gate seal spacer

[0031] 82: Epitaxial source / drain regions

[0032] 86: Gate spacer

[0033] 87: Contact Etch Stop Layer

[0034] 88: First interlayer dielectric layer

[0035] 90: Depression

[0036] 92: Gate dielectric layer

[0037] 92a: Interface layer

[0038] 92b: Dielectric layer with high dielectric constant

[0039] 94: First work function layer

[0040] 96: Bottom anti-reflective coating

[0041] 98: Photoresist layer

[0042] 100: Second work function layer

[0043] 102: Gate

[0044] 104: Gate mask

[0045] 106: Second interlayer dielectric layer

[0046] 108: Gate contact

[0047] 110: Source / drain contact

[0048] 200: Manufacturing tools

[0049] 202: Wafer holder

[0050] 204: First plasma generation chamber

[0051] 206: Sprinkler head

[0052] 208: Coil

[0053] 210a: First entrance

[0054] 210b: Second entrance

[0055] 212: First Opening

[0056] 214: Second plasma generation chamber DETAILED DESCRIPTION

[0057] The following content provides different embodiments or examples that can implement different structures of the present invention. The following specific components and arrangement embodiments are used to simplify the present invention and are not intended to limit the present invention. For example, the description of forming a first component on a second component includes an embodiment in which the two are in direct contact, or an embodiment in which the two are separated by other additional components but not in direct contact. In addition, multiple embodiments of the present invention may repeatedly use the same number for simplicity, but the components with the same number in multiple embodiments and / or settings do not necessarily have the same corresponding relationship.

[0058] In addition, the structure of the embodiments of the present invention is formed on another structure, connected to another structure, and / or coupled to another structure. The structure may directly contact another structure, or an additional structure may be formed between the structure and the other structure. In addition, spatial relative terms such as "below", "below", "lower", "above", "above", or similar terms can be used to simplify the relative relationship between an element and another element in the diagram. Spatially relative terms can be extended to elements used in other directions, rather than being limited to the illustrated direction. Elements can also be rotated 90° or other angles, so directional terms are only used to illustrate the direction in the diagram.

[0059] Various embodiments provide processes for forming an improved work function layer in a semiconductor device, provide semiconductor devices having an improved work function layer, and provide apparatus for performing a plasma treatment on the work function layer to form the improved work function layer. For example, a dielectric layer may be deposited on a semiconductor fin, and the work function layer may be deposited on the dielectric layer. In some embodiments, the work function layer may include tungsten carbonitride. The plasma treatment may include exposing the work function layer to a plasma generated from helium, butane, and hydrogen. Performing a plasma treatment on the work function layer may increase the density of the work function layer, reduce the grain size in the work function layer, reduce the carbon concentration in the work function layer, and increase the nitrogen and tungsten concentrations in the work function layer. Exposure of the work function layer to the plasma may further improve the adhesion between a subsequently deposited photoresist material (such as a bottom anti-reflective coating) and the work function layer. Exposure of the work function layer to the plasma may improve the pattern accuracy of the work function layer, improve the performance of a device containing the work function layer, reduce defects in a device containing the work function layer, increase the pass rate of wafer acceptance testing, and increase yield.

[0060] Figure 1 A three-dimensional diagram of a fin field effect transistor is shown in some embodiments. The fin field effect transistor includes a fin 52 on a substrate 50 (such as a semiconductor substrate). An isolation region such as a shallow trench isolation region 56 is located in the substrate 50, and the fin 52 protrudes from between adjacent isolation regions such as the shallow trench isolation region 56 and is higher than the isolation region. Although the isolation region such as the shallow trench isolation region 56 and the substrate 50 are separated in the description and drawings, the term "substrate" described herein may refer to a semiconductor substrate alone, or a semiconductor substrate containing an isolation region. In addition, although the fin 52 and the substrate 50 in the drawings are formed of a single continuous material, the fin 52 and / or the substrate 50 may include a single material or multiple materials. In the specification, the fin 52 refers to the portion extending between adjacent isolation regions such as the shallow trench isolation region 56.

[0061] The gate dielectric layer 92 is disposed along the sidewalls of the fin 52 and on the upper surface of the fin 52, and the gate 102 is disposed on the gate dielectric layer 92. The source / drain regions 82 are disposed on both sides of the fin 52 relative to the gate dielectric layer 92 and the gate 102. Figure 1 Reference cross sections used in subsequent figures are also shown. Reference cross section AA is along the longitudinal axis of gate 102 and is oriented perpendicular to the direction of current flow between source / drain regions 82 of the fin field effect transistor. Reference cross section BB is perpendicular to reference cross section AA and along the longitudinal axis of fin 52 and is oriented in the direction of current flow between source / drain regions 82 of the fin field effect transistor. Reference cross section CC is parallel to reference cross section AA and extends through the source / drain regions of the fin field effect transistor. Subsequent figures will refer to these reference cross sections for clarity.

[0062] Some embodiments described herein use a gate-last process to form a fin field effect transistor. In other embodiments, a gate-first process may be used. In addition, some embodiments may be implemented in planar devices such as planar field effect transistors.

[0063] Figures 2 to 15 and Figures 17 to 23B is a cross-sectional view of an intermediate stage of forming a fin field effect transistor in some embodiments. Figures 2 to 7 , Fig. 8A , Fig.9A , Fig. 10A , Fig.11A , Fig. 12A , Fig.13A , Fig.14 , Fig.15 , Fig.17 , Fig.18 , Fig.19A , Fig. 20 , Fig.21A , Fig.22A and Fig.23A Along Figure 1 Referring to cross section AA shown, the difference is multiple fins and / or FinFETs. Figure 8B , Fig. 9B , Fig. 10B , Fig. 11B , Fig. 12B , Fig. 13B , Fig.19B , Fig.19C , Fig. 21B , Fig. 21C , Fig. 22B ,and Fig. 23B Along Figure 1 Referring to cross section BB, the difference is multiple fins and / or FinFETs. Fig. 10C and Fig. 10D Along Figure 1 Reference cross section CC is shown, with the difference being multiple fins and / or FinFETs.

[0064] exist Figure 2In the invention, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate such as a bulk semiconductor, a semiconductor-on-insulator substrate, or the like, which may be doped (e.g., doped with p-type or n-type dopants) or undoped. The substrate 50 may be a wafer such as a silicon wafer. Generally speaking, a silicon-on-insulator substrate is a semiconductor material layer formed on an insulating layer. For example, the insulating layer may be a buried oxide layer, a silicon oxide layer, or the like. The insulating layer may be provided on a substrate, typically a silicon substrate or a glass substrate. Other substrates such as multilayer substrates or composition gradient substrates may also be used. In some embodiments, the semiconductor material of the substrate 50 may include silicon, germanium, a semiconductor compound (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), a semiconductor alloy (e.g., silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide), or a combination thereof.

[0065] The substrate 50 has a region 50N and a region 50P. The region 50N may be a region for forming an n-type device (e.g., an n-type metal oxide semiconductor transistor such as an n-type fin field effect transistor). The region 50P may be a region for forming a p-type device (e.g., a p-type metal oxide semiconductor transistor such as a p-type fin field effect transistor). The region 50N and the region 50P may be physically separated (e.g., separated by a separation line 51 shown in the figure), and any number of device structures (e.g., other active devices, doped regions, isolation structures, or the like) may be located between the region 50N and the region 50P.

[0066] exist Figure 3 In the embodiment of the present invention, fins 52 are formed in substrate 50. Fins 52 are semiconductor strips. In some embodiments, fins 52 are formed in substrate 50 by etching trenches in substrate 50. Etching can be any acceptable etching process, such as reactive ion etching, neutral beam etching, similar processes, or combinations thereof. Etching can be anisotropic.

[0067] The fins may be patterned by a suitable method. For example, the patterning method of the fins may use one or more photolithography processes, including double patterning or multiple patterning processes. Generally speaking, the double patterning or multiple patterning process combines photolithography with a self-alignment process, and the pattern spacing produced may be smaller than the pattern spacing obtained by using a single direct photolithography process. For example, one embodiment forms a sacrificial layer on a substrate and patterns the sacrificial layer using a photolithography process. A self-alignment process is used to form spacers along the sides of the patterned sacrificial layer. The sacrificial layer is then removed, and the retained spacers can then be used to pattern the fins. In some embodiments, a mask or other layer may be retained on the fin 52.

[0068] exist Figure 4In the embodiment, the insulating material 54 is formed on the substrate 50 and between the adjacent fins 52. The composition of the insulating material 54 may be an oxide such as silicon oxide, nitride, the like, or a combination thereof, and the method of forming the insulating material 54 may be high-density plasma chemical vapor deposition, flowable chemical vapor deposition (such as depositing a chemical vapor deposition-based material in a remote plasma system, and then curing the material to convert it into another material such as an oxide), a similar method, or a combination thereof. Other insulating materials formed by any acceptable process may also be used. In the embodiment, the insulating material 54 is silicon oxide formed by a flowable chemical vapor deposition process. Once the insulating material is formed, an annealing process may be performed. In one embodiment, the insulating material 54 is formed so that the excess insulating material 54 covers the fins 52. Although the insulating material 54 in the accompanying drawings is a single layer, some embodiments may use multiple layers of insulating material. For example, some embodiments may first form a liner layer (not shown) along the surface of the substrate 50 and the fin 52. The above-mentioned filling material may then be formed on the liner layer.

[0069] exist Figure 5 In the embodiment, the insulating material 54 is subjected to a removal process to remove excess insulating material 54 on the fin 52. In some embodiments, a planarization process such as chemical mechanical polishing, an etch back process, a combination of the above, or a similar process may be used. The planarization process exposes the fin 52 so that the fin 52 after the planarization process is completed is flush with the upper surface of the insulating material 54. In the embodiment where the mask remains on the fin 52, the planarization process may expose the mask or remove the mask to expose the upper surface of the mask or the fin 52. After the planarization process is completed, the insulating material 54 is flush.

[0070] exist Figure 6 In the embodiment of the present invention, the insulating material 54 is recessed to form a shallow trench isolation region 56. Due to the recess of the insulating material 54, the upper portion of the fin 52 in the region 50N and the region 50P protrudes from between the adjacent shallow trench isolation regions 56. In addition, the upper surface of the shallow trench isolation region 56 may have a flat surface, a protruding surface, a recessed surface (such as a dished surface), or a combination thereof as shown. By suitable etching, the upper surface of the shallow trench isolation region 56 may be flat, raised, and / or recessed. The method of recessing the shallow trench isolation region 56 may adopt an acceptable etching process, such as an etching process that is selective to the insulating material 54 (the rate at which the insulating material is etched is higher than the rate at which the fin 52 is etched). For example, the oxide removal process may adopt dilute hydrofluoric acid.

[0071] Matching Figures 2 to 6The process described is only one example of how to form the fin 52. In some embodiments, the fin may be formed by an epitaxial growth process. For example, a dielectric layer may be formed on the upper surface of the substrate 50, and a trench may be etched through the dielectric layer to expose the substrate 50 below. A homoepitaxial structure may be epitaxially grown in the trench. The dielectric layer is recessed so that the homoepitaxial structure may protrude from the dielectric layer to form the fin. In addition, the fin 52 of some embodiments may be a heteroepitaxial structure. For example, Figure 5 The fin in the substrate 50 may be recessed, and a material different from the fin 52 may be epitaxially grown on the recessed fin 52. In these embodiments, the fin 52 includes the recessed material, and the epitaxially grown material located on the recessed material. In other embodiments, a dielectric layer may be formed on the upper surface of the substrate 50, and a groove may be etched through the dielectric layer. A heteroepitaxial structure may then be epitaxially grown in the groove, and the heteroepitaxial structure may be made of a material different from the substrate 50. The dielectric layer is recessed so that the heteroepitaxial structure protrudes from the dielectric layer to form the fin 52. In some embodiments, a homoepitaxial or heteroepitaxial structure is epitaxially grown, and in-situ doping may be performed when the epitaxially grown material is grown to omit previous or subsequent implantation. However, in-situ doping and implantation doping may be used in combination.

[0072] In addition, the epitaxial growth of regions 50N (eg, n-type metal oxide semiconductor regions) and regions 50P (eg, p-type metal oxide semiconductor regions) using different materials may have advantages. In various embodiments, the composition of the upper portion of fin 52 may be silicon germanium (Si x Ge 1-x , where x can be 0 to 1), silicon carbide, pure germanium or substantially pure germanium, III-V semiconductor compounds, II-VI semiconductor compounds, or the like. For example, feasible materials for forming III-V semiconductor compounds include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, or the like.

[0073] exist Figure 6 In some embodiments, a suitable well region (not shown) may be formed in the fin 52 and / or the substrate 50. In some embodiments, a p-type well may be formed in the region 50N, and an n-type well may be formed in the region 50P. In some embodiments, a p-type well may be formed in the region 50N and the region 50P, or an n-type well may be formed in the region 50N and the region 50P.

[0074] In embodiments with different well area morphologies, a photoresist or other mask (not shown) may be used to achieve different implantation steps for regions 50N and 50P. For example, a photoresist may be formed on the fin 52 and shallow trench isolation region 56 in region 50N. The photoresist is patterned to expose region 50P (such as a p-type metal oxide semiconductor region) of the substrate 50. The photoresist may be formed using a spin coating technique and patterned using an acceptable photolithography technique. Once the photoresist is patterned, n-type impurities may be implanted into region 50P, and the photoresist may be used as a mask to substantially prevent n-type impurities from being implanted into region 50N (such as an n-type metal oxide semiconductor region). The concentration of n-type impurities such as phosphorus, arsenic, antimony, or the like implanted into the region may be less than or equal to 10 18 Atom / cm 3 , for example, between about 10 16 Atom / cm 3 to about 10 18 Atom / cm 3 After implantation, the photoresist can be removed, and the removal method can be an acceptable ashing process.

[0075] After implanting region 50P, a photoresist may be formed on fin 52 and shallow trench isolation region 56 in region 50P. The photoresist is patterned to expose region 50N (e.g., an n-type metal oxide semiconductor region) of substrate 50. The photoresist may be formed using a spin coating technique and patterned using an acceptable photolithography technique. Once the photoresist is patterned, p-type impurities may be implanted into region 50N, and the photoresist may serve as a mask to substantially prevent the implantation of p-type impurities into region 50P (e.g., a p-type metal oxide semiconductor region). The concentration of p-type impurities such as boron, boron fluoride, indium, or the like implanted into the region may be less than or equal to 10 18 Atom / cm 3 , for example, between about 10 16 Atom / cm 3 to about 10 18 Atom / cm 3 After implantation, the photoresist can be removed, and the removal method can be an acceptable ashing process.

[0076] After implanting regions 50N and 50P, annealing may be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments, in-situ doping may be performed when growing the epitaxial fin material, so implantation may be omitted. However, in-situ doping and implantation doping may be used in combination.

[0077] exist Figure 7In the embodiment, a dummy dielectric layer 60 is formed on the fin 52. For example, the dummy dielectric layer 60 may be silicon oxide, silicon nitride, a combination thereof, or the like, and may be formed by an acceptable technique such as deposition or thermal growth. A dummy gate layer 62 is formed on the dummy dielectric layer 60, and a mask layer 64 is formed on the dummy gate layer 62. The dummy gate layer 62 may be deposited on the dummy dielectric layer 60, and then the dummy gate layer 62 may be planarized, and the planarization method may be chemical mechanical polishing. The mask layer 64 may be deposited on the dummy gate layer 62. The dummy gate layer 62 may be a conductive or non-conductive material, and may include amorphous silicon, polycrystalline silicon, polycrystalline silicon germanium, metal nitride, metal silicide, metal oxide, or metal. The deposition method of the dummy gate layer 62 may be physical vapor deposition, chemical vapor deposition, sputtering deposition, or the like. The composition of the dummy gate layer 62 may be other materials that have high etch selectivity when etching the isolation region. For example, the mask layer 64 may include silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer 62 and a single mask layer 64 are formed on the region 50N and the region 50P. It is worth noting that the dummy dielectric layer 60 in the accompanying drawings only covers the fin 52, but this is only for illustrative purposes. In some embodiments, the dummy dielectric layer 60 may be deposited to cover the shallow trench isolation region 56 and extend between the dummy gate layer 62 and the shallow trench isolation region 56.

[0078] FIG. 8A to FIG. 13B Various additional steps are shown to form the apparatus of the embodiments. FIG. 8A to FIG. 13B The structures shown are located in regions 50N and 50P. For example, FIG. 8A to FIG. 13B The structure shown can be applied to the regions 50N and 50P. The structural differences between the regions 50N and 50P will be described in conjunction with each figure.

[0079] exist Fig. 8A and Figure 8B In the embodiment, the mask layer 64 can be patterned by using feasible photolithography and etching techniques (see Figure 7 ) to form a mask 74. The pattern of the mask 74 can then be transferred to the dummy gate layer 62 by an acceptable etching technique to form the dummy gate 72. In some embodiments (not shown), the pattern of the mask 74 can also be transferred to the dummy dielectric layer 60. The dummy gate 72 covers the respective channel regions 58 of the fins 52. The pattern of the mask 74 can be used to physically separate each adjacent dummy gate 72. The length direction of the dummy gate 72 can also be substantially perpendicular to the length direction of the respective fins 52.

[0080] exist Fig. 8A and Figure 8BIn the process, a gate sealing spacer 80 may be formed on the exposed surface of the dummy gate 72, the mask 74, and / or the fin 52. Thermal oxidation or deposition may be used, followed by anisotropic etching to form the gate sealing spacer 80. The gate spacer 80 may be composed of silicon oxide, silicon nitride, silicon oxynitride, or the like.

[0081] After forming the gate seal spacer 80, implantation for lightly doped source / drain regions (not shown) may be performed. Figure 6 Similar to the above implantation shown, a mask such as a photoresist may be formed on region 50N to expose region 50P, and an impurity of a suitable form (such as a p-type) may be implanted into the fin 52 exposed in region 50P. The mask may then be removed. A mask such as a photoresist may then be formed on region 50P to expose region 50N, and an impurity of a suitable form (such as an n-type) may be implanted into the fin 52 exposed in region 50N. The mask may then be removed. The n-type impurity may be any of the aforementioned n-type impurities, and the p-type impurity may be any of the aforementioned p-type impurities. The impurity concentration of the lightly doped source / drain region may be approximately 10 15 Atom / cm 3 to about 10 19 Atom / cm 3 Annealing can be used to repair implant damage and activate implanted impurities.

[0082] exist Fig.9A and Fig. 9B In the embodiment of the present invention, a gate spacer 86 is formed on the gate sealing spacer 80 along the sidewalls of the dummy gate 72 and the mask 74. The gate spacer 86 can be formed by conformally depositing an insulating material and then anisotropically etching the insulating material. The insulating material of the gate spacer 86 can be silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, a combination thereof, or the like.

[0083] It is worth noting that the above describes a general process for forming spacers and lightly doped source / drain regions. Other processes and sequences may also be used. For example, fewer or additional spacers may be used, a different sequence of steps may be used (such as not etching the gate sealing spacer 80 before forming the gate spacer 86 to produce an L-shaped gate sealing spacer), spacers may be formed and removed, and / or the like. In addition, different structures and steps may be used to form n-type and p-type devices. For example, lightly doped source / drain regions for n-type devices may be formed before forming the gate sealing spacer 80, and lightly doped source / drain regions for p-type devices may be formed after forming the gate sealing spacer 80.

[0084] exist Fig. 10A and Fig. 10BIn the embodiment of the present invention, epitaxial source / drain regions 82 are formed in the fins 52 to apply stress to the respective channel regions 58 to improve performance. The epitaxial source / drain regions 82 are formed in the fins 52 so that each dummy gate 72 is located between each pair of adjacent epitaxial source / drain regions 82. In some embodiments, the epitaxial source / drain regions may extend into the fins 52 or may pass through the fins 52. In some embodiments, gate spacers 86 are used to separate the epitaxial source / drain regions 82 from the dummy gates 72 by a suitable lateral distance to prevent the epitaxial source / drain regions 82 from shorting out to the gate subsequently formed in the final fin field effect transistor.

[0085] The epitaxial source / drain region 82 in region 50N (such as an n-type metal oxide semiconductor region) may be formed by masking region 50P (such as a p-type metal oxide semiconductor region) and etching the source / drain region of the fin 52 in region 50N to form a recess in the fin 52. The epitaxial source / drain region 82 in region 50N is then epitaxially grown in the recess. The epitaxial source / drain region 82 may include any acceptable material, such as a material suitable for an n-type fin field effect transistor. For example, if the fin 52 is silicon, the epitaxial source / drain region 82 in region 50N includes a material that can apply tensile stress to the channel region 58, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, or the like. The epitaxial source / drain region 82 in region 50N has a surface that is raised from the respective surface of the fin 52 and may have a crystal plane.

[0086] The epitaxial source / drain region 82 in region 50P (such as a p-type metal oxide semiconductor region) may be formed by masking region 50N (such as an n-type metal oxide semiconductor region) and etching the source / drain region of the fin 52 in region 50P to form a recess in the fin 52. The epitaxial source / drain region 82 in region 50P is then epitaxially grown in the recess. The epitaxial source / drain region 82 may include any acceptable material, such as a material suitable for a p-type fin field effect transistor. For example, if the fin 52 is silicon, the epitaxial source / drain region 82 in region 50P may include a material that applies compressive stress to the channel region 58, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, or the like. The epitaxial source / drain region 82 in region 50P may also have a surface that is raised from the individual surfaces of the fin 52 and may have a crystal plane.

[0087] Dopants may be implanted into the epitaxial source / drain regions 82 and / or the fins 52 to form source / drain regions, followed by annealing. This implantation step may be similar to the aforementioned process for forming lightly doped source / drain regions. The impurity concentration of the source / drain region may be between about 10 19 Atom / cm 3 to about 1021 Atom / cm 3 The n-type and / or p-type impurities used in the source / drain region may be any of the aforementioned impurities. In some embodiments, in-situ doping may be performed when the epitaxial source / drain region 82 is grown.

[0088] After the epitaxial process for forming epitaxial source / drain regions 82 in regions 50N and 50P is completed, the upper surfaces of the epitaxial source / drain regions have crystal planes that extend laterally outward from the sidewalls of fin 52. In some embodiments, these crystal planes cause adjacent epitaxial source / drain regions 82 of the same fin field effect transistor to merge, such as Fig. 10C In other embodiments, adjacent source / drain regions 82 are kept separate after the epitaxial process is completed, such as Fig. 10D As shown. Fig. 10C and Fig. 10D In the illustrated embodiment, the gate spacer 86 covers a portion of the sidewalls of the fin 52 extending over the shallow trench isolation region 56 to block epitaxial growth. In some other embodiments, the spacer etching step used to form the gate spacer 86 can be adjusted to remove the spacer material so that the epitaxial growth region can extend to the surface of the shallow trench isolation region 56.

[0089] exist Fig.11A and Fig. 11B In the process, a first interlayer dielectric layer 88 is deposited on Fig. 10A and Fig. 10B The structure shown in FIG. 1 is a perspective view of a first interlayer dielectric layer 88. The first interlayer dielectric layer 88 may be composed of a dielectric material, and its deposition method may be any suitable method such as chemical vapor deposition, plasma-assisted chemical vapor deposition, or flowable chemical vapor deposition. The dielectric material may include phosphosilicate glass, borosilicate glass, borophosphosilicate glass, undoped silicate glass, or the like. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer 87 is located between the first interlayer dielectric layer 88 and the epitaxial source / drain region 82, the mask 74, the gate spacer 86, and the gate sealing spacer 80. The contact etch stop layer 87 may include a dielectric material such as silicon nitride, silicon oxide, silicon oxynitride, or the like, and its etching rate is different from the etching rate of the first interlayer dielectric layer 88 above.

[0090] exist Fig. 12A and Fig. 12BIn the process, a planarization process such as chemical mechanical polishing can be performed to make the upper surface of the first interlayer dielectric layer 88 flush with the upper surface of the dummy gate 72 or the mask 74. The planarization process can also remove the mask 74 on the dummy gate 72, and the gate sealing spacer 80 and the gate spacer 86 along the sidewall of the mask 74. After the planarization process, the dummy gate 72, the gate sealing spacer 80, the gate spacer 86, and the upper surface of the first interlayer dielectric layer 88 are flush. In summary, the upper surface of the dummy gate 72 is exposed from the first interlayer dielectric layer 88. In some embodiments, the planarization process makes the upper surface of the first interlayer dielectric layer 88 flush with the upper surface of the mask 74, that is, the mask 74 is retained.

[0091] exist Fig.13A and Fig. 13B In the embodiment of the present invention, the dummy gate 72 and the mask 74, if present, are removed by an etching process to form a recess 90. A portion of the dummy dielectric layer 60 in the recess 90 may also be removed. In some embodiments, only the dummy gate 72 is removed and the dummy dielectric layer 60 is retained, and the recess 90 exposes the dummy dielectric layer 60. In some embodiments, the dummy dielectric layer 60 is removed from the recess 90 in the first region of the die (e.g., the core logic region), and the dummy dielectric layer 60 in the recess 90 in the second region of the die (e.g., the input / output region) is retained. In some embodiments, the removal method of the dummy gate 72 may be an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas, which may selectively etch the dummy gate 72 without etching the first interlayer dielectric layer 88 or the gate spacer 86. Each recess 90 exposes and / or is located on the channel region 58 of a respective fin 52. Each channel region 58 is located between a pair of adjacent epitaxial source / drain regions 82. When etching away the dummy gate 72, the dummy dielectric layer 60 can be used as an etching stop layer. After removing the dummy gate 72, the dummy dielectric layer 60 can be removed as appropriate.

[0092] Fig.14 , Fig.15 ,and Figures 17 to 20 The steps shown can be used to form dielectric layers and work function layers at Fig.13A and Fig. 13B in terms of structure. Fig.16A A manufacturing tool 200 is shown that can perform plasma processing on a work function layer deposited on a substrate 50 . Fig. 16B Shown is the work function composition after exposure to plasma generated at different gas flow rates. Fig.14 , Fig.15 , Fig.17 , Fig.18 , Fig.19A and Fig. 20 The structures in the regions 50N and 50P are shown, and Fig.19B and Fig.19C The structure in the display area 50P. Fig.14 , Fig.15 , Fig.17 , Fig.18 , Fig.19A and Fig. 20 Along Figure 1 Referring to cross section AA shown, the difference is multiple fins and / or FinFETs. Fig.19B and Fig.19C Along Figure 1 Referring to cross section BB, the difference is multiple fins and / or FinFETs.

[0093] exist Fig.14 In the embodiment, the gate dielectric layer 92 is deposited on Fig.13A and Fig. 13B The gate dielectric layer 92 may include an interface layer 92a and a high dielectric constant dielectric layer 92b deposited on the interface layer 92a. The interface layer 92a may be an oxide layer (such as a silicon oxide layer), the above-mentioned multilayer, or the like, and its formation method may be thermal oxidation of the fin 52, a chemical curing process, or a deposition process. The interface layer 92a may be conformally deposited on the upper surface and sidewalls of the fin 52 and the upper surface of the shallow trench isolation region 56. The composition of the high dielectric constant dielectric layer 92b may be a high dielectric constant dielectric material, such as hafnium oxide, lanthanum oxide, aluminum oxide, zirconium oxide, the above-mentioned multilayer, or the like. The dielectric constant of the high dielectric constant dielectric layer 92b is greater than or equal to about 3.9, greater than or equal to about 7.0, or greater than or equal to about 21.0. The high dielectric constant dielectric layer 92b may be conformally deposited on the upper surface and sidewalls of the interface layer 92a. In some embodiments of the present invention, the high-k dielectric layer 92 b may be formed by atomic layer deposition, chemical vapor deposition, or similar methods.

[0094] The gate dielectric layer 92 in the region 50N and the region 50P may be formed simultaneously, so that the composition of the gate dielectric layer 92 in each region is the same material. In some embodiments, the gate dielectric layer 92 in the region 50N and the region 50P may be formed by separate processes, so that the gate dielectric layer 92 in different regions may be different materials. When using separate processes, various masking steps may be used to mask and expose appropriate areas.

[0095] In some embodiments, a barrier layer (not shown) may be formed on the gate dielectric layer 92 as appropriate. The barrier layer may be formed between the gate dielectric layer 92 and a subsequently formed work function layer (e.g. Fig.15The barrier layer may be a metal layer, and may be composed of tantalum nitride or the like. The barrier layer may be formed by a deposition process such as atomic layer deposition, chemical vapor deposition, plasma assisted chemical vapor deposition, physical vapor deposition, sputtering deposition, or the like.

[0096] exist Fig.15 , a first work function layer 94 is deposited on a gate dielectric layer 92. The interface layer 92a and the high dielectric constant dielectric layer 92b are illustrated as a single gate dielectric layer 92 to simplify the drawing. The first work function layer 94 may be formed by a deposition process such as atomic layer deposition, chemical vapor deposition, plasma-assisted chemical vapor deposition, physical vapor deposition, sputtering deposition, or the like. In various embodiments, the first work function layer 94 may include a p-type work function metal. Examples of materials used for the first work function layer 94 may include tungsten carbonitride, titanium nitride, tantalum nitride, ruthenium, molybdenum, aluminum, tungsten nitride, zirconium silicide, molybdenum silicide, tantalum silicide, nickel silicide, other suitable p-type work function materials, or combinations thereof. In a specific embodiment, the first work function layer 94 may include tungsten carbonitride. In other embodiments, the first work function layer 94 may include any tungsten-based material, such as tungsten nitride or the like. The first work function layer 94 may include a single layer or multiple layers.

[0097] The first work function layer 94 may be deposited to a thickness of about 0.8 nm to about 1.5 nm, such as about 1.3 nm. The density of the deposited first work function layer 94 may be about 8.0 g / cm 3 To about 12.0g / cm 3 , such as about 9.4g / cm 3 In embodiments where the first work function layer 94 includes tungsten carbonitride, the carbon atom concentration in the first work function layer 94 may be about 1.0% to about 3.0% (e.g., about 1.5%), the tungsten atom concentration may be about 10.0% to about 30.0% (e.g., about 16.4%), the nitrogen atom concentration may be about 5.0% to about 15.0% (e.g., about 9.2%), and the ratio between tungsten atoms and nitrogen atoms may be about 1.10 to about 1.90 (e.g., about 1.71). The first work function layer 94 may have an orientation of β-W2N.

[0098] Fig.16AA manufacturing tool 200 is shown, which generates a plasma to perform a plasma treatment on the first work function layer 94 while depositing the first work function layer 94. The manufacturing tool 200 may include a wafer support 202 on which a substrate 50 may be placed. The wafer support 202 may be an electrostatic wafer holder that provides an electrostatic charge to clamp the substrate 50 on the wafer support 202 without a mechanical fixture. The manufacturing tool 200 also includes a first plasma generation chamber 204 and a showerhead 206 located on the wafer support 202, and a second plasma generation chamber 214 located between the showerhead 206 and the wafer support 202. The first plasma may be generated in the first plasma generation chamber 204 using a plasma generator such as a transformer coupled plasma system, an inductively coupled plasma system, a magnetically enhanced reactive ion etching system, an electron cyclotron resonance system, a remote plasma generator, or the like. In some embodiments, the first plasma generation chamber 204 may include a coil 208 therein, which may be used to generate the first plasma in the first plasma generation chamber 204. The first plasma may be used to generate a second plasma in the second plasma generating chamber 214 .

[0099] An excitation gas may be provided to the manufacturing tool 200 through a first inlet 210a located at the top of the first plasma generating chamber 204. The excitation gas may include reactive species and generated species.

[0100] The reactive species can generate a first metastable species that has a long lifespan. For example, the lifespan of the first metastable species generated from the reactive species is greater than about 2 seconds. Thus, the first metastable species can be generated in the first plasma generating chamber 204 and exist long enough to pass through the showerhead 206 and impact the substrate 50. The reactive species can also be a species that is about to react with the first work function layer 94. In some embodiments, the reactive species can include nitrogen, helium, hydrogen, combinations thereof, or the like.

[0101] The generated species may be a species that can generate a second metastable species, and the second metastable species can be used to generate a second plasma between the showerhead 206 and the substrate 50. The second plasma can be generated by transferring energy from the second metastable species to a reactive gas between the showerhead 206 and the substrate 50. In some embodiments, the generated species may include helium, argon, oxygen, combinations thereof, or the like.

[0102] A plasma generation process may be used to generate a first plasma in the first plasma generation chamber 204, and the process temperature may be about 100° C. to about 300° C. (e.g., about 200° C.). The pressure of the plasma generation process may be about 1.0 Torr to about 2.0 Torr (e.g., about 1.5 Torr), and the RF power provided to the coil 208 may be about 1000 W to about 3000 W (e.g., about 2000 W). In some embodiments, the excitation gas may include a reactive species (e.g., nitrogen) supplied at a flow rate of about 1000 sccm to about 9000 sccm (e.g., 5000 sccm), and a generated species (e.g., helium) supplied at a flow rate of about 1000 sccm to about 4500 sccm (e.g., about 2750 sccm). The first plasma generated using the above process conditions may generate metastable species in the first plasma, the energy of which is sufficient to generate the second plasma but insufficient to additionally erode or damage the first plasma generation chamber 204, the showerhead 206, the second plasma generation chamber 214, or the substrate 50.

[0103] The showerhead 206 may be a dual chamber metastable activated radical strip that can separate metastable species in the first plasma from charged species in the first plasma. For example, the first plasma may include metastable nitrogen N*, nitrogen ions N + , metastable helium He*, helium ion He + , and electronic - The showerhead 206 may be grounded and may be used to remove charged species (eg, nitrogen ions N + 、Helium ionHe + , and electronic - ), and provide metastable species without charged species (such as metastable nitrogen N* and metastable helium He*) to the second plasma generation chamber 214. Fig.16A As shown, metastable species are transported from the first plasma generation chamber 204 to the second plasma generation chamber 214 via the first opening 212 in the showerhead 206 .

[0104] A reaction gas may be provided to the second plasma generating chamber 214 through a second inlet 210b on the side of the first plasma generating chamber 204. The reaction gas may be used to reduce the energy of metastable species (such as metastable nitrogen N* and metastable helium He*) provided to the second plasma generating chamber 214, and may also react with the first work function layer 94. The reaction gas may be hydrogen, but may also be other gases such as oxygen or the like. Fig.16A As shown, the reactant gas passes through a second opening 212b in the showerhead 206 that is spaced apart from the first opening 212a.

[0105] The metastable species from the first plasma and the reactive gas then interact with each other between the showerhead 206 and the substrate 50. Energy is transferred from the metastable species (e.g., metastable nitrogen N* and metastable helium He*) to the reactive gas (e.g., hydrogen) to generate a second plasma directed toward the substrate 50. In embodiments where the reactive gas includes hydrogen, the energy transferred from the metastable species to the reactive gas may convert the hydrogen into metastable hydrogen H*. After the metastable species react with the reactive gas to form the second plasma, the second plasma may include metastable nitrogen N*, metastable helium He*, and metastable hydrogen H*. Since energy is transferred from the metastable species to the reactive gas to generate the second plasma, the energy of the second plasma is lower than the energy of the metastable species, which may reduce damage to the first work function layer 94. In addition, generating the second plasma in the second plasma generating chamber 214 may reduce erosion of chamber surface materials, which may result from the second plasma generated earlier in the process. In various embodiments, the flow rate of the reaction gas, such as hydrogen, may be about 1000 sccm to about 9000 sccm, such as about 5000 sccm.

[0106] The substrate 50 is exposed to the second plasma for a time sufficient to convert the first work function layer 94 to nitrogen saturation (e.g., a ratio of tungsten to nitrogen of less than about 1.2). For example, the substrate 50 may be exposed to the second plasma for a time from about 0 seconds to about 300 seconds (e.g., about 90 seconds). When the first work function layer 94 is exposed to the metastable nitrogen, a chemical reaction may occur, wherein the metastable nitrogen attaches to dangling bonds in the first work function layer 94 (e.g., tungsten). The metastable nitrogen reacts with the material of the first work function layer 94, causing the first work function layer 94 to recrystallize, increase the (111) crystal planes in the first work function layer 94, and increase the density of the first work function layer 94.

[0107] In a specific embodiment, the first work function layer includes tungsten and the reactive species includes nitrogen, and the first work function layer 94 after the plasma treatment process may have an orientation of β-W2N. In addition, the density of the first work function layer 94 after the plasma treatment may be about 9.4 g / cm 3 To about 12.0g / cm 3 , such as about 10.8g / cm 3 .

[0108] When the first work function layer 94 is exposed to the metastable hydrogen, the metastable hydrogen may react with the carbon contained in the first work function layer 94 to form volatile byproducts (such as hydrocarbons). The volatile byproducts may then be removed from the second plasma generation chamber 214. This may reduce the carbon concentration in the first work function layer 94. In addition, a portion of the metastable helium may be implanted into the first work function layer 94, the remaining metastable helium returns to the ground state, and the ground state helium is removed from the second plasma generation chamber 214. The second plasma generation chamber 214 may further include an exhaust outlet (not shown) that may be used to exhaust waste materials or reaction byproducts (such as volatile carbon byproducts, ground state helium, or the like). The exhaust outlet may be connected to a vacuum pump to assist in exhausting the waste materials.

[0109] The overall composition of the first work function layer 94 can be adjusted by increasing the nitrogen concentration, removing carbon, and recrystallizing the first work function layer 94. For example, plasma treatment on the first work function layer 94 can reduce the ratio between tungsten atoms and nitrogen atoms to about 1.20 to about 1.71, below about 1.20, or about 1.17. The atomic concentration of tungsten can be about 10.0% to about 30.0%, such as about 16.5%. The atomic concentration of nitrogen can be increased to about 9.2% to about 15.0%, such as about 14.1%. The atomic concentration of carbon can be reduced to about 0% to about 0.1%, such as below about 0.1%.

[0110] The increased nitrogen concentration in the first work function layer 94, coupled with increased density, reduced grain size, and changed crystalline morphology, can improve the subsequently deposited bottom anti-reflective coating (e.g. Fig.17 The bottom anti-reflection coating 96 (described later) shown in FIG. 1 is an adhesive layer between the bottom anti-reflection coating 96 and the first work function layer 94. Specifically, the contact angle between the bottom anti-reflection coating 96 and the first work function layer 94 after plasma treatment can be about 0 degrees to about 80 degrees (e.g., about 63 degrees), which is different from the contact angle between the bottom anti-reflection coating and the untreated work function layer, such as about 0 degrees. This can limit any peeling of the bottom anti-reflection coating 96 and improve the patterning process accuracy of the first work function layer 94.

[0111] Additionally, reducing the carbon concentration in the first work function layer 94 may increase compositional control over the first work function layer 94, since the carbon concentration in the first work function layer 94 is difficult to control. This may improve device performance and reduce device defects.

[0112] Fig. 16B The ratio of tungsten to tantalum and tungsten to oxygen in the first work function layer 94 changes, which corresponds to the flow rate changes of helium (provided generation species), hydrogen (provided reaction gas), and nitrogen (provided reaction species) provided to the first plasma generating chamber 204 and the second plasma generating chamber 214. Fig. 16BThe y-axis shows the ratio between tungsten and nitrogen (W / N) is 0.65 to 0.8, and the ratio between tungsten and oxygen (W / O) is 0.225 to 0.265, while the x-axis shows the helium flow rate is 0 sccm to 4500 sccm, the hydrogen flow rate is 1000 sccm to 5000 sccm, and the nitrogen flow rate is 0 sccm to 1000 sccm. Fig. 16B As shown, increasing the helium flow rate can reduce the ratio between tungsten and nitrogen, and the ratio between tungsten and oxygen. Increasing the hydrogen flow rate can increase the ratio between tungsten and nitrogen, and the ratio between tungsten and oxygen. Increasing the nitrogen flow rate can reduce the ratio between tungsten and nitrogen, and has little or no effect on the ratio between tungsten and oxygen. The flow rates of helium, hydrogen, and nitrogen can be changed to achieve the desired ratio between tungsten and nitrogen and the ratio between tungsten and oxygen in the first work function layer 94. In various embodiments, the ratio between tungsten and nitrogen is about 0.75, and the ratio between tungsten and oxygen is about 0.24. To achieve the above ratios, the helium flow rate provided to the first plasma generation chamber 204 is about 1000 sccm, the nitrogen flow rate provided to the first plasma generation chamber 204 is about 5000 sccm, and the hydrogen flow rate provided to the second plasma generation chamber 214 is about 4000 sccm.

[0113] exist Fig.17 In the process, a bottom anti-reflective coating 96 and a photoresist layer 98 are deposited on the first work function layer 94. The bottom anti-reflective coating 96 can be directly deposited on the first work function layer 94 by spin coating or the like. Plasma treatment is performed on the first work function layer 94 to increase the contact angle between the bottom anti-reflective coating 96 and the first work function layer 94 to between about 0 degrees and about 80 degrees, such as about 63 degrees. Plasma treatment increases the adhesion between the bottom anti-reflective coating 96 and the first work function layer 94, thereby eliminating the need for an additional intermediate layer (such as a hexamethyldisilazane layer) and reducing costs and process time. Fig.17 As shown, the topmost surface of the bottom anti-reflection coating 96 can be flush. Then, a photoresist layer 98 is formed on the bottom anti-reflection coating 96. The deposition method of the photoresist layer 98 can be a spin coating or a similar method. Fig.17 In the embodiment, the photoresist layer 98 is also patterned to expose the bottom anti-reflective coating layer 96 in the region 50N. The patterning method of the photoresist layer 98 can expose the photoresist layer 98 by a patterned energy source, and develop the photoresist layer 98 to remove the exposed portion or the unexposed portion of the photoresist layer 98.

[0114] exist Fig.18In the embodiment, the photoresist layer 98 is used as a mask, and the bottom anti-reflective coating layer 96 and the first work function layer 94 are etched. In one embodiment, the method for etching the bottom anti-reflective coating layer 96 may adopt a first etching process, which may be an isotropic etching process such as a reactive ion etching process. However, any suitable process (such as a wet etching process) and any suitable reactant may be used. The first work function layer 94 may be etched by a wet etching process, which may include an etchant such as diluted ozonated deionized water, a peroxide-based solution, or the like. Fig.18 As shown, the first work function layer 94 may be etched to expose the gate dielectric layer 92 in the region 50N, and the region 50P may be masked with a photoresist layer 98 and a bottom anti-reflective coating layer 96 .

[0115] exist FIG. 19A to FIG. 19C In the embodiment of the present invention, the photoresist layer 98 and the bottom anti-reflection coating layer 96 are removed to expose the first work function layer 94 in the region 50P. The removal method of the photoresist layer 98 and the bottom anti-reflection coating layer 96 can be any acceptable process, such as an ashing process, a stripping process, or the like. After removing the photoresist layer 98 and the bottom anti-reflection coating layer 96, a rinsing process can be performed on the substrate 50 to remove any residual debris or reactants. The rinsing process can use deionized water or the like.

[0116] Before performing the rinsing process on the substrate 50, a plasma treatment is performed on the first work function layer 94 to reduce defects caused by the rinsing process. For example, increasing the nitrogen concentration of the first work function layer 94 can reduce or avoid the first work function layer 94 from reacting with the rinsing solution (such as deionized water) used in the rinsing process. This can reduce the material loss of the plasma-treated first work function layer 94 caused by the rinsing process, so that the material loss of the first work function layer 94 can be less than or equal to 34%. Therefore, performing plasma treatment can improve the thickness control of the first work function layer 94, improve device performance, and reduce device defects.

[0117] Fig.19B and Fig.19C The cross-sectional views of the region 300 and the region 400 of the region 50P are shown respectively, and the short-channel fin field effect transistor is formed in the region 300, and the long-channel fin field effect transistor is formed in the region 400. The channel length W1 (also regarded as the gate width) in the region 300 can be about 3nm to about 6nm (such as 5nm), and the channel length W2 in the region 400 can be about 100nm to about 300nm (such as about 240nm). In the device of the prior art, during the process of removing the photoresist layer 98 and the bottom anti-reflective coating 96 and the rinsing process, the material removal amount of the first work function layer 94 in the region 300 or the region 400 is relatively large, resulting in a loading effect between the region 300 and the region 400.

[0118] Plasma treatment on the first work function layer 94 can reduce material loss of the first work function layer 94 in the region 300 and the region 400 caused by the process used to remove the photoresist layer 98 and the bottom anti-reflective coating layer 96 and the rinsing process. This can reduce the difference in thickness between the first work function layer 94 in the region 300 and the region 400 to reduce the loading effect. For example, after removing the photoresist layer 98 and the bottom anti-reflective coating layer 96, the thickness of the first work function layer 94 in the region 300 can be about 0.74 nm to about 0.84 nm, such as about 0.79 nm (with a standard deviation of about 0.05 nm); and the thickness of the first work function layer 94 in the region 400 can be about 0.66 nm to about 1.02 nm, such as about 0.84 nm (with a standard deviation of about 0.18 nm). The ratio between the thickness of the first work function layer 94 in the region 300 and the thickness of the first work function layer 94 in the region 400 may be about 0.81 to about 1.10 (e.g., about 1.06). Reducing the loading effect between the region 300 and the region 400 may improve the thickness control of the first work function layer 94, improve device performance, and reduce device defects.

[0119] exist Fig. 20 In the embodiment, the second work function layer 100 is deposited on the gate dielectric layer 92 and the first work function layer 94. The second work function layer 100 may be formed by a deposition process such as atomic layer deposition, chemical vapor deposition, plasma-assisted chemical vapor deposition, physical vapor deposition, sputtering deposition, or a similar process. The second work function layer 100 may include a material mainly composed of aluminum, a material mainly composed of silicon, or a material mainly composed of carbon. In various embodiments, the second work function layer 100 may include an n-type work function metal. Examples of materials used for the second work function layer 100 may include titanium, silver, tantalum aluminum, tantalum aluminum carbide, titanium aluminum, titanium aluminum nitride, titanium aluminum carbide, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, manganese, zirconium, aluminum carbide, aluminum carbonitride, aluminum nitride, other suitable n-type work function materials, or combinations thereof. The thickness of the second work function layer 100 may be about 1000 Å. to about For example, about The second work function layer 100 may or may not be patterned. In the embodiment where the second work function layer 100 is patterned, the second work function layer 100 may be patterned using a process that is the same as or similar to the process used to pattern the first work function layer 94 . Figures 14 to 20 The deposition and patterning techniques shown can be used to form any pattern and any number of work function layers in any number of areas, depending on the desired electrical performance. Fig. 20The structure shown is only one embodiment of a combination of a deposited and selectively etched gate dielectric layer and a work function layer, and other arrangements are possible. Depositing and patterning the work function layer according to the above embodiments can form a multi-threshold voltage gate, which can be used in electronic components such as transistors. Including a multi-threshold voltage gate can optimize speed, delay, and power in semiconductor devices.

[0120] exist FIG. 21A to FIG. 21C In the embodiment, the gate 102 is formed on the first work function layer 94 and the second work function layer 100 used for the replacement gate. Fig. 21B Display area 50N, and Fig. 21C Display area 50P. The gate 102 is deposited on the first work function layer 94 and the second work function layer 100 and fills the rest of the recess 90. The gate 102 may include a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, a combination of the above, or a multilayer thereof. After the material of the gate 102 is filled into the recess 90, a planarization process such as chemical mechanical polishing may be performed to remove the gate dielectric layer 92, the first work function layer 94, the second work function layer 100, and the excess portion of the gate 102 on the upper surface of the first interlayer dielectric layer 88. Therefore, the gate 102, the first work function layer 94, the second work function layer 100, and the retained portion of the gate dielectric layer 92 may form a replacement gate of the final fin field effect transistor. The gate 102, the first work function layer 94, the second work function layer 100, and the gate dielectric layer 92 may be collectively regarded as a "gate stack". The gate and gate stack may extend along the sidewalls of the channel region 58 of the fin 52 .

[0121] The gate 102 in the region 50N and the region 50P may be formed simultaneously, so that the composition of the gate 102 in each region is the same material. In some embodiments, the gate 102 in the region 50N and the region 50P may be formed by a separate process, so that the gate 102 in the region 50N and the region 50P may be different materials. When a separate process is used, a variety of masking steps may be used to mask and expose appropriate areas.

[0122] FIG. 22A to FIG. 23B The structure in the display area 50N. FIG. 22A to FIG. 23B The structure shown can be applied to the region 50N and the region 50P. As described above, the difference between the region 50N and the region 50P is the second work function layer 100 present in the region 50P.

[0123] exist Fig.22A and Fig. 22BIn some embodiments, the second interlayer dielectric layer 106 is deposited on the first interlayer dielectric layer 88. In some embodiments, the second interlayer dielectric layer 106 is a flowable film formed by a flowable chemical vapor deposition method. In some embodiments, the second interlayer dielectric layer 106 is composed of a dielectric material such as phosphosilicate glass, borosilicate glass, borophosphosilicate glass, undoped silicate glass, or the like, and its deposition method can be any suitable method such as chemical vapor deposition, plasma-assisted chemical vapor deposition, or the like. In some embodiments, before forming the second interlayer dielectric layer 106, the gate stack (including the gate dielectric layer 92 and the corresponding upper gate 102) is recessed, so that the recess is directly formed on the gate stack and between the two side portions of the gate sealing spacer 80, such as Fig.22A and Fig. 22B The gate mask 104 includes one or more layers of dielectric material such as silicon nitride, silicon oxynitride, or the like, which may be planarized after being filled into the recess to remove the excess portion of the dielectric material extending above the first interlayer dielectric layer 88. The gate contact 108 (eg, Fig.23A and Fig. 23B The following content shown below) passes through the gate mask 104 to contact the upper surface of the recessed gate 102.

[0124] like Fig.23A and Fig. 23B In some embodiments shown, the gate contact 108 and the source / drain contact 110 extend through the second interlayer dielectric layer 106 and the first interlayer dielectric layer 88. The openings for the source / drain contacts 110 may extend through the second interlayer dielectric layer 106 and the first interlayer dielectric layer 88, while the openings for the gate contact 108 extend through the second interlayer dielectric layer 106 and the gate mask 104. The openings may be formed using acceptable photolithography and etching techniques. A liner layer (such as a diffusion barrier layer, an adhesion layer, or the like) and a conductive material are formed in the openings. The liner layer may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process such as chemical mechanical polishing may be performed to remove excess material from the surface of the second interlayer dielectric layer 106. The remaining liner layer and conductive material may form source / drain contacts 110 and gate contacts 108 in the openings. An annealing process may be performed to form silicide at the interface between the epitaxial source / drain regions 82 and the source / drain contacts 110. The source / drain contacts 110 are physically and electrically coupled to the epitaxial source / drain regions 82, and the gate contacts 108 are physically and electrically coupled to the gate 102. The source / drain contacts 110 and the gate contacts 108 may be formed by different processes or the same process. Although Fig. 23BThe source / drain contacts 110 and the gate contacts 108 are shown formed in the same cross-section, but it should be understood that the source / drain contacts 110 and the gate contacts 108 can each be formed in different cross-sections to avoid shorting of the contacts.

[0125] Forming a semiconductor device according to the above method, including a method of exposing the first work function layer 94 to a plasma treatment, can increase the density of the first work function layer 94, reduce the grain size in the first work function layer 94, reduce the carbon concentration in the first work function layer 94, increase the nitrogen and tungsten concentrations in the first work function layer 94, reduce the ratio between tungsten and nitrogen in the first work function layer 94, and improve the adhesion of the bottom anti-reflective coating 96 to the first work function layer 94. This can improve the patterning process accuracy of the first work function layer 94, reduce defects in the semiconductor device, increase the yield of the semiconductor device, and improve the performance of the semiconductor device. In addition, depositing and patterning the work function layer according to the above embodiment can form a multi-threshold voltage gate, which can be used in electronic components such as transistors. Including a multi-threshold voltage gate can optimize speed, delay, and power in a semiconductor device.

[0126] In one embodiment, a method for forming a semiconductor device includes forming a semiconductor fin extending from a substrate; depositing a dielectric layer on the semiconductor fin; depositing a first work function layer on the dielectric layer; and exposing the first work function layer to a metastable plasma of a first reactant gas, a metastable plasma of a generated gas, and a metastable plasma of a second reactant gas, wherein the first reactant gas is different from the second reactant gas. In one embodiment, the method further includes depositing a bottom anti-reflective coating to physically contact the first work function layer after exposing the first work function layer to the metastable plasma. In one embodiment, the method further includes depositing a photoresist layer on the bottom anti-reflective coating; patterning the photoresist layer to form a patterned photoresist layer; using the patterned photoresist layer as a mask and etching the bottom anti-reflective coating to expose the first work function layer; using the bottom anti-reflective coating as a mask, etching the first work function layer to expose the dielectric layer; removing the bottom anti-reflective coating and the patterned photoresist layer; and forming a second work function layer on the dielectric layer and the first work function layer. In one embodiment, the step of etching the first work function layer uses an etchant containing ammonia. In one embodiment, the second work function layer comprises silicon, carbon, or aluminum. In one embodiment, the step of depositing the first work function layer comprises depositing a tungsten carbonitride material. In one embodiment, the method further comprises generating a first metastable plasma from a first reactant gas and a generated gas; and after generating the first metastable plasma, generating a second metastable plasma from the first metastable plasma and a second reactant gas. In one embodiment, the first reactant gas comprises nitrogen, the generated gas comprises helium, and the second reactant gas comprises hydrogen.

[0127] In another embodiment, a method for forming a semiconductor device includes generating a first plasma from a first precursor gas, wherein the first precursor gas includes helium; separating a plurality of metastable species in the first plasma from a plurality of charged species in the first plasma; mixing the metastable species with a second precursor gas, wherein the second precursor gas includes hydrogen, wherein the step of mixing the first plasma with the second precursor gas generates a second plasma; and exposing a work function layer on a substrate to the second plasma. In one embodiment, the first precursor gas further includes nitrogen, wherein the nitrogen gas in the first precursor gas has a flow rate of 1000 sccm to 9000 sccm, the helium gas in the first precursor gas has a flow rate of 1000 sccm to 9000 sccm, and the hydrogen gas in the second precursor has a flow rate of 1000 sccm to 4500 sccm. In one embodiment, the step of generating the first plasma is performed in a plasma generating chamber, wherein the temperature is 100° C. to 300° C., the pressure is 1 Torr to 2 Torr, and the RF power is 1000 W to 3000 W. In one embodiment, the step of separating a plurality of metastable species in the first plasma from a plurality of charged species in the first plasma is performed at least in part using a showerhead with a metastable activated radical band. In one embodiment, the step of mixing the metastable species with a second precursor gas is performed in a plasma generating chamber located between the showerhead and the substrate, wherein the metastable species flows through a plurality of first openings in the showerhead, and the second precursor gas flows through a plurality of second openings in the showerhead, and the first openings are separated from the second openings. In one embodiment, before exposing the work function layer to the second plasma, the work function layer includes tungsten carbonitride, and the step of exposing the work function layer to the second plasma reduces the concentration of carbon atoms in the work function layer to less than 0.1%. In one embodiment, the step of exposing the work function layer to the second plasma increases the density of the work function layer to at least 10.8 g / cm 3 .

[0128] In another embodiment, a semiconductor device includes a fin extending from a substrate; a dielectric layer located on the fin; a first work function layer located on the dielectric layer, the first work function layer including tungsten, nitrogen, and helium, wherein the carbon atomic concentration of the first work function layer is less than 0.1% and non-zero; a second work function layer located on the dielectric layer and the first work function layer, the second work function layer in the first region contacts the dielectric layer, and the second work function layer in the second region contacts the first work function layer; and a gate located on the first work function layer and the second work function layer. In one embodiment, the density of the first work function layer is 9.4 g / cm 3 Up to 12.0g / cm 3 In one embodiment, the second work function layer comprises aluminum, carbon, or silicon. In one embodiment, the ratio between tungsten and nitrogen in the first work function layer is less than 1.20. In one embodiment, the nitrogen atomic concentration of the first work function layer is 9.2% to 15.0%.

[0129] The features of the above embodiments are helpful for those skilled in the art to understand the present invention. Those skilled in the art should understand that the present invention can be used as a basis to design and change other processes and structures to achieve the same purpose and / or the same advantages of the above embodiments. Those skilled in the art should also understand that these equivalent substitutions do not depart from the concept and scope of the present invention, and can be changed, replaced, or modified without departing from the concept and scope of the present invention.

Claims

1. A method for forming a semiconductor device, comprising: forming a semiconductor fin extending from a substrate; depositing a dielectric layer on the semiconductor fin; depositing a first work function layer on the dielectric layer; and The first work function layer is exposed to a metastable plasma of a first reactant gas, a metastable plasma of a production gas, and a metastable plasma of a second reactant gas, wherein the first reactant gas is different from the second reactant gas. 2 . The method for forming a semiconductor device according to claim 1 , further comprising depositing a bottom anti-reflective coating to physically contact the first work function layer after exposing the first work function layer to the metastable plasma.

3. The method for forming a semiconductor device according to claim 2, further comprising: depositing a photoresist layer on the bottom anti-reflective coating; patterning the photoresist layer to form a patterned photoresist layer; Using the patterned photoresist layer as a mask, and etching the bottom anti-reflective coating to expose the first work function layer; Using the bottom anti-reflective coating as a mask, etching the first work function layer to expose the dielectric layer; removing the bottom anti-reflective coating and the patterned photoresist layer; as well as A second work function layer is formed on the dielectric layer and the first work function layer. 4 . The method for forming a semiconductor device according to claim 3 , wherein the step of etching the first work function layer uses an etchant containing ammonia. 5 . The method for forming a semiconductor device according to claim 3 , wherein the second work function layer comprises silicon, carbon, or aluminum. 6 . The method for forming a semiconductor device according to claim 1 , wherein the step of depositing the first work function layer comprises depositing a tungsten carbonitride material.

7. The method for forming a semiconductor device according to claim 1, further comprising: Generating a first metastable plasma from the first reaction gas and the product gas; as well as After the first metastable plasma is generated, a second metastable plasma is generated from the first metastable plasma and the second reaction gas. 8 . The method for forming a semiconductor device according to claim 7 , wherein the first reaction gas comprises nitrogen, wherein the generated gas comprises helium, and wherein the second reaction gas comprises hydrogen.

9. A method for forming a semiconductor device, comprising: Generating a first plasma from a first precursor gas, wherein the first precursor gas includes helium; separating a plurality of metastable species in the first plasma from a plurality of charged species in the first plasma; mixing the plurality of metastable species with a second precursor gas, wherein the second precursor gas comprises hydrogen, wherein the step of mixing the first plasma and the second precursor gas generates a second plasma; as well as A work function layer on a semiconductor fin extending from a substrate is exposed to the second plasma.

10. The method for forming a semiconductor device as claimed in claim 9, wherein the first precursor gas further comprises nitrogen, wherein the nitrogen gas flow rate in the first precursor gas is 1000 sccm to 9000 sccm, wherein the helium gas flow rate in the first precursor gas is 1000 sccm to 9000 sccm, and wherein the hydrogen gas flow rate in the second precursor gas is 1000 sccm to 4500 sccm.

11. The method for forming a semiconductor device according to claim 9, wherein the step of generating the first plasma is performed in a plasma generating chamber at a temperature of 100°C to 300°C, a pressure of 1 Torr to 2 Torr, and a radio frequency power of 1000W to 3000W.

12. The method of forming a semiconductor device according to claim 9, wherein the step of separating a plurality of metastable species in the first plasma from a plurality of charged species in the first plasma is at least partially performed using a showerhead with a metastable activated radical band.

13. The method of forming a semiconductor device as claimed in claim 12, wherein the step of mixing the plurality of metastable species with the second precursor gas is performed in a plasma generating chamber located between the showerhead and the substrate, wherein the plurality of metastable species flow through a plurality of first openings in the showerhead, and the second precursor gas flows through a plurality of second openings in the showerhead, and the plurality of first openings are separated from the plurality of second openings.

14. The method of forming a semiconductor device as claimed in claim 9, wherein before exposing the work function layer to the second plasma, the work function layer comprises tungsten carbonitride, and the step of exposing the work function layer to the second plasma reduces the carbon atomic concentration in the work function layer to less than 0.1%.

15. The method of forming a semiconductor device according to claim 9, wherein the step of exposing the work function layer to the second plasma increases the density of the work function layer to at least 10.8 g / cm 3 .

16. A semiconductor device comprising: a fin extending from a base plate; a dielectric layer disposed on the fin; a first work function layer, located on the dielectric layer, the first work function layer comprising tungsten, nitrogen, and helium, wherein the carbon atomic concentration of the first work function layer is less than 0.1% and non-zero, wherein the first work function layer is nitrogen saturated, and the ratio of tungsten to nitrogen in the first work function layer is less than 1.20; a second work function layer located on the dielectric layer and the first work function layer, the second work function layer in a first region contacts the dielectric layer, and the second work function layer in a second region contacts the first work function layer; and A gate is located on the first work function layer and the second work function layer.

17. The semiconductor device of claim 16, wherein the density of the first work function layer is 9.4 g / cm 3 Up to 12.0g / cm 3 .

18. The semiconductor device of claim 16, wherein the second work function layer comprises aluminum, carbon, or silicon.

19. The semiconductor device of claim 16, wherein a ratio between tungsten and nitrogen in the first work function layer is about 1.

17.

20. The semiconductor device of claim 16, wherein the nitrogen atomic concentration of the first work function layer is 9.2% to 15.0%.

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