Voltage Converter with Hysteretic Control

Abstract

The present invention provides a voltage converter with hysteresis control. Various embodiments relate to a voltage converter, which includes a control unit configured to operate in a hysteresis control mode. The control unit may be configured to receive a PWM signal, a duty cycle signal, at least one reference voltage, a factor of the output voltage of the voltage converter, and a factor of the input voltage of the voltage converter. The control unit may also be configured to compare at least one reference voltage with a factor of the output voltage and a factor of the input voltage. In addition, the control unit may be configured to generate a first control signal reflecting the PWM signal in response to at least one of the following: a factor of the input voltage is greater than at least one reference voltage, and a factor of the output voltage is greater than at least one reference voltage. The control unit may also be configured to generate a second different control signal including a low logic signal in response to a factor of the input voltage being less than or equal to at least one reference voltage.

Description

Technical Field

[0001] Embodiments described herein relate generally to voltage converters, and more particularly to voltage converters with hysteretic control. Still more particularly, various embodiments relate to voltage converters with hysteretic control for bypass mode transitions. Background Art

[0002] Voltage converters such as switch mode power supplies are widely used in various electronic devices, including computers and other sensitive devices that require a stable and efficient power supply. A switch mode power supply (SMPS) includes a switching device (e.g., a MOSFET) that switches on and off at a high frequency to convert power. The SMPS also includes one or more storage components (e.g., an inductor and / or a capacitor) to supply power (e.g., to a load) when the switching device is in a non-conducting state. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] While the present disclosure concludes with claims that particularly point out and distinctly claim specific embodiments, the various features and advantages of embodiments within the scope of the present disclosure may be more readily ascertained from the following description when read in conjunction with the accompanying drawings, in which:

[0004] Figure 1A showing a graph including a waveform indicative of a voltage converter supply current at a supply voltage;

[0005] Figure 1B showing a graph including a waveform indicative of the efficiency of the voltage converter at a supply voltage;

[0006] Figure 2 is a block diagram of a voltage converter according to various embodiments of the present disclosure;

[0007] Figure 3 is a simplified block diagram of a voltage converter according to various embodiments of the present disclosure;

[0008] Figure 4 shows a control unit according to various embodiments of the present disclosure;

[0009] Figure 5 is a block diagram of a power module including a voltage converter according to one or more embodiments of the present disclosure;

[0010] Figure 6 shows a graph including a waveform indicating a voltage converter supply current at a supply voltage according to one or more embodiments of the present disclosure;

[0011] Fig. 7A shows a graph depicting various parameters of a voltage converter transitioning to a bypass mode according to one or more embodiments of the present disclosure;

[0012] Figure 7B shows a graph depicting various parameters of a voltage converter transitioning out of bypass mode according to one or more embodiments of the present disclosure; and

[0013] Figure 8 is a flow chart of an exemplary method of operating a voltage converter according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0014] Various embodiments disclosed herein relate to a control unit, and to a voltage converter including a control unit. In at least some embodiments, the control unit may be configured to increase the efficiency of the voltage converter during a bypass transition, such as a transition from an operating mode (e.g., a pulse frequency modulation (PFM) mode) to a bypass mode, or from a bypass mode to another operating mode (e.g., a PFM mode). More specifically, various embodiments relate to operating the voltage converter in a hysteresis control mode when the voltage converter transitions from the PFM mode to the bypass mode. In other words, various embodiments relate to a voltage converter configured to transition from the PFM mode to the bypass mode by a hysteresis control mode, or to transition from the bypass mode to the PFM mode by a hysteresis control mode.

[0015] In the following detailed description, reference is made to the accompanying drawings which form a part of the present disclosure, and in the accompanying drawings, specific examples of embodiments in which the present disclosure may be implemented are shown by way of example. These embodiments are described in sufficient detail to enable one of ordinary skill in the art to practice the present disclosure. However, other embodiments may be utilized, and changes in structure, material, and method may be made without departing from the scope of the present disclosure.

[0016] The illustrations presented herein are not intended to be actual views of any particular method, system, device, or structure, but are merely idealized representations for describing embodiments of the present disclosure. The drawings presented herein are not necessarily drawn to scale. For the convenience of the reader, similar structures or components in the various drawings may retain the same or similar numbering; however, the similarity of numbering does not mean that the structures or components must be identical in size, composition, configuration, or any other characteristics.

[0017] The following description may include examples to help those skilled in the art practice the embodiments disclosed in the present invention. The use of the terms "exemplary", "by way of example" and "for example" means that the relevant description is illustrative, and although the scope of the present disclosure is intended to cover examples and legal equivalents, the use of such terms is not intended to limit the scope of the embodiments or the present disclosure to the specified components, steps, features or functions, etc.

[0018] It should be readily understood that the components of the embodiments as generally described herein and shown in the accompanying drawings may be arranged and designed in a variety of different configurations. Therefore, the following description of various embodiments is not intended to limit the scope of the present disclosure, but is merely representative of various embodiments. Although various aspects of the embodiments may be presented in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise indicated.

[0019] In addition, the specific embodiments shown and described are examples only and should not be construed as the only way to implement the present disclosure, unless otherwise specified herein. Elements, circuits, and functions can be shown in block diagram form so as not to obscure the present disclosure with unnecessary details. On the contrary, the specific embodiments shown and described are exemplary only and should not be construed as the only way to implement the present disclosure, unless otherwise specified herein. In addition, the partitioning of logic between block definitions and individual blocks is an example of a specific embodiment. It will be apparent to those of ordinary skill in the art that the present disclosure can be practiced through many other partitioning solutions. In most cases, details about timing considerations, etc. have been omitted, where such details are not required to obtain a complete understanding of the present disclosure and are within the capabilities of those of ordinary skill in the relevant art.

[0020] Those of ordinary skill in the art will appreciate that any of a variety of different technologies and techniques may be used to represent information and signals. For example, data, instructions, commands, information, signals, bits, and symbols that may be referenced throughout this specification may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof. For clarity of presentation and description, some of the accompanying drawings may show signals as single signals. Those of ordinary skill in the art will appreciate that a signal may represent a signal bus, where the bus may have a variety of bit widths, and the present disclosure may be implemented on any number of data signals, including a single data signal.

[0021] The various exemplary logic blocks, modules, and circuits described in conjunction with the embodiments disclosed herein may be implemented or implemented with a general purpose processor, a special purpose processor, a digital signal processor (DSP), an integrated circuit (IC), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic component, a discrete hardware component, or any combination thereof designed to implement the functions described herein. A general purpose processor (which may also be referred to herein as a host processor or simply a host) may be a microprocessor, but in an alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration. A general purpose computer including a processor is considered a special purpose computer when the general purpose computer is configured to execute computing instructions (e.g., software code) associated with the embodiments disclosed herein.

[0022] Embodiment can be described according to the process that is depicted as flow chart, flow diagram, structure diagram or block diagram.Although flow chart can describe operation action as sequential process, many of these actions can be performed in another sequence, in parallel or substantially simultaneously.In addition, the order of action can be rearranged.Process can correspond to method, thread, function, procedure, subroutine or subprogram without limitation.In addition, the method disclosed herein can be realized by hardware, software or both.If realized in software, these functions can be stored or transmitted to computer readable medium as one or more instructions or codes.Computer readable medium includes both computer storage medium and communication medium, and this communication medium includes any medium that is conducive to transferring computer program from one location to another location.

[0023] Unless such limitations are explicitly stated, any reference to elements herein using names such as "first," "second," etc. does not limit the number or order of those elements. Instead, these names may be used herein as a convenient method of distinguishing between two or more elements or instances of elements. Thus, reference to a first element and a second element does not mean that only two elements can be employed there, or that the first element must precede the second element in some manner. Furthermore, unless otherwise indicated, a group of elements may include one or more elements.

[0024] As used herein, the term "substantially" in reference to a given parameter, characteristic, or condition refers to and includes the degree to which a person of ordinary skill in the art would understand that a given parameter, characteristic, or condition is met with a small degree of variance, such as, for example, within acceptable manufacturing tolerances. By way of example, depending on the specific parameter, characteristic, or condition that is substantially met, the parameter, characteristic, or condition may be met by at least 90%, at least 95%, or even at least 99%.

[0025] As will be appreciated by those of ordinary skill in the art, a voltage converter (e.g., a buck converter) may operate in a continuous conduction mode (CCM) using pulse width modulation (PWM) during heavy load conditions. Additionally, during light load conditions, the voltage converter may operate in a discontinuous conduction mode (DCM). The efficiency under light load conditions in a voltage converter (e.g., a switch mode power supply (SMPS)) is typically improved by using a pulse frequency modulation (PFM) mode rather than a more standard pulse width modulation (PWM) mode by the SMPS controller. PWM can provide enhanced output voltage regulation, whereas PFM can provide greater efficiency under light current loads. Unfortunately, a side effect of PFM is a larger output ripple voltage that may reduce voltage output accuracy. When power conversion is not required and / or desired, the voltage converter may operate in a bypass mode, in which the input power is directly coupled to the output of the voltage converter.

[0026] As will be appreciated, in some voltage converters, when approaching bypass mode (e.g., from PFM mode), the voltage ramp (e.g., Vramp) may be clamped by pulses synchronized with the oscillator, and through such synchronous modulation, the switching activity may increase the quiescent current (IQ) of the voltage converter and reduce light load efficiency performance. In addition, in some conventional voltage converters, in order to generate a constant output voltage, when approaching bypass mode (e.g., from PFM mode) and / or after transitioning out of bypass mode (e.g., entering PFM mode), the switching activity may be undesirably increased.

[0027] As described more fully herein, according to various embodiments of the present disclosure, a hysteresis control mode (HCM) can be used to extend the duty time of the voltage converter when the voltage converter is transitioning toward the bypass mode and / or after the voltage converter is transitioned out of the bypass mode. More specifically, according to various embodiments, if the voltage converter is operated in the PFM mode, the HCM can be activated (i.e., the voltage converter can be transitioned from the PFM mode to the HCM) in response to a trigger (e.g., the supply voltage of the voltage converter is reduced to a value less than or equal to a threshold voltage). In the HCM, instead of transmitting a pulse width modulation (PWM) signal to the pulse generator (i.e., as would occur when the voltage converter is operated in the PFM mode), a static signal (e.g., a static low signal or a static high signal) is transmitted to the pulse generator to prevent the high-side transistor from switching. In addition, according to some embodiments, after transitioning to the HCM mode, and in response to another trigger (e.g., the output voltage of the voltage converter increases to a value equal to or greater than another threshold voltage), the HCM can be deactivated (i.e., the voltage converter can be transitioned from the HCM to the PFM mode). As described above, in HCM, rather than delivering a PWM signal to the pulse generator (ie, as would occur when the voltage converter is operated in PFM mode), a static signal is delivered to the pulse generator to prevent the high-side transistor from switching.

[0028] Thus, the HCM transmits a static signal to the pulse generator and thereby extends the “duty” time and prevents undesired switching of the high-side transistor, compared to a conventional voltage converter that may exhibit increased switching activity when approaching a bypass mode (i.e., when the voltage converter approaches a bypass mode). Additionally, the HCM transmits a static signal to the pulse generator and thereby extends the “duty” time and prevents undesired switching of the high-side transistor, compared to a conventional voltage converter that may exhibit increased switching activity after transitioning out of a bypass mode (e.g., entering a PFM mode).

[0029] For example, Figure 1A A graph 100 is shown, which includes a waveform 101 indicating a supply current at a supply voltage (also referred to herein as an "input voltage") of a conventional voltage converter. In addition, Figure 1B A graph 110 is shown that includes a waveform 111 indicating the efficiency of a conventional voltage converter at a supply voltage. At a supply voltage around about 3.3 volts (i.e., where the desired output voltage is approximately the same as the supply voltage), the supply current increases (e.g., Figure 1A 102 in the figure), so that the efficiency of the voltage converter is reduced (as indicated by Figure 1B 112 in the figure).

[0030] As described above, various embodiments disclosed herein can improve the efficiency of a voltage converter by reducing current consumption. More specifically, various embodiments can increase the efficiency of a voltage converter during a bypass transition, such as a transition from an operating mode (e.g., a pulse frequency modulation (PFM) mode) to a bypass mode, or from a bypass mode to another operating mode (e.g., a PFM mode).

[0031] Figure 2 is a block diagram illustrating a voltage converter 200 according to various embodiments of the present disclosure. The voltage converter 200 (which may also be referred to herein as a "switch mode power supply" (SMPS)) includes an adaptive duty cycle controller power driver 202, a power inductor 206, a load filter capacitor 208, and a voltage source 210 for providing an input voltage VIN. The voltage converter 200 is configured to generate an output voltage VOUT.

[0032] The adaptive duty cycle controller power driver 202 includes: a pulse generator 212, a duty generator 214, an oscillator 216, a slope compensation and period clamp circuit 218, a voltage comparator 220 (e.g., with hysteresis), an operational transconductance amplifier 222, and a voltage reference generator (e.g., a digital-to-analog converter (DAC)) 224 (e.g., to generate a reference voltage VREF). The adaptive duty cycle controller power driver 202 also includes: a dead time control circuit 226, a zero current detector 228, a high-side transistor driver 230, a low-side transistor driver 232, a high-side power transistor 234, a low-side power transistor 236, a high-side current sensor 238 (e.g., for sensing a high-side current) and a low-side current sensor 240 (e.g., for sensing a low-side current). For example, the power transistors 234 and 236 may include metal oxide semiconductor field effect transistors (MOSFETs), P-channel and N-channel, respectively. The high-side current value ISEN_hs may be supplied to the slope compensation and cycle clamp circuit 218 , and the low-side current value ISEN_ls may be supplied to the zero current detector 228 .

[0033] Dead time control circuit 226 is configured to prevent current breakdown in power transistors 234 and 236 , and zero current detector 228 is configured to determine when substantially no current flows through power inductor 206 (i.e., by monitoring a signal from low side current sensor 240 (e.g., low side current value ISEN_ls)).

[0034] The pulse generator 212 includes a flip-flop 250 and NAND gates 252 and 254. The duty generator 214 includes a timer 242 configured to receive an input voltage VIN, a reference voltage VREF, and a zero current (ZC) signal from a zero current detector 228.

[0035] As described more fully below, the voltage converter 200 includes a control loop for transitioning into and out of the bypass mode (i.e., wherein the transistor 234 is continuously turned on and a 100% duty cycle is achieved). More specifically, for example, the duty generator 214 is configured to receive an input voltage VIN and a reference voltage VREF. In addition, in some embodiments, the timer 242 can determine a target output voltage based on the reference voltage VREF. In other embodiments, the target output voltage can be provided to the timer 214. As will be understood by those of ordinary skill in the art, based on the input voltage VIN and the target output voltage, the timer 242 can generate a control signal TON synchronized with the oscillator 216. The control signal TON can include an "on time" determined based on the operating state of the voltage converter 200 (i.e., the input voltage VIN and the target output voltage). More specifically, as will be understood, the control signal TON can be asserted based on the current through the inductor 206. In addition, the duty generator 214 (and more specifically the timer 242) can estimate the required pulse width of the control signal TON depending on the ratio of the target output voltage to the input voltage VIN (e.g., determined via the reference voltage VREF). In one embodiment (not shown), the ratio of the instantaneous output voltage VOUT to the input voltage VIN can be monitored by the duty generator 214, and the estimation of the required pulse width of the control signal TON can be responsive thereto. The bypass mode is asserted by the duty generator 214 when the fixed control signal TON is high, and is deasserted by the duty generator 214 when the control signal TON begins to change again in an attempt to turn off the high-side switch 234.

[0036] The flip-flop 250 is configured to receive the supply voltage VDD at its D input, the control signal TON at its clock input, and the output of the NAND gate 252 at the reset input, and generate a duty cycle signal Qduty for controlling the duty cycle of the voltage converter 200. In response to the control signal TON turning to a logic high, the duty cycle signal Qduty will turn to high. The duty cycle signal Qduty can be coupled to the gate of the high-side power transistor 234 (i.e., via the dead time control 226 and the high-side driver 230), and the duty cycle signal Qduty can cause the transistor 234 to turn on when it is high, thereby coupling the voltage source 210 to the first end of the inductor 206. As will be understood, the duty cycle signal Qduty can turn to high in response to the rising edge of the control signal TON, and the duty cycle signal Qduty can be reset in response to the control signal TON turning to a low and the high control signal 280 received via the NAND gate 252.

[0037] The output voltage VOUT appearing at the second end of the inductor 206 and across the load filter capacitor 208 is coupled via a voltage divider to an operational transconductance amplifier 222, which is configured to provide a voltage VCOMP representing the output voltage VOUT divided by the voltage divider minus a reference voltage VREF. It should be noted that at DC, the output resistance of the transconductance amplifier 222 can sink the signal current, thereby generating a voltage VCOMP representing the error signal at the input of the transconductance amplifier 222. It should be noted that it is common to implement the error amplifier (e.g., in analog power conversion circuits) via a transconductance (i.e., current source) stage due to benefits, for example, in terms of noise sensitivity and / or stability with capacitive loads.

[0038] As will be appreciated, slope compensation and period clamp circuit 218 is configured to generate a voltage VRAMP (eg, having a sawtooth waveform), and comparator 220 generates a pulse width modulation (PWM) signal PWM based on a comparison of voltage VRAMP with voltage VCOMP.

[0039] The operation of the pulse generator 212, the duty generator 214, the slope compensation and cycle clamp circuit 218, the dead time control circuit 226, and the zero current detector 228 is known in the art, and some specific details about these components may not be discussed in more detail below. By way of example only, U.S. Patent Publication No. US2019 / 0081546 discloses a voltage converter including a pulse generator, a duty generator, a slope compensation and cycle clamp circuit, a dead time control circuit, and a zero current detector. The entirety of patent publication No. US2019 / 0081546 assigned to the assignee of the present disclosure is incorporated herein by reference.

[0040] In addition, according to various embodiments, the adaptive duty cycle controller power driver 202 includes a control unit 260. Figure 3 and 4 The control unit 260 described more fully is configured to receive the signal PWM (e.g., from the comparator 220) and generate a control signal 280. The control signal 280 can be transmitted to the pulse generator 212. According to some embodiments, the control unit 260 can also be configured to receive one or more reference voltages VREF (e.g., including voltage reference VREF1 and / or voltage reference VREF2 (see Figure 4)), a selected factor βOUT of the output voltage VOUT, and a selected factor αVIN of the input voltage VIN. As will be described more fully below, the control unit 260 can enable a hysteresis control mode (HCM), wherein, as described above and as described more fully below, a static signal can be transmitted to the pulse generator 212 (i.e., instead of a PWM signal) to extend the duty time and reduce the amount of switching during the bypass transition (e.g., when the voltage converter 200 transitions toward the bypass mode and / or after the voltage converter 200 transitions out of the bypass mode). Therefore, the efficiency of the voltage converter 200 can be improved.

[0041] It should be noted that although the control unit 260 Figure 2 2 is shown as being integrated in a specific buck converter (i.e., voltage converter 200), but the control unit 260 may be compatible with other voltage converters and / or other voltage converter control topologies. For example, the control unit 260 may be implemented by any suitable voltage converter, wherein the control unit 260 is configured to receive the PWM signal and other operating parameters (e.g., one or more voltages, such as an input voltage, an output voltage, and / or one or more reference voltages), and generate a control signal that may be transmitted to another component of the voltage converter (such as a pulse generator). For example, the reference Figure 3 According to various embodiments of the present disclosure, the voltage converter 300 includes a control unit 260. Figure 3 As shown, the control unit 260 is configured to receive the pulse width modulation signal PWM and the duty cycle signal Qduty, and generate a control signal 280, which can be transmitted to another component 302 of the voltage converter (such as a pulse generator). According to various embodiments, the control unit 260 can also be configured to receive one or more reference voltages (e.g., Figure 4 ), a voltage αVIN (eg, a selected factor of the input voltage of the voltage converter), and a voltage βOUT (eg, a selected factor of the output voltage of the voltage converter).

[0042] Figure 4 is a more detailed illustration of the control unit 260 according to various embodiments of the present disclosure. As shown, the control unit 260 includes a comparator 402 and a comparator 404. For example, each of the comparator 402 and the comparator 404 may include a low quiescent current (IQ) comparator, and in some embodiments, one or more of the comparator 402 and the comparator 404 may be implemented via a Schmitt trigger comparator.

[0043] As will be appreciated, comparator 404 monitors a signal representing input voltage VIN that changes slowly (i.e., changes at a low frequency), but may have some small high frequency noise superimposed thereon. Therefore, for comparator 404, chattering may be prevented via hysteresis. For a fixed alpha ratio and reference voltage VREF2, the amount of hysteresis of comparator 404 may determine a certain level of input voltage level VIN at which the HCM will be disabled (i.e., with increasing VIN) after enabling the HCM (i.e., with decreasing VIN).

[0044] Additionally, no hysteresis may be required for comparator 402 since the switching of comparator 402 will be latched by flip-flop 408. However, the minimum amount of hysteresis used to extend the low pulse generated by inverter 406 may be beneficial and may not affect circuit operation (e.g., because it will take a long time before another switching event of comparator 402 is generated).

[0045] The comparator 402 is configured to receive a voltage βOUT (ie, a factor β of the output voltage VOUT (eg, see Figure 2 )), and receives a first reference voltage VREF1 at its inverting input, and the comparator 404 is configured to receive a voltage αVIN (ie, a factor α of the input voltage VIN (eg, see Figure 2 )) and receives a second reference voltage VREF2 at its non-inverting input. According to some embodiments, the first voltage reference VREF1 can be equal to the second voltage reference VREF2 (e.g., the inverting input of comparator 402 and the non-inverting input of comparator 404 can be tied to a single reference voltage), such as in Figure 2 In the example shown in FIG. 4 , a single voltage reference VREF is used, and in other embodiments, the first voltage reference VREF1 and the second voltage reference VREF2 may not be equal (i.e., comparators 402 and 404 are configured to receive different reference voltages). In addition, in some embodiments, the first voltage reference VREF1 and / or the second voltage reference VREF2 may be equal to the reference voltage VREF, such as Figure 2 shown.

[0046] The control unit 260 also includes an inverter 406 coupled to the output of the comparator 402, and a circuit 408 (e.g., also referred to herein as a flip-flop) coupled to the output of the comparator 404. For example, the circuit 408 may include a gated SR flip-flop. In other embodiments, a non-gated SR flip-flop may be provided for the circuit 408. The comparator 402 is configured to transmit the signal RST_Qext to the inverter 406, and the inverter 406 is configured to transmit a signal (e.g., a reset signal) to the flip-flop 408. In addition to receiving signals from the inverter 406, the flip-flop 408 is also configured to receive the signal HCM_EN from the output of the comparator 404 at its set input and receive the duty cycle signal Qduty at its clock input. The flip-flop 408 is configured to generate outputs Qext and QextB, which are inverted signals of each other.

[0047] In addition, the control unit 260 includes an inverter 410 coupled to the output of the flip-flop 408 and configured to receive the output Qext. The control unit 260 also includes an AND gate 412 having an input coupled to the output of the inverter 410 and configured to receive the PWM signal (e.g., from Figure 2 According to some embodiments, AND gate 412 can generate control signal 280, which can be transmitted to, for example, a pulse generator (e.g., Figure 2 In some embodiments, the inverter 410 and the AND gate 412 may be collectively referred to herein as a circuit.

[0048] As will be described more fully herein, in HCM, control signal 280 may be a control signal (e.g., a first control signal) having a static value (e.g., a low logic value), and in another mode (e.g., PFM mode), control signal 280 may be a control signal (e.g., a second, different control signal) that reflects a PWM signal.

[0049] It should be noted that the control unit 260 is provided as an exemplary control unit, and other possible configurations are also within the scope of the present disclosure. For example, the input of the comparator 402 can be reversed, and the inverter 406 can be removed. In addition, as another example, the AND gate 412 can be replaced by one or more other logic gates (e.g., a NAND gate and / or a NOR gate). In another example, the inverter 410 can be removed and the signal QextB can be coupled to the AND gate 412. In yet another example, the flip-flop 408 may not be necessary, and the output Qext can be determined based on the outputs of the comparators 402 and 404 and a lookup table (LUT).

[0050] In some embodiments, the reference voltage VREF1 may be equal to an upper output voltage threshold (also referred to herein as an "activation voltage" or "transition voltage"). For example, for a target output voltage of 3.3 volts, the upper output voltage threshold may be approximately 3.414 volts (103.45% of 3.3 volts). In addition, the lower output voltage threshold may include a voltage equal to or close to a value of the target output voltage (also referred to herein as a "normal nominal output voltage"), such as 3.3 volts. In addition, in some embodiments, the second reference voltage VREF2 may be equal to an input voltage threshold (also referred to herein as an "activation voltage" or "transition voltage"). For an example with a target output voltage of 3.3 volts, the input voltage threshold (i.e., the second reference voltage VREF2) may be approximately 3.6 volts (e.g., 109.09% of 3.3 volts). In this example, if the voltage VIN is greater than the input voltage threshold, the PFM mode may be used (i.e., the control signal 280 reflects a PWM signal), and if the voltage VIN decreases to or below the input voltage threshold, the HCM may be used (i.e., the control signal 280 is a static (e.g., low) value).

[0051] More specifically, for example, the HCM may be activated in response to the voltage αVIN becoming equal to or falling below a first activation voltage (i.e., an input voltage threshold), thereby setting the signal HCM_EN to high. When HCM_EN is high, at the next rising edge of Qduty, the output Qext will be high, thereby setting the control signal 280 to low, regardless of the signal PWM. Using the next rising edge of Qduty to clock the flip-flop 408 ensures synchronous operation, however, if synchronous operation is not required, the HCM may be asynchronously activated in response to the voltage αVIN becoming equal to or falling below the first activation voltage. If the voltage βOUT increases to above a second activation voltage (i.e., an upper output voltage threshold (e.g., 3.414 volts)), the duty cycle signal Qduty may be reset. More specifically, if the voltage βOUT increases above the second activation voltage, the flip-flop 408 will be reset, and since the reset input is not clocked, the output Qext will turn low, so that the AND gate 412 passes the received signal PWM to the control signal 280, and in response to the signal PWM turning high, the flip-flop 250 can be reset (see Figure 2 If the output voltage VOUT (see Figure 2 ) does not increase above the second activation voltage, typically because VIN is not high enough under the current load conditions to achieve this, the flip-flop 408 is not reset, and the voltage converter 200, 300 keeps the high switch 234 turned on regardless of the Figure 2The state of the control signal TON generated by the timer 242 is determined by the state of the control signal TON. When VIN drops so that the duty generator 214 provides a 100% duty cycle, that is, TON is set to a fixed high signal, the bypass mode has been entered from the HCM mode.

[0052] More specifically, refer to Figure 2 and Figure 4 , during the expected operation, if the voltage αVIN is greater than the second reference voltage VREF2, the voltage converter 200 may operate in the PFM mode. In addition, in response to the voltage αVIN becoming equal to or less than the second reference voltage VREF2 (the "first activation voltage"), the voltage converter 200 may transition from the PFM mode to the HCM mode (i.e., the signal HCM_EN may be asserted and the output Qext may transition to high at the next rising edge of the signal Qduty, and the output of the inverter 410 may be low, so that the control signal 280 is a static value). In addition, in response to the "duty request" (i.e., via the timer 242), the control signal TON may transition to high and the signal Qduty may transition to high (i.e., until the flip-flop 250 is reset by the PWM signal transmitted via the control unit 260).

[0053] Therefore, VIN drops below the input voltage threshold VREF2, enabling HCM mode. If VIN is sufficient, under the current load condition, in order to support VOUT greater than the output voltage threshold upper limit VREF2, when VOUT has risen to greater than the output voltage threshold upper limit VREF2, the voltage converter 200, 300 will return to PFM mode. Unless VIN has risen above the input voltage threshold VREF2, this cycle will be repeated on each rising edge of Qduty. If VIN is not sufficient, under the current load condition, in order to support VOUT greater than the output voltage threshold upper limit VREF2, in HCM mode, the voltage converter 200, 300 is maintained with the high-side switch high until VIN drops so that the duty generator 214 provides a 100% duty cycle, that is, TON is set to a fixed high signal, and has entered the bypass mode from the HCM mode. In bypass mode and HCM, the high-side switch 234 is continuously turned on and achieves a 100% duty cycle. In other words, when operating in HCM, if the output voltage VOUT does not recover to be higher than the output voltage upper threshold VREF1, the flip-flops 408 and 250 will not be reset, so that the high-side transistor 234 will remain turned on (i.e., in the on state). In addition, in response to the input voltage VIN increasing to a level sufficient to support the output voltage VOUT to be greater than the output voltage upper threshold VREF1 (e.g., 103.45% of the target output voltage), based on the control signal TON and the signal RST_Qext, the voltage converter 200 can be converted from the bypass mode to the PFM.

[0054] Therefore, in response to the voltage βOUT becoming equal to or greater than the first reference voltage VREF1 (“second activation voltage”), the voltage converter can transition from the HCM or bypass mode to the PFM mode. More specifically, in response to the voltage βOUT becoming equal to or greater than the first reference voltage VREF1, the signal RST_Qext can transition to high, the flip-flop 408 can be reset, and thus the output Qext can transition to low at the next rising edge of the signal Qduty, which will allow the AND gate 412 to pass the signal PWM, so that the control signal 280 can include (i.e., reflect) the signal PWM, and the duty cycle signal Qduty can be reset.

[0055] refer to Figure 2 and Figure 4 , the intended operation of the voltage converter 200 and more specifically the control unit 260 will now be described. In this example, the output voltage lower threshold ("target output voltage") is equal to 3.3 volts, the reference voltage VREF1 is equal to β*3.414 volts, and the reference voltage VREF2 is equal to α*3.6 volts.

[0056] In this example, if the voltage αVIN is greater than α*3.6 volts, the signal HCM_EN is low, and therefore the output Qext is low, the control signal 280 may include (i.e., reflect) the signal PWM, and the voltage converter 200 operates in PFM mode. Additionally, if the voltage αVIN becomes less than or equal to α*3.6 volts, the signal HCM_EN may transition to high, the output Qext may transition to high, the control signal 280 will be low, and the voltage converter 200 may operate in HCM. It should be noted that during HCM, the high-side transistor 234 is turned on (i.e., based on the control signal TON going high, which sets Qduty high to clock the flip-flop 408), and the control signal 280 is a static value (i.e., the signal PWM is not transmitted to Figure 2 Thus, during HCM (eg, when voltage converter 200 transitions toward bypass mode), the “duty” time may continue and current consumption may be reduced due to the reduction in switching activity.

[0057] In addition, in response to the output voltage VOUT becoming less than 3.3 volts (e.g., due to a decrease in the input voltage VIN and / or an increase in the load), based on the high control signal TON, the voltage converter 200 can transition from HCM to bypass mode, wherein the high-side transistor 234 will be turned on (i.e., in an on state), however, it should be noted that the high-side transistor 234 is already turned on due to the HCM mode. Therefore, HCM can be considered an extended bypass mode.

[0058] Continuing with this example, in an embodiment in which VOUT is further provided to a timer 242, in response to the output voltage VOUT increasing to or greater than 3.3 volts, based on a logic low control signal TON (e.g., based on a signal generated via the timer 242), the voltage converter 200 can be transitioned from the bypass mode to the HCM. In this example, because the trigger 408 is not reset, the output Qext is still high, since Qduty has not yet been transformed, the control signal 280 is still low, the trigger 250 is not reset, and therefore the high-side transistor 234 can remain turned on. Therefore, during the HCM period (i.e., after the voltage converter 200 transitions out of the bypass mode and transitions toward the PFM mode), the current consumption can be reduced due to the lack of switching activity. In summary, during the HCM transition from the bypass mode, the controller 200, 300 is used to extend the bypass mode by utilizing the HCM.

[0059] In addition, in response to voltage βOUT becoming greater than β*3.414, signal RST_Qext can transition high, flip-flop 408 can be reset, output Qext can go low, and thus control signal 280 will include (i.e., reflect) signal PWM. In addition, flip-flop 250 can be reset, and voltage converter 200 can transition from HCM to PFM mode. It should be noted that in Figure 2 In the configuration shown (eg, a buck converter), the output voltage VOUT may not be greater than the input voltage VIN, and thus the signal RST_Qext may not transition high when the signal HCM_EN is high.

[0060] The above has been described in an embodiment in which the control unit 260 is separate from the duty generator 214. In another embodiment, the control unit 260 is integrated into the duty generator 214. In this embodiment, the HCM mode and the bypass mode are not defined separately. The operation of the comparators 402 and 404, the flip-flop 408, the inverter 410 and the AND gate 412 can be implemented in the duty generator 214, or can be set as an essential part of the logic of the duty generator 214.

[0061] As will be appreciated, HCM, which may be suitable for light loads, may increase efficiency during bypass transitions. However, in some cases, HCM may slightly increase output voltage ripple. Thus, an end user may wish to consider the tradeoffs of HCM, and according to some embodiments, the voltage converter may be enabled for operation in HCM by the end user (e.g., via register bits and / or I 2 C bus—control not shown). For example, Figure 5 FIG. 5 shows a power module 500 including a voltage converter 502 according to various embodiments of the present disclosure. The voltage converter 502 may include Figure 2The voltage converter 200 shown or Figure 3 According to some embodiments, the power module 500 may include a control unit (e.g., Figure 2 For example, the power module 500 can be connected to one or more inputs of the control unit 260 via the bus 504 (e.g., I 2 C bus) receives one or more inputs (eg, to set one or more bits) for causing a control unit (eg, Figure 2 The control unit 260) is capable of operating in HCM as described herein.

[0062] In addition, according to various embodiments, a control unit (e.g., Figure 4 The threshold voltage of the control unit 260) can be settable, and therefore, the activation and / or transition points (also referred to herein as activation and / or transition voltages) of the control unit can be programmable. The programmable activation point can provide a predictable input-output differential, which can prevent rapid inductor current accumulation and reduce sensitivity to regulation comparator delays. In at least these embodiments, the end user can consider application-level trade-offs (e.g., efficiency versus performance) to determine whether HCM is desired, and if so, what settings are desired.

[0063] Figure 6 A graph 600 including a waveform indicating a supply current at a supply voltage of a voltage converter according to one or more embodiments of the present disclosure is shown. More specifically, the graph 600 includes a waveform 602 of a supply current at a supply voltage of a voltage converter that does not utilize an HCM. In addition, the graph 600 includes a waveform 604 of a supply current at a supply voltage of a voltage converter that utilizes an HCM (e.g., voltage converter 200). As shown in the graph 600, a voltage converter that utilizes an HCM (e.g., during a bypass transition) can exhibit significant improvements in efficiency compared to a voltage converter that does not utilize an HCM.

[0064] Fig. 7A A graph 700 depicting various parameters of a voltage converter transitioning into and out of HCM is shown. More specifically, graph 700 includes a graph indicating input voltage (e.g., Figure 2 , and a waveform 702 indicating an input voltage VIN, and an output voltage (eg, Figure 2 As shown in graph 700, as the input voltage decreases (e.g., from 3.8V to 3.3V), the voltage converter transitions from PFM mode, through HCM, and then to bypass mode, where the high-side transistor (e.g., Figure 2The transistor 234) is continuously turned on.

[0065] Figure 7B Another graph 710 depicting various parameters of a voltage converter transitioning into and out of HCM is shown. More specifically, graph 710 includes an indication of input voltage (e.g., Figure 2 The waveform 712 of the input voltage VIN) and the output voltage (eg, Figure 2 As shown in graph 710, as the input voltage increases (eg, from 3.3V to 3.8V), the voltage converter transitions from bypass mode, through HCM, and then to PFM mode.

[0066] Figure 8 is a flow chart of an exemplary method 800 of operating a voltage converter according to various embodiments of the present disclosure. In some embodiments, the method 800 may be performed by a device or system, such as Figure 2 The voltage converter 200, Figure 2 , Figure 3 and Figure 4 The control unit 260, Figure 3 The voltage converter 300, and / or Figure 5 Although shown as discrete blocks, various blocks may be divided into additional blocks, combined into fewer blocks, or eliminated, depending on the desired implementation.

[0067] At block 802, one or more signals may be received at a control unit of a voltage converter, and method 800 may proceed to block 804. For example, one or more signals may be received at a control unit (e.g., Figure 4 The control unit 260 receives at least one of the following: a PWM signal (eg, Figure 4 signal PWM), duty cycle signal (for example, Figure 4 A duty cycle signal Qduty), at least one reference voltage (eg, Figure 2 The first reference voltage VREF1 and / or the second reference voltage VREF2), the output voltage of the voltage converter (eg, Figure 2 The output voltage VOUT) factor (for example, Figure 4 OUT), and / or the input voltage of the voltage converter (e.g., Figure 2 The input voltage VIN) factor (for example, Figure 4 voltage αVIN).

[0068] At block 804, at least one reference voltage may be compared to a factor of the output voltage and a factor of the input voltage, and the method 800 may proceed to block 806. More specifically, for example, a first comparator (e.g., Figure 4 The comparator 402 of FIG. 4 may compare a first reference voltage (eg, reference voltage VREF1) with the voltage βOUT, and a second comparator (eg, Figure 4 The comparator 404 may compare a second reference voltage (eg, reference voltage VREF2) with the voltage αVIN.

[0069] At block 806, a first control signal reflecting the PWM signal may be generated in response to at least one of the following: a factor of the input voltage being greater than at least one reference voltage, and a factor of the output voltage being greater than at least one reference voltage, and the method 800 may proceed to block 808. More specifically, for example, the first control signal may be generated in response to at least one of the following: the voltage αVIN being greater than a second reference voltage (e.g., the second reference voltage VREF2), and the voltage βOUT being greater than a first reference voltage (e.g., the first reference voltage VREF1). For example, Figure 4 The AND gate 412 may generate a control signal 280 reflecting the PWM signal in response to the PWM signal and the high signal generated by the inverter 410 .

[0070] At block 808, a second different control signal including a static signal, which in one embodiment is a low logic signal, may be generated in response to a factor of the input voltage being less than or equal to at least one reference voltage. More specifically, for example, the second different control signal may be generated in response to the voltage αVIN being less than or equal to a second reference voltage (e.g., the second reference voltage VREF2) and the voltage βOUT being less than or equal to the first reference voltage (e.g., the first reference voltage VREF1). For example, Figure 4 AND gate 412 may generate control signal 280 in a static low state in response to the low signal generated by inverter 410 .

[0071] Modifications, additions, or omissions may be made to method 800 without departing from the scope of the present disclosure. For example, the operations of method 800 may be implemented in a different order. Furthermore, the operations and actions outlined are provided only as examples, and some of the operations and actions may be optional, combined into fewer operations and actions, or expanded into additional operations and actions without departing from the essence of the disclosed embodiments. For example, a control signal (e.g., Figure 4 The control signal 280 of may be transmitted to another component within the voltage converter, such as a pulse generator (e.g., Figure 2In addition, for example, a duty cycle signal (e.g., duty cycle signal Qduty) may be generated based on one of the first control signal and the second control signal (e.g., via the pulse generator). In addition, the duty cycle of the voltage converter may be set based on the generated duty cycle signal. As another example, the duty cycle of the voltage converter may be set based on the bus (e.g., Figure 5 One or more signals received by the bus 504) to activate and / or program the control unit.

[0072] Those of ordinary skill in the art will recognize that the various embodiments of the present disclosure have many advantages, including but not limited to reducing switching in voltage converters. Therefore, various embodiments can reduce quiescent current and improve the performance of voltage converters, which can lead to extended battery life of related devices. In addition, those of ordinary skill in the art will recognize that the described embodiments can be applicable to various voltage converters (e.g., buck converters, boost converters, buck-boost converters, etc.). In addition, various embodiments can be particularly used for but not limited to portable applications, such as applications in mobile devices or the Internet of Things (IoT), which may require robust, efficient and cost-effective regulators. In addition, various embodiments can be used for high-performance voltage regulators, such as required by various microcontrollers or microprocessor cores. The voltage converter including various embodiments disclosed herein can show high conversion efficiency and / or high output voltage accuracy, such as desired by portable devices, microcontrollers and / or microprocessor cores.

[0073] As used in the present disclosure, the term "module" or "component" may refer to a specific hardware implementation that is configured to perform the actions of a module or component and / or software object or software routine that may be stored on and / or executed by general-purpose hardware of a computing system (e.g., a computer-readable medium, a processing device, without limitation). In some embodiments, the different components, modules, engines, and services described in the present disclosure may be implemented as objects or processes executed on a computing system (e.g., as separate threads). Although some of the systems and methods described in the present disclosure are generally described as being implemented in software (stored on and / or executed by general-purpose hardware), specific hardware implementations or combinations of software and specific hardware implementations are possible and contemplated.

[0074] The terms used in this disclosure, especially in the appended claims (e.g., the bodies of the appended claims), are generally intended to be “open” terms (e.g., the term “including” should be interpreted as “including but not limited to,” the term “having” should be interpreted as “having at least,” the term “comprising” should be interpreted as “including but not limited to,” etc.).

[0075] Additionally, if a specific number of an introduced claim recitation is intended, such intent will be expressly recited in the claim, and in the absence of such recitation, no such intent is present. For example, as an aid to understanding, the following appended claims may contain the use of the introductory phrases "at least one" and "one or more" to introduce claim recitations. However, the use of such phrases should not be construed to imply that a claim recitation introduced by the indefinite article "a" or "an" will limit any particular claim containing such introduced claim recitation to an embodiment containing only one such recitation, even when the same claim includes the introductory phrases "one or more" or "at least one" and an indefinite article, such as "a" or "an" (e.g., "a" and / or "an" may be interpreted to mean "at least one" or "one or more"); the same is true of the use of definite articles used to introduce claim recitations.

[0076] Furthermore, even if a particular number of an introduced claim recitation is explicitly recited, one skilled in the art will recognize that such recitation should be interpreted to mean at least the recited number (e.g., the basic recitation of "two recitations" in the absence of other modifiers means at least two recitations or two or more recitations). Furthermore, in those cases where a convention similar to "at least one of A, B, and C, etc." or "one or more of A, B, and C, etc." is used, such construction is generally intended to include only A, only B, only C, both A and B, both A and C, both B and C, or all three of A, B, and C, etc.

[0077] In addition, any discrete word or phrase presenting two or more additional terms, whether in the specification, claims or drawings, should be understood to include the possibility of one of the terms, either of the two terms, or both of the two terms. For example, the phrase "A or B" should be understood to include the possibility of "A" or "B" or "A and B".

[0078] Although the present invention is described herein in conjunction with certain illustrated embodiments, those of ordinary skill in the art will recognize and appreciate that the present invention is not so limited. Rather, many additions, deletions, and modifications may be made to the illustrated embodiments and the described embodiments without departing from the scope of the present invention as claimed below and its legal equivalents. Furthermore, features from one embodiment may be combined with features of another embodiment while still being included within the scope of the present invention as contemplated by the inventor.

Claims

1. A voltage converter, comprising: A control unit, the control unit comprising: a first comparator configured to receive at least one reference voltage and a factor of the output voltage of the voltage converter and generate a first signal; a second comparator configured to receive the at least one reference voltage and a factor of the input voltage of the voltage converter and generate a second signal; a circuit configured to receive the first signal, the second signal, and a duty cycle signal and generate a third signal; and a logic gate configured to receive a pulse width modulation (PWM) signal and the third signal and generate a control signal; and a pulse generator configured to receive the control signal and generate the duty cycle signal based on the control signal, Wherein the control signal comprises a static logic signal in response to: the factor of the input voltage being less than or equal to the at least one reference voltage, and the factor of the output voltage being less than or equal to the at least one reference voltage.

2. The voltage converter of claim 1 , wherein the control signal reflects the PWM signal in response to at least one of: the factor of the input voltage being greater than the at least one reference voltage, and the factor of the output voltage being greater than the at least one reference voltage. 3 . The voltage converter of claim 1 , wherein the control signal reflects the PWM signal in response to the factor of the output voltage being greater than the at least one reference voltage. 4 . The voltage converter of claim 1 , wherein the control signal reflects the PWM signal during a pulse frequency modulation (PFM) mode. 5 . The voltage converter of claim 1 , wherein the control signal comprises the static logic signal during a bypass mode and a hysteretic control mode. 6 . The voltage converter of claim 1 , wherein the at least one reference voltage comprises a first reference voltage and a second different reference voltage, wherein the first comparator is configured to receive the first reference voltage and the second comparator is configured to receive the second different reference voltage.

7. A voltage converter, comprising: A control unit, the control unit being configured to: receiving a pulse width modulation (PWM) signal, a duty cycle signal, at least one reference voltage, a factor of an output voltage of the voltage converter, and a factor of an input voltage of the voltage converter; comparing the at least one reference voltage to each of the factor of the output voltage and the factor of the input voltage; A first control signal reflecting the PWM signal is generated in response to at least one of: The factor of the input voltage is greater than the at least one reference voltage, and the factor of the output voltage is greater than the at least one reference voltage; as well as A second different control signal is generated as a static logic signal in response to the factor of the input voltage being less than or equal to the at least one reference voltage.

8. The voltage converter according to claim 7, wherein the control unit comprises: a first comparator configured to receive the at least one reference voltage and the factor of the output voltage; a second comparator configured to receive the at least one reference voltage and the factor of the input voltage; a first inverter having an input configured to receive an output of the first comparator; a flip-flop having a first input configured to receive the output of the second comparator, a second input configured to receive the output of the first inverter, and a third input configured to receive the duty cycle signal; a second inverter configured to receive an output of the flip-flop; and An AND gate having a first input configured to receive the PWM signal and a second input configured to receive an output of the second inverter.

9. The voltage converter according to claim 7, wherein the control unit comprises: a first comparator configured to receive the at least one reference voltage and the factor of the output voltage and generate a first signal; a first inverter configured to receive the first signal and generate a second signal; a second comparator configured to receive the at least one reference voltage and the factor of the input voltage and generate a third signal; a trigger configured to receive the second signal, the third signal, and the duty cycle signal and generate a fourth signal; a second inverter configured to receive the fourth signal and generate a fifth signal; and An AND gate is configured to receive the PWM signal and the fifth signal and generate a control signal. 10 . The voltage converter of claim 7 , further comprising a pulse generator configured to generate the duty cycle signal based on one of the first control signal and the second different control signal.

11. The voltage converter of claim 10, wherein the pulse generator comprises: a first NAND gate, wherein the first NAND gate is configured to receive the duty cycle signal and a third control signal; a second NAND gate configured to receive an output of the first NAND gate and one of the first control signal and the second different control signal; and a second flip-flop configured to receive the output of the second NAND gate and generate the duty cycle signal. 12 . The voltage converter of claim 7 , wherein the at least one reference voltage comprises a first reference voltage and a second reference voltage. 13 . The voltage converter according to claim 12 , wherein the control unit is configured to compare the first reference voltage with the factor of the output voltage, and to compare the second reference voltage with the factor of the input voltage.

14. A method of operating a voltage converter, comprising: receiving, at a control unit of a voltage converter, a pulse width modulation (PWM) signal, a duty cycle signal, at least one reference voltage, a factor of an output voltage of the voltage converter, and a factor of an input voltage of the voltage converter; comparing, via the control unit, the at least one reference voltage with each of the factor of the output voltage and the factor of the input voltage; generating, via the control unit, a first control signal reflecting the PWM signal in response to at least one of: the factor of the input voltage being greater than the at least one reference voltage, and the factor of the output voltage being greater than the at least one reference voltage; as well as A second different control signal is generated via the control unit as a static logic signal in response to the factor of the input voltage being less than or equal to the at least one reference voltage and the factor of the output voltage being less than or equal to the at least one reference voltage. 15 . The method of claim 14 , further comprising generating the duty cycle signal based on one of the first control signal and the second different control signal.

16. The method of claim 14, further comprising transmitting one of the first control signal and the second different control signal to a pulse generator.

17. The method of claim 14, further comprising enabling the control unit based on a signal received via a bus.

18. The method of claim 14, wherein generating the first control signal comprises: receiving the PWM signal and a logic high signal at an AND gate; And the first control signal is output from the AND gate.

19. The method of claim 14, wherein generating the second different control signal comprises: receiving the PWM signal and a logic low signal at an AND gate; And the second different control signal is outputted from the AND gate.

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