Through-Silicon Via Inspection Circuit with Copy Path

Abstract

This application relates to a TSV inspection circuit having a replication path. Disclosed herein is a device comprising: a first semiconductor chip; a first TSV and a second TSV that penetrate the first semiconductor chip; a first path including the first TSV; a second path including the second TSV; a first charging circuit configured to charge the first path; a second charging circuit configured to charge the second path; a first discharging circuit configured to discharge the first path; a second discharging circuit configured to discharge the second path; and a comparator circuit configured to compare the potential of the first path with the potential of the second path.

Description

Technical Field

[0001] This application relates to memory devices, and more particularly to a TSV inspection circuit with a replication path for use in a memory device. Background Art

[0002] A semiconductor chip for use in a memory device (such as HBM (High Bandwidth Memory)) includes a plurality of TSVs (Through-Silicon Vias), each TSV being arranged to penetrate a semiconductor substrate in some cases. The TSVs provided in each semiconductor chip are connected via micro-bumps to the TSVs provided at the same planar position in another semiconductor chip, so that a signal path penetrating multiple semiconductor substrates is formed. If a particular TSV has a conduction failure or the connection portion between two TSVs has a connection failure, the corresponding signal path becomes defective and is practically unusable. In this case, a spare signal path is used to replace the faulty signal path, so that the failure can be recovered. The inspection of each signal path and the replacement using the spare signal path can be performed not only in the manufacturing stage but also during actual use (i.e., in the initialization cycle after power-on). In the case where the inspection of the signal path is performed during the initialization cycle, the inspection time that can be assigned to each signal path can be extremely short. Therefore, it is not easy to perform a correct inspection for all signal paths. Summary of the Invention

[0003] One aspect of this application is directed to an apparatus, which includes: a first semiconductor chip; a first TSV and a second TSV that penetrate the first semiconductor chip; a first path including the first TSV; a second path including the second TSV; a first charging circuit configured to charge the first path; a second charging circuit configured to charge the second path; a first discharging circuit configured to discharge the first path; a second discharging circuit configured to discharge the second path; and a comparator circuit configured to compare the potential of the first path with the potential of the second path.

[0004] Another aspect of the present application is directed to a device that includes a plurality of first semiconductor chips stacked vertically on top of each other, the plurality of first semiconductor chips including respective first paths and second paths through the plurality of first semiconductor chips; and an interface chip stacked on the plurality of first semiconductor chips such that the interface chip is coupled to each of the first ends of the first path and the second path, the interface chip being configured to control: charging each of the second ends of the first path and the second path with a first voltage; and comparing the potential of the first ends of the first path and the second path after charging each of the second ends of the first path and the second path with the first voltage.

[0005] Another aspect of the present application is directed to a device that includes: a semiconductor chip; a plurality of first TSVs penetrating the semiconductor chip; a second TSV penetrating the semiconductor chip; a first circuit configured to select one of the plurality of first TSVs; a second circuit configured to apply a first potential to the selected one of the first TSVs and the second TSV in response to a first timing signal; a third circuit configured to apply a second potential different from the first potential to the selected one of the first TSVs and the second TSV in response to a second timing signal; and a fourth circuit configured to compare the potential of the selected one of the first TSVs with the potential of the second TSV. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a schematic diagram showing the configuration of a semiconductor device according to the present invention.

[0007] Figure 2 is a schematic plan view showing the layout of a plurality of TSVs.

[0008] Figure 3 is a circuit diagram showing a circuit connected to a TSV in a memory core chip.

[0009] Figure 4 is a circuit diagram showing a circuit connected to a TSV in an interface chip.

[0010] Figure 5 is a circuit diagram showing a first circuit example in which a signal path is inspected.

[0011] Figure 6 and Figure 7 is a timing diagram showing the operation of the circuit shown in Figure 5

[0012] Figure 8 is a circuit diagram showing a second circuit example in which a signal path is inspected.​

[0013] Figure 9 is a circuit diagram showing a third circuit example of the test signal path therein.

[0014] Figure 10 is a circuit diagram showing a fourth circuit example of the test signal path therein. Detailed implementation manners

[0015] Various embodiments of the present invention will be explained in detail below with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings, which illustrate, in a diagrammatic way, specific aspects and embodiments in which the present invention can be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present invention. Other embodiments can be used, and structural, logical, and electrical changes can be made without departing from the scope of the present invention. The various embodiments disclosed herein are not necessarily mutually exclusive, because some of the disclosed embodiments can be combined with one or more other disclosed embodiments to form new embodiments.

[0016] Figure 1The semiconductor device shown has a configured HBM in which eight memory core chips 20 to 27 are stacked on an interface chip 10. However, the semiconductor device to which the present invention is applicable is not limited to HBM. Each of the memory core chips 20 to 27 is a semiconductor chip in which a memory core including a memory cell array is integrated. The interface chip 10 is a semiconductor chip that controls the memory core chips 20 to 27. The interface chip 10 and the memory core chips 20 to 26 each have a plurality of TSVs 30 provided to penetrate the semiconductor substrate. All of the interface chip 10 and the memory core chips 20 to 27 are stacked in a face-down manner (that is, in a manner such that the main surface on which transistors and wiring patterns (both not shown) are formed faces down). Therefore, in the memory core chip 27 located in the uppermost layer, there is no need for TSVs 30. However, the memory core chip 27 located in the uppermost layer may have TSVs 30. Almost all of the TSVs 30 provided in the memory core chips 20 to 26 are respectively connected to the front surface TSV pads 31A located at the same planar position. At the same time, most of the TSVs 30 provided in the interface chip 10 and most of the front surface TSV pads 31A provided on the interface chip 10 are in different planar positions from each other. Among the TSVs 30 provided in the interface chip 10 and the memory core chips 20 to 26, the TSVs 30 located at the same planar position are connected to each other in a cascaded connection manner via the front surface TSV pads 31A, the TSV bumps 31B, and the back surface TSV pads 31C. In this way, a plurality of signal paths 32 are formed. Commands and write data output from the interface chip 10 are supplied to the memory core chips 20 to 27 via the signal paths 32. Read data output from the memory core chips 20 to 27 is supplied to the interface chip 10 via the signal paths 32. External terminals 33 are provided on the interface chip 10, and signal transmission to and signal reception from an external circuit are performed via the external terminals.

[0017] As Figure 2 shown, in each of the interface chip 10 and the memory core chips 20 to 26, the TSVs 30 are arranged in a matrix form. A selection circuit 34 is assigned to each TSV 30. The selection circuit 34 is used in the inspection of the signal paths 32, which is performed during the manufacturing stage and during the initialization period after power-on. As Figure 2As shown, one corresponding one of the selection signal lines Y0, Y1, Y2, Y3, ... is assigned to the TSV 30 arranged in the x direction. One corresponding one of the selection signal lines X0, X1, X2, X3, ... is assigned to the TSV 30 arranged in the y direction. The selection signal lines Y0, Y1, Y2, Y3, ... supply the selection signals Ysel0, Ysel1, Ysel2, Ysel3, ... to the corresponding selection circuits 34 respectively. The selection signal lines X0, X1, X2, X3, ... supply the selection signals Xsel0, Xsel1, Xsel2, Xsel3, ... to the corresponding selection circuits 34 respectively. The selection circuit 12 activates any one of the selection signals Ysel0, Ysel1, Ysel2, Ysel3, ... and deactivates all the remaining signals. The selection circuit 14 activates any one of the selection signals Xsel0, Xsel1, Xsel2, Xsel3, ... and deactivates all the remaining signals. In this way, any one of the selection circuits 34 is activated to select one of the corresponding TSVs 30.

[0018] Each selection circuit 34 included in each of the memory chips 20 to 27 includes a P-channel MOS transistor 41 and a NAND gate circuit 42 that controls the transistor 41, as Figure 3 shown. The NAND gate circuit 42 receives a corresponding one of the selection signals Xsel0, Xsel1, Xsel2, Xsel3, ..., a corresponding one of the selection signals Ysel0, Ysel1, Ysel2, Ysel3, ..., and a selection signal SliceEn (which selects one of the memory core chips 20 to 27 that includes the NAND gate circuit 42), and activates the selection signal XYselF to a low level when all the received signals are at an active level (high level). In each of the memory core chips 20 to 27, a P-channel MOS transistor 43 and the P-channel MOS transistor 41 are connected in series between the power supply VDD and the TSV 30. The test signal TESTF is supplied to the gate electrode of the transistor 43. Therefore, when both the test signal TESTF and the selection signal XYselF are activated to a low level, the TSV 30 is connected to the power supply VDD. For example, the power supply VDD is a high-potential side power supply. In this case, when both the test signal TESTF and the selection signal XYselF are activated, the signal path 32 is charged via the TSV 30.

[0019] The selection circuit 34 included in the interface chip 10 has the same circuit configuration as the selection circuit 34 included in the memory core chips 20 to 27, as Figure 4As shown in. In the interface chip 10, the transistor 41 and the N-channel MOS transistor 47 are connected in series between the TSV 30 and the power supply VSS. The test clock signal CLK is supplied to the gate electrode of the transistor 47. Therefore, when the test clock signal CLK is activated to a high level and the selection signal XYselF is activated to a low level, the TSV 30 is connected to the power supply VSS. For example, the power supply VSS is a low-potential side power supply. In this case, when both the test clock signal CLK and the selection signal XYselF are activated, the signal path 32 is discharged via the TSV 30.

[0020] As Figure 3 and 4 shown in, the output buffer 45 and the input receiver 46 are connected in parallel between the internal circuit 44 and the TSV 30 included in each of the interface chip 10 and the memory core chips 20 to 27. Therefore, the data, commands, etc. output from the internal circuit 44 are supplied to the signal path 32 via the output buffer 45 and the TSV 30. In addition, the data, commands, etc. supplied from the signal path 32 are input to the internal circuit 44 via the TSV 30 and the input receiver 46.

[0021] As Figure 5 shown in, a plurality of signal paths 32 include a copy path 32R. The copy path 32R is used as a reference in the inspection of other signal paths 32 and has the same configuration as the signal path 32, except that the transistor 48 for receiving the enable signal EnF is used to replace the transistor 41 and a dummy resistor Rd is inserted in series. The enable signal EnF is always activated during the test period. The parasitic capacitance C1 added to each signal path 32 and the parasitic capacitance C2 added to the copy path 32R are designed to have substantially the same value. Each signal path 32 is connected to the node N1 via the transistor 41 provided on the interface chip 10, and the copy path 32R is connected to the node N2 via the transistor 48 provided on the interface chip 10. The interface chip 10 includes a comparator circuit 49 that compares the level at the node N1 with the level at the node N2 in response to the comparison signal COMP.

[0022] Refer to Figure 6 and 7 to describe Figure 5 the operation of the circuit shown in. Figure 6 shows the waveforms in the case where there is no fault in each signal path 32, and Figure 7 shows the waveforms in the case where there is a fault in a part of the signal path 32. First, in the case where any one of the selection signals Xsel0, Xsel1, Xsel2, Xsel3,... (in Figure 6and 7 In the example shown in, the selection signal Xsel0) is activated to a high level state, and the selection signals Ysel0, Ysel1, Ysel2, Ysel3,... are sequentially activated to a high level. Therefore, the TSVs 30 arranged in a matrix form as shown in Figure 2 are sequentially selected, and the corresponding one in the signal path 32 is charged via the selected TSV 30. It is sufficient to perform the charging of the signal path 32 in any one of the memory core chips 20 to 27, and charging in other memory core chips is not required. Preferably, the charging of each signal path 32 is performed in the memory core chip 27 in the uppermost layer. By charging each signal path 32 in the memory core chip 27 in the uppermost layer, all the TSVs 30 included in the signal path 32 can be tested. At the same time, in the case where there is a fault in the signal path 32, by charging each signal path 32 in any one of the memory core chips 20 to 26 that are not in the uppermost layer, it is possible to specify which one of the memory core chips 20 to 26 contains the defective TSV 30. In the case of charging each signal path 32 in the memory core chip 27 in the uppermost layer, it is sufficient to activate the selection signal SliceEn corresponding to the memory core chip 27 in the uppermost layer to a high level and deactivate the selection signals SliceEn corresponding to the other memory core chips 20 to 26 to a low level. Similarly for the interface chip 10, the corresponding selection signal SliceEn is activated to a high level. The replication path 32R is also charged by activating the enable signal EnF for the memory core chip 27 in the uppermost layer and the interface chip 10.

[0023] such as Figure 6 and 7As shown, one cycle of the test clock signal CLK coincides with the active periods of the selection signals Ysel0, Ysel1, Ysel2, Ysel3, …. Thus, during the first half of the cycle (during which one of the selection signal paths 32 is selected), the transistor 47 is turned on, and thus discharges the selected signal path 32 and the replica path 32R and places the nodes N1 and N2 at the VSS level. At the same time, during the second half of the cycle (during which one of the selection signal paths 32 is selected), the transistor 47 is turned off, and thus the discharge of the selected signal path 32 and the replica path 32R stops. When the discharge of the selected signal path 32 and the replica path 32R stops, the selected signal path 32 and the replica path 32R are charged via the transistors 41 and 48, respectively, such that the levels at the nodes N1 and N2 rise. At this time, the rising rate of the level at the node N1 is determined by the resistance value of the signal path 32 and the parasitic capacitance C1. In addition, the rising rate of the level at the node N2 is determined by the resistance value of the replica path 32R and the parasitic capacitance C2. Although the parasitic capacitance C2 of the replica path 32R is substantially the same as the parasitic capacitance C1 of the signal path 32 as described above, unless the signal path 32 has a fault, the charging rate of the replica path 32R is lower than the charging rate of the signal path 32 because the dummy resistor Rd is inserted in series into the replica path 32R. Figure 6 The waveforms in the case where each signal path 32 does not have a fault are shown, and the level at the node N1 rises faster than the level at the node N2. The comparison signal COMP is activated at the timing after the test clock signal CLK is changed from high level to low level and before the test clock signal CLK is changed to high level again. When the comparison signal COMP is activated, the comparator circuit 49 performs an operation of comparing the level at the node N1 with the level at the node N2 with each other, and when the level at the node N1 is higher, places the output signal OUT of the comparator circuit at the high level. This means that the signal path 32 does not have a fault, and the fault signal FAIL remains inactive.

[0024] At the same time, Figure 7Displays waveforms in a case where the signal paths 32 corresponding to the selection signals Xsel0 and Ysel2 have faults. When there is a fault in the signal path 32, the resistance value of the signal path is high and the charging rate of the signal path 32 decreases. Due to the fault in the signal path 32, the following situation can be considered: due to the fault in the connection part via the TSV bump 31B, the resistance of the TSV 30 itself becomes high and the resistance of the signal path 32 becomes high. If the resistance value of the signal path 32 is higher than the resistance value of the copy path 32R, the level at the node N1 rises more slowly than the level at the node N2. In this case, when the comparison signal COMP is activated, the comparator circuit 49 sets its output signal OUT to a low level. This means that the signal path 32 has a fault, and the fault signal FAIL is activated. When the fault signal FAIL is activated, the corresponding signal path 32 is deactivated and replaced with a spare signal path.

[0025] As a method for checking the signal path 32, a method can also be considered in which instead of using the copy path 32R as a reference, a constant reference voltage is used. That is, a method of connecting one of the input terminals of the comparator circuit 49 to the node N1 and applying a constant reference voltage to the other input terminal of the comparator circuit 49 is considered. However, in this method, the determination result of the pass or fail can be changed by the frequency of the test clock signal CLK. For example, in a case where the actual frequency of the test clock signal CLK is higher than the designed value, the charging time of the signal path 32 is shorter than expected, and thus a defect-free signal path 32 can be determined to be defective. On the contrary, in a case where the actual frequency of the test clock signal CLK is lower than the designed value, the charging time of the signal path 32 is longer than expected, and thus a defective signal path 32 is determined to be defect-free. In addition, the off-leak current from the output buffer 45 also flows into the signal path 32. Therefore, when the charging time of the signal path 32 becomes longer than expected, the risk of determining a defective signal path 32 to be defect-free increases, and even a completely disconnected signal path 32 can be determined to be defect-free. On the contrary, the semiconductor device according to the embodiment of the present invention uses the copy path 32R as a reference. Therefore, even if the actual frequency of the test clock signal CLK is different from the designed actual frequency, this difference evenly affects the signal path 32 and the copy path 32R. In addition, the off-leak current from the output buffer 45 also evenly affects the signal path 32 and the copy path 32R. Therefore, correct inspection can be performed for each signal path 32. In addition, since correct inspection can be performed even when the frequency of the test clock signal CLK is designed to be high, it is possible to complete the inspection of several signal paths 32 with a sufficient margin during the initialization period after power-on (even in a case where the inspection is performed during the initialization period).

[0026] In addition, a plurality of dummy resistors Rd0 to Rd2 connected in parallel can be inserted into the replication path 32R, as shown in Figure 8 . By further inserting transistors 50 to 52 in series into the corresponding dummy resistors Rd0 to Rd2 and by turning on one or both or more than two of the transistors 50 to 52 using one or both or more than two of the selection signals S0 to S2, it is possible to change the resistance value of the replication path 32R. Therefore, it is possible to switch the resistance value in which the signal path 32 is determined to be defective by the selection signals S0 to S2. In this case, preferably, the resistance values of the dummy resistors Rd0 to Rd2 are different from each other.

[0027] In addition, as shown in Figure 9 , in each of the memory core chips 20 to 26 and the interface chip 10, two TSVs 30 can be used to configure the replication path 32R while the two TSVs 30 are connected in parallel. With this configuration, even in a case where there is a failure in a part of the TSVs 30 configuring the replication path 32R, the inspection of the signal path 32 can still be correctly performed. In this case, the resistance value of the replication path 32R is slightly reduced due to the parallel connection of the two TSVs 30. However, the total resistance value of the eight TSVs 30 included in the replication path 32R is about 1Ω and is sufficiently low compared to the on-resistance of the transistor 48. Therefore, the reduction in the resistance value of the replication path 32R has almost no influence on the inspection. In addition, three or more of the TSVs 30 can be connected in parallel.

[0028] In addition, a dummy capacitor Cd can be connected to the replication path 32R instead of inserting a dummy resistor Rd into the replication path 32R, as shown in Figure 10 . Also in this case, an operation substantially the same as the operation of the circuit shown in Figure 5 can be performed because the time constant of the replication path 32R is greater than the time constant of the signal path 32.

[0029] While the invention has been disclosed in the context of specific preferred embodiments and examples, those skilled in the art will understand that the invention extends beyond the specifically disclosed embodiments to other alternative embodiments and / or uses of the invention and its obvious modifications and equivalents. Additionally, those skilled in the art will readily appreciate other modifications within the scope of the invention based on the invention. It is also contemplated that various combinations or sub-combinations of the specific features and aspects of the embodiments can be made and still fall within the scope of the invention. It should be understood that the various features and aspects of the disclosed embodiments can be combined with or substituted for one another to form different modes of the disclosed invention. Accordingly, it is intended that the scope of at least some of the invention disclosed herein should not be limited by the specific disclosed embodiments described above.

Claims

1. A device, comprising: A first semiconductor chip; A first TSV and a second TSV that penetrate the first semiconductor chip; A first path that includes the first TSV; A second path that includes the second TSV; A first charging circuit configured to charge the first path; A second charging circuit configured to charge the second path; A first discharging circuit configured to discharge the first path; A second discharging circuit configured to discharge the second path; And A comparator circuit configured to compare the potential of the first path including the first TSV with the potential of the second path including the second TSV.

2. The device according to claim 1, wherein the first charging circuit and the second charging circuit are configured to charge the first path and the second path simultaneously.

3. The device according to claim 1, wherein the first discharging circuit and the second discharging circuit are configured to discharge the first path and the second path simultaneously.

4. The device according to claim 1, further comprising a second semiconductor chip, with the first semiconductor chip stacked on the second semiconductor chip, wherein the first discharging circuit and the second discharging circuit are formed on the second semiconductor chip.

5. The device according to claim 4, wherein the first semiconductor chip is a memory core chip, and wherein the second semiconductor chip is an interface chip.

6. The device according to claim 5, further comprising a third semiconductor chip stacked on the first semiconductor chip and the second semiconductor chip, wherein the first charging circuit and the second charging circuit are formed on the third semiconductor chip.

7. The device according to claim 6, wherein the third semiconductor chip is another memory core chip.

8. The device according to claim 1, wherein the second path includes a dummy resistor circuit connected in series to the second TSV.

9. The device according to claim 8, wherein the dummy resistor circuit includes a plurality of resistor elements connected in parallel.

10. The device according to claim 1, further comprising a third TSV that penetrates the first semiconductor chip, wherein the second path includes the second TSV and the third TSV connected in parallel.

11. A device, comprising A plurality of first semiconductor chips stacked one above the other, the plurality of first semiconductor chips including a first path and a second path respectively passing through the plurality of first semiconductor chips; and An interface chip stacked on the plurality of first semiconductor chips such that the interface chip is coupled to each of the first ends of the first path and the second path, the interface chip being configured to control: Charging each of the second ends of the first path and the second path simultaneously with a first voltage; and After charging each of the second ends of the first path and the second path with the first voltage, the potential of the first end of the first path is compared with that of the first end of the second path.

12. The apparatus according to claim 11, wherein the interface chip is configured to control discharging each of the first ends of the first path and the second path.

13. The apparatus according to claim 12, wherein the interface chip is configured to control discharging each of the first ends of the first path and the second path during a first period and to control charging each of the second ends of the first path and the second path during a second period after the first period.

14. The apparatus according to claim 13, wherein the interface chip is configured to control comparing the potential of the first end of the first path with that of the first end of the second path during the second period.

15. The apparatus according to claim 14, wherein the interface chip is configured to stop discharging each of the first ends of the first path and the second path during the second period.

16. The apparatus according to claim 11, wherein in the absence of a bad connection, the second path has a higher resistance or capacitance than the first path.

17. The apparatus according to claim 16, wherein in the presence of a bad connection, the second path has a lower resistance or capacitance than the first path.

18. The apparatus according to claim 11, further comprising a second semiconductor chip stacked on the plurality of first semiconductor chips such that the plurality of first semiconductor chips are sandwiched between the interface chip and the second semiconductor chip, wherein each of the second ends of the first path and the second path is located at the second semiconductor chip.

19. An apparatus comprising: a semiconductor chip; a plurality of first TSVs penetrating the semiconductor chip; a second TSV penetrating the semiconductor chip; a first circuit configured to select one of the plurality of first TSVs; a second circuit configured to apply a first potential to the selected one of the first TSVs and the second TSV in response to a first timing signal; a third circuit configured to apply a second potential different from the first potential to the selected one of the first TSVs and the second TSV in response to a second timing signal; and a fourth circuit configured to compare the potential of the selected one of the first TSVs with the potential of the second TSV.

20. The apparatus according to claim 19, wherein the plurality of first TSVs are arranged in a matrix form, and wherein the first circuit includes: a plurality of row selection lines, each of which is commonly assigned to two or more of the first TSVs arranged in a row direction; A plurality of column selection lines, each of which is commonly assigned to two or more of the first TSVs arranged in the column direction; A row selection circuit configured to activate one of the row selection lines; and A column selection circuit configured to activate one of the column selection lines.

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