Clock data recovery circuit

Abstract

A clock data recovery circuit is provided. The clock data recovery circuit includes the following components: a phase detector, a charge pump, a first switch, a second switch, a capacitor, a third switch, and a voltage-controlled oscillator. The phase detector outputs a phase adjustment signal by comparing a clock signal for a first node with an input signal. The charge pump adjusts the charge amount of a second node based on the phase adjustment signal. The first switch includes a terminal connected to the second node and another terminal connected to a third node. The second switch includes a terminal receiving a bias voltage and another terminal connected to the third node. The capacitor includes a first electrode connected to the third node. The voltage-controlled oscillator includes a control terminal connected to the third node and an output terminal connected to the first node via the third switch.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0115129, filed with the Korean Intellectual Property Office on September 19, 2019, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The technical field relates to clock data recovery circuits and display devices including clock data recovery circuits. Background Technology

[0004] Display devices help users obtain information and entertainment. Modern display devices include liquid crystal displays, organic light-emitting diode displays, and plasma displays.

[0005] The display device may include a timing controller and at least one driver unit. The timing controller may supply grayscale values ​​to the driver unit. The driver unit may supply data voltages corresponding to the grayscale values ​​to the pixels. The pixels may emit light with a brightness level corresponding to the data voltages, so that the display device can display an image.

[0006] The timing controller can supply grayscale values ​​and other data at various speeds. For example, depending on the implementation and / or product, the data supply speed of the timing controller can range from 1Gbps to 4Gbps. A driver unit is required to generate a clock signal with a frequency corresponding to the data supply speed of the timing controller.

[0007] If the timing controller has a wide range of data supply speeds, the driver unit may take an unexpectedly long time to generate a clock signal with the corresponding frequency. Summary of the Invention

[0008] Implementations may involve a clock data recovery circuit capable of rapidly generating a clock signal having an appropriate frequency corresponding to various data supply rates. Implementations may also involve a display device including a clock data recovery circuit.

[0009] According to an embodiment, the clock data recovery circuit may include the following components: a phase detector, a charge pump, a first switch, a second switch, a capacitor, and a voltage-controlled oscillator. The phase detector is configured to output a phase adjustment signal by comparing a clock signal of the first node with an input signal. The charge pump is configured to adjust the charge amount of the second node according to the phase adjustment signal. The first switch includes a terminal connected to the second node and another terminal connected to the third node. The second switch includes a terminal with an applied bias voltage and another terminal connected to the third node. The capacitor includes a first electrode connected to the third node. The voltage-controlled oscillator includes a control terminal connected to the third node and an output terminal connected to the first node via the third switch.

[0010] The conduction periods of the first and second switches may not overlap, and the conduction period of the third switch may not overlap.

[0011] When one of the third switches is in the ON state, the first switch can be in the ON state, and the second switch can be in the OFF state.

[0012] When all third switches are in the off state, the first switch is in the off state, and the second switch can be in the on state.

[0013] The clock data recovery circuit may also include a fourth switch, wherein the fourth switch includes one terminal connected to the output terminal of the voltage-controlled oscillator having the highest frequency band and the other terminal connected to the first node.

[0014] When the fourth switch is in the ON state, the first switch can be in the OFF state, and the second switch can be in the ON state.

[0015] The clock data recovery circuit may also include a register and a fifth switch, wherein the fifth switch includes one terminal connected to the fourth node of the phase detector and another terminal connected to the register.

[0016] When the fifth switch is in the ON state, the first switch can be in the OFF state, the second switch can be in the ON state, and the fourth switch can be in the ON state.

[0017] The clock data recovery circuit may also include an oscillator controller, wherein the oscillator controller is configured to reference a value stored in a register to turn on one of the third switches and allow the others of the third switches to remain off.

[0018] The clock data recovery circuit may further include a NOR gate and a first flip-flop, wherein the NOR gate is configured to receive a lock signal, a clock training signal and an enable signal, and the first flip-flop is configured to receive the input signal of the NOR gate through its input terminal, receive a synchronization signal through its control terminal and output control signals for the first switch, the second switch, the fourth switch and the fifth switch.

[0019] The synchronization signal can be a signal that is different from the clock signal.

[0020] The oscillator controller can switch the level of the enable signal when one of the third switches is turned on.

[0021] When the level of the lock signal switches from the lock level to the unlock level, the level of the enable signal can be switched.

[0022] The oscillator controller can shut off all third switches when the level of the lock signal switches from the lock level to the unlock level.

[0023] The phase detector may include a second flip-flop, a third flip-flop, and a first XOR gate, wherein the second flip-flop is configured to receive an input signal through its input terminal, receive a clock signal through its control terminal, and includes an output terminal connected to a fourth node; the third flip-flop includes an input terminal connected to the output terminal of the second flip-flop, receives the clock signal through its control terminal, and the first XOR gate includes a first input terminal connected to the fourth node, a second input terminal connected to the output terminal of the third flip-flop, and an output terminal that outputs a portion of the phase adjustment signal.

[0024] The phase detector may further include a fourth flip-flop, a fifth flip-flop, and a second XOR gate, wherein the fourth flip-flop is configured to receive an input signal through its input terminal and to receive an inverted signal of a clock signal through its control terminal, the fifth flip-flop includes an input terminal connected to the output terminal of the fourth flip-flop, the fifth flip-flop receives the clock signal through its control terminal, and the second XOR gate includes a first input terminal connected to the output terminal of the fifth flip-flop, a second input terminal connected to the output terminal of the fourth flip-flop, and an output terminal for the remaining portion of the output phase adjustment signal.

[0025] According to an embodiment, the display device may include the following elements: a pixel connected to a data line and a data driver configured to supply a data voltage to the data line. The data driver includes a clock data recovery circuit, a decoder, and a data voltage generator. The clock data recovery circuit is configured to receive a clock data signal via the clock data line and generate a clock signal using a clock training symbol in the clock data signal. The decoder is configured to decode grayscale values ​​in the clock data signal using the clock signal. The data voltage generator is configured to convert grayscale values ​​into data voltages. The clock data recovery circuit includes a phase detector, a charge pump, a first switch, a second switch, a capacitor, and a voltage-controlled oscillator. The phase detector is configured to output a phase adjustment signal by comparing a clock signal of a first node with an input signal. The charge pump is configured to adjust the charge amount of a second node according to the phase adjustment signal. The first switch includes a terminal connected to the second node and another terminal connected to a third node. The second switch includes a terminal with an applied bias voltage and another terminal connected to the third node. The capacitor includes a first electrode connected to the third node. The voltage-controlled oscillator includes a control terminal connected to the third node and an output terminal connected to the first node via the third switch.

[0026] The clock data recovery circuit may further include a fourth switch, a register, and a fifth switch, wherein the fourth switch includes one terminal connected to the output terminal of the voltage-controlled oscillator having the highest frequency band and the other terminal connected to the first node, and the fifth switch includes one terminal connected to the fourth node of the phase detector and the other terminal connected to the register.

[0027] The clock data recovery circuit may further include an oscillator controller, a NOR gate, and a first flip-flop, wherein the oscillator controller is configured to reference a value stored in a register to turn on one of the third switches and allow the others of the third switches to remain off, the NOR gate is configured to receive a lock signal, a clock training signal, and an enable signal, and the first flip-flop is configured to receive the input signal of the NOR gate through its input terminal, receive a synchronization signal through its control terminal, and output control signals for the first switch, the second switch, the fourth switch, and the fifth switch.

[0028] The phase detector may include a second flip-flop, a third flip-flop, a first XOR gate, a fourth flip-flop, a fifth flip-flop, and a second XOR gate. The second flip-flop is configured to receive an input signal via its input terminal, receive a clock signal via its control terminal, and includes an output terminal connected to a fourth node. The third flip-flop includes an input terminal connected to the output terminal of the second flip-flop and receives the clock signal via its control terminal. The first XOR gate includes a first input terminal connected to the fourth node, a second input terminal connected to the output terminal of the third flip-flop, and an output terminal that outputs a portion of the phase adjustment signal. The fourth flip-flop is configured to receive an input signal via its input terminal and receive an inverted signal of the clock signal via its control terminal. The fifth flip-flop includes an input terminal connected to the output terminal of the fourth flip-flop and receives the clock signal via its control terminal. The second XOR gate includes a first input terminal connected to the output terminal of the fifth flip-flop, a second input terminal connected to the output terminal of the fourth flip-flop, and an output terminal that outputs the remainder of the phase adjustment signal.

[0029] The implementation may involve a clock data recovery circuit. The clock data recovery circuit may include a phase detector, a charge pump, a first switch, a second switch, a capacitor, a voltage-controlled oscillator, and a third switch. The phase detector outputs a phase adjustment signal by comparing a clock signal from the first node with an input signal. The charge pump adjusts the amount of charge in the second node according to the phase adjustment signal. A first terminal of the first switch is electrically connected to the second node. A second terminal of the first switch is electrically connected to the third node even when electrically disconnected from the first terminal of the first switch. A first terminal of the second switch can receive a bias voltage. A second terminal of the second switch is electrically connected to the third node even when electrically disconnected from the first terminal of the second switch. The capacitor may include a first electrode electrically connected to the third node; the voltage-controlled oscillator may include control terminals and output terminals. Each of the control terminals is electrically connected to the third node. The third switch may electrically connect its output terminals to the first node.

[0030] The conducting period of the first switch may not overlap with the conducting period of the second switch. The conducting period of the first of the third switches may not overlap with the conducting period of the second of the third switches.

[0031] When one of the third switches is turned on, the first switch can be turned on, and the second switch can be turned off.

[0032] When all third switches are turned off, the first switch can be turned off and the second switch can be turned on.

[0033] The clock data recovery circuit may include a fourth switch. The first terminal of the fourth switch may be electrically connected to the output terminal of the voltage-controlled oscillator having the highest frequency band. The second terminal of the fourth switch may be electrically connected to the first node even if it is not electrically connected to the first terminal of the fourth switch.

[0034] When the fourth switch is turned on, the first switch can be turned off, and the second switch can be turned on.

[0035] The clock data recovery circuit may include a register and a fifth switch. The first terminal of the fifth switch may be electrically connected to a fourth node. The fourth node may be included in a phase detector. The second terminal of the fifth switch may be electrically connected to the register even if it is not electrically connected to the first terminal of the fifth switch.

[0036] When the fifth switch is turned on, the first switch can be turned off, the second switch can be turned on, and the fourth switch can be turned on.

[0037] The clock data recovery circuit may include an oscillator controller, wherein the oscillator controller is configured to reference a value stored in a register to turn on one of the third switches and allow the others of the third switches to remain off.

[0038] The clock data recovery circuit may include the following components: a NOR gate and a first flip-flop, wherein the NOR gate is configured to receive a latch signal, a clock training signal, and an enable signal. The input terminal of the first flip-flop may receive the output signal of the NOR gate. The control terminal of the first flip-flop may receive a synchronization signal. The output terminal of the first flip-flop may output control signals for a first switch, a second switch, a fourth switch, and a fifth switch.

[0039] The synchronization signal may be different from the clock signal.

[0040] The oscillator controller can switch the level of the enable signal when one of the third switches is turned on.

[0041] When the level of the lock signal switches from the lock level to the unlock level, the level of the enable signal can be switched.

[0042] The oscillator controller can shut off all third switches when the level of the lock signal switches from the lock level to the unlock level.

[0043] The phase detector may include a second flip-flop, a third flip-flop, and a first XOR gate.

[0044] The input terminals of the second flip-flop can receive input signals. The control terminals of the second flip-flop can receive clock signals. The output terminals of the second flip-flop can be electrically connected to the fourth node.

[0045] The input terminal of the third flip-flop can be electrically connected to the output terminal of the second flip-flop. The control terminal of the third flip-flop can receive a clock signal.

[0046] The first input terminal of the first XOR gate can be electrically connected to the fourth node. The second input terminal of the first XOR gate can be electrically connected to the output terminal of the third flip-flop. The output terminal of the first XOR gate can output the first part of the phase adjustment signal.

[0047] The phase detector may include a fourth flip-flop, a fifth flip-flop, and a second XOR gate.

[0048] The input terminals of the fourth flip-flop can receive input signals. The control terminals of the fourth flip-flop can receive an inverted clock signal.

[0049] The input terminal of the fifth flip-flop can be electrically connected to the output terminal of the fourth flip-flop. The control terminal of the fifth flip-flop can receive a clock signal.

[0050] The first input terminal of the second XOR gate can be electrically connected to the output terminal of the fifth flip-flop. The second input terminal of the second XOR gate can be electrically connected to the output terminal of the fourth flip-flop. The output terminal of the second XOR gate can output the second part of the phase adjustment signal.

[0051] The implementation may relate to a display device. The display device may include a data line, pixels electrically connected to the data line, and a data driver for supplying data voltage to the data line.

[0052] The data driver may include the following components: a clock data recovery circuit, a decoder, and a data voltage generator, wherein the clock data recovery circuit is configured to receive a clock data signal via a clock data line and is configured to generate a clock signal using clock training symbols in the clock data signal; the decoder is configured to decode grayscale values ​​in the clock data signal using the clock signal; and the data voltage generator is configured to convert grayscale values ​​into data voltages.

[0053] The clock data recovery circuit may include a phase detector, a charge pump, a first switch, a second switch, a capacitor, a voltage-controlled oscillator, and a third switch. The phase detector outputs a phase adjustment signal by comparing the clock signal of the first node with the input signal. The charge pump adjusts the charge amount of the second node according to the phase adjustment signal. A first terminal of the first switch is electrically connected to the second node. A second terminal of the first switch is electrically connected to the third node even when electrically disconnected from the first terminal of the first switch. A first terminal of the second switch can receive a bias voltage. A second terminal of the second switch is electrically connected to the third node even when electrically disconnected from the first terminal of the second switch. The capacitor may include a first electrode electrically connected to the third node; the voltage-controlled oscillator may include control terminals and output terminals. Each of the control terminals is electrically connected to the third node. The third switch may electrically connect its output terminals to the first node.

[0054] The clock data recovery circuit may include a fourth switch, a register, and a fifth switch.

[0055] The first terminal of the fourth switch can be electrically connected to the output terminal of the voltage-controlled oscillator with the highest frequency band. The second terminal of the fourth switch can be electrically connected to the first node even if it is not electrically connected to the first terminal of the fourth switch.

[0056] The first terminal of the fifth switch may be electrically connected to the fourth node. The fourth node may be included in the phase detector. The second terminal of the fifth switch may be electrically connected to the register even if it is not electrically connected to the first terminal of the fifth switch.

[0057] The clock data recovery circuit may include the following components: an oscillator controller, a NOR gate, and a first flip-flop. The oscillator controller is configured to reference a value stored in a register to turn on one of the third switches and allow the others in the third switch to remain off. The NOR gate is configured to receive a latch signal, a clock training signal, and an enable signal. The input terminal of the first flip-flop may receive the output signal of the NOR gate. The control terminal of the first flip-flop may receive a synchronization signal. The output terminal of the first flip-flop may output control signals for the first, second, fourth, and fifth switches.

[0058] The phase detector may include a second flip-flop, a third flip-flop, a first XOR gate, a fourth flip-flop, a fifth flip-flop, and a second XOR gate.

[0059] The input terminals of the second flip-flop can receive input signals. The control terminals of the second flip-flop can receive clock signals. The output terminals of the second flip-flop can be electrically connected to the fourth node.

[0060] The input terminal of the third flip-flop can be electrically connected to the output terminal of the second flip-flop. The control terminal of the third flip-flop can receive a clock signal.

[0061] The first input terminal of the first XOR gate can be electrically connected to the fourth node. The second input terminal of the first XOR gate can be electrically connected to the output terminal of the third flip-flop. The output terminal of the first XOR gate can output the first part of the phase adjustment signal.

[0062] The input terminals of the fourth flip-flop can receive input signals. The control terminals of the fourth flip-flop can receive an inverted clock signal.

[0063] The input terminal of the fifth flip-flop can be electrically connected to the output terminal of the fourth flip-flop. The control terminal of the fifth flip-flop can receive a clock signal.

[0064] The first input terminal of the second XOR gate can be electrically connected to the output terminal of the fifth flip-flop. The second input terminal of the second XOR gate can be electrically connected to the output terminal of the fourth flip-flop. The output terminal of the second XOR gate can output the second part of the phase adjustment signal. Attached Figure Description

[0065] Figure 1 This is a block diagram illustrating a display device according to an embodiment.

[0066] Figure 2 This is a circuit diagram showing the pixels according to an embodiment.

[0067] Figure 3 This is a block diagram illustrating a data driver according to an embodiment.

[0068] Figure 4 This is a block diagram illustrating a driver unit according to an embodiment.

[0069] Figure 5 , Figure 6 and Figure 7 This is a diagram illustrating an example of a signal provided from a timing controller according to an embodiment.

[0070] Figure 8 This is a block diagram illustrating a transceiver according to an embodiment.

[0071] Figure 9 This is a circuit diagram illustrating a clock data recovery circuit according to an embodiment.

[0072] Figure 10 , Figure 11 , Figure 12 , Figure 13 and Figure 14 This illustrates the calibration mode according to an embodiment. Figure 9 The diagram shows the operation of the clock data recovery circuit.

[0073] Figure 15 This illustrates the implementation in normal mode. Figure 9 The diagram shows the operation of the clock data recovery circuit.

[0074] Figure 16 This is a diagram illustrating a data voltage generator according to an embodiment. Detailed Implementation

[0075] Exemplary embodiments are described with reference to the accompanying drawings. Actual embodiments may be implemented in various forms and are not limited to the exemplary embodiments.

[0076] Identical or similar elements may be designated by the same reference numerals.

[0077] For clarity and description, the dimensions of the components shown in the accompanying drawings may be exaggerated.

[0078] Each of the terms “connection” and “link” may mean “electrical connection”. The term “insulation” may mean “electrical insulation” or “electrical isolation”. The term “other” may mean “another”. A signal may mean an instance of a signal, for example, a clock signal may mean an instance of a clock signal such that a first element can receive a first instance of the clock signal and a second element can receive a second instance of the clock signal.

[0079] While the terms "first," "second," etc., can be used to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Without departing from the teachings of one or more embodiments, a first element may be referred to as a second element. The description of an element as a "first" element may not require or imply the presence of a second element or other elements. The terms "first," "second," etc., can be used to distinguish different categories or groups of elements. For brevity, the terms "first," "second," etc., may respectively represent "first category (or first group)," "second category (or second group)," etc.

[0080] Figure 1 This is a diagram showing the display device 10 according to an embodiment.

[0081] Reference Figure 1 The display device 10 may include a timing controller 11, a data driver 12, a scan driver 13, and a pixel unit 14.

[0082] The timing controller 11 can receive grayscale values ​​and control signals for each respective frame from an external device. The timing controller 11 can render the grayscale values ​​to correspond to the specifications of the display device 10. For example, the external device can provide red, green, and blue grayscale values ​​for each unit point. When the pixel unit 14 has a PenTile...TM In this configuration, adjacent unit points share pixels, and therefore, multiple pixels may not correspond one-to-one with their respective grayscale values. Accordingly, it is necessary to render the grayscale values. When multiple pixels correspond one-to-one with their respective grayscale values, it is not necessary to render the grayscale values. Rendered or unrendered grayscale values ​​can be provided to the data driver 12. The timing controller 11 can provide control signals suitable for their specifications to the data driver 12, the scan driver 13, and the like to achieve frame display.

[0083] The data driver 12 can generate data voltages to be supplied to multiple data lines DL1, DL2, DL3, ..., DLn by using grayscale values ​​and control signals. For example, the data driver 12 can sample grayscale values ​​using a clock signal and apply multiple data voltages corresponding to the multiple grayscale values ​​to the multiple data lines DL1, DL2, DL3, ..., DLn on a pixel-row basis. Here, n can be an integer greater than 0.

[0084] The scan driver 13 can generate scan signals to be provided to multiple scan lines SL1, SL2, SL3, ..., SLm by using a clock signal, a scan start signal, and the like received from the timing controller 11. Here, m can be an integer greater than 0.

[0085] Scan driver 13 can sequentially supply scan signals with pulses having an on-level to multiple scan lines SL1 to SLm. Scan driver 13 may include scan stages configured as shift registers. Scan driver 13 can generate scan signals by sequentially transmitting a scan start signal in the form of pulses with an on-level to the next scan stage under the control of a clock signal.

[0086] Pixel unit 14 includes multiple pixels. Each pixel can be connected to a corresponding data line and a corresponding scan line. Pixel PXij can mean a pixel connected to the i-th scan line and the j-th data line. Here, i and j can be integers greater than 0.

[0087] Figure 2 This is a diagram illustrating pixel PXij according to an embodiment.

[0088] Reference Figure 2 Pixel PXij may include multiple transistors T1 and T2, storage capacitor Cst, and light-emitting diode LD.

[0089] A circuit implemented using an N-type transistor is described as an example. Those skilled in the art can design a circuit implemented using a P-type transistor by changing the polarity of the voltage applied to the gate terminal. Those skilled in the art can design a circuit implemented using a combination of P-type and N-type transistors. A P-type transistor indicates a transistor in which the amount of current flowing in the negative direction increases as the voltage difference between the gate and source electrodes increases. An N-type transistor indicates a transistor in which the amount of current flowing in the positive direction increases as the voltage difference between the gate and source electrodes increases. Transistors can be configured to include one or more of various forms such as thin-film transistors (TFTs), field-effect transistors (FETs), bipolar junction transistors (BJTs), and the like.

[0090] The gate electrode of the first transistor T1 can be connected to the first electrode of the storage capacitor Cst, the first electrode of the first transistor T1 can be connected to the first power line ELVDDL, and the second electrode of the first transistor T1 can be connected to the second electrode of the storage capacitor Cst. The first transistor T1 can be referred to as the driving transistor.

[0091] The gate electrode of the second transistor T2 can be connected to the i-th scan line SLi, the first electrode of the second transistor T2 can be connected to the j-th data line DLj, and the second electrode of the second transistor T2 can be connected to the gate electrode of the first transistor T1. The second transistor T2 can indicate the scan transistor.

[0092] The anode of the light-emitting diode (LD) can be connected to the second electrode of the first transistor T1, and the cathode of the LD can be connected to the second power supply line ELVSSL. The LD can be configured as an organic light-emitting diode, an inorganic light-emitting diode, a quantum dot light-emitting diode, etc.

[0093] A first power supply voltage may be applied to a first power supply line ELVDDL, and a second power supply voltage may be applied to a second power supply line ELVSSL. For example, the first power supply voltage may be higher than the second power supply voltage.

[0094] When a scan signal with a conduction level (high level) is applied through the i-th scan line SL1, the second transistor T2 is turned on. The data voltage applied to the j-th data line DLj is stored in the first electrode of the storage capacitor Cst.

[0095] A positive drive current corresponding to the voltage difference between the first and second electrodes of the storage capacitor Cst flows between the first and second electrodes of the first transistor T1. Accordingly, the light-emitting diode LD emits light with a brightness corresponding to the data voltage.

[0096] Next, when a scan signal with a turn-off level (low level here) is applied through the i-th scan line SL1, the second transistor T2 is turned off, and the j-th data line DLj and the first electrode of the storage capacitor Cst are electrically separated from each other. Therefore, although the data voltage of the j-th data line DLj is changed, the voltage stored in the first electrode of the storage capacitor Cst remains unchanged.

[0097] The implementation method can be applied not only to Figure 2 The pixel PXij shown can also be applied to other pixels in pixel unit 14.

[0098] Figure 3 This is a diagram illustrating the data driver 12 according to an embodiment.

[0099] Reference Figure 3 The data driver 12 may include one or more driver units 120. When the display device 10 includes only one driver unit 120, the driver unit 120 and the data driver 12 may be the same, and all data lines DL1 to DLn may be connected to one driver unit 120. When the display device 10 includes multiple driver units 120, the multiple data lines DL1 to DLn may be grouped into data line groups, and each data line group may be connected to a corresponding driver unit 120.

[0100] Multiple driver units 120 can use a single clock training line (SFC) as a common bus. For example, the timing controller 11 can simultaneously transmit a signal indicating the supply of clock training symbols to all driver units 120 via a single clock training line (SFC).

[0101] The driver unit 120 can be connected to the timing controller 11 via a dedicated clock data line DCSL. When the display device 10 includes multiple driver units 120, the multiple driver units 120 can be connected to the timing controller 11 via their respective clock data lines DCSL.

[0102] At least one clock data line DCSL can be provided to driver unit 120. For example, when it is difficult to achieve the desired transmission signal bandwidth using only one clock data line DCSL, multiple clock data lines DCSL can be connected to each driver unit 120 to achieve the desired transmission signal bandwidth. Even when the clock data lines DCSL are configured as differential signal lines to remove common-mode noise, each driver unit 120 may still require multiple clock data lines DCSL.

[0103] Figure 4 This is a diagram showing the driver unit 120 according to an embodiment.

[0104] Reference Figure 4The driver unit 120 may include a transceiver 121 and a data voltage generator 122.

[0105] Transceiver 121 can receive clock data signals from timing controller 11 via clock data line DCSL. Transceiver 121 can also receive clock training signals from timing controller 11 via clock training line SFC.

[0106] Transceiver 121 can generate a clock signal using a clock training signal and a clock data signal, and can sample a data signal DCD from the clock data signal using the generated clock signal. Transceiver 121 can provide the sampled data signal DCD to data voltage generator 122. Transceiver 121 can also provide a source shift clock SSC to data voltage generator 122.

[0107] Data voltage generator 122 can receive data signal DCD and source shift clock SSC from transceiver 121. Data voltage generator 122 can generate data voltage using source shift clock SSC and data signal DCD.

[0108] The data voltage generator 122 can synchronously apply a data voltage corresponding to the grayscale value of the pixel connected to the corresponding scan line to multiple data lines DL1 to DLn during the period when the on-level scan signal is applied to the scan line. For example, when the on-level scan signal is applied to the i-th scan line SLi, the data voltage generator 122 can apply a data voltage corresponding to the grayscale value of pixel PXij to the j-th data line DLj.

[0109] Figures 5 to 7 This is a diagram illustrating an example of signals provided from the timing controller 11.

[0110] Reference Figure 5 Each image frame's frame time period can include a vertical blanking period and a valid data period. For example, the nth frame time period FRPn can include a vertical blanking period VBPn and a valid data period ADPn.

[0111] Multiple valid data periods ADP(n-1) and ADPn may correspond to the supply periods of grayscale values ​​that constitute the image frames to be displayed by pixel unit 14. Grayscale values ​​may be included in pixel data PXD.

[0112] The vertical blanking period (VBPn) can be located between the effective data period (ADP(n-1)) of the previous frame and the effective data period (ADPn) of the current frame. Clock training, frame setup, and virtual data feeding can be performed during the vertical blanking period (VBPn). The vertical blanking period (VBPn) can sequentially include the feeding period of virtual data (DMD), the feeding period of clock training symbols (CTP), the feeding period of frame data (FRD), and the feeding period of virtual data (DMD).

[0113] During the vertical blanking period VBPn, the timing controller 11 applies a low logic level L clock training signal to the clock training line SFC to notify the data driver 12 that the clock training symbol CTP is being supplied to the clock data line DCSL. When no clock training symbol CTP is supplied, the timing controller 11 may apply a high logic level H clock training signal to the clock training line SFC.

[0114] Reference Figure 6 An exemplary clock training symbol (CTP) is shown. For example, in a clock training symbol CTP, 10 bits AD, D0, D1, D2, D3, D4, D5, D6, D7, and D8 can constitute a unit data. The period during which a unit bit is supplied to the clock data line DCSL can be referred to as a unit interval (1UI). The period during which a unit data is supplied to the clock data line DCSL can be referred to as a period. For each unit data, the ratio of high to low levels repeats 6:4 and 4:6. The clock training symbol CTP may be configured differently depending on the implementation and / or product.

[0115] Reference Figure 7 The diagram illustrates an exemplary plurality of data control signals HBP, SOL, and CONF. For example, in each of the plurality of data control signals HBP, SOL, and CONF, 10 bits AD, D0, D1, D2, D3, D4, D5, D6, D7, and D8 may constitute a unit data. Each unit data includes a transition bit AD. Although the transition bit AD may be configured differently depending on the implementation and / or product, the transition bit AD may be configured to have a level different from the level of the immediately preceding bit. In some implementations and / or products, the transition bit AD may be configured to have a level different from the level of the next bit.

[0116] The horizontal blanking period signal HBP can notify the driver unit 120 that the pixel row corresponding to the pixel data PXD (e.g., pixels connected to the same scan line) has been changed. In an embodiment, the horizontal blanking period signal HBP is configured as 1110011000, but this may vary depending on the embodiment and / or product.

[0117] The start SOL of a line can notify the driver unit 120 that the supply of a signal for the modified pixel row has begun. In one embodiment, the unit data column of the start SOL of a line is configured as 1111111111, but this may vary depending on the embodiment and / or product.

[0118] The configuration signal CONF may include operational options for the driver unit 120. For example, the configuration signal CONFp may indicate that subsequent data is pixel data (PXD) or virtual data (DMD). For example, the configuration signal CONFf may indicate that subsequent data is frame data (FRD).

[0119] Although not shown in the accompanying drawings, pixel data PXD can represent the grayscale value of the pixel corresponding to bits D0, D1, D2, D3, D4, D5, D6, D7, and D8, other than the conversion bits AD of the unit data. The configuration of pixel data PXD may vary depending on the implementation method and / or product.

[0120] Figure 8 This is a diagram showing a transceiver 121 according to an embodiment.

[0121] Reference Figure 8 The transceiver 121 may include a clock data recovery circuit 1211, a decoder 1212, a lock detector 1213, and a frequency divider 1214.

[0122] The clock data recovery circuit 1211 can receive clock data signals via the clock data line DCSL, and can generate a clock signal CLK using the clock training symbol CTP in the clock data signal. The clock data recovery circuit 1211 can receive clock training signals via the clock training line SFC. The clock data recovery circuit 1211 can receive a lock signal FL.

[0123] Decoder 1212 can decode grayscale values ​​and other data in the clock data signal using the clock signal CLK. For example, decoder 1212 can sample the data signal DCD from the clock data signal using the clock signal CLK.

[0124] The lock detector 1213 can output a lock signal FL indicating whether the clock signal CLK has been locked by comparing the clock signal CLK and the clock data signal. When the clock signal CLK is successfully locked, the lock signal FL may have a locked level. When the clock signal CLK is not locked, the lock signal FL may have an unlocked level.

[0125] Frequency divider 1214 can generate a source shift clock SSC with a shift frequency by using the clock signal CLK.

[0126] Figure 9 This is a diagram showing the clock data recovery circuit 1211 according to an embodiment.

[0127] Reference Figure 9 The clock data recovery circuit 1211 may include the following components: a phase detector PD, a charge pump CP, a loop filter LPF, multiple voltage-controlled oscillators VCO1, VCO2, VCO3 and VCO4, multiple third switches SW31, SW32, SW33 and SW34, a fourth switch SW4, a fifth switch SW5, a register REG, an oscillator controller VCC, a NOR gate, and a first flip-flop FF1.

[0128] The multiple flip-flops FF1, FF2, FF3, FF4 and FF5 included in the clock data recovery circuit 1211 can be D flip-flops or another type of flip-flop.

[0129] The phase detector PD outputs a phase adjustment signal by comparing the clock signal CLK of the first node N1 with the input signal. The input signal can be a clock data signal input via the clock data line DCSL. The phase adjustment signal can include a rising signal and a falling signal. For example, a portion (or a first portion) of the phase adjustment signal can be a falling / on / off signal used to turn the seventh switch SW7 on / off. The remaining portion (or a second portion) of the phase adjustment signal can be a rising / on / off signal used to turn the sixth switch SW6 on / off.

[0130] The phase detector PD may include a second flip-flop FF2, a third flip-flop FF3, a fourth flip-flop FF4, a fifth flip-flop FF5, a first XOR gate XOR1, and a second XOR gate XOR2.

[0131] The second flip-flop FF2 can receive an input signal through its input terminal, a clock signal CLK through its control terminal, and may include an output terminal connected to the fourth node N4. The third flip-flop FF3 may have an input terminal connected to the output terminal of the second flip-flop FF2, and can receive the clock signal CLK through its control terminal. The first XOR gate XOR1 may include a first input terminal connected to the fourth node N4, a second input terminal connected to the output terminal of the third flip-flop FF3, and an output terminal that outputs a portion of the phase adjustment signal. The first XOR gate XOR1 may output a high logic level falling signal when signals of different logic levels are applied to the first and second input terminals. In other cases, the first XOR gate XOR1 may output a low logic level signal.

[0132] The fourth flip-flop FF4 can receive an input signal through its input terminals and can receive the inverted signal CLKB of the clock signal CLK through its control terminals. The inverted signal CLKB has a logic level (high or low) different from the logic level (low or high) of the clock signal CLK. The fifth flip-flop FF5 may include an input terminal connected to the output terminal of the fourth flip-flop FF4 and can receive the clock signal CLK through its control terminals. The second XOR gate XOR2 may include a first input terminal connected to the output terminal of the fifth flip-flop FF5, a second input terminal connected to the output terminal of the fourth flip-flop FF4, and an output terminal for the remaining portion of the output phase adjustment signal. The second XOR gate XOR2 can output a rising signal with a high logic level when signals of different logic levels are applied to the first and second input terminals. In other cases, the second XOR gate XOR2 can output a signal with a low logic level.

[0133] The charge pump CP can adjust the amount of charge at the second node N2 according to the phase adjustment signal. For example, the charge pump CP may include a first current source CS1, a sixth switch SW6, a seventh switch SW7, and a second current source CS2.

[0134] One terminal of the sixth switch SW6 can be connected to the first current source CS1, and the other terminal of the sixth switch SW6 can be connected to the second node N2. When the sixth switch SW6 is turned on, the first current source CS1 can increase the charge of the second node N2.

[0135] One terminal of the seventh switch SW7 can be connected to the second node N2, and the other terminal of the seventh switch SW7 can be connected to the second current source CS2. When the seventh switch SW7 is turned on, the second current source CS2 can reduce the charge on the second node N2.

[0136] One terminal of the first switch SW1 can be connected to the second node N2, and the other terminal of the first switch SW1 can be connected to the third node N3. The first switch SW1 can be controlled by the inverted signal CALB of the calibration signal CAL. The inverted signal CALB has a different logic level (high or low) than the logic level (low or high) of the calibration signal CAL.

[0137] The loop filter LPF generates control voltages for multiple voltage-controlled oscillators VCO1, VCO2, VCO3, and VCO4 at the first electrode of the capacitor CAP, which is electrically connected to the third node N3. These control voltages correspond to the amount of charge controlled by the charge pump CP.

[0138] The loop filter LPF may include a second switch SW2 and a capacitor CAP. The second switch SW2 may include one terminal to which a bias voltage VB is applied and another terminal connected to a third node N3. The second switch SW2 may be controlled according to a calibration signal CAL. The first electrode of the capacitor CAP may be connected to the third node N3. The second electrode of the capacitor CAP may be connected to a reference node (e.g., ground). The bias voltage VB may be the highest of several control voltages acceptable to multiple voltage-controlled oscillators VCO1, VCO2, ..., and VCOk (e.g., VCO4). As the control voltage becomes higher, the multiple voltage-controlled oscillators VCO1, VCO2, VCO3, and VCO4 may generate a clock signal CLK with a higher frequency.

[0139] Multiple voltage-controlled oscillators VCO1, VCO2, VCO3, and VCO4 may each include control terminals connected to a third node N3, and may also include output terminals connected to a first node N1 via multiple third switches SW31, SW32, SW33, and SW34. The multiple third switches SW31, SW32, SW33, and SW34 may be controlled by an oscillator controller VCC.

[0140] Multiple voltage-controlled oscillators VCO1, VCO2, VCO3, and VCO4 may have different frequency bands. For example, the first voltage-controlled oscillator VCO1 may have the highest frequency band. The second voltage-controlled oscillator VCO2 may have a frequency band lower than that of the first voltage-controlled oscillator VCO1 but higher than that of the third voltage-controlled oscillator VCO3. The third voltage-controlled oscillator VCO3 may have a frequency band lower than that of the second voltage-controlled oscillator VCO2 but higher than that of the fourth voltage-controlled oscillator VCO4. The fourth voltage-controlled oscillator VCO4 may have the lowest frequency band.

[0141] In this implementation, the frequency bands of the multiple voltage-controlled oscillators VCO1, VCO2, VCO3, and VCO4 may not overlap. For example, the first voltage-controlled oscillator VCO1 may have a frequency band exceeding 3 GHz and less than or equal to 4 GHz. The second voltage-controlled oscillator VCO2 may have a frequency band exceeding 2 GHz and less than or equal to 3 GHz. The third voltage-controlled oscillator VCO3 may have a frequency band exceeding 1 GHz and less than or equal to 2 GHz. The fourth voltage-controlled oscillator VCO4 may have a frequency band exceeding 0 GHz and less than or equal to 1 GHz.

[0142] In this implementation, the frequency bands of the multiple voltage-controlled oscillators VCO1, VCO2, VCO3, and VCO4 may partially overlap. For example, the first voltage-controlled oscillator VCO1 may have a frequency band greater than or equal to 2.9 GHz and less than or equal to 4 GHz. The second voltage-controlled oscillator VCO2 may have a frequency band greater than or equal to 1.9 GHz and less than or equal to 3 GHz. The third voltage-controlled oscillator VCO3 may have a frequency band greater than or equal to 0.9 GHz and less than or equal to 2 GHz. The fourth voltage-controlled oscillator VCO4 may have a frequency band greater than or equal to 0 GHz and less than or equal to 1 GHz.

[0143] The total number of voltage-controlled oscillators can be set according to the specifications of the voltage-controlled oscillators. In this embodiment, the clock data recovery circuit 1211 includes four voltage-controlled oscillators, VCO1, VCO2, VCO3, and VCO4.

[0144] One terminal of the fourth switch SW4 can be connected to the output terminal of the first voltage-controlled oscillator VCO1 (which has the highest frequency band among the multiple voltage-controlled oscillators VCO1, VCO2, VCO3, and VCO4), and the other terminal of the fourth switch SW4 can be connected to the first node N1. The fourth switch SW4 can be controlled according to the calibration signal CAL.

[0145] One terminal of the fifth switch SW5 can be connected to the fourth node N4 (included in the phase detector PD), and the other terminal of the fifth switch SW5 can be connected to the register REG. The fifth switch SW5 can be controlled according to the calibration signal CAL.

[0146] When the fifth switch SW5 is in the ON state, the register REG can receive the sampled signal from the fourth node N4. The minimum capacity of the register REG can be set according to the worst symbol of the clock training symbol CTP, the minimum data supply rate of the timing controller 11, and the maximum frequency of the first voltage-controlled oscillator VCO1. For example, refer to Figure 11 The worst-case scenario for the clock training symbol CTP is when a 6UI low-level signal (or high-level signal) and a 6UI high-level signal (or low-level signal) are consecutively applied to the clock data line DCSL. For example, the minimum data supply speed of the timing controller 11 can be 1Gbps. For example, the maximum frequency of the first voltage-controlled oscillator VCO1 can be 4GHz. Therefore, the register REG may require at least 50UI of storage space to identify the clock training symbol CTP. For example, 24UI of storage space may be required to identify the 6UI low-level signal (or high-level signal), 24UI of storage space may be required to identify the 6UI high-level signal (or low-level signal), and an additional 2UI of storage space may be required as a pre- and / or post-hoc margin.

[0147] Referring to the value stored in register REG, the oscillator controller VCC can turn on one of the multiple third switches SW31, SW32, SW33 and SW34 and allow the others of the multiple third switches SW31, SW32, SW33 and SW34 to remain off.

[0148] When one of the multiple third switches SW31, SW32, SW33 and SW34 is turned on, the oscillator controller VCC can switch the level of the enable signal EN to a high logic level.

[0149] When the level of the lock signal FL switches from the lock level to the unlock level, the oscillator controller VCC can turn off all third switches SW31, SW32, SW33, and SW34. This prevents any of the third switches SW31, SW32, SW33, and SW34 from being simultaneously connected to the first node N1 along with the fourth switch SW4 in subsequent calibration modes.

[0150] The NOR gate can receive the latch signal FL, the clock training signal, and the enable signal EN. When the latch signal FL, the clock training signal, and the enable signal EN are all at low logic levels, the NOR gate can provide a high logic level output signal. In other cases, the NOR gate can provide a low logic level output signal.

[0151] When the level of the lock signal FL switches from the lock level to the unlock level, the level of the enable signal EN can be switched. For example, when the level of the lock signal FL switches from the lock level to the unlock level, the level of the enable signal EN can be switched to a low logic level.

[0152] For example, when the lock signal FL is in the locked state, the lock signal FL may have a high logic level, and when the lock signal FL is in the unlocked state, the lock signal FL may have a low logic level.

[0153] The first flip-flop FF1 can receive the output signal of the NOR gate through its input terminals, receive the synchronization signal SYNC through its control terminals, and output control signals for the first switch SW1, the second switch SW2, the fourth switch SW4, and the fifth switch SW5. The control signal can be the calibration signal CAL. The synchronization signal SYNC can be different from the clock signal CLK. For example, the synchronization signal SYNC can be a horizontal synchronization signal. The duration of the horizontal synchronization signal can be equal to the duration of the horizontal blanking time signal HBP.

[0154] Figures 10 to 14 This illustrates the calibration mode according to an embodiment. Figure 9 The diagram shows the operation of the clock data recovery circuit 1211.

[0155] The clock data recovery circuit 1211 can operate in either calibration mode or normal mode. In calibration mode, the calibration signal CAL can have a high logic level. In normal mode, the calibration signal CAL can have a low logic level.

[0156] For example, when the display device 10 is powered on, the lock signal FL, the clock training signal, and the enable signal EN can all have a low logic level. Correspondingly, the NOR gate can output a high logic level.

[0157] The oscillator controller VCC can shut off all third switches SW31, SW32, SW33 and SW34.

[0158] The first flip-flop FF1 can output the calibration signal CAL in sync with the timing of the SYNC signal. The calibration signal CAL can have a high logic level, and the inverted signal CALB of the calibration signal CAL can have a low logic level.

[0159] When a high-logic-level calibration signal CAL is output, switches SW2, SW4, and SW5 can be turned on. Switch SW1 can be turned off by the inverted signal CALB of the calibration signal CAL. Accordingly, nodes N2 and N3 are electrically disconnected from each other, and node N3 is unaffected by the operation of the phase detector PD and charge pump CP (see [link to documentation]). Figure 10 ).

[0160] Accordingly, a bias voltage VB is applied to the third node N3, and a clock signal CLK corresponding to the highest frequency of the first voltage-controlled oscillator VCO1 is output to the first node N1. For example, the clock signal CLK may have 4 GHz.

[0161] Accordingly, the second flip-flop FF2 can generate a sampled signal by sampling the clock training symbol CTP of the clock data line DCSL based on the clock signal CLK. The generated sampled signal can be stored in the register REG.

[0162] The oscillator controller VCC can refer to the value stored in the register REG to turn on one of the multiple third switches SW31, SW32, SW33, and SW34 that is connected to a voltage-controlled oscillator with a frequency band corresponding to the data supply speed of the timing controller 11. The oscillator controller VCC can also allow the other of the multiple third switches SW31, SW32, SW33, and SW34 to remain in the off state.

[0163] For example, refer to Figure 11 The timing controller 11 can supply the clock training symbol CTP at 1Gbps. The sampling signal repeats a high logic level for 24UI, a low logic level for 16UI, a high logic level for 16UI, and a low logic level for 24UI. The oscillator controller VCC can refer to the value stored in the register REG to identify that the data supply speed of the timing controller 11 corresponds to 1Gbps, and turns on the third switch SW34 connected to the fourth voltage-controlled oscillator VCO4, which has a frequency band of more than 0GHz and less than or equal to 1GHz.

[0164] For example, refer to Figure 12 The timing controller 11 can supply the clock training symbol CTP at 2Gbps. The sampling signal repeats the high logic level of 12UI, the low logic level of 8UI, the high logic level of 8UI, and the low logic level of 12UI. The oscillator controller VCC can refer to the value stored in the register REG to identify that the data supply speed of the timing controller 11 corresponds to 2Gbps, and turns on the third switch SW33 connected to the third voltage-controlled oscillator VCO3, which has a frequency band of more than 1GHz and less than or equal to 2GHz.

[0165] For example, refer to Figure 13 The timing controller 11 can supply the clock training symbol CTP at 3Gbps. The sampling signal repeats 8UI high logic level, 6 (or 5)UI low logic level, 5 (or 6)UI high logic level, and 8UI low logic level. The oscillator controller VCC can refer to the value stored in the register REG to identify that the data supply speed of the timing controller 11 corresponds to 3Gbps, and turns on the third switch SW32 connected to the second voltage-controlled oscillator VCO2 with a frequency band of more than 2GHz and less than or equal to 3GHz.

[0166] For example, refer to Figure 14 The timing controller 11 can supply the clock training symbol CTP at 4Gbps. The sampling signal repeats the high logic level of 6UI, the low logic level of 4UI, the high logic level of 4UI, and the low logic level of 6UI. The oscillator controller VCC can refer to the value stored in the register REG to identify that the data supply speed of the timing controller 11 corresponds to 4Gbps, and turns on the third switch SW31 connected to the first voltage-controlled oscillator VCO1 with a frequency band of more than 3GHz and less than or equal to 4GHz.

[0167] When one of the third switches SW31, SW32, SW33, and SW34 is turned on, the oscillator controller VCC can switch the level of the enable signal EN to a high logic level. According to an embodiment, after the fourth switch SW4 is turned on, the oscillator controller VCC turns on the selected third switch, thereby preventing two or more voltage-controlled oscillators from being simultaneously connected to the first node N1.

[0168] Figure 15 This illustrates an embodiment. Figure 9 The diagram shows the operation of the clock data recovery circuit 1211 in normal mode.

[0169] like Figure 15 As shown, the third switch SW33 can be turned on to select the third voltage-controlled oscillator VCO3.

[0170] Since the enable signal EN switches to a high logic level, a low logic level calibration signal CAL can be output through the NOR gate and the first flip-flop FF1. The inverted signal CALB has a high logic level.

[0171] When the calibration signal CAL is output at a low logic level, switches SW2, SW4, and SW5 can be turned off. Switch SW1 can be turned on by the inverted signal CALB of the calibration signal CAL. Accordingly, nodes N2 and N3 can be connected to each other. Therefore, node N3 is affected by the operation of the phase detector PD and the charge pump CP.

[0172] Therefore, the clock signal CLK can be locked in normal mode by selecting the third voltage-controlled oscillator VCO3 in calibration mode. Through the operation of the phase detector PD, charge pump CP, and loop filter LPF, the frequency and phase of the clock signal CLK output from the third voltage-controlled oscillator VCO3 can follow the frequency and phase of the clock training symbol CTP.

[0173] The time elapsed from the point when the clock data recovery circuit 1211 enters normal mode to the point when the frequency and phase of the clock signal CLK follow the frequency and phase of the clock training symbol CTP (i.e., the time elapsed until the level of the lock signal FL switches from the unlock level to the lock level) can be called the lock time.

[0174] According to the embodiment, the locking operation of the clock signal CLK is performed by using a voltage-controlled oscillator having a frequency band suitable for the data supply rate of the timing controller 11 in calibration mode, thereby reducing the locking time. For example, in a conventional clock data recovery circuit without a calibration mode, the locking time required to follow a 1.1Gbps data supply rate by sequentially reducing the clock frequency by 4GHz can be referred to as the first time. In the clock data recovery circuit 1211 of this embodiment, the time required to select the third voltage-controlled oscillator VCO3 by executing the calibration mode can be referred to as the second time. In normal mode, the locking time required for a 2GHz clock frequency starting from the third voltage-controlled oscillator VCO3 of this embodiment to follow a 1.1Gbps data supply rate can be referred to as the third time.

[0175] When the storage space of register REG is set to 50 UI, the second time can be approximately 20 ns. As an experimental result, the sum of the second and third times can be equal to approximately 1 / 4 of the first time.

[0176] Therefore, according to the implementation, the lock-in time is reduced so that a clock signal CLK of appropriate frequency can be generated quickly in accordance with the various data supply speeds of the timing controller 11.

[0177] In this implementation, the clock data recovery circuit 1211 can enter calibration mode even when the clock signal CLK is unlocked during image frame display. When the clock signal CLK is unlocked, the level of the lock signal FL can switch from the locked level to the unlocked level. The level of the enable signal EN can switch to a low logic level. When the display device 10 enters the vertical blanking period VBPn, the level of the clock training signal can switch to a low logic level. Therefore, the calibration signal CAL can be output through the NOR gate and the first flip-flop FF1, and the calibration mode can be executed again during the vertical blanking period VBPn.

[0178] Figure 16 This is a diagram showing the data voltage generator 122 according to an embodiment.

[0179] Reference Figure 16 The data voltage generator 122 may include a shift register SHR, a sampling latch SLU, a holding latch HLU, a digital-to-analog converter DAU, and an output buffer BFU.

[0180] The data signal DCD received from transceiver 121 may include source start pulse SSP, grayscale value GD, source output enable SOE, and the like.

[0181] The shift register SHR can sequentially generate sampled signals while shifting the source start pulse SSP at each time interval of the source shift clock SSC. The number of sampled signals can correspond to the number of data lines DLj to DLn. In an example, the number of sampled signals can be equal to the number of data lines DLj to DLn. In an embodiment, when the display device 10 further includes a demultiplexer located between the data driver 12 and the multiple data lines DLj to DLn, the number of sampled signals can be less than the number of data lines DLj to DLn. In an embodiment, the demultiplexer may not be implemented.

[0182] The sampling latch SLU may include sampling latch units whose total number corresponds to the total number of multiple data lines DLj to DLn, and may sequentially receive grayscale values ​​GD of image frames from the timing controller 11. The sampling latch SLU may store the grayscale values ​​GD sequentially received from the shift register SHR in the corresponding sampling latch units in response to sampling signals sequentially supplied from the shift register SHR.

[0183] The hold latch HLU may include hold latch units whose total number corresponds to the number of data lines DLj to DLn. When the input source output is SOE enabled, the hold latch HLU may store the grayscale value GD stored in the sample latch unit in the hold latch unit.

[0184] A digital-to-analog converter (DAU) may include a total number of DAUs corresponding to the total number of multiple data lines DLj to DLn. For example, the number of DAUs may be equal to the number of multiple data lines DLj to DLn. Each of the multiple DAUs may apply a grayscale voltage GV corresponding to the grayscale value GD stored in the corresponding latching unit to the corresponding data line.

[0185] The grayscale voltage GV can be provided from a grayscale voltage generator (not shown). The grayscale voltage generator may include a red grayscale voltage generator, a green grayscale voltage generator, and a blue grayscale voltage generator. The grayscale voltage GV can be set such that the brightness corresponding to each grayscale level follows a gamma curve.

[0186] The output buffer BFU may include buffer units BUFj to BUFn. For example, each of buffer units BUFj to BUFn may be an operational amplifier. Each of buffer units BUFj to BUFn may be a voltage follower configured to apply the output of the corresponding digital-to-analog converter to the corresponding data line. For example, the inverting terminal of each of buffer units BUFj to BUFn may be connected to the output terminal of the buffer unit, and the non-inverting terminal of the buffer unit may be connected to the output terminal of the corresponding digital-to-analog converter. The output of buffer units BUFj to BUFn may be a data voltage.

[0187] For example, the output terminal of the j-th buffer unit BUFj can be connected to the j-th data line DLj and can receive the buffer power supply voltage VDD and the ground power supply voltage GND. The buffer power supply voltage VDD determines the upper limit of the output voltage (i.e., the data voltage) of the buffer unit BUFj. The ground power supply voltage GND determines the lower limit of the output voltage of the buffer unit BUFj. Depending on the configuration of the buffer unit BUFj, one or more other voltages may be applied to the buffer unit BUFj in addition to or instead of the buffer power supply voltage VDD and the ground power supply voltage GND. One or more other voltages may be control voltages used to determine the slew rate of the buffer unit BUFj. The control voltage differs from the buffer power supply voltage VDD in that the control voltage is not the voltage used to determine the upper or lower limit of the output voltage of the buffer unit BUFj.

[0188] According to the implementation method, a clock signal with an appropriate frequency can be generated quickly in response to various data supply speeds.

[0189] Exemplary embodiments have been disclosed. Although specific terminology has been used, it is used and interpreted in a general and descriptive sense only and not for limiting purposes. Unless specifically indicated otherwise, features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments. Various changes may be made to the exemplary embodiments without departing from the scope defined by the appended claims.

Claims

1. A clock data recovery circuit comprising: a phase detector configured to output a phase adjustment signal by comparing a clock signal of a first node and an input signal; a charge pump configured to adjust an amount of charge of a second node according to the phase adjustment signal; a first switch, wherein a first terminal of the first switch is electrically connected to the second node, and wherein a second terminal of the first switch is electrically connected to a third node; a second switch, wherein a first terminal of the second switch is configured to receive a bias voltage, and wherein a second terminal of the second switch is electrically connected to the third node; a capacitor comprising a first electrode electrically connected to the third node; a plurality of voltage controlled oscillators respectively comprising a plurality of control terminals and respectively comprising a plurality of output terminals, wherein each of the plurality of control terminals is electrically connected to the third node, and wherein the plurality of voltage controlled oscillators have different frequency bands; a plurality of third switches configured to electrically connect the plurality of output terminals to the first node respectively; and an oscillator controller configured to turn on a third switch coupled with a voltage controlled oscillator having a frequency band corresponding to a data supply speed, wherein the third switch is one of the plurality of third switches, and wherein the voltage controlled oscillator is one of the plurality of voltage controlled oscillators, a fourth switch, wherein a first terminal of the fourth switch is electrically connected to an output terminal of a voltage controlled oscillator having a highest frequency band among the plurality of voltage controlled oscillators, and wherein a second terminal of the fourth switch is electrically connected to the first node.

2. The clock data recovery circuit of claim 1, wherein, a turn-on period of the first switch does not overlap with a turn-on period of the second switch, and wherein a turn-on period of a first one of the plurality of third switches does not overlap with a turn-on period of a second one of the plurality of third switches.

3. The clock data recovery circuit of claim 1, wherein, when one of the plurality of third switches is turned on, the first switch is turned on, and the second switch is turned off, and wherein when all of the plurality of third switches are turned off, the first switch is turned off, and the second switch is turned on.

4. The clock data recovery circuit of claim 1, wherein, when the fourth switch is turned on, the first switch is turned off, and the second switch is turned on. 5.The clock data recovery circuit of claim 1, further comprising: a register; and a fifth switch, wherein a first terminal of the fifth switch is electrically connected to a fourth node, wherein the fourth node is included in the phase detector, and wherein a second terminal of the fifth switch is electrically connected to the register. when the fifth switch is turned on, the first switch is turned off, the second switch is turned on, and the fourth switch is turned on.

6. The clock data recovery circuit of claim 5, wherein, 7.The clock data recovery circuit of claim 5, further comprising: a NOR gate configured to receive a lock signal, a clock training signal, and an enable signal; and a register configured to receive the clock training signal. ​ a first flip-flop, wherein an input terminal of the first flip-flop is configured to receive an output signal of the NOR gate, wherein a control terminal of the first flip-flop is configured to receive a synchronization signal, and wherein an output terminal of the first flip-flop is configured to output a control signal for the first switch, the second switch, the fourth switch, and the fifth switch, and wherein the oscillator controller is configured to turn on one of the plurality of third switches and allow others of the plurality of third switches to remain turned off with reference to a value stored in the register.

8. The clock data recovery circuit of claim 7, wherein, the oscillator controller is further configured to switch a level of the enable signal when one of the plurality of third switches is turned on, wherein the level of the enable signal is switched when the level of the lock signal is switched from a lock level to an unlock level, and wherein the oscillator controller is further configured to turn off all of the plurality of third switches when the level of the lock signal is switched from the lock level to the unlock level.

9. The clock data recovery circuit of claim 7, wherein, The phase detector comprises: a second flip-flop, wherein an input terminal of the second flip-flop is configured to receive the input signal, wherein a control terminal of the second flip-flop is configured to receive the clock signal, and wherein an output terminal of the second flip-flop is electrically connected to the fourth node; a third flip-flop, wherein an input terminal of the third flip-flop is electrically connected to the output terminal of the second flip-flop, and wherein a control terminal of the third flip-flop is configured to receive the clock signal; a first XOR gate, wherein a first input terminal of the first XOR gate is electrically connected to the fourth node, wherein a second input terminal of the first XOR gate is electrically connected to an output terminal of the third flip-flop, and wherein an output terminal of the first XOR gate is configured to output a first part of the phase adjustment signal; a fourth flip-flop, wherein an input terminal of the fourth flip-flop is configured to receive the input signal, and wherein a control terminal of the fourth flip-flop is configured to receive an inverted clock signal of the clock signal; a fifth flip-flop, wherein an input terminal of the fifth flip-flop is electrically connected to an output terminal of the fourth flip-flop, and wherein a control terminal of the fifth flip-flop is configured to receive the clock signal; and a second XOR gate, wherein a first input terminal of the second XOR gate is electrically connected to an output terminal of the fifth flip-flop, wherein a second input terminal of the second XOR gate is electrically connected to the output terminal of the fourth flip-flop, and wherein an output terminal of the second XOR gate is configured to output a second part of the phase adjustment signal.

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