Encapsulation terminal cavity and its manufacturing method
By designing cavities of a specific shape in the conductive terminals, the problem of over-etching was solved, ensuring a stable connection between the conductive terminals and the PCB, improving the reliability of AOI fillet slope inspection, and achieving a stable electrical connection of the conductive terminals.
Patent Information
- Application Number
- CN202010999449.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Priority Date
- 2019-09-30
- Filing Date
- 2020-09-22
- Publication Date
- 2025-11-14
- Estimated Expiration
- 2040-09-22
AI Technical Summary
In existing technologies, the etching process is prone to over-etching when forming conductive terminals, which leads to unsuccessful etching when the length of the conductive terminal exceeds the threshold. Furthermore, the reliability of AOI fillet slope inspection is reduced, making it difficult to form a stable solder connection.
A novel conductive terminal design is adopted, and a cavity is etched to form a cavity that extends at least half of the bottom surface and at least half of the side surface of the conductive terminal. The etching depth is controlled to ensure that the conductive material flows stably in the reflow soldering process and forms a connection that meets the AOI fillet slope requirements.
This effectively avoids over-etching, ensures the stability of conductive terminal connections, improves the reliability of AOI fillet slope inspection, and achieves a stable electrical connection between conductive terminals and the PCB.
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Figure CN112582367B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a packaged terminal cavity and a method for producing the same. Background Technology
[0002] Circuits are formed on semiconductor dies and then encapsulated within a molded component (e.g., epoxy resin) to protect the circuits from damage caused by external factors such as moisture, heat, and blunt force. Summary of the Invention
[0003] In some instances, a package includes: a molded part; and a conductive terminal that contacts the molded part and has a first surface exposed to a first surface of the molded part. The conductive terminal includes a cavity having a first portion extending along at least half of the first surface of the conductive terminal and a second portion extending along less than half of the first surface of the conductive terminal.
[0004] In some instances, a method includes: providing a conductive material layer; positioning a photoresist on the conductive material layer; positioning a mask over the photoresist; and exposing and developing the photoresist via the mask to create a pattern on the photoresist. The method further includes using the pattern to etch the conductive material layer to create a cavity having a first portion extending along at least half of a first surface of the conductive material layer and a second portion extending along less than half of the first surface of the conductive material layer, the first portion and the second portion being in fluid communication with each other. The method further includes using the conductive material layer to create a chip package, the first surface of the conductive material layer being exposed to a first surface of the chip package. Attached Figure Description
[0005] For a detailed description of the various examples, reference will now be made to the accompanying drawings, in which:
[0006] Figure 1 A side view depicting a package with conductive terminals according to various examples.
[0007] Figure 2 A bottom view depicting a package with conductive terminals according to various examples.
[0008] Figure 3 Perspective views depicting packages with conductive terminals according to various examples.
[0009] Figure 4A and 4B Depicts cross-sectional views of conductive terminals according to various examples.
[0010] Figure 5A bottom view depicting a portion of a lead frame strip containing conductive terminals, based on various examples.
[0011] Figures 6A-6H The process flow for manufacturing conductive terminals is described based on various examples.
[0012] Figure 7 A flowchart depicts a method for manufacturing conductive terminals based on various examples. Detailed Implementation
[0013] To facilitate communication with external electronic devices, circuitry within the package is electrically coupled to conductive terminals. These conductive terminals are positioned inside the package but exposed on one or more outer surfaces of the package. By coupling the conductive terminals to external electronic devices, a pathway is formed to exchange electrical signals between the internal circuitry and the external electronic devices via the conductive terminals.
[0014] Such packages are often mounted on printed circuit boards (PCBs), such as in smartphones, personal computers, or other electronic devices. To mount the package onto the PCB, a conductive material, such as solder, is appropriately positioned between the conductive terminals of the package and electrical contacts on the PCB to which the conductive terminals are to be coupled. The conductive material is then melted and subsequently allowed to solidify (this process is often referred to as "reflow soldering"), thereby creating an electrical path between the circuitry within the package and one or more other electronic devices mounted on the PCB. Such packages, and more specifically, the conductive terminals of the package are therefore referred to as "wettable." For example, these conductive terminals may be referred to as "solder-wettable."
[0015] A stable connection is desired between the conductive terminals of the package and the corresponding electrical contacts on the PCB, as weak connections are easily broken, thereby terminating the possibility of electrical communication. One technique for establishing such a stable connection involves creating a single cavity on the bottom surface of the conductive terminal, on the side surface of the conductive terminal, and at the corner of the conductive terminal between the bottom and side surfaces. During a reflow soldering process, a conductive material (e.g., solder) establishes the aforementioned connection between the conductive terminal and the PCB, and simultaneously, a portion of the conductive material flows into this cavity via the bottom surface, through the cavity, and out of the cavity at a portion located on the side surface of the conductive terminal. The portion of the conductive material flowing out of the side surface of the conductive terminal is called a "rounded corner." If the amount of conductive material used during the reflow soldering process is sufficient to establish a stable connection, the rounded corner will have a sharply sloping surface, with the highest point of the rounded corner slope at the side surface of the conductive terminal and the lowest point at the surface of the PCB. On the other hand, if the amount of conductive material used is insufficient to form a stable connection, or if it otherwise impairs the reflow soldering process, the rounded corner will not have a sufficient slope and will be relatively flat. For example, appropriate instruments such as automated optical inspection (AOI) tools can be used to determine the fillet slope. Checking the fillet slope is often used to determine whether a stable connection has been formed.
[0016] During leadframe fabrication, photolithography and etching processes are used to form cavities in the conductive terminals. The cavity shape is typically a quadrant sphere, making it appear approximately semi-circular on each of the bottom and side surfaces of the conductive terminal. Etching such cavities into the conductive terminal is generally successful when the terminal length is less than or equal to a certain threshold. However, when the terminal length exceeds this threshold, the etching process is often unsuccessful because the etchant penetrates too deeply into the conductive terminal, often eroding through it. Reducing the surface area of the conductive terminal exposed for etching does not satisfactorily correct this problem, as it decreases the reliability of the AOI fillet slope inspection described above. Typically, for reliable AOI fillet slope inspection, the length of the conductive terminal surface exposed for etching (and therefore, the cavity length) should be at least half the length of the conductive terminal.
[0017] This invention describes various examples of novel conductive terminals and methods for manufacturing novel conductive terminals. During lead frame manufacturing, the novel conductive terminal is etched to form a cavity within the terminal, overcoming the challenges described above. Specifically, the cavity has a first portion extending along at least half of the bottom surface of the conductive terminal and a second portion extending along less than half of the bottom surface of the conductive terminal. Furthermore, the cavity extends along at least half of the side surface of the conductive terminal. This conductive terminal offers several technical advantages. For example, the formation of this generally shaped cavity mitigates the risk of over-etching challenges described above because reducing the size of the second portion relative to the first portion reduces the amount of etchant used to form the cavity. This ability to control the etching rate provides significant technical advantages because it imparts the advantage of a wide cavity region extending along at least half of the surface of the conductive terminal (e.g., conforming to customer specifications) while avoiding the disadvantages traditionally associated with such wide cavity regions (e.g., etch-through). Furthermore, the general shape of the cavity facilitates proper AOI fillet slope testing because the length of the first portion along the bottom surface (and the length of the cavity along the side surface) is at least 50% of the length of the conductive terminal.
[0018] Figure 1-3 Various views of a package including multiple conductive terminals are provided, at least some of which are novel conductive terminals described herein. Figure 4A and 4B Provides a cross-sectional view of a novel conductive terminal. Figure 5-7 The fabrication of this novel conductive terminal is depicted. Each of these figures will now be described in turn.
[0019] Figure 1 A side view is depicted of a package 100 (e.g., a quad flat no-lead (QFN) package) with conductive terminals according to various embodiments. Specifically, package 100 includes a molded part 102 (e.g., epoxy resin) having multiple surfaces including a bottom surface 112 and side surfaces 114. Package 100 can accommodate, for example, a semiconductor die mounted on a die pad. Package 100 further includes multiple conductive terminals 104 on each side surface of package 100 and on the bottom surface of package 100. The surfaces of conductive terminals 104 exposed to the side surface 114 are marked with the numeral 104A. Package 100 further includes multiple conductive terminals 108 on each side surface of package 100 and on the bottom surface of package 100. The surfaces of conductive terminals 108 exposed to the side surface 114 are marked with the numeral 108A. Conductive terminals 108 differ from conductive terminals 104 in their respective lengths, wherein conductive terminals 108 are longer than conductive terminals 104. In some instances, conductive terminal 108 is at least 0.500 mm longer than conductive terminal 104. In some instances, the length of conductive terminal 108 is between 0.300 mm and 1.0 mm, and the length of conductive terminal 104 is between 0.200 mm and 0.300 mm.
[0020] Still referencing Figure 1 Conductive terminal 104 includes a cavity 106. A portion of cavity 106 extending along the surface 104A of conductive terminal is designated 106A. Similarly, conductive terminal 108 includes a cavity 110. A portion of cavity 110 extending along the surface 108A of conductive terminal is designated 110A. In some embodiments, a portion 106A of cavity 106 extends along at least half the length of its respective conductive terminal 104, and the portion 106A abuts the edge (or corner) of its respective conductive terminal 104. In some embodiments, a portion 110A of cavity 110 extends along at least half the length of its respective conductive terminal 108, and the portion 110A abuts the edge of its respective terminal 108. Cavities 106 and 110 allow conductive material (e.g., solder) to flow through them during a reflow soldering process.
[0021] Figure 2 A bottom view depicting package 100 according to various instances is provided. Package 100 includes... Figure 1 The conductive terminals 104, 108 and cavities 106, 110 are the same as those depicted in the text and described above. However, Figure 2 The conductive terminals 104, 108 and cavities 106, 110 formed on the bottom surface 112 of the package 100 are depicted. The surface of the conductive terminal 104 exposed to the bottom surface 112 is marked with the numeral 104B. The surface of the conductive terminal 108 exposed to the bottom surface 112 is marked with the numeral 108B. A portion of the cavity 106 extending along the bottom surface 104B of the conductive terminal is marked as 106B. The portion 106B abuts the edge of its corresponding conductive terminal 104 and extends along at least half the length of its corresponding conductive terminal 104. The portions 106A and 106B are in fluid communication with each other.
[0022] Still referencing Figure 2The portions of cavity 110 extending along the bottom surface 108B of the conductive terminal are designated as 110B and 110C. Portion 110B of cavity 110 is adjacent to the edge of its corresponding conductive terminal 108, and extends at least half the length of its corresponding conductive terminal 108. In some instances, the lengths of portions 110A and 110B are the same for each cavity 110. Portion 110C of cavity 110 is positioned further from the edge of its corresponding conductive terminal 108 than its corresponding portion 110B. In some instances, portion 110C extends less than half the length of its corresponding conductive terminal 108. In some instances, portion 110C is formed in a circular or semi-circular manner in the plane of the bottom surface 108B. In some instances, portions 110A, 110B, and 110C are in fluid communication with each other. During the reflow soldering process, conductive material (e.g., solder) may flow into cavities 106 and 110 via portions 106B and 110B / 110C, respectively, and flow out of cavities 106 and 110 via portions 106A and 110A, respectively. The fillets formed when the conductive material flows out of portions 106A and / or 110A and onto the PCB can be evaluated using AOI technology, as explained above.
[0023] Figure 3 Depicts perspective views of encapsulation 100 based on various instances. Figure 3 The inverted package 100 is depicted, with the bottom surface 112 at the top. As explained above, conductive terminals 104, 108 are exposed on the bottom and side surfaces of the molded part 102, and cavities 106, 110 abut the corners of their respective conductive terminals 104, 108, as shown. When the package 100 is mounted to a PCB (or other surface), conductive material is deposited (e.g., printed) on the PCB at the locations where the conductive terminals 104, 108 of the package 100 will make electrical contact with the PCB. The bottom surface 112 is then mounted to the PCB and aligned with the conductive material such that the conductive material aligns with the cavities 106, 110 along the bottom surface 112. During the reflow soldering process, conductive material flows into cavities 106, 110 via portions 106B, 110B, and 110C, and flows out of the cavities via portions 106A and 110A, thereby forming the aforementioned rounded corners on the PCB surface adjacent to portions 106A and 110A. Because the lengths of portions 106A, 106B, 110A, and 110B are at least half the length of their corresponding conductive terminals, the rounded corner visual inspection process described above can be properly performed. Furthermore, once the reflow soldering process is complete, the reflow-soldered conductive material hardens and forms a connection between each conductive terminal 104, 108 and the corresponding location on the PCB to which the terminal will be electrically coupled.
[0024] Figure 4A and 4B Cross-sectional views of conductive terminals are depicted according to various examples. Specifically, Figure 4A Draw along lines 200 and 202 respectively. Figure 2 Cross-sectional view of conductive terminals 104 and 108. Figure 4A The conductive terminals 104A and 108A and bottom surfaces 104B and 108B are shown. Figure 4A The view represents two conductive terminals 104, 108, because conductive terminals 104, 108 are similar or possibly identical along lines 200, 202, although the scope of the invention is not limited thereto. Cavities 106, 110 are also depicted. In some instances, cavity 106 has the same depth along line 200 as cavity 110 has the same depth along line 202. Figure 4B Draw along line 204 ( Figure 2 A cross-sectional view of the conductive terminal 108. The cavity 110 along line 204 does not extend as deeply into the conductive terminal 108 as the cavity 110 along line 202, and therefore... Figure 4A The cavity 110 appears to be deeper than Figure 4B Cavity 110. Figure 4B The conductive terminal side surface 108A and bottom surface 108B are also depicted respectively.
[0025] Figure 5 Depict a bottom view of a portion of the leader box with 500 according to various examples. Figure 5 The view shown depicts the bottom surfaces 104B and 108B of the conductive terminals before they are trimmed and encapsulated into package 100. (See the following text relative to...) Figure 6A-7 The described etching of the bottom surfaces 104B and 108B of the conductive terminals forms cavities 106 and 110. As shown, the photolithography and etching processes can be configured as desired to produce any of a variety of cavity shapes, sizes, and configurations, meaning that the scope of the invention is not limited to the specific cavity sizes, shapes, and configurations explicitly disclosed herein. After the cavity is formed, the lead frame strip 500 can be sawn along line 502. Because of the error range in the sawing process, the lead frame strip 500 can actually be sawn anywhere between amplitudes 504 and 506. Therefore, the cavity should be formed to account for this error range. For example, a portion 110B of cavity 110 can be formed to a sufficient depth in the plane corresponding to the bottom surface 108B of the conductive terminal such that a portion 110B exists within the sawn conductive terminal, regardless of where the lead frame strip 500 is sawn within amplitudes 504 and 506. The specific locations of 504 and 506 depend on the precise method and size of the leadframe manufacturing and can be adjusted as desired (e.g., to facilitate deeper subsequent etching, which may occur, for example, when the area between locations 504 and 506 is increased).
[0026] Figures 6A-6H The process flow for manufacturing conductive terminals, such as conductive terminal 108, is described according to various examples. Figure 7A flowchart depicts a method 700 for manufacturing a conductive terminal, such as conductive terminal 108, according to various examples. The method involves performing operations on the bottom surfaces 104B and 108B of the conductive terminal relative to... Figure 6A-7 The photolithography and etching processes described are now described in series. Figure 6A -H and 7. Method 700 includes providing a conductive material layer, such as a conductive material suitable for manufacturing a lead frame (e.g., copper) (702). Figure 6A The supply of conductive material layer 600 is depicted. Next, method 700 includes positioning a photoresist on the conductive material layer (704). Figure 6B The step of adding photoresist 602 onto the conductive material layer 600 is described. Next, method 700 includes positioning a mask over the photoresist (706). Figure 6C The step of positioning mask 604 over photoresist 602 is depicted. Mask 604 can be customized such that, after exposure and development of photoresist 602 as described below, appropriate areas of conductive material 600 are exposed to etch cavities 106 and / or 110. Thus, for example, mask 604 is at least partially shaped similarly to portions 110B, 110C of cavity 110.
[0027] Method 700 further includes exposing the photoresist via a mask and developing the photoresist to create a pattern on the photoresist (708). Figure 6D The image depicts light 606 being applied to photoresist 602 via mask 604, thereby making region 608 soluble in the developer, such as... Figure 6E The description. Figure 6F The development of photoresist 602 and, more specifically, region 608, causes region 608 to be removed according to a pattern of mask 604, as depicted in numeral 610. Method 700 then includes using the pattern to etch a conductive material layer to create an aperture having a first portion extending along at least half of a first surface of the conductive material layer and a second portion extending along less than half of the first surface of the conductive material layer, the first portion and the second portion being in fluid communication with each other (710). Figure 6G The etching of this cavity in the conductive material layer 600 is depicted using any suitable etchant, such as a chemical etchant suitable for etching copper. The numeral 110 depicts the etched cavity 110. Similar techniques can be used to etch cavity 106.
[0028] Next, method 700 includes stripping the photoresist (712), such as Figure 6HThe removal of photoresist 602 is depicted. Method 700 optionally includes etching a conductive material layer to form additional features as desired. One or more rounds of additional etching can be used to etch any of a variety of additional features into the conductive material layer 600. In some instances, multiple rounds of etching can be used to etch cavity 110. For example, a mask can be specifically designed to etch only partially during the first round of etching, and another mask can be used in the second round of etching to form, for example... Figure 1 and 2 The features shown in the diagram. Method 700 further includes optionally depositing a conductive material layer with, for example, nickel-palladium-gold or another suitable plating alloy. Method 700 further includes using the conductive material layer to fabricate a chip package, with a first surface of the conductive material layer exposed on a first surface (716) of the chip package. For example, etched conductive material may be incorporated into the chip package as conductive terminals for transmitting electrical signals to and from a semiconductor die housed within the chip package.
[0029] The foregoing discussion is intended to illustrate the principles and various embodiments of the invention. Once fully understood, numerous variations and modifications will become apparent to those skilled in the art. The following claims are intended to cover all such variations and modifications.
Claims
1. A package comprising: Molded parts; and A conductive terminal, which contacts the molded part and has a first surface exposed to a first surface of the molded part, the conductive terminal comprising a cavity having a first portion extending along at least half of the first surface of the conductive terminal and a second portion extending along less than half of the first surface of the conductive terminal, wherein the first portion and the second portion are in fluid communication with each other, the cavity being exposed at a corner of the conductive terminal, at which the first surface of the conductive terminal meets the second surface of the conductive terminal, and wherein the second portion is positioned further away from the corner than the first portion.
2. The package of claim 1, wherein the cavity extends at least half the length of the second surface of the conductive terminal.
3. The package according to claim 1, wherein the second portion has a semi-circular shape in the plane of the first surface.
4. The package according to claim 1, further comprising another conductive terminal having a length greater than that of the other conductive terminal.
5. The package according to claim 1, wherein the package comprises a quad flat no-leads QFN package.
6. The package of claim 1, wherein at least a portion of the conductive terminal comprises a nickel-palladium-gold plating.
7. A package comprising: Molded parts; and A conductive terminal, which contacts the molded part, wherein a first surface of the conductive terminal is exposed to a first surface of the molded part and a second surface of the conductive terminal is exposed to a second surface of the molded part, the conductive terminal comprising a cavity exposed to the first surface and the second surface of the conductive terminal. The cavity is comprised of a first portion and a second portion on the first surface of the conductive terminal, the first portion extending along at least half the length of the first surface of the conductive terminal, and the second portion extending along less than half the length of the first surface of the conductive terminal. The first portion and the second portion are in fluid communication with each other. The cavity is exposed at a corner of the conductive terminal, where the first surface and the second surface of the conductive terminal meet. The second portion is positioned further from the corner than the first portion. The cavity extends at least half the length of the first surface of the conductive terminal.
8. The package of claim 7, wherein the package comprises a quad flat no-leads (QFN) package.
9. The package of claim 7, wherein the conductive terminal comprises a nickel-palladium-gold plating.
10. An etching method, comprising: Provide a conductive material layer; The photoresist is positioned on the conductive material layer; Position the mask above the photoresist; The photoresist is exposed through the mask and the photoresist is developed to create a pattern on the photoresist; The conductive material layer is etched using the pattern to create a cavity having a first portion extending along at least half of a first surface of the conductive material layer and a second portion extending along less than half of the first surface of the conductive material layer, the first portion and the second portion being in fluid communication with each other. and The conductive material layer is used to create a chip package, wherein the first surface of the conductive material layer is exposed on the first surface of the chip package. The cavity is exposed at a corner where the first surface and the second surface of the conductive material layer meet, and the second portion is positioned further away from the corner than the first portion.
11. The etching method of claim 10, wherein the cavity extends along at least half of the second surface of the conductive material layer.
12. The etching method of claim 10, wherein the second surface of the conductive material layer is exposed to the second surface of the chip package.
13. The etching method of claim 10, further comprising plating at least a portion of the conductive material layer with nickel-palladium-gold.
14. A package comprising: Molded parts; and The first conductive terminal and the second conductive terminal that are in contact with the molded part; The first conductive terminal includes a first surface exposed to a first surface of the molded part, and the first conductive terminal includes a first cavity having a first portion extending along at least half of the first surface of the first conductive terminal and a second portion extending along less than half of the first surface of the first conductive terminal. The second conductive terminal includes a first surface exposed to the first surface of the molded part, and the second conductive terminal includes a second cavity having a first portion extending along less than half of the first surface of the second conductive terminal. The first portion and the second portion of the first conductive terminal are in fluid communication with each other. The first cavity and the second cavity are respectively exposed at the corner of the first conductive terminal and the corner of the second conductive terminal, wherein the first surface of the first conductive terminal and the second surface of the first conductive terminal meet at the corner of the first conductive terminal, and the first surface of the second conductive terminal and the second surface of the second conductive terminal meet at the corner of the second conductive terminal. The second portion of the first conductive terminal is positioned further away from the corner than the first portion of the first conductive terminal.
15. The package of claim 14, wherein the area of the first surface of the first conductive terminal is greater than the area of the first surface of the second conductive terminal.
Citation Information
Patent Citations
Method of manufacturing semiconductor device and semiconductor device
US20160254214A1