Vertical nonvolatile memory device

Abstract

A vertical nonvolatile memory device includes a stack including gate patterns and interlayer insulation patterns stacked in a stacking direction, the stack having a through-hole extending in the stacking direction in the gate pattern and in the interlayer insulation pattern; a semiconductor pillar in the through-hole and extending in the stacking direction; a data storage structure between the gate pattern and the semiconductor pillar in the through-hole, the data storage structure including a charge storage layer; and a dummy charge storage layer in the through-hole on a sidewall of the interlayer insulation pattern toward the semiconductor pillar.

Description

TECHNICAL FIELD

[0001] Embodiments relate to a vertical nonvolatile memory device. BACKGROUND

[0002] A nonvolatile memory device retains stored data even when power is not supplied thereto. To increase the integration of a nonvolatile memory device, unit transistors can be stacked in a vertical direction. SUMMARY

[0003] Embodiments are directed to a vertical nonvolatile memory device including a stack including gate patterns and interlayer insulation patterns alternately stacked in a stacking direction, the stack having through holes extending in the stacking direction in the gate patterns and in the interlayer insulation patterns, the stack including a recessed hole communicating with the through holes and recessed from sidewalls of the interlayer insulation patterns in a direction toward the gate patterns, a data storage structure including a blocking insulation layer in the recessed hole in contact with the gate patterns, a charge storage layer in the recessed hole in contact with the blocking insulation layer, and a tunnel insulation layer in contact with the charge storage layer and extending in the stacking direction in the through holes, a semiconductor pillar in contact with the data storage structure and extending in the stacking direction in the through holes and the recessed hole, and a dummy charge storage layer in the through holes on the sidewalls of the interlayer insulation patterns toward the semiconductor pillar.

[0004] Embodiments are directed to a vertical nonvolatile memory device including a stack including gate patterns and interlayer insulation patterns alternately stacked in a stacking direction, the stack having through holes extending in the stacking direction in the gate patterns and in the interlayer insulation patterns, the stack including a recessed hole communicating with the through holes and recessed from sidewalls of the interlayer insulation patterns in a direction toward the gate patterns, a data storage structure including a blocking insulation layer in the recessed hole in contact with the gate patterns, a charge storage layer in the recessed hole in contact with the blocking insulation layer, and a tunnel insulation layer in contact with the charge storage layer and extending in the stacking direction in the through holes, a semiconductor pillar in contact with the data storage structure and extending in the stacking direction in the through holes and the recessed hole, and a dummy charge storage layer in the through holes on the sidewalls of the interlayer insulation patterns toward the semiconductor pillar.

[0005] Embodiments are also directed to a vertical nonvolatile memory device including a stack including gate patterns and interlayer insulation patterns alternately stacked, the stack having a through-hole extending in a stacking direction in the gate patterns and the interlayer insulation patterns, the stack including a curved surface recessed hole recessed from a sidewall of the interlayer insulation patterns in a direction of the gate patterns, the curved surface recessed hole being in communication with the through-hole and having a curved surface; a curved surface data storage structure in the curved surface recessed hole, the curved surface data storage structure including a curved surface blocking insulation layer in contact with the gate patterns, a curved surface charge storage layer in contact with the curved surface blocking insulation layer, and a curved surface tunnel insulation layer in contact with the curved surface charge storage layer in the curved surface recessed hole and extending in the stacking direction in the through-hole; an isolation insulation layer in the curved surface recessed hole and the through-hole in the stacking direction to contact the curved surface charge storage layer; a dummy charge storage layer on a sidewall of the interlayer insulation patterns in the through-hole, the dummy charge storage layer being separated by the isolation insulation layer; and a curved surface semiconductor pillar on a sidewall of the curved surface tunnel insulation layer and one side of the dummy charge storage layer and extending in the stacking direction in the through-hole. BRIEF DESCRIPTION OF DRAWINGS

[0006] Features will become apparent to those of ordinary skill in the art upon examination of the following details description of example embodiments in conjunction with the accompanying drawings, in which:

[0007] Figure 1 and Figure 2 A circuit diagram of a vertical nonvolatile memory device according to an example embodiment is shown;

[0008] Figure 3 A plan view of a main portion of a cell transistor in a vertical nonvolatile memory device according to an example embodiment is shown;

[0009] Figure 4A A cross-sectional view of the vertical nonvolatile memory device shown in Figure 3 along line A-A' according to an example embodiment is shown;

[0010] Figure 4B An enlarged view of a region of Figure 4A is shown;

[0011] Figure 5A A cross-sectional view of a vertical nonvolatile memory device according to an example embodiment is shown;

[0012] Figure 5B An enlarged view of a region of Figure 5A is shown;

[0013] Figure 6A to Figure 6K A cross-sectional view for describing a method of manufacturing a vertical nonvolatile memory device according to an example embodiment is shown;

[0014] Figure 7A to Figure 7H A cross-sectional view for describing a method of manufacturing a vertical nonvolatile memory device according to an example embodiment is shown.

[0015] Figure 8A and Figure 8B A cross-sectional view for describing a method of manufacturing a vertical nonvolatile memory device according to an example embodiment is shown.

[0016] Figure 9A and Figure 9B A cross-sectional view for describing a method of manufacturing a vertical nonvolatile memory device according to an example embodiment is shown.

[0017] Figure 10A and Figure 10B A cross-sectional view for describing a method of manufacturing a vertical nonvolatile memory device according to an example embodiment is shown.

[0018] Figure 11 A schematic block diagram of a vertical nonvolatile memory device according to an example embodiment is shown.

[0019] Figure 12 A schematic diagram of a card according to an example embodiment is shown; and

[0020] Figure 13 A schematic diagram of a system according to an example embodiment is shown. DETAILED DESCRIPTION

[0021] Hereinafter, a vertical nonvolatile memory device will be described taking a negative-and (NAND) flash memory device as an example.

[0022] Figure 1 and Figure 2 is a circuit diagram of a vertical nonvolatile memory device 10 according to an example embodiment.

[0023] Figure 1 and Figure 2 are a two-dimensional circuit diagram and a three-dimensional circuit diagram, respectively, of a vertical nonvolatile memory device 10, i.e., a NAND flash memory device.

[0024] In the vertical nonvolatile memory device 10, N number of cell transistors M0 to Mn (M0 ~ Mn) are connected in series to constitute a cell string S. A plurality of cell strings S are connected in parallel between a bit line BL0 to BLn (BL0 ~ BLn) and a ground selection line GSL.

[0025] In the present example embodiment, the vertical nonvolatile memory device 10 includes cell strings S in which cell transistors M0 to Mn are connected in series, word lines WL0 to WLn (WL0 to WLn) for selecting the cell transistors M0 to Mn, and a row decoder configured to drive the word lines WL0 to WLn.

[0026] In the present example embodiment, the vertical nonvolatile memory device 10 includes a string selection line SSL connected to one side of the cell string S and including a string selection transistor ST1, bit lines BL0 to BLn connected to a drain of the string selection transistor ST1, and a ground selection line GSL connected to the other side of the cell string S and including a ground selection transistor ST2. Further, in the vertical nonvolatile memory device 10, a common source line CSL is connected to a source of the ground selection transistor ST2.

[0027] The vertical nonvolatile memory device 10 can include a unit string including the cell string S and the string selection transistor ST1 and the ground selection transistor ST2 connected to the upper and lower portions of the cell string S, respectively. Although Figure 1 and Figure 2 One string selection transistor ST1 and one ground selection transistor ST2 are shown connected to the cell string S to constitute a unit string, but two or more string selection transistors ST1 can be formed, and two or more ground selection transistors ST2 can be formed.

[0028] The cell transistors M0 to Mn can include 2m cell transistors formed in one cell string S (where m is a natural number equal to or greater than 1). For example, two, four, eight, or sixteen cell transistors M0 to Mn can be connected in series in one cell string S. For convenience, Figure 1 and Figure 2 Only four of the cell transistors M0 to Mn and four of the word lines WL0 to WLn are shown in FIG. 1.

[0029] In Figure 2 In FIG. 1, the X direction can be a direction in which the word lines WL0 to WLn extend, i.e., a word line direction. The Y direction can be a direction in which the bit lines BL0 to BLn extend, i.e., a bit line direction. The Z direction can be a direction perpendicular to the word lines WL0 to WLn and the bit lines BL0 to BLn.

[0030] Figure 3 is a plan view of a main portion of a cell transistor in the vertical nonvolatile memory device 10 according to an example embodiment.

[0031] The vertical nonvolatile memory device 10 can include a substrate 202 (see Figure 4AMultiple stacked STSs are placed on top of each other and spaced apart. The stacked STSs can be formed on the XY plane. The stacked STSs can be formed on the plane formed along the word line direction (X direction) and the bit line direction (Y direction).

[0032] Through-holes 261, spaced apart from each other, can be formed in the stack STS. Through-holes 261 can be holes penetrating the stack STS from its top surface to its bottom surface. Recessed holes 262 can be formed around the through-holes 261 in the stack STS. Recessed holes 262 can be holes recessed into the stack STS. Recessed holes 262 can be holes extending from the interior of the through-holes 261 toward the stack STS. Recessed holes 262 can communicate with the through-holes 261.

[0033] The vertical structure VS can be formed in the through-hole 261 and the recessed hole 262. As described below, the cell transistors of the vertical non-volatile memory device 10 can be formed in the vertical structure VS. The vertical structure VS may include semiconductor pillars 274 (see...). Figure 4A ), data storage structure 288 (see Figure 4B ), Virtual charge storage layer 281 (see Figure 4A ) and insulating layer 285 (see Figure 4A ).

[0034] Figure 4A According to an example implementation Figure 3 The image shows a cross-sectional view of the vertical non-volatile storage device 10, taken along line A-A'. Figure 4B It shows Figure 4A A magnified view of a region.

[0035] Figure 4A The vertical non-volatile memory device 10 can have a bilaterally symmetrical structure along the through-hole 261. Therefore, although Figure 4A Based on only Figure 3 Half of the through-hole 261 shows the vertical non-volatile storage device 10, but it will be understood that, relative to... Figure 4A As shown in the orientation, the gate pattern 320 and the interlayer insulating pattern 220 can also be formed on the right side of the through-hole 261.

[0036] For convenience, Figure 4A The vertical non-volatile memory device 10 is shown with only three word lines WL0, WL1 and WL2 and three unit transistors M0, M1 and M2. Figure 4B A magnified image of a word line WL0 and a unit transistor M0 is shown for the vertical non-volatile memory device 10. Figure 4A and Figure 4B In the text, the X direction can be the direction of the character line, and the Z direction can be the direction perpendicular to the direction of the character line.

[0037] According to the present example embodiment, the vertical nonvolatile memory device 10 includes a stack STS. The stack STS can include the gate patterns 320 and the interlayer insulation patterns 220 alternately stacked on the substrate 202. The gate patterns 320 can include first to third gate patterns 311, 313, and 315.

[0038] The substrate 202 can include a single-crystal semiconductor material. The substrate 202 can include, for example, a single-crystal silicon substrate. The single-crystal silicon substrate can include a single-crystal silicon wafer, for example, a P-type single-crystal silicon wafer. An impurity region (not shown), for example, an N-type impurity region, serving as a common source line CSL (see Figure 1 and Figure 2 ) can be formed in the substrate 202.

[0039] The interlayer insulation patterns 220 can include first to fourth interlayer insulation patterns 211, 213, 215, and 217. As described below, the gate patterns 320 can be formed in cavities 278 between the first to fourth interlayer insulation patterns 211, 213, 215, and 217. The cavities 278 can be gaps between the first to fourth interlayer insulation patterns 211, 213, 215, and 217.

[0040] In Figure 4A and Figure 4B , a height Lg of the gate patterns 320, for example, a height Lg of the first gate pattern 311, can indicate a gate length Lg in, for example, a Z direction or a vertical direction. A height Ls of the interlayer insulation patterns 220 can indicate a space length between the gate patterns 320 in, for example, the Z direction or the vertical direction.

[0041] The stack STS can include through-holes 261 extending in a stacking direction, that is, a Z direction, in the gate patterns 320 and the interlayer insulation patterns 220. The stacking direction, that is, the Z direction, can be a direction in which the gate patterns 320 and the interlayer insulation patterns 220 are stacked.

[0042] The stack STS can include a recessed hole 262 that can be recessed toward the gate patterns 320 from a sidewall 220SW of the interlayer insulation patterns 220 by a first depth R1. The recessed hole 262 can be in communication with the through-holes 261. A surface of the recessed hole 262 (the surface in contact with the gate patterns 320) can be curved.

[0043] When the recessed hole 262 is formed, a data storage structure 288 can be formed or buried in the recessed hole 262, and thus, separation between the cell transistors M0, M1, and M2 can be easily performed. In another implementation, the recessed hole 262 can not be formed.

[0044] A vertical structure VS can be formed in the through-hole 261. The vertical structure VS can include a semiconductor pillar 274 extending in the stacking direction in the through-hole 261. The semiconductor pillar 274 can include a semiconductor pattern having a cylindrical shape or a columnar shape on the substrate 202. As shown in FIG. 2A, the semiconductor pillar 274 can be arranged repeatedly at regular intervals from each other in the X direction and the Y direction. Figure 3 and Figure 4A As shown in FIG. 2A, the semiconductor pillar 274 can be arranged repeatedly at regular intervals from each other in the X direction and the Y direction.

[0045] The semiconductor pillar 274 can be formed on the substrate 202 to extend in the vertical direction. The semiconductor pillar 274 can include, for example, a single-crystal silicon layer. The semiconductor pillar 274 can provide an active region of a vertical nonvolatile semiconductor memory device. For example, the semiconductor pillar 274 can serve as a channel layer of the unit transistors M0, M1, and M2.

[0046] The data storage structure 288 can be located between the gate pattern 320 and the semiconductor pillar 274. When the recess hole 262 is formed, the semiconductor pillar 274 can be in contact with the data storage structure 288, and can extend in the stacking direction in the through-hole 261.

[0047] The data storage structure 288 can include a charge storage layer 280. The charge storage layer 280 can include a charge-trapping layer. The data storage structure 288 can include, in order from a direction toward the gate pattern 320, a tunnel insulating layer 272, the charge storage layer 280, and blocking insulating layers 266 and 284 on the semiconductor pillar 274.

[0048] The tunnel insulating layer 272 can include a tunnel oxide layer. The tunnel insulating layer 272 can be a thermal oxide film formed by, for example, thermally oxidizing a surface of the semiconductor pillar 274. The tunnel insulating layer 272 can include silicon oxide formed by, for example, a thermal oxidation process. The tunnel insulating layer 272 can include an oxide formed by, for example, a chemical vapor deposition method.

[0049] The charge storage layer 280 can include silicon nitride or metal oxide capable of trapping a charge. In this case, the charge can be stored in the charge storage layer 280 by a charge-trapping method. The charge storage layer 280 can include silicon nitride that can be deposited with a small thickness.

[0050] The blocking insulating layers 266 and 284 can include silicon oxide or metal oxide having a dielectric constant higher than that of silicon oxide. The unit transistors M0, M1, and M2 can be electrically turned on and off by Fowler-Nordheim tunneling (F-N tunneling) or hot electron injection.

[0051] In an example embodiment, a recessed hole 262 recessed from a sidewall of the interlayer insulation pattern 220 can be formed, and the data storage structure 288 can include a blocking insulation layer 266 and 284 in contact with the gate pattern 320 in the recessed hole 262, a charge storage layer 280 in contact with the blocking insulation layer 266 and 284 in the recessed hole 262, and a tunnel insulation layer 272 in contact with the charge storage layer 280 and extending in the through hole 261 in the stacking direction.

[0052] In an example embodiment, the recessed hole 262 can be formed to have a curved surface or side surface, and the data storage structure 288 can have a curved surface in contact with the curved surface of the recessed hole 262. Accordingly, the data storage structure 288 can include a curved surface type data storage structure.

[0053] The curved surface type data storage structure 288 can include a curved surface type blocking insulation layer 284 and 266, a curved surface type charge storage layer 280 in contact with the curved surface type blocking insulation layer 284 and 266, and a curved surface type tunnel insulation layer 272 in contact with the curved surface type charge storage layer 280 in the curved surface type recessed hole 262 and extending in the through hole 261 in the stacking direction. The data storage structure 288 having a curved surface can be in contact with the gate pattern 320 through the curved surface, and can improve the electrical characteristics of the unit transistors M0, M1, and M2.

[0054] In the present example embodiment, the gate pattern 320 and the interlayer insulation pattern 220 are alternately formed along the sidewall of the semiconductor pillar 274 and the data storage structure 288 is between the gate pattern 320 and the interlayer insulation pattern 220. Accordingly, the unit transistors M0, M1, and M2 can be formed on the sidewall of the semiconductor pillar 274. The unit transistors M0 to Mn formed on the semiconductor pillar 274, respectively, can constitute one unit string S. The unit transistors M0, M1, and M2 can be connected in series in the vertical direction along the semiconductor pillar 274.

[0055] The vertical structure VS can include a dummy charge storage layer 281 formed on the sidewall of the interlayer insulation pattern 220 toward the semiconductor pillar 274 in the through hole 261. The dummy charge storage layer 281 can have a curved type surface profile. The dummy charge storage layer 281 can be formed on a portion of the sidewall of the interlayer insulation pattern 220. The dummy charge storage layer 281 can be a layer in which no charge is stored during the operation of the unit transistors M0, M1, and M2.

[0056] The vertical structure VS can include an isolation insulating layer 285 formed in the through-hole 261 in contact with the charge storage layer 280. The isolation insulating layer 285 can include silicon oxide or metal oxide. The isolation insulating layer 285 can be integral with at least one of the barrier insulating layers 266 and 284.

[0057] In an example embodiment, when the recessed hole 262 is formed to have a curved surface, the isolation insulating layer 285 can be formed in the through-hole 261 and the curved recessed hole 262 in the stacking direction while being in contact with the curved surface type charge storage layer 280.

[0058] In the present example embodiment, the charge storage layer 280 is separated from the dummy charge storage layer 281 by the isolation insulating layer 285. Accordingly, the charge storage layer 280 can be separated and insulated from the dummy charge storage layer 281 by the isolation insulating layer 285. The charge storage layer 280 and the dummy charge storage layer 281 can have a discontinuous structure in which the charge storage layer 280 and the dummy charge storage layer 281 do not continuously extend in the stacking direction in the through-hole 261. The charge storage layer 280 and the dummy charge storage layer 281 can be on different lines in the stacking direction in the through-hole 261.

[0059] In an example embodiment, when the recessed hole 262 is formed to be recessed from the sidewall of the interlayer insulating pattern 220, the isolation insulating layer 285 can be formed in the recessed hole 262 and the through-hole 261 in the stacking direction in contact with the charge storage layer 280. The charge storage layer 280 can be separated from the dummy charge storage layer 281 by the isolation insulating layer 285.

[0060] In an example embodiment, when the recessed hole 262 is formed to be recessed from the sidewall of the interlayer insulating pattern 220, the isolation insulating layer 285 can be formed on the sidewall of the interlayer insulating pattern 220 and under the interlayer insulating pattern 220. When the recessed hole 262 is formed, the dummy charge storage layer 281, the isolation insulating layer 285, and the charge storage layer 280 can be connected to each other in the stacking direction in the recessed hole 262 and the through-hole 261.

[0061] In an example embodiment, when the curved surface type recessed hole 262 is formed to be recessed from the sidewall of the interlayer insulating pattern 220, the curved surface type semiconductor pillar 274 can extend in the stacking direction in the through-hole 261 on the sidewall of the curved surface type tunnel insulating layer 272 and one side of the dummy charge storage layer 281.

[0062] The gate pattern 320 can be formed in the cavity 278 between the interlayer insulating patterns 220 to be in contact with the sidewall of the data storage structure 288. The sidewall of the gate pattern 320 (facing the semiconductor pillar 274) can be in contact with the sidewall of the data storage structure 288.

[0063] The barrier insulating layers 266 and 284 included in the data storage structure 288 can include a plurality of insulating layers. The barrier insulating layers 266 and 284 can include a first barrier insulating layer 266 formed on a sidewall of the charge storage layer 280 and a second barrier insulating layer 284 formed on the first barrier insulating layer 266.

[0064] In an example embodiment, when the recessed hole 262 recessed from the sidewall of the interlayer insulating pattern 220 is formed, the second barrier insulating layer 284 among the barrier insulating layers 266 and 284 can be in complete contact with the gate pattern 320 in the recessed hole 262. Accordingly, the second barrier insulating layer 284 included in the barrier insulating layers 266 and 284 can be formed to be in complete contact with the sidewall of the gate pattern 320. The second barrier insulating layer 284 can be formed to be in integral contact with the sidewall of the gate pattern 320.

[0065] In an example embodiment, when the curved surface type recessed hole 262 recessed from the sidewall of the interlayer insulating pattern 220 is formed, the curved surface type barrier insulating layers 266 and 284 can be in complete contact with the gate pattern 320 in the curved surface type recessed hole 262. The curved surface type barrier insulating layers 266 and 284 can be in integral contact with the sidewall of the gate pattern 320. The curved surface type barrier insulating layers 266 and 284 can include a first barrier insulating layer 266 on a sidewall of the charge storage layer 280 and a second barrier insulating layer 284 on a sidewall of the first barrier insulating layer 266 and in contact with the gate pattern 320.

[0066] The barrier insulating layers 266 and 284 can have a discontinuous structure in which the barrier insulating layers 266 and 284 do not continuously extend in a stacking direction in the through hole 261. The charge storage layer 280 included in the data storage structure 288 can be formed on a portion of the sidewall of the gate pattern 320. The tunnel insulating layer 272 can have a continuous structure extending in the stacking direction in the through hole 261.

[0067] In the vertical nonvolatile memory device 10 having the above-described structure, the charge storage layers 280 are separated and insulated by the isolation insulating layers 285. Accordingly, in the vertical nonvolatile memory device 10, when the cell transistors M0, M1, and M2 operate, the charge storage characteristics or the charge retention characteristics of the charge storage layers 280 can be improved.

[0068] In the vertical nonvolatile memory device 10, the dummy charge storage layers 281 and / or the isolation insulating layers 285 formed on the sidewall of the interlayer insulating pattern 220 can improve the insulation characteristics or the separation characteristics between the cell transistors M0, M1, and M2.

[0069] In the vertical nonvolatile memory device 10, the data storage structure 288 can be formed in the recessed hole 262 recessed from the interlayer insulating pattern 220. In this case, since the cell transistors M0, M1, and M2 can be easily separated from each other, the data storage characteristics of the vertical nonvolatile memory device 10 can be improved.

[0070] In the vertical nonvolatile memory device 10, the curved surface type data storage structure 288 can be formed in the curved surface type recessed hole 262 recessed from the sidewall of the interlayer insulating pattern 220. In this case, the curved surface type data storage structure 288 can be in contact with the gate pattern 320 through the curved surface, and thus the electrical characteristics of the cell transistors M0, M1, and M2 can be improved.

[0071] Figure 5A is a cross-sectional view of a vertical nonvolatile memory device 10-1 according to an example embodiment; Figure 5B is Figure 5A is an enlarged view of a region of

[0072] In addition to the difference in the configuration of the data storage structure 288a and the isolation insulating layer 294 and the difference in the surface profile of the dummy charge storage layer 281a, Figure 5A and Figure 5B The vertical nonvolatile memory device 10-1 of Figure 4A and Figure 4B may be the same as the vertical nonvolatile memory device 10 of Figure 5A and Figure 5B In the vertical nonvolatile memory device 10-1 of Figure 4A and Figure 4B the same components as those of the vertical nonvolatile memory device 10 of and

[0073] may be identified with the same reference numerals, and some descriptions already set forth above can be briefly restated or omitted. Figure 5A Figure 5A Figure 3 The vertical nonvolatile memory device 10-1 of Figure 5A may have a double-sided symmetric structure along the through hole 261. Thus, although only the vertical nonvolatile memory device 10-1 based on one half (1 / 2) of the through hole 261 in

[0074] will be understood that the gate pattern 320 and the interlayer insulating pattern 220 can also be formed on the right side of the through hole 261 with respect to the orientation shown in

[0075] The stack STS-1 can include a through-hole 261 extending in a stacking direction, i.e., a Z direction, in the gate pattern 320 and the interlayer insulating pattern 220. The stack STS-1 can include a recessed hole 262-1 recessed from a sidewall 220SW of the interlayer insulating pattern 220 in a direction toward the gate pattern 320 by a second depth R2. The second depth R2 can be smaller than Figure 4A and Figure 4B a first depth R1 of the recessed hole 262 of the stack STS as illustrated.

[0076] In the present example embodiment, as a result of the isolation insulating layer 294 and the isolation insulating layer 285 being formed differently, the second depth R2 can be smaller than the first depth R1. The recessed hole 262-1 can be in communication with the through-hole 261. A surface of the recessed hole 262-1 in contact with the gate pattern 320 can be a curved surface.

[0077] When the recessed hole 262-1 is formed, the data storage structure 288a can be formed or buried in the recessed hole 262-1, and thus, separation between the unit transistors M0, M1, and M2 can be easily performed. In another implementation, the recessed hole 262-1 can not be formed.

[0078] A vertical structure VS-1 can be formed in the through-hole 261. The vertical structure VS-1 can include a semiconductor pillar 274 extending in the stacking direction in the through-hole 261. The data storage structure 288a can be between the gate pattern 320 and the semiconductor pillar 274. When the recessed hole 262-1 is formed, the semiconductor pillar 274 can be in contact with the data storage structure 288a and extend in the stacking direction in the through-hole 261.

[0079] The data storage structure 288a can include a tunnel insulating layer 272, a charge storage layer 280, and a blocking insulating layer 266 stacked in order in a direction toward the gate pattern 320 on the semiconductor pillar 274. In contrast to Figure 4A and Figure 4B The data storage structure 288a can include the blocking insulating layer 266 (also referred to as a first blocking insulating layer 266), each of which includes a single insulating layer. The blocking insulating layer 266 can include silicon oxide or metal oxide.

[0080] The vertical structure VS-1 can include a dummy charge storage layer 281a formed in the through-hole 261 on a sidewall of the interlayer insulating pattern 220 toward the semiconductor pillar 274. A surface profile of the dummy charge storage layer 281a can be different from Figure 4A and Figure 4B a surface profile of the dummy charge storage layer 281 as illustrated. For example, the dummy charge storage layer 281a can have a straight surface profile.

[0081] The vertical structure VS-1 can include an isolation insulating layer 294 formed in contact with the charge storage layer 280 in the through-hole 261. The isolation insulating layer 294 can include silicon oxide or metal oxide. In contrast to the isolation insulating layer 285 of Figure 4A and Figure 4B The isolation insulating layer 294 can not be integrally formed with the barrier insulating layer 266.

[0082] The charge storage layer 280 is separated and insulated from the dummy charge storage layer 281a by the isolation insulating layer 294. The charge storage layer 280 and the dummy charge storage layer 281a can have a discontinuous structure in which the charge storage layer 280 and the dummy charge storage layer 281a do not extend continuously in the stacking direction in the through-hole 261. The charge storage layer 280 and the dummy charge storage layer 281a can be on different lines in the stacking direction in the through-hole 261.

[0083] In an example embodiment, when the recessed hole 262-1 recessed from the sidewall of the interlayer insulating pattern 220 is formed, the isolation insulating layer 294 can be on the sidewall of the interlayer insulating pattern 220 and under the interlayer insulating pattern 220. When the recessed hole 262-1 is formed, the dummy charge storage layer 281a, the isolation insulating layer 294, and the charge storage layer 280 can be connected to each other in the stacking direction in the recessed hole 262-1 and the through-hole 261.

[0084] The barrier insulating layer 266 included in the data storage structure 288a can each include a single insulating layer. In an example embodiment, when the recessed hole 262-1 recessed from the sidewall of the interlayer insulating pattern 220 is formed, the barrier insulating layer 266 can be in complete contact with the gate pattern 320 in the recessed hole 262-1. Accordingly, the barrier insulating layer 266 can be formed to be in complete contact with the sidewall of the gate pattern 320. The barrier insulating layer 266 can be formed to be in partial contact with the sidewall of the gate pattern 320. The barrier insulating layer 266 can have a discontinuous structure in which the barrier insulating layer 266 does not continuously extend in the stacking direction in the through-hole 261.

[0085] The vertical nonvolatile memory device 10-1 having the above-described structure can have the same advantages as the vertical nonvolatile memory device 10 of Figure 4A and Figure 4B

[0086] Figure 6A to Figure 6K is a cross-sectional view for describing a method of manufacturing a vertical nonvolatile memory device 10 according to an example embodiment.

[0087] Figure 6A to Figure 6K is a cross-sectional view for describing a method of manufacturing a vertical nonvolatile memory device 10 according to an example embodiment. Figure 4A and Figure 4B ​A view of the stages in the method of vertical non-volatile storage device 10.

[0088] exist Figure 6A to Figure 6K In, with Figure 4A and Figure 4B Components that are identical to those in the drawings are indicated by the same reference numerals, and some of the descriptions above may be briefly restated or omitted.

[0089] In this example implementation, refer to Figure 6A Interlayer insulating layer 220a and sacrificial layer 260a are on substrate 202 (see Figure 4A and Figure 4B Stack them alternately several times. For example, as... Figure 6A As shown, the first interlayer insulating layer 211a, the first sacrificial layer 237a, the second interlayer insulating layer 213a, the second sacrificial layer 245a, the third interlayer insulating layer 215a, the third sacrificial layer 253a and the fourth interlayer insulating layer 217a can be sequentially formed on the substrate 202.

[0090] although Figure 6A The diagram shows an interlayer insulating layer 220a and a sacrificial layer 260a alternately formed on a substrate 202, but the sacrificial layer 260a and the interlayer insulating layer 220a may also be alternately formed on the substrate 202. The sacrificial layer 260a may be a molded layer.

[0091] The sacrificial layer 260a and the interlayer insulating layer 220a can be formed by chemical vapor deposition. The sacrificial layer 260a may include a material that is etch-selective to the interlayer insulating layer 220a. The sacrificial layer 260a may include a material that can be easily removed by a wet etching process. The sacrificial layer 260a may include silicon nitride. The interlayer insulating layer 220a may include silicon oxide.

[0092] The first sacrificial layer 237a may comprise a triple layer of a first lower sacrificial layer 231a, a first intermediate sacrificial layer 233a, and a first upper sacrificial layer 235a. The first intermediate sacrificial layer 233a may comprise a material having an etch rate higher than that of the material in the first lower sacrificial layer 231a and the first upper sacrificial layer 235a. In one example embodiment, the first intermediate sacrificial layer 233a may comprise silicon nitride (SiN) having a higher nitrogen (N) concentration than the SiN in the first lower sacrificial layer 231a and the SiN in the first upper sacrificial layer 235a.

[0093] The second sacrificial layer 245a can include a triple layer of a second lower sacrificial layer 239a, a second intermediate sacrificial layer 241a, and a second upper sacrificial layer 243a. The second intermediate sacrificial layer 241a can include a material having an etching rate higher than etching rates of a material of the second lower sacrificial layer 239a and a material of the second upper sacrificial layer 243a. In an example embodiment, the second intermediate sacrificial layer 241a can include SiN having a nitrogen concentration higher than nitrogen concentrations of SiN of the second lower sacrificial layer 239a and SiN of the second upper sacrificial layer 243a.

[0094] The third sacrificial layer 253a can include a triple layer of a third lower sacrificial layer 247a, a third intermediate sacrificial layer 249a, and a third upper sacrificial layer 251a. The third intermediate sacrificial layer 249a can include a material having an etching rate higher than etching rates of a material of the third lower sacrificial layer 247a and a material of the third upper sacrificial layer 251a. In an example embodiment, the third intermediate sacrificial layer 249a can include SiN having a nitrogen concentration higher than nitrogen concentrations of SiN of the third lower sacrificial layer 247a and SiN of the third upper sacrificial layer 251a.

[0095] Referring to Figure 6B The sacrificial pattern 260 and the interlayer insulation pattern 220 can be formed by etching the sacrificial layer 260a and the interlayer insulation layer 220a. The sacrificial pattern 260 can include the first sacrificial pattern 237, the second sacrificial pattern 245, and the third sacrificial pattern 253.

[0096] The first sacrificial pattern 237 can include a triple pattern of the first lower sacrificial pattern 231, the first intermediate sacrificial pattern 233, and the first upper sacrificial pattern 235. The second sacrificial pattern 245 can include a triple pattern of the second lower sacrificial pattern 239, the second intermediate sacrificial pattern 241, and the second upper sacrificial pattern 243.

[0097] The third sacrificial pattern 253 can include a triple pattern of the third lower sacrificial pattern 247, the third intermediate sacrificial pattern 249, and the third upper sacrificial pattern 251. The interlayer insulation pattern 220 can include the first interlayer insulation pattern 211, the second interlayer insulation pattern 213, the third interlayer insulation pattern 215, and the fourth interlayer insulation pattern 217.

[0098] A recessed hole 262 recessed from a sidewall 220SW of the interlayer insulation pattern 220 can be formed on one side of the sacrificial pattern 260. A sidewall of the recessed hole 262 can be of a curved surface type. The first, second, and third intermediate sacrificial patterns 233, 241, and 249 included in the sacrificial pattern 260 can have an etching rate higher than that of the first, second, and third lower sacrificial patterns 231, 239, and 247 and the first, second, and third upper sacrificial patterns 235, 243, and 251, and thus, the sidewall of the recessed hole 262 can be formed to have a curved surface.

[0099] In an example embodiment, a through-hole 261 penetrating the sacrificial pattern 260 and the interlayer insulation pattern 220 from an upper portion to a lower portion thereof can be formed. When the through-hole 261 is formed, the recessed hole 262 can communicate with the through-hole 261. The through-hole 261 can be a trench hole.

[0100] Referring to Figure 6C A first insulating layer 264 for burying the recessed hole 262 and the through-hole 261 can be formed. The first insulating layer 264 can include, for example, SiN.

[0101] Referring to Figure 6D The first insulating layer 264 can be etched to form a first barrier insulating layer 266 in the recessed hole 262. Thus, the first barrier insulating layer 266 can be formed on a sidewall of the sacrificial pattern 260. The first barrier insulating layer 266 can be formed in a portion of the recessed hole 262. The first barrier insulating layer 266 can protect a charge storage layer in a subsequent process.

[0102] Referring to Figure 6E A reinforcement layer 268 can be formed in the recessed hole 262 at upper and lower edges of the first barrier insulating layer 266. The reinforcement layer 268 can be formed on one side of each of the first lower sacrificial pattern 231, the first upper sacrificial pattern 235, the second lower sacrificial pattern 239, the second upper sacrificial pattern 243, the third lower sacrificial pattern 247, and the third upper sacrificial pattern 251.

[0103] The reinforcement layer 268 can be formed by oxidizing some portions exposed in the recessed hole 262. The reinforcement layer 268 can include silicon oxide. The reinforcement layer 268 can protect a charge storage material layer 270 (see Figure 6F ) in a subsequent process.

[0104] Referring to Figure 6FThe charge storage material layer 270, the tunnel insulating layer 272, and the semiconductor pillar 274 can be formed in the stack direction in the recessed hole 262 and the through hole 261. The charge storage material layer 270 can be formed on one side of the first barrier insulating layer 266 and the reinforcement layer 268 in the recessed hole 262.

[0105] The charge storage material layer 270 can include SiN. The tunnel insulating layer 272 can be formed on one side of the charge storage material layer 270 in the stack direction. The tunnel insulating layer 272 can include silicon oxide. The semiconductor pillar 274 can be formed on one side of the tunnel insulating layer 272 in the stack direction.

[0106] Referring to Figure 6G The sacrificial pattern 260 between the interlayer insulating patterns 220 can be removed by an etching process to form preliminary cavities 276 between the interlayer insulating patterns 220. The sacrificial pattern 260 can have etching selectivity with respect to the interlayer insulating patterns 220. Accordingly, the sacrificial pattern 260 can be easily removed by the etching process. When the sacrificial pattern 260 is etched, the reinforcement layer 268 can serve to protect the charge storage material layer 270.

[0107] Referring to Figure 6H The height of the preliminary cavities 276 can be further increased by further etching the surface of the interlayer insulating patterns 220 exposed in the preliminary cavities 276 to form final cavities 278. Hereinafter, the final cavities 278 are referred to as cavities 278. When the interlayer insulating patterns 220 are etched, the reinforcement layer 268 can also be removed by etching.

[0108] Referring to Figure 6I The charge storage material layer 270 can be etched by using the first barrier insulating layer 266 as an etching mask to form a charge storage layer 280. Via the cavities 278, the charge storage material layer 270 can be etched by using the first barrier insulating layer 266 as an etching mask. Accordingly, the charge storage layer 280 can be formed on one side of the first barrier insulating layer 266 and one side of the tunnel insulating layer 272. When the charge storage layer 280 is formed, dummy charge storage layers 281 can be formed on the sidewalls of the interlayer insulating patterns 220. In this way, the charge storage layer 280 and the dummy charge storage layers 281 can be separated from each other.

[0109] Referring to Figure 6J In the cavities 278 and the through hole 261, a second insulating layer 284a can be formed on and beside the first barrier insulating layer 266, the charge storage layer 280, and the dummy charge storage layers 281, and on the sidewalls of the interlayer insulating patterns 220. The second insulating layer 284a can include, for example, SiN.

[0110] Referring to Figure 6KThe second insulating layer 284a can be etched to form a second barrier insulating layer 284. Thus, a data storage structure 288 including the tunnel insulating layer 272, the charge storage layer 280, and the first and second barrier insulating layers 266 and 284 can be formed on one side of the semiconductor pillar 274.

[0111] In addition, an isolation insulating layer 285 can be formed between the charge storage layer 280 and the dummy charge storage layer 281. The second barrier insulating layer 284 and the isolation insulating layer 285 can include the same material.

[0112] Subsequently, as shown in FIG. 32, a gate pattern 320 can be formed in the cavity 278 to complete the vertical nonvolatile memory device 10 (see FIGS. 33 and 34). Figure 4A Figure 4B Figure 4A Figure 4B

[0113] Figure 7A to Figure 7H is a cross-sectional view for describing a method of manufacturing a vertical nonvolatile memory device according to an example embodiment.

[0114] Figure 7A to Figure 7H shows stages in a method of manufacturing the vertical nonvolatile memory device 10 of Figure 4A Figure 4B

[0115] In addition to forming the reinforcing layer 292 on the entire portion in the recessed hole 262, Figure 7A to Figure 7H Figure 6A to Figure 6K Figure 7A to Figure 7H Figure 4A Figure 4B Figure 6A to Figure 6K

[0116] Referring to FIG. 31, the manufacturing process shown in FIGS. 32 and 33 is performed. Next, a reinforcing material layer 290 can be formed in the recessed hole 262. The reinforcing material layer 290 can be formed entirely in the recessed hole 262. The reinforcing material layer 290 can be formed on one side of the first lower sacrificial pattern 231, the first intermediate sacrificial pattern 233, the first upper sacrificial pattern 235, the second lower sacrificial pattern 239, the second intermediate sacrificial pattern 241, the second upper sacrificial pattern 243, the third lower sacrificial pattern 247, the third intermediate sacrificial pattern 249, and the third upper sacrificial pattern 251. Figure 7A Figure 6A Figure 6B The reinforcing material layer 290 can be formed by, for example, completely oxidizing the portion exposed in the recessed hole 262. The reinforcing material layer 290 can include, for example, silicon oxide.

[0117] ​​​​​​​​​​​​​​​

[0118] Referring to Figure 7B A first insulating layer 264 can be formed to bury the via hole 261 and the recessed hole 262 in which the reinforcing material layer 290 is formed. The first insulating layer 264 includes SiN.

[0119] Referring to Figure 7C The first insulating layer 264 can be etched to form a first barrier insulating layer 266 in the recessed hole 262. Accordingly, the first barrier insulating layer 266 can be formed on the sidewall of the sacrificial pattern 260. When the first barrier insulating layer 266 is formed, the reinforcing material layer 290 can be partially etched and become a first reinforcing layer 292a. The first reinforcing layer 292a can be formed in some portions of the recessed hole 262.

[0120] The first reinforcing layer 292a can not be formed on a portion of the sidewall of each of the first lower sacrificial pattern 231, the first upper sacrificial pattern 235, the second lower sacrificial pattern 239, the second upper sacrificial pattern 243, the third lower sacrificial pattern 247, and the third upper sacrificial pattern 251. The first reinforcing layer 292a can not be formed at the upper edge and the lower edge of the first barrier insulating layer 266. The first reinforcing layer 292a can protect the charge storage material layer 270 (see Figure 7E )

[0121] Referring to Figure 7D The second reinforcing layer 292b can be formed in contact with the upper edge portion and the lower edge portion of the first barrier insulating layer 266 and the first reinforcing layer 292a. The second reinforcing layer 292b can be formed on one side of the first lower sacrificial pattern 231, the first upper sacrificial pattern 235, the second lower sacrificial pattern 239, the second upper sacrificial pattern 243, the third lower sacrificial pattern 247, and the third upper sacrificial pattern 251.

[0122] The second reinforcing layer 292b can be formed by oxidizing some portions exposed in the recessed hole 262. The second reinforcing layer 292b can include silicon oxide. The second reinforcing layer 292b can protect the charge storage material layer 270 (see Figure 7E ) in a subsequent process.

[0123] A reinforcing layer 292 including the first reinforcing layer 292a and the second reinforcing layer 292b can be formed in the recessed hole 262. Accordingly, the reinforcing layer 292 can be completely formed in the recessed hole 262.

[0124] Referring to Figure 7EThe charge storage material layer 270, the tunnel insulating layer 272, and the semiconductor pillar 274 can be formed in the recessed hole 262 and the through hole 261 in a stacking direction, for example, so as to extend in the Z direction. The charge storage material layer 270 can be formed on one side of the first barrier insulating layer 266 and the reinforcement layer 292 in the recessed hole 262.

[0125] Referring to Figure 7F The sacrificial pattern 260 between the interlayer insulating patterns 220 can be removed by an etching process to form preliminary cavities 276 between the interlayer insulating patterns 220. The sacrificial pattern 260 can have etching selectivity with respect to the interlayer insulating patterns 220. Thus, the sacrificial pattern 260 can be easily removed by the etching process. The reinforcement layer 292 can be used to protect the charge storage material layer 270 when the sacrificial pattern 260 is etched.

[0126] Referring to Figure 7G The height of the preliminary cavities 276 can be further increased by further etching the surface of the interlayer insulating patterns 220 exposed in the preliminary cavities 276 to form final cavities 278. Hereinafter, the final cavities 278 are referred to as cavities 278. The reinforcement layer 292 can also be removed by etching when the interlayer insulating patterns 220 are etched.

[0127] Referring to Figure 7H The charge storage material layer 270 can be etched by using the first barrier insulating layer 266 as an etching mask to form a charge storage layer 280, as in Figure 6I Thus, the charge storage layer 280 can be formed on one side of the first barrier insulating layer 266 and one side of the tunnel insulating layer 272. When the charge storage layer 280 is formed, a dummy charge storage layer 281 can be formed on the sidewall of the interlayer insulating pattern 220. In this way, the charge storage layer 280 and the dummy charge storage layer 281 can be separated from each other.

[0128] Subsequently, as shown in Figure 6J and Figure 6K A data storage structure 288 including the tunnel insulating layer 272, the charge storage layer 280, and the first barrier insulating layer 266 and the second barrier insulating layer 284 can be formed on one side of the semiconductor pillar 274. In addition, an isolation insulating layer 285 can be formed between the charge storage layer 280 and the dummy charge storage layer 281. The second barrier insulating layer 284 and the isolation insulating layer 285 can include the same material.

[0129] Subsequently, as shown in Figure 4A and Figure 4B A gate pattern 320 can be formed in the cavity 278 to complete the vertical nonvolatile memory device 10 (seeFigure 4A and Figure 4B ).

[0130] Figure 8A and Figure 8B is a cross-sectional view for describing a method of manufacturing a vertical nonvolatile memory device 10-1 according to an example embodiment.

[0131] Figure 8A and Figure 8B stages in a method of manufacturing a vertical nonvolatile memory device 10-1. Figure 5A and Figure 5B are shown.

[0132] In addition to forming the isolation insulating layer 294, Figure 8A and Figure 8B may be almost the same as Figure 7A to Figure 7H and Figure 6A to Figure 6K In Figure 8A and Figure 8B , members identical to those of Figure 5A and Figure 5B , Figure 6A to Figure 6K and Figure 7A to Figure 7H are denoted by the same reference numerals, and the above-explained descriptions can be briefly restated or omitted.

[0133] Referring to Figure 8A , the manufacturing processes of Figure 6A to Figure 6I may be performed. Alternatively, the manufacturing processes of Figure 7A to Figure 7H may be performed. Figure 8A The manufacturing processes shown in Figure 6I and Figure 7H are described above (see, for example, FIGS. 1A to 1C), and thus will be omitted.

[0134] Referring to Figure 8A and Figure 8B , Figure 8A , a surface portion of the charge storage layer 280 in Figure 8A and a surface portion of the dummy charge storage layer 281 in Figure 8B may be oxidized to form the isolation insulating layer 294 in Figure 8B and the dummy charge storage layer 281a in . The isolation insulating layer 294 can be formed between the charge storage layer 280 and the dummy charge storage layer 281a. In the through-hole 261, the dummy charge storage layer 281a can be formed toward the semiconductor pillar 274 on the sidewall of the interlayer insulating pattern 220. Thus, the data storage structure 288a including the tunnel insulating layer 272, the charge storage layer 280, and the first blocking insulating layer 266 can be formed on one side of the semiconductor pillar 274.

[0135] Subsequently, as shown in Figure 5A and Figure 5B .As shown, the gate pattern 320 can be formed in the cavity 278 to complete the vertical nonvolatile memory device 10-1.

[0136] Figure 9A and Figure 9B are cross-sectional views showing stages in a method of manufacturing the vertical nonvolatile memory device 10-1 according to an example embodiment.

[0137] Figure 9A and Figure 9B for describing an embodiment of a method of manufacturing Figure 5A the vertical nonvolatile memory device 10-1.

[0138] In addition to the method of forming the isolation insulating layer 294, Figure 9A and Figure 9B may be almost the same as Figure 7A to Figure 7H and Figure 6A to Figure 6K In Figure 9A and Figure 9B , the same members as those of Figure 5A and Figure 5B , Figure 6A to Figure 6K and Figure 7A to Figure 7H are denoted by the same reference numerals, and the above-explained descriptions can be briefly restated or omitted.

[0139] Referring to Figure 9A , the manufacturing process shown in Figure 6A to Figure 6I may be performed. Alternatively, the manufacturing process of Figure 7A to Figure 7H may be performed. When the manufacturing process shown in Figure 6A to Figure 6I or Figure 7A to Figure 7H is performed, the portion 283 of the dummy charge storage layer 281 can be left.

[0140] Referring to Figure 9A and Figure 9B , Figure 9A the left portion 283 of the dummy charge storage layer 281 can be oxidized to form the isolation insulating layer 294 in Figure 9B and the dummy charge storage layer 281a in Figure 9B . When the isolation insulating layer 294 is formed, the surfaces of the charge storage layer 280 and the dummy charge storage layer 281 can also be oxidized. The isolation insulating layer 294 can be formed between the charge storage layer 280 and the dummy charge storage layer 281a.

[0141] Thus, the data storage structure 288a including the tunnel insulating layer 272, the charge storage layer 280, and the first barrier insulating layer 266 can be formed on one side of the semiconductor pillar 274. In the via hole 261, the dummy charge storage layer 281a on the sidewall of the interlayer insulating pattern 220 can be formed toward the semiconductor pillar 274.

[0142] Subsequently, as shown in Figure 5A and Figure 5B , a gate pattern 320 can be formed in the cavity 278 to complete the vertical nonvolatile memory device 10-1.

[0143] Figure 10A and Figure 10B are cross-sectional views showing stages in a method of manufacturing the vertical nonvolatile memory device 10-1 according to an example embodiment.

[0144] Figure 10A and Figure 10B for describing an embodiment of the method of manufacturing Figure 5A and Figure 5B the vertical nonvolatile memory device 10-1 shown in

[0145] In addition to the method of forming the isolation insulating layer 294, Figure 10A and Figure 10B may be almost the same as Figure 7A to Figure 7H and Figure 6A to Figure 6K In Figure 10A and Figure 10B , the same components as those of Figure 5A and Figure 5B , Figure 6A to Figure 6K and Figure 7A to Figure 7H are denoted by the same reference numerals, and the same description will be briefly given or omitted.

[0146] Referring to Figure 10A , the manufacturing process shown in Figure 6A to Figure 6H may be performed. Alternatively, the manufacturing process shown in Figure 7A to Figure 7G may be performed. Subsequently, referring to Figure 10B , the charge storage material layer 270 can be oxidized to form the isolation insulating layer 294. The isolation insulating layer 294 can be formed between the charge storage layer 280 and the dummy charge storage layer 281a.

[0147] Thus, a data storage structure 288a including the tunnel insulating layer 272, the charge storage layer 280, and the blocking insulating layer 266 can be formed on one side of the semiconductor pillar 274. In the via hole 261, the dummy charge storage layer 281a on the sidewall of the interlayer insulating pattern 220 can be formed toward the semiconductor pillar 274.

[0148] Subsequently, as shown in Figure 5A and Figure 5B , a gate pattern 320 can be formed in the cavity 278 to complete the vertical nonvolatile memory device 10-1.

[0149] Figure 11 is a schematic block diagram of a vertical nonvolatile memory device 1000 according to an example embodiment.

[0150] The vertical nonvolatile memory device 1000 can include a NAND cell array 1100 and a core circuit unit 1200. For example, the NAND cell array 1100 can include the vertical nonvolatile memory device described above. The core circuit unit 1200 can include a control logic 1210, a row decoder 1220, a column decoder 1230, a sense amplifier 1240, and / or a page buffer 1250.

[0151] The control logic 1210 can communicate with the row decoder 1220, the column decoder 1230, and / or the page buffer 1250. The row decoder 1220 can communicate with the NAND cell array 1100 having a stacked structure through a string select line SSL, a word line WL, and / or a ground select line GSL. The column decoder 1230 can communicate with the NAND cell array 1100 through a bit line BL. The sense amplifier 1240 can be connected to the column decoder 1230 when a signal is output from the NAND cell array 1100, and can not be connected to the column decoder 1230 when a signal is transmitted to the NAND cell array 1100.

[0152] The control logic 1210 can transmit a row address signal to the row decoder 1220, and the row decoder 1220 can decode the signal and transmit the decoded row address signal to the NAND cell array 1100 through the string select line SSL, the word line WL, and the ground select line GSL. The control logic 1210 can transmit a column address signal to the column decoder 1230 or the page buffer 1250, and the column decoder 1230 can decode the column address signal and transmit the decoded column address signal to the NAND cell array 1100 through the bit line BL. A signal of the NAND cell array 1100 having a stacked structure can be transmitted to the sense amplifier 1240 through the column decoder 1230, amplified in the sense amplifier 1240, and transmitted to the control logic 1210 via the page buffer 1250.

[0153] Figure 12 is a schematic view of a card 5000 according to an example embodiment.

[0154] The card 5000 can include a controller 5100 and a memory 5200. The controller 5100 and the memory 5200 can be arranged to exchange electrical signals. For example, the memory 5200 can transmit data when the controller 5100 issues a command. The memory 5200 can include a vertical nonvolatile memory device according to an example embodiment.

[0155] The vertical nonvolatile memory device according to various example embodiments can be arranged as a "NAND" and "NOR" architecture memory array (not shown) to correspond to the design of the related logic gate. The card 5000 can be used in a memory device such as a memory stick card, a smart media card (SM), a secure digital (SD) card, a mini secure digital (SD) card, a multimedia card (MMC), or the like.

[0156] Figure 13 is a schematic diagram of a system 6000 according to an example embodiment.

[0157] The system 6000 can include a controller 6100, an input / output device 6200, a memory 6300, and an interface 6400. The system 6000 can be a mobile system, or a system that transmits or receives data. The mobile system can include a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, a memory card, or the like.

[0158] The controller 6100 can execute a program and control the system 6000. The controller 6100 can be, for example, a microprocessor, a digital signal processor, a microcontroller, or the like. The input / output device 6200 can be used to input or output data of the system 6000. The system 6000 can be connected to an external device such as a personal computer or a network by using the input / output device 6200 to exchange data with the external device. The input / output device 6200 can be, for example, a keypad, a keyboard, or a display.

[0159] The memory 6300 can store a code and / or data for the operation of the controller 6100, and / or store data processed in the controller 6100. The memory 6300 can include a vertical nonvolatile memory device according to an example embodiment. The interface 6400 can be a data transmission path between the system 6000 and another external device. The controller 6100, the input / output device 6200, the memory 6300, and the interface 6400 can communicate with each other via a bus 6500.

[0160] The system 6000 can be used, for example, in a mobile phone, an MP3 player, navigation, a portable multimedia player (PMP), a solid state disk (SSD), or a home appliance.

[0161] As a summary and review, in a NAND flash memory device, one cell can include one transistor, and the cell transistors can be stacked vertically to increase integration. When the cell transistors included in the nonvolatile memory device are stacked in a vertical direction, the charge storage characteristics of each cell transistor located in the vertical direction are important.

[0162] As described above, the embodiments can provide a vertical nonvolatile memory device in which the charge storage characteristics of each unit transistor located in the vertical direction can be improved.

[0163] Exemplary embodiments have been disclosed herein, and although specific terminology has been used, it is used and interpreted in a general and descriptive sense only, and not for limiting purposes. In some instances, it will be apparent to those skilled in the art at the time of filing this application that features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless expressly indicated otherwise. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

[0164] Korean Patent Application No. 10-2019-0119821, filed on September 27, 2019, with the Korean Intellectual Property Office and entitled "Vertical Non-volatile Storage Device," is incorporated herein by reference in its entirety.

Claims

1. A vertical nonvolatile memory device, comprising: a stack including gate patterns and interlayer insulation patterns stacked in a stacking direction, the stack having through-holes extending in the stacking direction in the gate patterns and in the interlayer insulation patterns, the stack further including recessed holes that communicate with the through-holes and are recessed from sidewalls of the interlayer insulation patterns in a direction toward the gate patterns; semiconductor pillars in the through-holes and extending in the stacking direction; a data storage structure between the gate patterns and the semiconductor pillars in the through-holes, the data storage structure including a charge storage layer in the recessed holes; and a dummy charge storage layer in the through-holes on sidewalls of the interlayer insulation patterns toward the semiconductor pillars, the dummy charge storage layer being formed of the same charge storage material as the charge storage layer.

2. The vertical nonvolatile memory device of claim 1, wherein the charge storage layer and the dummy charge storage layer have a discontinuous structure in which the charge storage layer and the dummy charge storage layer do not continuously extend in the stacking direction in the through-holes.

3. The vertical nonvolatile memory device of claim 1, further comprising an isolation insulation layer in the through-holes in contact with the charge storage layer, wherein the charge storage layer is separated from the dummy charge storage layer by the isolation insulation layer.

4. The vertical nonvolatile memory device of claim 1, wherein the charge storage layer is on portions of sidewalls of the gate patterns, and the dummy charge storage layer is on portions of sidewalls of the interlayer insulation patterns.

5. The vertical nonvolatile memory device of claim 1, wherein the data storage structure includes a tunnel insulation layer, the charge storage layer, and a barrier insulation layer formed in that order on the semiconductor pillars in a direction toward the gate patterns.

6. The vertical nonvolatile memory device of claim 5, wherein the barrier insulation layer includes a single insulation layer or a plurality of insulation layers.

7. The vertical nonvolatile memory device of claim 5, wherein the barrier insulation layer is on all or a portion of sidewalls of the gate patterns.

8. The vertical nonvolatile memory device of claim 5, wherein the barrier insulation layer has a discontinuous structure in which the barrier insulation layer does not continuously extend in the stacking direction in the through-holes.

9. The vertical nonvolatile memory device of claim 5, wherein the tunnel insulation layer has a continuous structure in which the tunnel insulation layer extends in the stacking direction in the through-holes.

10. The vertical nonvolatile memory device of claim 1, wherein the charge storage layer and the dummy charge storage layer are on different lines in the stacking direction in the through-holes.

11. A vertical nonvolatile memory device, comprising: ​ a stack including gate patterns and interlayer insulation patterns alternately stacked in a stacking direction, the stack having through-holes extending in the stacking direction in the gate patterns and the interlayer insulation patterns, the stack including a recessed hole communicating with the through-holes and recessed from a sidewall of the interlayer insulation patterns in a direction toward the gate patterns; a data storage structure including a blocking insulation layer in contact with the gate patterns in the recessed hole, a charge storage layer in contact with the blocking insulation layer in the recessed hole, and a tunnel insulation layer in contact with the charge storage layer and extending in the stacking direction in the through-holes; a semiconductor pillar in contact with the data storage structure and extending in the stacking direction in the through-holes and the recessed hole; a dummy charge storage layer on the sidewall of the interlayer insulation patterns in the through-holes toward the semiconductor pillar; and a separation insulation layer disposed in the stacking direction and in contact with the charge storage layer in the recessed hole and the through-holes, wherein the charge storage layer is separated from the dummy charge storage layer by the separation insulation layer.

12. The vertical nonvolatile memory device of claim 11, wherein the blocking insulation layer is in contact with an entirety of a sidewall of the gate pattern in the recessed hole.

13. The vertical nonvolatile memory device of claim 11, wherein the blocking insulation layer is in contact with a portion of a sidewall of the gate pattern in the recessed hole.

14. The vertical nonvolatile memory device of claim 11, wherein: a surface of the recessed hole contacting the gate pattern is curved, and a surface of the data storage structure contacting the curved surface of the recessed hole is curved.

15. A vertical nonvolatile memory device, comprising: a stack including gate patterns and interlayer insulation patterns alternately stacked, the stack having through-holes extending in a stacking direction in the gate patterns and the interlayer insulation patterns, the stack including a curved surface recessed hole recessed from a sidewall of the interlayer insulation patterns in a direction toward the gate patterns, the curved surface recessed hole communicating with the through-holes and having a curved surface; a curved surface data storage structure in the curved surface recessed hole, the curved surface data storage structure including a curved surface blocking insulation layer in contact with the gate patterns, a curved surface charge storage layer in contact with the curved surface blocking insulation layer, and a curved surface tunnel insulation layer in contact with the curved surface charge storage layer in the curved surface recessed hole and extending in the stacking direction in the through-holes; a separation insulation layer in the curved surface recessed hole and the through-holes in the stacking direction to contact the curved surface charge storage layer; a dummy charge storage layer on the sidewall of the interlayer insulation patterns in the through-holes, the dummy charge storage layer separated by the separation insulation layer; and a separation insulation layer in the curved surface recessed hole and the through-holes in the stacking direction to contact the curved surface charge storage layer. a curved surface semiconductor pillar extending in the stacking direction on a side wall of the curved surface tunnel insulating layer and on a side of the dummy charge storage layer and in the through-hole.

16. The vertical nonvolatile memory device of claim 15, wherein the isolation insulating layer is on the side wall of the interlayer insulating pattern and under the interlayer insulating pattern.

17. The vertical nonvolatile memory device of claim 15, wherein the dummy charge storage layer, the isolation insulating layer, and the curved surface charge storage layer are connected to each other in the stacking direction in the curved surface recessed hole and the through-hole.

18. The vertical nonvolatile memory device of claim 15, wherein: the curved surface blocking insulating layer is in integral contact with a side wall of the gate pattern in the curved surface recessed hole, and the curved surface blocking insulating layer includes a first insulating layer on a side wall of the curved surface charge storage layer and a second insulating layer on a side wall of the first insulating layer and in contact with the gate pattern.

19. The vertical nonvolatile memory device of claim 16, wherein: the curved surface blocking insulating layer is in partial contact with a side wall of the gate pattern in the curved surface recessed hole, and the curved surface blocking insulating layer includes an insulating layer on a side wall of the curved surface charge storage layer.

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