Semiconductor-on-insulator (SOI) substrate, method for forming the same, and integrated circuit

Abstract

Embodiments of the present application are directed to a method for forming a semiconductor-on-insulator (SOI) substrate having a thick device layer and a thick insulator layer. In some embodiments, the method includes forming an insulator layer covering a processing substrate, and epitaxially forming a device layer on a sacrificial substrate. The sacrificial substrate is bonded to the processing substrate such that the device layer and the insulator layer are located between the sacrificial substrate and the processing substrate, and the sacrificial substrate is removed. The removal includes performing an etch on the sacrificial substrate until the device layer is reached. Since the device layer is formed epitaxially and transferred to the processing substrate, the device layer can be formed to have a relatively large thickness. Additionally, since epitaxy is not affected by the thickness of the insulator layer, the insulator layer can be formed to have a relatively large thickness. Embodiments of the present invention also relate to a semiconductor-on-insulator (SOI) substrate, a method for forming the same, and an integrated circuit.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor-on-insulator (SOI) substrate, a method of forming the same, and an integrated circuit. Background Art

[0002] Integrated circuits have traditionally been formed on bulk semiconductor substrates. In recent years, semiconductor-on-insulator (SOI) substrates have emerged as an alternative to bulk semiconductor substrates. An SOI substrate includes a processing substrate, an insulator layer overlying the processing substrate, and a device layer overlying the insulator layer. Among them, the SOI substrate results in reduced parasitic capacitance, reduced leakage current, reduced latch-up, and improved semiconductor device performance (e.g., lower power consumption and higher switching speed). Summary of the Invention

[0003] Embodiments of the present invention provide a semiconductor-on-insulator (SOI) substrate, including: a processing substrate; a device layer overlying the processing substrate; and an insulator layer separating the processing substrate from the device layer, the insulator layer contacting the device layer at a first interface and contacting the processing substrate at a second interface, wherein the insulator layer includes a getter material having a getter concentration profile having a first peak concentration at the first interface, a second peak concentration at the second interface, and a valley concentration at a position between the first interface and the second interface, the valley concentration being less than each of the first peak concentration and the second peak concentration.

[0004] Another embodiment of the present invention provides a method for forming a semiconductor-on-insulator (SOI) substrate, the method including: receiving a processing substrate; receiving a device substrate and an oxide layer, wherein the oxide layer is disposed on a surface of at least one of the processing substrate and the device substrate, the oxide layer including metal contaminants; bonding the processing substrate to the device substrate such that the oxide layer separates the processing substrate from the device substrate; and wherein, before bonding the processing substrate to the device substrate, the oxide layer undergoes a getter process, wherein a halogen substance is provided in the oxide layer to scavenge the metal contaminants.

[0005] Another embodiment of the present invention provides an integrated circuit, comprising: a processing substrate; an insulator layer disposed above the processing substrate; a device layer including single crystal silicon disposed above the insulator layer, wherein one or more semiconductor devices are disposed in or above the device layer; and an interconnect structure disposed above the device layer, wherein the interconnect structure operably couples the one or more semiconductor devices to each other; and wherein the insulator layer separates the processing substrate from the device layer, and wherein the insulator layer includes a getter material embedded in an insulating material of the insulator layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustrative purposes only. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figure 1 Cross-sectional views of some embodiments of a semiconductor-on-insulator (SOI) substrate are shown, wherein a getter material is disposed in the insulator layer.

[0008] Figures 2A to 2I Shows a depiction Figure 1 of cross-sectional views of various getter concentration profiles of an SOI substrate.

[0009] Figure 3 Cross-sectional views of some embodiments of an SOI substrate are shown, wherein a getter material is disposed in the insulator layer.

[0010] Figure 4 Shows a depiction Figure 3 of the getter concentration profile of an SOI substrate.

[0011] Figure 5 Cross-sectional views of some embodiments of an SOI substrate are shown, wherein a getter material is disposed in the insulator layer.

[0012] Figure 6 Shows a depiction Figure 5 of the getter concentration profile of an SOI substrate.

[0013] Figure 7 Shows Figure 1 top views of some embodiments of an SOI substrate.

[0014] Figure 8 Shows some embodiments of cross-sectional views of a semiconductor structure of an SOI substrate in which Figure 1 is applied.

[0015] Figure 9shows a manufacturing method according to Figure 1 and Figures 2A to 2I for some embodiments.

[0016] Figure 10 shows a manufacturing method according to Figure 3 and Figure 4 for some embodiments.

[0017] Figure 11 shows a manufacturing method according to Figure 5 and Figure 6 for some embodiments.

[0018] Figures 12 to 23 shows various embodiments of a method for forming an SOI substrate. DETAILED DESCRIPTION

[0019] The present invention provides many different embodiments or examples for implementing the different features of the present invention. Specific embodiments or examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include embodiments in which the first component and the second component are in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component such that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0020] In addition, for ease of description, spatially relative terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. In addition to the orientation shown in the figures, the spatially relative terms are intended to include different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0021] Various embodiments of the present application are directed to methods for forming SOI substrates and chips including such SOI substrates. As understood in some aspects of the present invention, some SOI substrates include an insulator layer that includes mobile metal contaminants such as sodium and / or potassium. These mobile metal contaminants may inadvertently enter the insulator layer of the SOI substrate during processing and tend to cause higher leakage currents and / or reduce the breakdown voltage in the insulator layer. Thus, to mitigate the effects of these metal contaminants, some aspects of the present invention include an SOI substrate in which the insulator layer is fortified with a getter material having a getter concentration profile. The getter material may include a halogen such as fluorine (F) or chlorine (Cl). The getter material binds to the mobile metal contaminants to reduce current leakage and / or increase the breakdown voltage in the insulator layer. Thus, the presence of the getter material in the insulator layer binds these metal contaminants, thereby reducing the leakage current and / or increasing the breakdown voltage of the insulator layer.

[0022] Reference Figure 1 , a cross-sectional view 100 of some embodiments of an SOI substrate 102 is provided. The SOI substrate 102 includes a processing substrate 104, an insulator layer 106 located above the processing substrate 104, and a device layer 108 located above the insulator layer 106. The insulator layer 106 separates the processing substrate 104 from the device layer 108. The insulator layer 106 includes an upper insulating region 106u that covers the upper surface 104u of the processing substrate 104 to separate the upper surface 104u of the processing substrate 104 from the device layer 108. In some embodiments, the insulator layer 106 further includes a lower insulating region 106l that covers the lower surface 104l of the processing substrate 104 and a sidewall insulating region 106s that covers the sidewall 104s of the processing substrate 104. In some embodiments, the upper insulating region 106u has a first thickness t1 between the upper surface 104u of the processing substrate 104 and the device layer 108, while the lower insulating region 106l and the sidewall insulating region 106s have a second thickness t2. In some embodiments, the first thickness t1 is greater than the second thickness t2.

[0023] In Figure 1 some embodiments, the insulator layer 106 includes a getter material having a getter concentration profile. The getter material may include a halogen such as fluorine (F) or chlorine (Cl). The getter material binds to mobile metal contaminants that occur in the insulator layer 106 during the fabrication and / or processing of the SOI substrate, such as alkali metals including sodium (Na) and / or potassium (K). Without the getter material, these metal contaminants would cause higher leakage currents and / or reduce the breakdown voltage in the insulator layer 106. Thus, the presence of the getter material in the insulator layer 106 binds these metal contaminants, thereby reducing the leakage current and / or increasing the breakdown voltage of the insulator layer.

[0024] In some cases, it may be based on Figure 9 formed Figure 1 embodiments in which a first insulating layer 902 is formed around the processing substrate 104 and a second insulating layer 904 is formed around the device layer 108. Then the processing substrate 104 and the device layer 108 are bonded together (906) such that the first insulating layer 902 and the second insulating layer 904 contact each other to establish an upper insulating region 106u, a sidewall insulating region 106s, and a lower insulating region 106l. In some embodiments, for example, by etching and chemical mechanical planarization or polishing operations, sidewall portions and upper surface portions of the second insulating layer 904 around the device layer 108 are removed ( Figure 9 the rightmost portion). More particularly, in Figure 9 at least one of the first insulating layer 902 and the second insulating layer 904 may be formed to include a getter material having a getter concentration profile. Thus, in some embodiments, only the first insulating layer 902 includes the getter material, while the second insulating layer 904 does not exhibit the getter material; while in other embodiments, only the second insulating layer 904 includes the getter material, while the first insulating layer 902 does not exhibit the getter material. In other embodiments, both the first insulating layer 902 and the second insulating layer 904 include the getter material.

[0025] Viewed together Figure 1 and Figure 9 it can be understood that the getter concentration profile can take various forms according to the implementation, as described now in Figures 2A to 2I herein. Figures 2A to 2I illustrates various non-limiting examples of getter concentration profiles, which can correspond to the respective embodiments of Figure 9 manufactured in accordance with Figure 1 herein.

[0026] In Figures 2A to 2C each of the first insulating layer 902 around the processing substrate 104 and the second insulating layer 904 around the device layer 108 includes a getter material. In Figures 2A to 2C the first insulating layer 902 around the processing substrate 104 exhibits a first getter concentration profile, and the first getter concentration profile is generally symmetric about the central region of the processing substrate 104. Thus, the first insulating layer 902 exhibits a first getter concentration profile, and the first insulating layer 902 includes an upper region having an upper getter concentration profile 202 and a bottom region having a bottom getter concentration profile 204. The second insulating layer 904 around the device layer 108 exhibits a second getter concentration profile 206 that is the same as or different from the first getter concentration profile. Thus, in Figures 2A to 2C the example, the upper regions of the first insulating layer 902 and the second insulating layer 904 jointly establish Figure 1the upper insulating region 106u.

[0027] More specifically, in Figure 2A , the total getter concentration profile of the upper insulating region 106u has a first peak concentration 208 at the first interface 105, a second peak concentration 208 at the second interface 107, and a valley concentration 210 at a position between the first interface and the second interface. In Figure 2A 's example, the first peak concentration 208 is equal to the second peak concentration 208, and the valley concentration 210 is less than each of the first peak concentration 208 and the second peak concentration 208. The lower insulating region 106l of the first insulating layer has a getter concentration profile that is substantially symmetric to the getter concentration profile 202 of the upper insulating region 106u of the first insulating layer 902. In some embodiments, each of the first peak concentration 208 and the second peak concentration 208 is in the range between 1x10 18 atoms / cm 3 and 5x10 21 atoms / cm 3 of chlorine or fluorine, and the valley concentration 210 is in the range between 1x10 14 atoms / cm 3 and 2x10 17 atoms / cm 3 of chlorine or fluorine. This getter concentration profile 204 provides a high concentration of chlorine and / or fluorine atoms at the interfaces 108 / 106 and 104 / 106. These chlorine and / or fluoride ions are mobile metal ions and reduce the metal ion source at the interface (e.g., Na + (ion) + Cl - (ion) --> NaCl (stable compound)), thereby reducing interface leakage and increasing the breakdown voltage of the first insulating layer 902.

[0028] In Figure 2B , the total getter concentration profile of the upper insulating region 106u again has a first peak concentration 212 at the first interface 105, a second peak concentration 212 at the second interface 107, and a valley concentration 216 at a position between the first interface 105 and the second interface 107. However, in Figure 2B , the total getter concentration profile has a maximum peak concentration 214 at the central region of the upper insulating region 106u. Defects in the interface tend to trap metal ions, resulting in leakage paths. Figure 2A 's concentration [Cl][F] has a higher possibility of trapping metal ions in the defects at the interface, thus increasing the breakdown voltage of the upper insulating region 106u. In Figure 2BIn the example, the first peak concentration 212 is equal to the second peak concentration 212, and the valley concentration 216 is less than each of the first peak concentration 212 and the second peak concentration 212. The lower insulating region 106l of the first insulating layer 902 has a getter concentration profile 204, which is in turn substantially symmetric with the getter concentration profile 202 of the upper insulating region 106u of the first insulating layer 902. In some embodiments, each of the first peak concentration 212 and the second peak concentration 212 is in the range between 1x10 18 atoms / cm 3 and 5x10 21 atoms / cm 3 of chlorine or fluorine, and the valley concentration 216 is in the range between 1x10 14 atoms / cm 3 and 2x10 17 atoms / cm 3 of chlorine or fluorine.

[0029] In Figure 2C , the total getter concentration profile of the upper insulating region 106u again has a first peak concentration 218 at the first interface 105, a second peak concentration 218 at the second interface 107, and a valley concentration 220 at a position between the first interface 105 and the second interface 107. However, in Figure 2C , the total getter concentration profile has a maximum peak concentration 218 at the central region of the upper insulating region 106u, and the maximum peak concentration 218 at the central region is equal to the first peak concentration 218 and the second peak concentration 218. The lower insulating region 106l of the first insulating layer 902 has a getter concentration profile 204, which is again symmetric with the getter concentration profile 202 of the upper insulating region 106u of the first insulating layer 902. In other embodiments, each of the first peak concentration, the second peak concentration, and the valley concentration may be equal, and the concentration of chlorine or fluorine on the upper insulating region 106u, the lower insulating region 106l, and / or the first insulating layer 902 and / or the second insulating layer 904 may be uniform. In some embodiments, each of the first peak concentration 218 and the second peak concentration 218 is in the range between 1x10 18 atoms / cm 3 and 5x10 21 atoms / cm 3 of chlorine or fluorine, and the valley concentration 220 is in the range between 1x10 14 atoms / cm 3 and 2x10 17 atoms / cm 3 of chlorine or fluorine.

[0030] In Figures 2D to 2FIn , only the first insulating layer 902 includes a getter material, and the second insulating layer 904 does not include a getter material. This can simplify processing of the device layer 108, thereby providing a good solution in some respects because it simplifies processing while still providing reduced leakage and enhanced voltage breakdown for the SOI substrate because the getter material binds metal contaminants that might otherwise adversely affect leakage and / or breakdown voltage. Figure 2D In , the first peak concentration 222 is greater than the second peak concentration 224, and the valley concentration 226 is less than each of the first peak concentration 222 and the second peak concentration 224. Figure 2E In, the first peak concentration 228 is less than the second peak concentration 230, and the valley concentration 232 is less than each of the first peak concentration 228 and the second peak concentration 230. Figure 2F In some embodiments, the first peak concentration 234 is equal to the second peak concentration 234, and the valley concentration 236 is less than each of the first peak concentration 234 and the second peak concentration 234. In some embodiments, each of the first peak concentration 222, 230, 234 and the second peak concentration 224, 228 and / or 234 is less than 1x10 18 Atom / cm 3 and 5x10 21 Atom / cm 3 and the valley concentrations 226, 232 and / or 236 are each within 1x10 of chlorine or fluorine 14 Atom / cm 3 and 2x10 17 Atom / cm 3 in the range between.

[0031] exist Figures 2G to 2I In , only the second insulating layer 904 includes a getter material, and the first insulating layer 902 does not include a getter material. This can simplify the processing of the substrate 104, thereby providing a good solution in some aspects because it simplifies processing while still providing reduced leakage and enhanced voltage breakdown for the SOI substrate because the getter material binds metal contaminants that might otherwise adversely affect leakage and / or breakdown voltage. Figure 2G In the embodiment, the first peak concentration 238 is greater than the second peak concentration 240, and the valley concentration 242 is less than each of the first peak concentration 238 and the second peak concentration 240. Figure 2H In, the first peak concentration 244 is less than the second peak concentration 246, and the valley concentration 248 is less than each of the first peak concentration 244 and the second peak concentration 246. Figure 2IAmong them, the first peak concentration 250 is equal to the second peak concentration 250, and the valley concentration 252 is less than each of the first peak concentration 250 and the second peak concentration 250. In some embodiments, each of the first peak concentrations 238, 246, and / or 250 and the second peak concentrations 240, 244, and / or 250 is in the range between 1×10 18 atoms / cm 3 and 5×10 21 atoms / cm 3 and each of the valley concentrations 242, 248, and / or 252 is in the range between 1×10 14 atoms / cm 3 and 2×10 17 atoms / cm 3 between.

[0032] Now turning to Figure 3 , another embodiment can be seen, where the SOI substrate 102 includes a processing substrate 104, a device layer 108 located above the processing substrate 104, and an insulator layer 106 that separates the processing substrate 104 from the device layer 108. The insulator layer 106 contacts the device layer 108 at the second interface 107 and contacts the processing substrate 104 at the first interface 105. The first interface 105 corresponds to the point where the upper surface 104u of the processing substrate 104 contacts the insulator layer 106.

[0033] As Figure 4 shown, in Figure 3 some embodiments, the insulator layer 106 includes a getter material having a getter concentration profile. The getter concentration profile has a first peak concentration 402 at the second interface 107, a second peak concentration 404 at the first interface 105, and a valley concentration 406 at a position 408 between the first interface 105 and the second interface 107. The first peak concentration 402 is less than the second peak concentration 404, but in other embodiments, it can be greater than or equal to the second peak concentration 404. Additionally, as Figure 4 shown, in Figure 3 some embodiments, the getter material extending into the portion of the device layer 108 is at a first concentration, and the getter material extending into the portion of the processing substrate 104 is at a second concentration, with the first concentration being less than the second concentration.

[0034] In some cases, it can be formed according to Figure 10 formed Figures 3 to 4In an embodiment, a first insulating layer 902 is formed around the handle substrate 104. The handle substrate 104 and the first insulating layer 902 are then bonded to the device layer 108 (1006) such that the first insulating layer 902 establishes the upper insulating region 106u, the sidewall insulating region 106s, and the lower insulating region 106l. In some embodiments, the upper surface portion of the device layer 108 is then removed, for example, by etching and / or chemical mechanical planarization or grinding operations. Figure 10 More specifically, in Figure 10 In the embodiment, the first insulating layer 902 may be formed to include a getter material having a getter concentration profile, such as Figure 4 Although Figure 4 An exemplary doping concentration profile is shown, but other exemplary doping concentrations (such as in Figures 2A to 2I ) may optionally be used Figure 4 middle.

[0035] Figure 5 Another embodiment is shown in which an SOI substrate 102 includes a handle substrate 104, a device layer 108 located above the handle substrate 104, and an insulator layer 106 separating the handle substrate 104 from the device layer 108. The insulator layer 106 is confined between the device layer 108 and the handle substrate 104, such that the lowermost surface of the insulator layer 106 corresponds to the uppermost surface of the handle substrate 104, and the uppermost surface of the insulator layer 106 corresponds to the lowermost surface of the device layer 108.

[0036] like Figure 6 As shown, in Figure 5 In some embodiments, the insulator layer 106 includes a getter material having a getter concentration profile. The getter concentration profile has a first peak concentration at the first interface 105, a second peak concentration at the second interface 107, and a valley concentration at a location between the first interface 105 and the second interface 107. Figure 6 , the first peak concentration is less than the second peak concentration.

[0037] In some cases, it can be based on Figure 11 form Figures 5 to 6 In an embodiment, a second insulating layer 904 is formed around the device layer 108. The device layer 108 and the second insulating layer 904 are then bonded to the handle substrate 104 (1106), so that the second insulating layer 904 establishes the upper insulating region 106u. In some embodiments, the upper surface portion of the device layer 108 and the portion of the second insulating layer 904 are then removed, for example, by etching and / or chemical mechanical planarization or grinding operations ( Figure 11 More specifically, in Figure 11 In the embodiment, the second insulating layer 904 may be formed to include a layer having aFigure 6 a getter material of the getter concentration profile shown. Although Figure 6 an exemplary doping concentration profile is shown, other exemplary doping concentrations (such as those shown and / or described in Figures 2A to 2I ) may optionally be used for Figure 6 in.

[0038] Thus, in each of Figures 9 to 11 , a processing substrate 104 is received, and a device layer 108 is also received. At least one of the processing substrate 104 and the device layer 108 has an insulator layer on its surface, such as an upper insulating region 106u in the form of an oxide, where the oxide layer includes metal contaminants. For example, the processing substrate 104 may include a first insulating layer 902, and / or the device layer 108 may include a second insulating layer 904, where the first and / or second insulating layer 902 / 904 may include metal contaminants. The processing substrate 104 is bonded to the device layer 108 such that the oxide layer (upper insulating region 106u) separates the processing substrate 104 from the device layer 108. Before bonding the processing substrate 104 to the device layer 108, the insulating layer (902 or 904) undergoes a gettering process, where a halogen species is provided in the insulating layer to scavenge metal contaminants. For example, the gettering process may be used during the initial formation of the first insulating layer 902 and / or the second insulating layer 904, or may be used as a cleaning / purifying process applied to the first insulating layer 902 and / or the second insulating layer 904 after those layers are formed.

[0039] In some embodiments, the gettering process includes subjecting the first insulating layer 902 and / or the second insulating layer 904 to an atmosphere heated to a temperature between 950 °C and 1150 °C for 0.5 hours to 27 hours, where the atmosphere includes trans-1,2-dichloroethylene, nitrogen, and oxygen.

[0040] In some embodiments, after the gettering process, the first insulating layer 902 and / or the second insulating layer 904 has a chlorine concentration profile that has a first peak chlorine concentration at an outer surface region of the insulating layer, the first peak chlorine concentration being in the range of 5×10 18 atoms / cm 3 to 2×10 21 atoms / cm 3 . In an inner region of the first insulating layer 902 and / or the second insulating layer 904, the minimum chlorine concentration of the first insulating layer 902 and / or the second insulating layer 904 is also less than the first peak chlorine concentration.

[0041] In some embodiments, the getter process subjects the first insulating layer 902 and / or the second insulating layer 904 to a first atmosphere that is heated to a first temperature between 700 °C and 950 °C for 5 minutes to 30 minutes, has an HCl gas flow rate between 0.1 standard liters per minute (slm) and 10 slm, an oxygen flow rate between 0.5 slm and 20 slm, and a nitrogen flow rate between 1.0 slm and 30 slm. In other embodiments, the first temperature can be increased and can be in the range between 950 °C and 1100 °C. After subjecting the first insulating layer 902 and / or the second insulating layer 904 to the first atmosphere, the first insulating layer 902 and / or the second insulating layer 904 is subjected to a second atmosphere that is heated to a temperature between 950 °C and 1100 °C for between 0.5 hours and 24 hours, wherein the second atmosphere includes hydrogen, nitrogen, and oxygen. In some embodiments, after the getter process, the first insulating layer 902 and / or the second insulating layer 904 has a chlorine concentration profile at the outer surface region of the first insulating layer 902 and / or the second insulating layer 904, and the first peak chlorine concentration of the chlorine concentration profile is in the range of 5×10 18 atoms / cm 3 to 2×10 21 atoms / cm 3 and has a minimum chlorine concentration less than the first peak chlorine concentration in the inner region of the insulating layer.

[0042] In some embodiments, the getter process subjects the first insulating layer 902 and / or the second insulating layer 904 to a first atmosphere that is heated to a first temperature of about 400 °C for 5 minutes to 30 minutes,

[0043] wherein the first atmosphere includes fluorine gas. After subjecting the first insulating layer 902 and / or the second insulating layer 904 to the first atmosphere, the first insulating layer 902 and / or the second insulating layer 904 is subjected to a second atmosphere that is heated to a temperature between 950 °C and 1100 °C for between 0.5 hours and 24 hours, wherein the second atmosphere includes hydrogen, nitrogen, and oxygen. In some embodiments, after the getter process, the first insulating layer 902 and / or the second insulating layer 904 has a fluorine concentration profile that has a first peak fluorine concentration in the range of 1×10 18 atoms / cm 3 to 1×10 20 atoms / cm 3 at the outer surface region of the first insulating layer 902 and / or the second insulating layer 904, and has a minimum chlorine concentration less than the first peak fluorine concentration in the inner region of the first insulating layer 902 and / or the second insulating layer 904.

[0044] Figure 1 andFigures 2A to 2I and Figures 3 to 6 The SOI substrate shown can be used in various situations. For example, the SOI substrate is used with high-voltage devices, BCD devices, eFlash devices, CMOS image sensors, NIR image sensors, and other devices. The high-voltage device can be, for example, a device that operates at a voltage greater than about 100 volts. In some embodiments, the SOI substrate 102 has a circular top layout and / or has a diameter of about 200, 300, or 450 millimeters. In other embodiments, the SOI substrate 102 has some other shape and / or some other size. Additionally, in some embodiments, the SOI substrate 102 is a semiconductor wafer. The processing substrate 104 can be or include, for example, single-crystalline silicon, some other silicon material, some other semiconductor material, or any combination of the foregoing.

[0045] In some embodiments, the processing substrate 104 has a high resistivity and / or a low oxygen concentration. The high resistivity can be, for example, greater than about 1, 3, 4, or 9 kiloohms per centimeter (kΩ / cm), and / or can be, for example, about 1 - 4 kΩ / cm, about 4 - 9 kΩ / cm, or about 1 - 9 kΩ / cm. The low oxygen concentration can be, for example, less than about 1, 2, 5 parts per million atoms (ppma), and / or can be, for example, between about 0.1 - 2.5 ppma, about 2.5 - 5.0 ppma, or about 0.1 - 5.0 ppma. The low oxygen concentration and the high resistivity reduce the substrate and / or radio frequency (RF) losses, respectively. In some embodiments, the processing substrate 104 has a low resistivity. The low resistivity reduces the cost of the processing substrate 104 but may cause an increase in substrate and / or RF losses. The low resistivity can be, for example, less than about 8, 10, or 12 Ω / cm, and / or can be, for example, between about 8 - 12 Ω / cm, between about 8 - 10 Ω / cm, or between about 10 - 12 Ω / cm. In some embodiments, the processing substrate 104 is doped with a p-type or n-type dopant. The resistivity of the processing substrate 104 can be controlled, for example, by the doping concentration of the processing substrate 104. For example, increasing the doping concentration can decrease the resistivity, while decreasing the doping concentration can increase the resistivity, and vice versa. In some embodiments, the thickness T of the processing substrate 104 hs is about 720 - 780 micrometers, about 720 - 750 micrometers, or about 750 - 780 micrometers.

[0046] The insulator layer 106 is located on the processing substrate 104 and can be or include, for example, silicon oxide, silicon-rich oxide (SRO), some other oxides, some other dielectrics, or any combination of the foregoing. In some embodiments, the insulator layer 106 completely covers the upper surface 104us of the processing substrate 104. In some embodiments, the insulator layer 106 completely surrounds the processing substrate 104. The insulator layer 106 has a first insulator thickness T1 at the top of the processing substrate 104 between the device layer 108 and the processing substrate 104. The first insulator thickness T1 is relatively large to provide a high degree of electrical insulation between the processing substrate 104 and the device layer 108. For example, a high degree of electrical insulation enables reduced leakage current between devices (not shown) on the device layer 108 and / or can enhance the performance of the devices, for example. In some embodiments, the first insulator thickness T1 is about 0.2 - 2.5 microns, about 0.2 - 1.35 microns, or about 1.35 - 2.5 microns and / or greater than about 1 or 2 microns. In some embodiments, the insulator layer 106 has a second insulator thickness T2 at the bottom of the processing substrate 104 and / or along the sidewalls of the processing substrate 104. In some embodiments, the second insulator thickness T2 is less than the first insulator thickness T1. In some embodiments, the second insulator thickness T2 is about 20 - 6000 angstroms, about 20 - 3010 angstroms, or about 3010 - 6000 angstroms.

[0047] In some embodiments, such as in Figure 1 or Figure 3 for example, the insulator layer 106 has a stepped profile at the SOI edge portions 102e of the SOI substrate 102, and the SOI edge portions 102e are on opposite sides of the SOI substrate 102, respectively. In some embodiments, the insulator layer 106 has an upper surface at the SOI edge portions 102e, and the upper surface is recessed vertically by a vertical recess amount VR i . The vertical recess amount VR i can be, for example, about 20 - 6000 angstroms, about 20 - 3010 angstroms, or about 3010 - 6000 angstroms. In some embodiments, the sum of the vertical recess amount VR i and the second insulator thickness T2 is equal to or approximately equal to the first insulator thickness T1. In some embodiments, the insulator layer 106 has a first outer sidewall at the inner edge of the SOI edge portion 102e, and the first outer sidewall is recessed laterally by an insulator lateral recess amount LR i from a second outer sidewall at the outer edge of the insulator layer 106. The insulator lateral recess amount LR i can be, for example, about 0.8 - 1.2 millimeters, about 0.8 - 1.0 millimeters, or about 1.0 - 1.2 millimeters.

[0048] The device layer 108 is located on top of the insulator layer 106 and can be, for example, or include single-crystalline silicon, some other silicon, some other semiconductor material, or any combination of the foregoing. In some embodiments, the device layer 108 and the processing substrate 104 are the same semiconductor material (e.g., single-crystalline silicon). The device layer 108 has a relatively large thickness T d . The relatively large thickness of the device layer 108 can, for example, enable the formation of large semiconductor junctions (e.g., PN junctions) upon which certain devices (e.g., NIR image sensors) rely. In some embodiments, the thickness T d of the device layer 108 is large, greater than about 0.2, 0.3, 1.0, 5.0, or 8.0 microns, and / or is about 0.2 - 8.0 microns, about 0.2 - 4.0 microns, or about 4.0 - 8.0 microns. In some embodiments, the device layer 108 has sidewalls that are at the SOI edge portion 102e and laterally recess from the sidewalls of the processing substrate 104 by a device lateral recess amount LR d . The device lateral recess amount LR d can be, for example, about 1.4 - 2.5 millimeters, about 1.4 - 1.9 millimeters, or about 1.9 - 2.5 millimeters. Additionally, the device lateral recess amount LR d can be, for example, greater than or equal to the insulator lateral recess amount LR i .

[0049] Reference Figure 7 , a top view 700 of some embodiments of the SOI substrate 102 is provided Figure 1 . The SOI substrate 102 is circular and includes a plurality of IC die 702 arranged in a grid across the device layer 108. For ease of illustration, only some of the IC die 702 are labeled 702. In some embodiments, the diameter D of the SOI substrate 102 is about 150, 200, 300, or 450 millimeters. In some embodiments, the first outer sidewall 106sw1 of the insulator layer 106 laterally recesses from the second outer sidewall 106sw2 of the insulator layer 106 by the insulator lateral recess amount LR i . In some embodiments, the sidewalls 108sw of the device layer 108 laterally recess from the sidewalls 104sw (shown in dashed lines) of the processing substrate 104 by the device lateral recess amount LR d . The insulator lateral recess amount LR i can be, for example, about 0.8 - 1.2 millimeters, about 0.8 - 1.0 millimeters, or about 1.0 - 1.2 millimeters. The device lateral recess amount LR d can be, for example, greater than the insulator lateral recess amount LR i and / or can be, for example, about 1.4 - 2.5 millimeters, about 1.4 - 1.9 millimeters, or about 1.9 - 2.5 millimeters.

[0050] Reference Figure 8, provides some cross-sectional views 800 of semiconductor structures that are consistent with Figure 7 and in which Figure 1 the SOI substrate 102 is applied. The semiconductor structure includes a plurality of semiconductor devices 802 that are laterally spaced apart above the device layer 108. The semiconductor devices 802 can be, for example, metal-oxide-semiconductor field-effect transistors (MOSFETs), some other metal-oxide-semiconductor (MOS) devices, some other insulated-gate field-effect transistors (IGFETs), some other semiconductor devices, or any combination of the foregoing. Additionally, the semiconductor devices 802 can be, for example, high-voltage devices, BCD devices, eFlash devices, CMOS image sensors, NIR image sensors, some other devices, or any combination of the foregoing.

[0051] In some embodiments, the semiconductor devices 802 include corresponding source / drain regions 804, corresponding selectively conductive channels 806, corresponding gate dielectric layers 808, corresponding gate electrodes 810, and corresponding spacers 812. For ease of illustration, only some of the source / drain regions 804 are labeled 804, only one selectively conductive channel 806 is labeled 806, only one gate dielectric layer 808 is labeled 808, only one gate electrode 810 is labeled 810, and the spacers 812 are labeled 812. The source / drain regions 804 and the selectively conductive channels 806 are located in the device layer 108. The source / drain regions 804 are respectively located at the ends of the selectively conductive channels 806, and each selectively conductive channel 806 extends from one source / drain region 804 to another source / drain region 804. The source / drain regions 804 have a first doping type and directly adjoin a portion of the device layer 108 that has a second doping type opposite to the first doping type.

[0052] The gate dielectric layers 808 are respectively located above the selectively conductive channels 806, and the gate electrodes 810 are respectively located above the gate dielectric layers 808. The gate dielectric layers 808 can be or include, for example, silicon oxide and / or some other dielectric material, and / or the gate electrodes 810 can be or include, for example, doped polysilicon, metal, some other conductive material, or any combination of the foregoing. The spacers 812 are located above the source / drain regions 804 and line the sidewalls of the gate electrodes 810 and the sidewalls of the gate dielectric layers 808, respectively. The spacers 812 can be or include, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, some other dielectric, or any combination of the foregoing.

[0053] The back-end-of-line (BEOL) interconnect structure 814 covers the SOI substrate 102 and the semiconductor device 802. The BEOL interconnect structure 814 includes an interconnect dielectric layer 816, a plurality of lines 818, and a plurality of vias 820. For ease of illustration, only some of the lines 818 are labeled 818, and only some of the vias 820 are labeled 820. The interconnect dielectric layer 816 can be or include, for example, borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), undoped silicate glass (USG), some other low-k dielectrics, silicon oxide, some other dielectrics, or any combination of the foregoing. As used herein, a low-k dielectric can be or include, for example, a dielectric having a dielectric constant k less than about 3.9, 3, 2, or 1.

[0054] The lines 818 and the vias 820 are alternately stacked in the interconnect dielectric layer 816 and define a conductive path extending to the semiconductor device 802. The conductive path can, for example, electrically couple the semiconductor device 802 to other devices (e.g., other semiconductor devices), contact pads, or some other structure. The lines 818 and the vias 820 can be or include, for example, copper, aluminum copper, aluminum, tungsten, some other metals, or any combination of the foregoing. In some embodiments, the topmost line of the lines 818 is thicker than the lines 818 below it.

[0055] Although described with respect to Figure 1 the embodiment of the SOI substrate 102 in Figure 7 and Figure 8 it should be understood that Figures 7 to 8 the embodiment of the SOI substrate 102 in Figures 2A to 2I and / or Figures 3 to 6 can optionally be used with SOI substrate components of

[0056] Referring to Figures 12 to 23 a series of cross-sectional views 1200-2300 of some embodiments of a method for forming and using the SOI substrate 102 are provided. Although the method is shown as forming Figure 1 the embodiment of the SOI substrate 102 in Figure 3 , Figure 5 the embodiment of the SOI substrate 102 in Figures 12 to 23 it should be understood that the structures shown in

[0057] are not limited to the method and can be separate and independent of the method. Figure 12As shown in the cross-sectional view 1200, a processing substrate 104 is provided. In some embodiments, the processing substrate 104 is or includes single-crystalline silicon, some other silicon material, some other semiconductor material, or any combination of the foregoing. In some embodiments, the processing substrate 104 has a circular top layout and / or has a diameter of about 200, 300, or 450 millimeters. In other embodiments, the processing substrate 104 has some other shape and / or some other size. Additionally, in some embodiments, the processing substrate 104 is a semiconductor wafer. In some embodiments, the processing substrate 104 has a high resistivity and / or a low oxygen concentration. The high resistivity and the low oxygen concentration respectively reduce the substrate and / or RF losses. The high resistivity can be, for example, greater than about 1, 3, 4, or 9 kΩ / cm, and / or can be, for example, between about 1 - 4 kΩ / cm, between about 4 - 9 kΩ / cm, or between about 1 - 9 kΩ / cm. The low oxygen concentration can be, for example, less than about 1, 2, or 5 parts per million atoms (ppma), and / or can be, for example, between about 0.1 - 2.5 ppma, between about 2.5 - 5.0 ppma, or between about 0.1 - 5.0 ppma. In some embodiments, the processing substrate 104 has a low resistivity to reduce the substrate cost because, for example, a high resistivity substrate can be more expensive than a low resistivity substrate. The low resistivity can be, for example, less than about 8, 10, or 12 Ω / cm, and / or can be, for example, about 8 - 12 Ω / cm, about 8 - 10 Ω / cm, or about 10 - 12 Ω / cm. In some embodiments, the processing substrate 104 is doped with a p-type or n-type dopant. The resistivity of the processing substrate 104 can be controlled, for example, by the doping concentration of the processing substrate 104. In some embodiments, the thickness T of the processing substrate 104 hs is about 720 - 780 micrometers, about 720 - 750 micrometers, or about 750 - 780 micrometers.

[0058] is also shown by Figure 12 the cross-sectional view 1200 that a first insulator layer 106a is formed on the upper surface 104us of the processing substrate 104. In some embodiments, the first insulator layer 106a completely covers the upper surface 104us of the processing substrate 104. In at least some embodiments where the processing substrate 104 has a high resistivity, completely covering the upper surface 104us can, for example, prevent arcing during plasma processing performed thereafter. In some embodiments, the first insulator layer 106a completely surrounds the processing substrate 104. In some embodiments, the first insulator layer 106a is or includes silicon oxide and / or some other dielectric. In some embodiments, the thickness T of the first insulator layer 106a fi’ is about 0.2 - 2.0 micrometers, about 0.2 - 1.1 micrometers, or about 1.1 - 2.0 micrometers.

[0059] In some embodiments, the process for forming the first insulator layer 106a includes depositing the first insulator layer 106a by thermal oxidation, chemical vapor deposition (CVD), physical vapor deposition (PVD), some other deposition process, or any combination of the foregoing. For example, the first insulator layer 106a can be deposited by a dry oxidation process using oxygen (e.g., O2) or some other gas as an oxidant. As another example, the first insulator layer 106a can be deposited by a wet oxidation process using water vapor as an oxidant. In some embodiments, the first insulator layer 106a is formed at a temperature of about 800 - 1100 degrees Celsius (°C), about 800 - 950 °C, or about 950 - 1100 °C. For example, in the case of forming the first insulator layer 106a by thermal oxidation (e.g., any one of wet and dry oxidation processes), the first insulator layer 106a can be formed at these temperatures.

[0060] As Figure 13 shown in the cross-sectional view 1300 of ss a sacrificial substrate 1302 is provided. In some embodiments, the sacrificial substrate 1302 is or includes single-crystalline silicon, some other silicon material, some other semiconductor material, or any combination of the foregoing. In some embodiments, the sacrificial substrate 1302 is doped with a p-type or n-type dopant and / or has a low resistivity. The low resistivity can be, for example, less than about 0.01 or 0.02 Ω / cm and / or can be, for example, about 0.01 - 0.2 Ω / cm. In some embodiments, the sacrificial substrate 1302 has a lower resistivity than the processing substrate 104. In some embodiments, the sacrificial substrate 1302 has a circular top layout and / or has a diameter of about 200, 300, or 450 millimeters. In other embodiments, the sacrificial substrate 1302 has some other shape and / or some other size. In some embodiments, the sacrificial substrate 1302 is a bulk semiconductor substrate and / or a semiconductor wafer. In some embodiments, the thickness T ss of the sacrificial substrate 1302 hs is the same as or about the same as the thickness T

[0061] It is also shown by Figure 13 the cross-sectional view 1300 of d that a device layer 108 is formed on the sacrificial substrate 1302. The device layer 108 has a thickness T dis from about 0.7 - 10.0 microns, about 0.7 - 5.0 microns, or about 5.0 - 10.0 microns, and / or greater than about 0.7, 5.0, or 10.0 microns. In some embodiments, device layer 108 is or comprises single crystal silicon, some other silicon material, some other semiconductor material, or any combination of the foregoing. In some embodiments, device layer 108 is or comprises the same semiconductor material as sacrificial substrate 1302, has the same doping type as sacrificial substrate 1302, has a lower doping concentration than sacrificial substrate 1302, or any combination of the foregoing. For example, sacrificial substrate 1302 may be or comprise P+ single crystal silicon, while device layer 108 may be or comprise P- single crystal silicon. In some embodiments, device layer 108 has a low resistivity. The low resistivity may be, for example, greater than the resistivity of sacrificial substrate 1302. Additionally, the low resistivity may be, for example, less than about 8, 10, or 12 Ω / cm, and / or may be, for example, about 8 - 12 Ω / cm, about 8 - 10 Ω / cm, or about 10 - 12 Ω / cm. In some embodiments, device layer 108 has the same doping type, the same doping concentration, the same resistivity as processing substrate 104, or any combination of the foregoing. In some embodiments, the process for forming device layer 108 includes molecular beam epitaxy (MBE), vapor phase epitaxy (VPE), liquid phase epitaxy (LPE), some other epitaxial process, or any combination of the foregoing.

[0062] As Figure 14 shown in cross-sectional view 1400 of, patterned device layer 108 and sacrificial substrate 1302 are provided. The patterning removes an edge region 1304 defined by device layer 108 and sacrificial substrate 1302. By removing edge region 1304, the formation of defects at edge region 1304 during subsequent grinding and / or chemical wet etching is prevented. Edge defects tend to concentrate at edge region 1304 and have a negative impact on the quality of device layer 108. Additionally, the patterning forms a flange 1402 at the edge of sacrificial substrate 1302. Flange 1402 is defined by sacrificial substrate 1302 and has a pair of flange segments on opposite sides of sacrificial substrate 1302, respectively. In some embodiments, flange 1402 has a top layout that extends along the edge of sacrificial substrate 1302 in an annular path or some other closed path. In some embodiments, flange 1402 has a width W of about 0.8 - 1.2 mm, about 0.8 - 1.0 mm, or about 1.0 - 1.2 mm. In some embodiments, flange 1402 is recessed a distance D below the upper surface or top surface of device layer 108, where distance D is about 30 - 120 microns, about 30 - 75 microns, or about 75 - 120 microns. In some embodiments, flange 1402 is further recessed below the upper surface or top surface of sacrificial substrate 1302.

[0063] In some embodiments, patterning is performed by a lithography / etch process or some other patterning process. Additionally, in some embodiments, patterning includes forming a mask 1404 over the device layer 108, etching the device layer 108 and the sacrificial substrate 1302 with the mask 1404 in place, and removing the mask 1404. For example, the mask 1404 is formed such that the device layer 108 and the sacrificial substrate 1302 are completely covered, except at the edge region 1304. In some embodiments, the mask 1404 is or includes silicon nitride, silicon oxide, some other hard mask material, photoresist, some other mask material, or any combination of the foregoing. In some embodiments, a wafer edge exposure (WEE) processing tool is used to form the mask 1404. For example, the process for forming the mask 1404 can include: depositing a photoresist layer on the device layer 108; selectively exposing an edge portion of the photoresist layer to radiation using a WEE processing tool; and developing the photoresist layer to form the mask 1404.

[0064] As Figure 15 shown in the cross-sectional view 1500 of, the device layer 108 and the sacrificial substrate 1302 are cleaned to remove etch residues and / or other undesired by-products generated during the performance of previous processes. In some embodiments, the cleaning process uses a physical brush or a water sprayer to scrub the device layer 108 and the sacrificial substrate 1302. In some embodiments, the cleaning process uses a chemical solution to clean the device layer 108 and the sacrificial substrate 1302. The chemical solution can be, for example, or include hydrofluoric acid or some other chemical solution. In some embodiments, the cleaning increases the distance D by which the flange 1402 is recessed below the upper surface or top surface of the device layer 108.

[0065] As Figure 16 shown in the cross-sectional view 1600 of, a second insulator layer 106b is formed on the upper surface 108us of the device layer 108. In some embodiments, the second insulator layer 106b completely covers the upper surface 108us of the device layer 108. In some embodiments, the second insulator layer 106b completely surrounds the sacrificial substrate 1302 and the device layer 108. In some embodiments, the second insulator layer 106b is or includes silicon oxide and / or some other dielectric. In some embodiments, the second insulator layer 106b is the same dielectric material as the first insulator layer 106a. In some embodiments, the thickness T of the second insulator layer 106b si’ is about 20 - 6000 angstroms, about 20 - 3010 angstroms, or about 3010 - 6000 angstroms.

[0066] In some embodiments, the process for forming the second insulator layer 106b includes depositing the second insulator layer 106b by thermal oxidation, CVD, PVD, some other deposition process, or any combination of the foregoing. For example, the second insulator layer 106b can be deposited by a dry oxidation process using oxygen (e.g., O2) or some other gas as an oxidant. As another example, the second insulator layer 106b can be deposited by a wet oxidation process using water vapor as an oxidant. In some embodiments, the second insulator layer 106b is formed at a temperature of about 750 - 1100 °C, about 750 - 925 °C, or about 925 - 1100 °C. For example, in the case of forming the second insulator layer 106b by thermal oxidation (e.g., any one of wet and dry oxidation processes), the second insulator layer 106b can be formed at these temperatures. In some embodiments, the second insulator layer 106b is formed at a temperature lower than that of the first insulator layer 106a.

[0067] As Figure 17 shown in the cross-sectional view 1700 of

[0068] the sacrificial substrate 1302 is bonded to the processing substrate 104 such that the device layer 108, the first insulator layer 106a, and the second insulator layer 106b are located between the processing substrate 104 and the sacrificial substrate 1302. The bonding presses the first insulator layer 106a and the second insulator layer 106b together and forms a bond 1702 at the interface where the first insulator layer 106a and the second insulator layer 106b are in direct contact. This bonding can be performed, for example, by fusion bonding, vacuum bonding, or some other bonding process. Fusion bonding can be performed, for example, at a pressure of about 1 standard atmosphere (atm), about 0.5 - 1.0 atm, about 1.0 - 1.5 atm, or about 0.5 - 1.5 atm. Vacuum bonding can be performed, for example, at a pressure of about 0.5 - 100 millibars (mBar), about 0.5 - 50 mBar, or about 50 - 100 mBar. Figure 17 In some embodiments, a bonding anneal is performed to strengthen the bond 1702. In some embodiments, the bonding anneal is performed at a temperature of about 300 - 1150 °C, about 300 - 725 °C, or about 735 - 1150 °C. In some embodiments, the bonding anneal is performed for about 2 - 5 hours, about 2 - 3.5 hours, or about 3.5 - 5 hours. In some embodiments, the bonding anneal is performed at a pressure of about 1 atm, about 0.5 - 1.0 atm, about 1.0 - 1.5 atm, or about 0.5 - 1.5 atm. In some embodiments, the bonding anneal is performed while nitrogen (e.g., N2) and / or some other gas flows

[0069] As Figure 18As shown in the cross-sectional view 1800, a first thinning process is performed on the second insulator layer 106b and the sacrificial substrate 1302. The first thinning process removes the upper portion of the second insulator layer 106b and further removes the upper portion of the sacrificial substrate 1302. In some embodiments, the first thinning process is performed on the second insulator layer 106b and the sacrificial substrate 1302 until the device layer 108 and the sacrificial substrate 1302 together have a predetermined thickness T pd . The predetermined thickness T pd can be, for example, about 20 - 45 microns, about 20 - 32.5 microns, or about 32.5 - 45 microns.

[0070] In some embodiments, the first thinning process is performed in part or in whole by a mechanical grinding process. In some embodiments, the first thinning process is performed in part or in whole by chemical mechanical polishing (CMP). In some embodiments, the first thinning process is performed by a mechanical grinding process followed by CMP. As described above, removing the edge region prevents the formation of edge defects at the edge region 1304 during grinding. Edge defects tend to form and concentrate at the edge region 604 during grinding and negatively affect the quality of the device layer 108.

[0071] As Figure 19 shown in the cross-sectional view 1900, the sacrificial substrate 1302 is etched. The etching stops on the device layer 108 and removes the sacrificial substrate 1302. In some embodiments, the etching further removes portions of the second insulator layer 106b that are on the sidewalls of the sacrificial substrate 1302 and the sidewalls of the device layer 108. Additionally, in some embodiments, the etching laterally etches the sidewalls 108sw of the device layer 108. Due to the lateral etching, the sidewalls 108sw of the device layer 108 can be, for example, curved and / or concave. After the etching is completed, the thickness T d of the device layer 108 can be, for example, about 0.6 - 9.5 microns, about 0.6 - 5.05 microns, or about 5.05 - 9.5 microns. In some embodiments, the etching minimally reduces the thickness T d of the device layer 108 due to, for example, over-etching.

[0072] In some embodiments, etching is performed by hydrofluoric acid / nitric acid / acetic acid (HNA) etching, some other wet etching, dry etching, or some other etching. HNA etching can etch the sacrificial substrate 1302, for example, using a chemical solution containing hydrofluoric acid, nitric acid, and acetic acid. The etching has a first etching rate for the material of the sacrificial substrate 1302 and also has a second etching rate for the material of the device layer 108, and the second etching rate is less than the first etching rate. In some embodiments, the first etching rate is about 90 - 100 times, 90 - 95 times, or 95 - 100 times greater than the second etching rate. For example, these embodiments of the first and second etching rates can be produced when the first etching is performed by HNA etching, the sacrificial substrate 1302 is or includes P+ monocrystalline silicon, and the device layer 108 is or includes P- monocrystalline silicon.

[0073] Since etching (e.g., HNA etching) is used to remove the sacrificial substrate 1302, the removal of the sacrificial substrate 1302 can be highly controlled, for example. Thus, the thickness T of the device layer 108 d can be highly uniform across the entire device layer, for example, and the total thickness variation (TTV) of the device layer 108 can be very low, for example. The TTV can be low, less than about 500 or 1500 angstroms. In some embodiments, the TTV decreases as the thickness T of the device layer 108 d decreases. For example, the TTV can be less than about 500 angstroms, where the thickness T of the device layer 108 d is less than about 3000 angstroms, and the TTV can be greater than about 500 angstroms but less than about 1500 angstroms, where the thickness T of the device layer 108 d is greater than about 3000 angstroms.

[0074] As shown in the cross-sectional view 2000 of Figure 20 , the device layer 108 is patterned. The patterning removes the edge portion 108e of the device layer 108. By removing the edge portion 108e, the edge defects formed at the edge portion 108e during etching are removed. The edge defects reduce the quality of the device layer 108 and are formed due to lateral etching into the sidewalls 108sw of the device layer 108 during etching. The patterning further recesses the sidewalls 108sw of the device layer 108 laterally. In some embodiments, after removing the edge portion 108e, the sidewalls 108sw of the device layer 108 are recessed laterally from the sidewalls of the processing substrate 104 by a device lateral recess amount LR d . The device lateral recess amount LR d can be, for example, about 1.4 - 2.5 millimeters, about 1.4 - 1.95 millimeters, or about 1.95 - 2.5 millimeters.

[0075] In some embodiments, patterning is performed by a lithography / etch process or some other patterning process. Additionally, in some embodiments, patterning includes forming a mask 2002 over the device layer 108, etching the device layer 108 with the mask 2002 in place, and removing the mask 2002. The mask 2002 can be, for example, or include, silicon nitride, silicon oxide, some other hard mask material, photoresist, some other mask material, or any combination of the foregoing. The mask 2002 can be formed, for example, such that the device layer 108 is completely covered except at the edge portion 108e, and / or can be formed, for example, using a wafer edge exposure (WEE) processing tool. In some embodiments, the process of forming the mask 2002 using a WEE process tool includes: depositing a photoresist layer on the device layer 108; selectively exposing an edge portion of the photoresist layer to radiation using a WEE processing tool; and developing the photoresist layer to form the mask 2002. The etching can be performed, for example, by dry etching or some other etching, and / or can stop, for example, on the first insulator layer 106a and the second insulator layer 106b. In some embodiments where the processing substrate 104 has a high resistivity (e.g., a resistivity greater than about 1 kΩ / cm) and the etching is performed using dry etching, the first insulator layer 106a and the second insulator layer 106b prevent arc formation by completely covering and / or completely surrounding the processing substrate 104. The mask 2002 can be removed, for example, by plasma ashing or some other removal. Plasma ashing can include, for example, exposing the mask 2002 to an O2 plasma and can be performed, for example, when the mask 2002 is photoresist or includes photoresist.

[0076] In some embodiments, a cleaning process is performed after patterning to remove etch residues and / or other undesired by-products generated during patterning. In some embodiments, the cleaning process removes oxides formed on the device layer 108 during patterning. The cleaning process can be performed, for example, using hydrofluoric acid (HF) or some other chemical solution. Hydrogen fluoride can be, for example, about 0.1%-2.0%, about 0.1%-1.0%, or about 1.0%-2.0% by volume of the HF acid. The remainder of the HF acid can be, for example, deionized water or some other water.

[0077] As Figure 21 shown in the cross-sectional view 2100 of d . In some embodiments, the second thinning process reduces the thickness T of the device layer 108 dReduced to about 0.3 - 8.0 microns, about 0.3 - 4.15 microns, or about 4.15 - 8.0 microns, and / or greater than about 0.3, 1.0, 2.0, 5.0, or 8.0 microns. The device layer 108, the first insulator layer 106a, the second insulator layer 106b, and the processing substrate 104 together define the SOI substrate 102. In some embodiments, the second thinning process is performed by CMP, some other thinning process, or any combination of the foregoing.

[0078] Since the device layer 108 is formed by epitaxy and transferred to the processing substrate 104, the device layer 108 can be formed to have a relatively large thickness (e.g., a thickness greater than about 0.3 microns). Epitaxy is not subject to the thickness limitations associated with other methods of forming device layers. Additionally, since epitaxy is not affected by the thickness of the first insulator layer 106a and the second insulator layer 106b, the first insulator layer 106a and the second insulator layer 106b can be formed individually and / or jointly to have a relatively large thickness (e.g., a thickness greater than about 1 μm). The relatively large thickness of the device layer 108 can, for example, enable the formation of large semiconductor junctions (e.g., PN junctions) upon which some devices (e.g., NIR image sensors) rely. The relatively large thickness of the first insulator layer 106a and the second insulator layer 106b can, for example, facilitate enhanced electrical isolation between devices on the device layer 108 and / or reduce leakage current between devices. Devices that can benefit from the relatively large thickness include, for example, high-voltage devices, BCD devices, eFlash devices, CMOS image sensors, NIR image sensors, some other devices, or any combination of the foregoing.

[0079] As Figure 22 shown in cross-section 2200 of

[0080] In some embodiments, semiconductor device 802 includes corresponding source / drain regions 804, corresponding selectively conductive channels 806, corresponding gate dielectric layers 808, corresponding gate electrodes 810, and corresponding spacers 812. For ease of illustration, only some of the source / drain regions 804 are labeled 804, only one selectively conductive channel 806 is labeled 806, only one gate dielectric layer 808 is labeled 808, only one gate electrode 810 is labeled 810, and only one spacer 812 is labeled 812. The source / drain regions 804 and the selectively conductive channels 806 are located in device layer 108. The source / drain regions 804 are respectively located at the ends of the selectively conductive channels 806, and each selectively conductive channel 806 extends from one source / drain region 804 to another source / drain region 804. The gate dielectric layers 808 are respectively located over the selectively conductive channels 806, and the gate electrodes 810 are respectively located over the gate dielectric layers 808. The spacers 812 are located over the source / drain regions 804 and line the sidewalls of the gate electrodes 810 respectively.

[0081] In some embodiments, the process for forming semiconductor device 802 includes depositing a dielectric layer covering device layer 108 and further depositing a conductive layer covering the dielectric layer. The conductive layer and the dielectric layer are patterned (e.g., by a lithography / etch process) into the gate electrodes 810 and the gate dielectric layers 808. Dopants are implanted into device layer 108 with the gate electrodes 810 in place to define lightly doped portions of the source / drain regions 804, and a spacer layer covering the source / drain regions 804 and the gate electrodes 810 is formed. The spacer layer is etched back to form the spacers 812, and dopants are implanted into device layer 108 with the spacers 812 in place to extend the source / drain regions 804.

[0082] Thus, some embodiments of the present invention relate to a semiconductor-on-insulator (SOI) substrate that includes a processing substrate, a device layer located over the processing substrate, and an insulator layer separating the processing substrate from the device layer. The insulator layer contacts the device layer at a first interface and contacts the processing substrate at a second interface. The insulator layer includes getter material having a getter concentration profile. The getter concentration profile has a first peak concentration at the first interface, a second peak concentration at the second interface, and a valley concentration at a position between the first interface and the second interface. The valley concentration is less than each of the first peak concentration and the second peak concentration.

[0083] In the above SOI substrate, wherein the device layer is disposed above the upper surface of the processing substrate; and wherein the insulator layer covers the upper surface of the processing substrate to separate the upper surface of the processing substrate from the device layer, covers the lower surface of the processing substrate, and covers the sidewalls of the processing substrate.

[0084] In the above SOI substrate, wherein the device layer is disposed above the upper surface of the processing substrate; and wherein the insulator layer covers the upper surface of the processing substrate to separate the upper surface of the processing substrate from the device layer, covers the lower surface of the processing substrate, and covers the sidewalls of the processing substrate, the second interface corresponds to the point where the upper surface of the processing substrate contacts the insulator layer, and the first peak concentration is less than the second peak concentration.

[0085] In the above SOI substrate, wherein the device layer is disposed above the upper surface of the processing substrate; and wherein the insulator layer covers the upper surface of the processing substrate to separate the upper surface of the processing substrate from the device layer, covers the lower surface of the processing substrate, and covers the sidewalls of the processing substrate, the second interface corresponds to the point where the upper surface of the processing substrate contacts the insulator layer, and the first peak concentration is equal to the second peak concentration.

[0086] In the above SOI substrate, wherein the device layer is disposed above the upper surface of the processing substrate; and wherein the insulator layer covers the upper surface of the processing substrate to separate the upper surface of the processing substrate from the device layer, covers the lower surface of the processing substrate, and covers the sidewalls of the processing substrate, the second interface corresponds to the point where the upper surface of the processing substrate contacts the insulator layer, and the first peak concentration is equal to the second peak concentration, the getter material is present in the device layer at a first concentration and in the processing substrate at a second concentration, and the first concentration is less than the second concentration.

[0087] In the above SOI substrate, wherein the device layer is disposed above the upper surface of the processing substrate; and wherein the insulator layer covers the upper surface of the processing substrate to separate the upper surface of the processing substrate from the device layer, covers the lower surface of the processing substrate, and covers the sidewalls of the processing substrate, the first peak concentration is equal to the second peak concentration.

[0088] In the above SOI substrate, wherein the first peak concentration is less than the second peak concentration.

[0089] In the above SOI substrate, wherein the first peak concentration is less than the second peak concentration, the insulator layer is confined between the device layer and the processing substrate such that the lowermost surface of the insulator layer corresponds to the uppermost surface of the processing substrate, and the uppermost surface of the insulator layer corresponds to the lowermost surface of the device layer.

[0090] In the above SOI substrate, wherein the getter material comprises chlorine or fluorine.

[0091] In the above SOI substrate, wherein each of the first peak concentration and the second peak concentration is at least 1×10 18 atoms / cm 3 and the valley concentration is between 1×10 14 atoms / cm 3 and 2×10 17 atoms / cm 3 in the range.

[0092] Other embodiments relate to a method for forming a semiconductor-on-insulator (SOI) substrate. In the method, a processing substrate is received. A device substrate is also received, wherein at least one of the processing substrate and the device substrate has an oxide layer on its surface. The oxide layer includes metal contaminants. The processing substrate is bonded to the device substrate such that the oxide layer separates the processing substrate from the device substrate. Before bonding the processing substrate to the device substrate, the oxide layer is subjected to a getter process, wherein a halogen species is provided in the oxide layer to scavenge metal contaminants.

[0093] In the above method, wherein the getter process includes: subjecting the oxide layer to an atmosphere heated to a temperature of 950 °C to 1150 °C for 0.5 hours to 27 hours, wherein the atmosphere includes trans-1,2-dichloroethylene, nitrogen, and oxygen.

[0094] In the above method, wherein the getter process includes: subjecting the oxide layer to an atmosphere heated to a temperature of 950 °C to 1150 °C for 0.5 hours to 27 hours, wherein the atmosphere includes trans-1,2-dichloroethylene, nitrogen, and oxygen. After the getter process, the oxide layer has a chlorine concentration profile having a first peak chlorine concentration in the range of 5×10 18 atoms / cm 3 to 2×10 21 atoms / cm 3 at the outer surface region of the oxide layer and having a minimum chlorine concentration less than the first peak chlorine concentration in the inner region of the oxide layer.

[0095] In the above method, the getter process includes: subjecting the oxide layer to a first atmosphere, the first atmosphere being heated to a first temperature in the range of 700 °C to 950 °C for 5 minutes to 30 minutes, wherein the first atmosphere includes hydrochloric acid; and after subjecting the oxide layer to the first atmosphere, subjecting the oxide layer to a second atmosphere, the second atmosphere being heated to a temperature in the range of 950 °C to 1100 °C for 0.5 hour to 24 hours, wherein the second atmosphere includes hydrogen, nitrogen, and oxygen.

[0096] In the above method, the getter process includes: subjecting the oxide layer to a first atmosphere, the first atmosphere being heated to a first temperature in the range of 700 °C to 950 °C for 5 minutes to 30 minutes, wherein the first atmosphere includes hydrochloric acid; and after subjecting the oxide layer to the first atmosphere, subjecting the oxide layer to a second atmosphere, the second atmosphere being heated to a temperature in the range of 950 °C to 1100 °C for 0.5 hour to 24 hours, wherein the second atmosphere includes hydrogen, nitrogen, and oxygen, wherein, after the getter process, the oxide layer has a chlorine concentration profile that has a first peak chlorine concentration in the range of 5×10 18 atoms / cm 3 to 2x10 21 atoms / cm 3 and has a minimum chlorine concentration less than the first peak chlorine concentration in the inner region of the oxide layer.

[0097] In the above method, the getter process includes: subjecting the oxide layer to a first atmosphere, the first atmosphere being heated to a first temperature of 400 °C for 5 minutes to 30 minutes, wherein the first atmosphere includes fluorine; and after subjecting the oxide layer to the first atmosphere, subjecting the oxide layer to a second atmosphere, the second atmosphere being heated to a temperature in the range of 950 °C to 1100 °C for 0.5 hour to 24 hours, wherein the second atmosphere includes hydrogen, nitrogen, and oxygen.

[0098] In the above method, the getter process includes: subjecting the oxide layer to a first atmosphere, the first atmosphere being heated to a first temperature of 400 °C for 5 minutes to 30 minutes, wherein the first atmosphere includes fluorine gas; and after subjecting the oxide layer to the first atmosphere, subjecting the oxide layer to a second atmosphere, the second atmosphere being heated to a temperature in the range between 950 °C and 1100 °C for 0.5 hours to 24 hours, wherein the second atmosphere includes hydrogen, nitrogen, and oxygen, wherein after the getter process, the oxide layer has a fluorine concentration profile that has a first peak fluorine concentration in the range of 1×10 18 atoms / cm 3 to 1×10 20 atoms / cm 3 and has a minimum chlorine concentration in the interior region of the oxide layer that is less than the first peak fluorine concentration.

[0099] There are other embodiments related to an integrated circuit that includes a processing substrate, an insulator layer disposed above the processing substrate, and a device layer including single-crystalline silicon disposed above the insulator layer. One or more semiconductor devices are disposed in or above the device layer, and an interconnect structure is disposed above the device layer. The interconnect structure operably couples the one or more semiconductor devices to each other. The insulator layer separates the processing substrate from the device layer, and the insulator layer includes a getter material embedded in the insulating material of the insulator layer.

[0100] In the above integrated circuit, the getter material includes chlorine or fluorine, and the insulating material includes an oxide.

[0101] In the above integrated circuit, the getter material has a concentration in the range between 1×10 14 atoms / cm 3 and 1×10 20 atoms / cm 3 .

[0102] The present invention outlines the features of several embodiments, enabling those skilled in the art to better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments presented herein. Those skilled in the art should also be aware that such equivalent configurations and do not depart from the spirit and scope of the present invention, and they can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor-on-insulator substrate, comprising: A processed substrate; A device layer located above the upper surface of the processed substrate; And An insulator layer that covers the upper surface of the processed substrate to separate the upper surface of the processed substrate from the device layer, the insulator layer also covers the lower surface of the processed substrate and the sidewalls of the processed substrate, the insulator layer contacts the device layer at a first interface and contacts the processed substrate at a second interface, wherein the insulator layer includes metal contaminants and a getter material bonded to the metal contaminants, the getter material has a getter concentration profile, the getter concentration profile has a first peak concentration at the first interface, a second peak concentration at the second interface, and a valley concentration at a position between the first interface and the second interface, the valley concentration being less than each of the first peak concentration and the second peak concentration.

2. The semiconductor-on-insulator substrate according to claim 1, wherein The insulating material of the insulator layer includes an oxide.

3. The semiconductor-on-insulator substrate according to claim 1, wherein, The second interface corresponds to the point where the upper surface of the processed substrate contacts the insulator layer, and the first peak concentration is less than the second peak concentration.

4. The semiconductor-on-insulator substrate according to claim 1, wherein, The second interface corresponds to the point where the upper surface of the processed substrate contacts the insulator layer, and the first peak concentration is equal to the second peak concentration.

5. The semiconductor-on-insulator substrate according to claim 4, wherein, The getter material is present in the device layer at a first concentration and in the processed substrate at a second concentration, the first concentration being less than the second concentration.

6. The semiconductor substrate on insulator according to claim 1, wherein, The first peak concentration is equal to the second peak concentration.

7. The semiconductor-on-insulator substrate according to claim 1, wherein, The first peak concentration is less than the second peak concentration.

8. The semiconductor-on-insulator substrate according to claim 7, wherein, The insulator layer is restricted between the device layer and the processed substrate such that the lowermost surface of the insulator layer corresponds to the uppermost surface of the processed substrate, and the uppermost surface of the insulator layer corresponds to the lowermost surface of the device layer.

9. The semiconductor-on-insulator substrate according to claim 1, wherein, The getter material includes chlorine or fluorine.

10. The semiconductor-on-insulator substrate according to claim 1, wherein, Each of the first peak concentration and the second peak concentration is at least 1×10 of chlorine or fluorine 18 atoms / cm 3 , and the valley concentration is between 1×10 14 atoms / cm 3 and 2×10 17 atoms / cm 3 in the range.

11. A method for forming a semiconductor-on-insulator substrate, the method comprising: Receiving a processed substrate; Receiving a device substrate and an oxide layer, wherein the oxide layer covers the upper surface of the processed substrate, the lower surface of the processed substrate, and the sidewalls of the processed substrate, the oxide layer includes metal contaminants; Bonding the oxide layer above the upper surface of the processed substrate to the device substrate such that the oxide layer separates the upper surface of the processed substrate from the device substrate, the oxide layer contacts the device substrate at a first interface and contacts the processed substrate at a second interface; and Wherein, before bonding the processed substrate to the device substrate, the oxide layer is subjected to a gettering process, wherein a halogen substance is provided in the oxide layer to scavenge the metal contaminants. After the gettering process, the concentration profile of the halogen substance in the oxide layer has a first peak concentration at the first interface, a second peak concentration at the second interface, and a valley concentration at a position between the first interface and the second interface, and the valley concentration is less than each of the first peak concentration and the second peak concentration.

12. The method according to claim 11, wherein, The gettering process includes: subjecting the oxide layer to an atmosphere heated to a temperature of 950 °C to 1150 °C for 0.5 hour to 27 hours, wherein the atmosphere includes trans-1,2-dichloroethylene, nitrogen, and oxygen.

13. The method according to claim 12, wherein, After the suction process, the oxide layer has a chlorine concentration profile that has a first peak chlorine concentration in the range of 5×10 18 atoms / cm 3 to 2×10 21 atoms / cm 3 at the outer surface region of the oxide layer and has a minimum chlorine concentration less than the first peak chlorine concentration in the inner region of the oxide layer.

14. The method according to claim 11, wherein, The gettering process includes: subjecting the oxide layer to a first atmosphere heated to a first temperature in the range of 700 °C to 950 °C for 5 minutes to 30 minutes, wherein the first atmosphere includes hydrochloric acid; and after subjecting the oxide layer to the first atmosphere, subjecting the oxide layer to a second atmosphere heated to a temperature in the range of 950 °C to 1100 °C for 0.5 hour to 24 hours, wherein the second atmosphere includes hydrogen, nitrogen, and oxygen.

15. The method according to claim 14, wherein, After the suction process, the oxide layer has a chlorine concentration profile that has a first peak chlorine concentration in the range of 5×10 18 atoms / cm 3 to 2×10 21 atoms / cm 3 at the outer surface region of the oxide layer, and has a minimum chlorine concentration less than the first peak chlorine concentration in the inner region of the oxide layer.

16. The method according to claim 11, wherein, The gettering process includes: subjecting the oxide layer to a first atmosphere heated to a first temperature of 400 °C for 5 minutes to 30 minutes, wherein the first atmosphere includes fluorine; and after subjecting the oxide layer to the first atmosphere, subjecting the oxide layer to a second atmosphere heated to a temperature in the range of 950 °C to 1100 °C for 0.5 hour to 24 hours, wherein the second atmosphere includes hydrogen, nitrogen, and oxygen.

17. The method according to claim 16, wherein, After the suction process, the oxide layer has a fluorine concentration profile that has a first peak fluorine concentration in the range of 1×10 18 atoms / cm 3 to 1x10 20 atoms / cm 3 at the outer surface region of the oxide layer and has a minimum chlorine concentration less than the first peak fluorine concentration in the inner region of the oxide layer.

18. An integrated circuit, comprising: a processed substrate; an insulator layer disposed above the processed substrate; a device layer including single-crystalline silicon disposed above an upper surface of the processed substrate, wherein one or more semiconductor devices are disposed in or above the device layer; and an interconnect structure disposed above the device layer, wherein the interconnect structure operably couples the one or more semiconductor devices to each other; and Wherein, the insulator layer covers the upper surface of the processing substrate to separate the upper surface of the processing substrate from the device layer, the insulator layer also covers the lower surface of the processing substrate and covers the sidewalls of the processing substrate, the insulator layer contacts the device layer at a first interface, and contacts the processing substrate at a second interface, and wherein the insulator layer includes metal contaminants embedded in the insulating material of the insulator layer and getter materials bonded to the metal contaminants, the getter concentration profile of the getter materials has a first peak concentration at the first interface, a second peak concentration at the second interface, and a valley concentration at a position between the first interface and the second interface, the valley concentration being less than each of the first peak concentration and the second peak concentration.

19. The integrated circuit according to claim 18, wherein, The getter material includes chlorine or fluorine, and the insulating material includes an oxide.

20. The integrated circuit according to claim 18, wherein the getter material has a concentration in the range between 1×10 14 atoms / cm 3 and 1×10 20 atoms / cm 3 .

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