Digital Predistortion Implementation Method, System, Readable Storage Medium and DPD Device

Abstract

The present invention discloses a method, a system, a readable storage medium and a DPD device for realizing digital pre-distortion. The method includes the following steps: after the system is powered on, allocate a fixed digital pre-distortion (DPD) function core, and perform system function initialization based on the DPD function core; after the system function initialization, perform data communication with a field programmable gate array (FPGA) based on the DPD function core. The method of the present invention allocates a fixed digital pre-distortion (DPD) function core, performs system function initialization based on the DPD function core, and after the system function initialization, performs data communication with a field programmable gate array (FPGA) based on the DPD function core, thereby overcoming the problems of large resource consumption and high power consumption in the implementation of the FPGA.

Description

Technical Field

[0001] The present invention relates to the field of communication technologies, and in particular, to a method and system for implementing digital pre-distortion, a readable storage medium, and a DPD device. Background Art

[0002] In a communication system, a power amplifier is a device that is widely used and indispensable. After the amplitude of the input signal exceeds its linear region, the output of this device inevitably generates non-linear distortion, which leads to in-band distortion of the signal and interference of adjacent-band signals. Therefore, the non-linear distortion must be quickly and effectively controlled within a certain range to solve this problem. How to quickly and effectively control the distortion of the power amplifier is a key issue faced by the industry at present.

[0003] The general system methods currently used in the industry are mainly divided into two categories. One category is to implement data acquisition, DPD algorithms, and control output based on FPGA (Field-Programmable Gate Array); the other category is the DSP-FPGA architecture, where FPGA implements data acquisition, transmits the data to DSP (Digital Signal Processing) to complete DPD algorithm processing, and then DSP sends the data back to FPGA to control the output.

[0004] However, the defects of the existing hardware solutions are as follows: as the number of antennas increases, the resource requirements become larger and the cost increases. Summary of the Invention

[0005] Embodiments of the present invention provide a method and system for implementing digital pre-distortion, a readable storage medium, and a DPD device, so as to overcome the problems of large resource consumption and high power consumption in FPGA implementation, and solve the problems of low transmission rate and low processing efficiency in the DSP-FPGA architecture.

[0006] In a first aspect, a first embodiment of the present invention proposes a method for implementing digital pre-distortion, and the method includes the following steps:

[0007] After the system is powered on, allocate a fixed digital pre-distortion (DPD) function core, and perform system function initialization based on the DPD function core;

[0008] After the system function initialization, perform data communication with a field-programmable gate array (FPGA) based on the DPD function core.

[0009] Optionally, before allocating a fixed digital pre-distortion (DPD) function core, the method further includes: configuring the DPD function of the system.

[0010] Optionally, initializing the system functions based on the DPD functional core includes:

[0011] Setting an interrupt handler for the DPD functional core;

[0012] After the interrupt handler is triggered, the DPD functional core reads the communication data returned by the FPGA.

[0013] Optionally, before performing data communication between the DPD functional core and a field programmable gate array (FPGA), the method further includes:

[0014] Configuring a data transfer format between the DPD functional core and the FPGA.

[0015] Optionally, performing data communication between the DPD functional core and a field programmable gate array (FPGA) includes:

[0016] The DPD functional core notifies the FPGA to report data based on the data transfer format;

[0017] After the interrupt handler is triggered, the DPD functional core reads the communication data returned by the FPGA;

[0018] Performing data processing on the communication data by the DPD functional core;

[0019] Sending the data processing result to the FPGA based on the data transfer format by the DPD functional core.

[0020] Optionally, the data transfer format is a serial port transfer format or an Ethernet data format;

[0021] In the case where the data transfer format is a serial port transfer format:

[0022] Configuring the data transfer format between the DPD functional core and the FPGA further includes configuring a serial port transceiver identifier for data transfer between the DPD functional core and the FPGA;

[0023] In the case where the data transfer format is an Ethernet data format:

[0024] Configuring the data transfer format between the DPD functional core and the FPGA further includes configuring a cooperative transfer identifier for data transfer within the processing chip by the DPD functional core.

[0025] In a second aspect, a digital predistortion implementation system according to a second embodiment of the present invention is used to allocate a fixed digital predistortion (DPD) functional core after power-on;

[0026] Initialize the system functions based on the DPD functional core;

[0027] After the system functions are initialized, perform data communication with the Field Programmable Gate Array (FPGA) based on the DPD functional core.

[0028] Optionally, the system processor is further configured to set an interrupt handler for the DPD functional core;

[0029] After the interrupt handler is triggered, the DPD functional core reads the communication data returned by the FPGA.

[0030] Optionally, the system processor is further configured to configure the data transfer format between the DPD functional core and the FPGA.

[0031] Optionally, the data transfer format is a serial port transfer format or an Ethernet data format;

[0032] In the case where the data transfer format is a serial port transfer format:

[0033] Configuring the data transfer format between the DPD functional core and the FPGA further includes configuring a serial port transceiver identifier for data transfer between the DPD functional core and the FPGA.

[0034] In the case where the data transfer format is an Ethernet data format:

[0035] Configuring the data transfer format between the DPD functional core and the FPGA further includes configuring a cooperative transfer identifier for data transfer within the processing chip by the DPD functional core.

[0036] In a third aspect, a computer-readable storage medium is proposed in the third embodiment of the present invention. An implementation program for information transfer is stored on the computer-readable storage medium. When the program is executed by a processor, the steps of the method described in the first embodiment are implemented.

[0037] In a fourth aspect, a DPD device is proposed in the fourth embodiment of the present invention, including: a memory, a processor, and a computer program stored on the memory and executable on the processor. When the computer program is executed by the processor, the steps of the method described in the first embodiment are implemented.

[0038] In an embodiment of the present invention, a fixed digital pre-distortion (DPD) function is allocated, and system function initialization is performed based on the DPD function. After the system function initialization, data communication with a field-programmable gate array (FPGA) is performed based on the core of the DPD function, thereby overcoming the problems of large resource consumption and high power consumption in the implementation of the FPGA, and at the same time solving the problems of low transmission rate and low processing efficiency in the DSP-FPGA architecture, achieving positive technical effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 It is a schematic flowchart of an embodiment of the present invention;

[0040] Figure 2 It is a schematic diagram of the details of the process of an embodiment of the present invention;

[0041] Figure 3 It is a processing flowchart of a single core completing DPD in an embodiment of the present invention;

[0042] Figure 4 It is a DPD processing flowchart of a single core and a high-speed link in an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0043] Hereinafter, exemplary embodiments of the present disclosure will be described in more detail with reference to the drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure can be more thoroughly understood and the scope of the present disclosure can be fully conveyed to those skilled in the art.

[0044] A first embodiment of the present invention proposes a method for implementing digital pre-distortion, as Figure 1 、 Figure 2 shown, the method includes the following steps:

[0045] After the system is powered on, a fixed digital pre-distortion (DPD) function core is allocated, and system function initialization is performed based on the DPD function core;

[0046] After the system function initialization, data communication with a field-programmable gate array (FPGA) is performed based on the DPD function core.

[0047] In this embodiment, the DPD function core refers to one of the physical cores of the processor. The number of cores refers to the number of cores physically, that is, hardware-wise, in the processor. For example, a dual-core includes 2 relatively independent core unit groups, and a quad-core includes 4 relatively independent core unit groups. For another example, if a certain processor has 16 cores and 32 threads, allocating the DPD function core means allocating one of the 16 cores of the processor as a fixed DPD function core.

[0048] Through the above technical solution, the method of the present invention overcomes the problems of large resource consumption and high power consumption in FPGA implementation. At the same time, it also solves the problems of low transmission rate and low processing efficiency in the DSP-FPGA architecture, achieving positive technical effects.

[0049] In this embodiment, a method for implementing the DPD function under the multi-core SMP architecture is used as an example. The method of the present invention includes the following steps:

[0050] Perform data reception and transmission processing and plan memory under the multi-core SMP architecture.

[0051] Allocate a fixed core under the multi-core SMP architecture for the implementation of the DPD function and complete the initialization of related functions.

[0052] Plan the FPGA data processing flow.

[0053] Specifically, in this embodiment, as Figure 2 shown, during system power-on, the system modifies the function of core 11 of the multi-core processor to change it from the original load sharing mode to the DPD exclusive mode; the DPD module is bound to core 11 of the multi-core processor to complete the initialization of memory application and related tasks.

[0054] After the system completes the initialization of memory application and related tasks, data communication with the field programmable gate array FPGA is performed based on the DPD function core.

[0055] Optionally, in an alternative embodiment of the present invention, before allocating a fixed digital predistortion DPD function core, the method further includes: configuring the DPD function of the system.

[0056] Specifically, configure the processing of data reception and transmission under the multi-core SMP architecture, including configuring the kernel to complete the reception processing of the data and placing the data in the specified memory space; defining the data structures and transceiver interfaces required for the DPD function.

[0057] After the configuration is completed, configure an independent core under the multi-core SMP architecture to complete the DPD function, including the initialization of the DPD module, including global scheduling tasks, data acquisition tasks, and table extraction tasks.

[0058] The main data for DPD processing to interact with the FPGA is as follows.

[0059] Register Read / Write DPD Table Read / Write Trapping Table Read / Write DPD Data Read Sampling Configuration RAM Read / Write

[0060] The FPGA sequentially completes the functions of register reading and writing, data acquisition and feedback, and table configuration according to the message control word of the DPD module.

[0061] Optionally, before performing data communication between the DPD functional core and a field programmable gate array (FPGA), the method further includes:

[0062] Configuring a data transmission format between the DPD functional core and the FPGA.

[0063] The configuring of the data transmission format between the DPD functional core and the FPGA further includes configuring a serial port transceiver identifier for use in data transmission between the DPD functional core and the FPGA.

[0064] Specifically, in this embodiment, as Figure 3 shown, in a multi-core symmetric multi-processing (SMP) architecture, data communication is completed through a direct serial connection between the DPD module and the FPGA.

[0065] In this embodiment, the data definition between the DPD module and the FPGA in a multi-core SMP architecture is as follows.

[0066] Data Start Read / Write Control Read / Write Entry Load Data End 0x5a5a 2Byte 2Byte 1448Byte 0xa5a5

[0067] Optionally, in an alternative embodiment of the present invention, the initializing of the system functions based on the DPD functional core includes:

[0068] Setting an interrupt handler based on the DPD functional core;

[0069] After the interrupt handler is triggered, the DPD functional core reads the communication data returned by the FPGA.

[0070] As Figure 3 shown, in this embodiment, the system kernel (such as the Linux system kernel) adds an interrupt handler for core 11 (core11 in the figure) during the initialization process. When the DPD module (DPD functional core) needs data, it sends a message through a low-speed link (serial port) to notify the FPGA to report data. After the interrupt handler is triggered, core 11 retrieves the data from the cache.

[0071] Optionally, in yet another alternative embodiment of the present invention, the data communication between the DPD functional core and the field programmable gate array (FPGA) includes:

[0072] The DPD functional core notifies the FPGA to report data based on the data transmission format;

[0073] Intercepting the communication data returned by the FPGA to the DPD functional core through the interrupt handler;

[0074] Performing data processing on the communication data by the DPD functional core;

[0075] The data processing result is sent to the FPGA based on the data transmission format through the DPD functional core.

[0076] Specifically, after the data transmission format between the above DPD functional core and the FPGA is configured, in this embodiment, when the DPD module needs data, a message is sent through the serial port to inform the FPGA to report data. After the data is sent back, an interrupt is triggered to core 11. The DPD functional core starts a timed query task. After querying that the required data has been received, the DPD functional core starts a thread to complete the DPD algorithm calculation. After completion, the calculated data is sent to the FPGA through the serial port.

[0077] Furthermore, in this embodiment, the processing chip MSC0 is directly connected to the FPGA through the serial port, as Figure 2 、 Figure 3 shown. When the DPD functional core core11 needs data, it informs the FPGA through the serial port. The FPGA reports data through the serial port and transmits it to the buffer BUF. The system kernel triggers an interrupt handler and notifies the DPD functional core core11. The DPD functional core core11 retrieves the data from the buffer BUF. At the same time, core11 starts a timed query task. After querying that the required data has been received, core11 starts a thread to run the calculation program to complete the DPD algorithm calculation. On the basis of the foregoing embodiment, further explanation is as follows. For example, if a certain processor has 16 cores and 32 threads, the selected core 11 can simulate two logical cores, that is, two threads. During operation, one thread of core11 can be selected to complete the algorithm calculation. After completion, the calculated data is sent to the FPGA through the serial port. See Figure 3 for the XC data transmission in

[0078] On the basis of the existing system, in this embodiment, the FPGA completes data acquisition, uses the defined data structure, and completes data transceiver processing through the ordinary path (serial port). In the multi-core SMP architecture, one core is used to receive data, complete the DPD operation, and use the defined data transceiver flag to send the data back to the FPGA through the low-speed path for control.

[0079] Compared with the prior art, the method of this embodiment reduces the demand for FPGA resources, saves hardware resources, and improves resource utilization.

[0080] A second embodiment of the present invention proposes a digital pre-distortion implementation method, as Figure 1 、 Figure 2 shown. The method includes the following steps:

[0081] After the system is powered on, allocate a fixed digital pre-distortion (DPD) function core, and initialize the system functions based on the DPD function core;

[0082] After the system functions are initialized, perform data communication with the field programmable gate array (FPGA) based on the DPD function core.

[0083] In this embodiment, the DPD function core refers to one of the physical cores of the processor. The number of cores refers to the number of cores physically, that is, hardware-wise, in the processor. For example, a dual-core includes 2 relatively independent core units, and a quad-core contains 4 relatively independent core units. Another example is that a certain processor has 16 cores and 32 threads, then allocating the DPD function core means allocating one of the 16 cores of the processor as a fixed DPD function core.

[0084] Through the above technical solution, the method of the present invention overcomes the problems of large resource consumption and high power consumption in FPGA implementation, and at the same time solves the problems of low transmission rate and low processing efficiency in the DSP-FPGA architecture, achieving positive technical effects.

[0085] In this embodiment, the method for implementing the DPD function under the multi-core symmetric multi-processing (SMP) architecture is used as an example. The method of the present invention includes the following steps:

[0086] Perform data reception and transmission processing and plan the memory under the multi-core SMP architecture.

[0087] Allocate a fixed core under the multi-core SMP architecture for the implementation of the DPD function and complete the initialization of related functions.

[0088] Plan the FPGA data processing flow.

[0089] Specifically, in this embodiment, as Figure 2 shown, during system power-on, modify the function of core 11 of the multi-core processor to change it from the original load-sharing mode to the DPD exclusive mode; bind the DPD module to core 11 of the multi-core processor, and complete the initialization of memory application and related tasks.

[0090] After completing the initialization of memory application and related tasks, perform data communication with the field programmable gate array (FPGA) based on the DPD function core.

[0091] Optionally, in an alternative embodiment of the present invention, before allocating a fixed digital pre-distortion (DPD) function core, the method further includes: configuring the DPD function of the system.

[0092] Specifically, configure the processing of data reception and transmission under the multi-core SMP architecture, including configuring the kernel to complete the reception processing of the data and placing the data in the specified memory space; define the data structures and transceiver interfaces required for the DPD function.

[0093] After the configuration is completed, configure an independent core under the multi-core SMP architecture to complete the DPD function. The initialization of the DPD module includes global scheduling tasks, data acquisition tasks, and table extraction tasks. The main data for the DPD processing to interact with the FPGA is as follows.

[0094] Register Read / Write DPD Table Read / Write Trapping Table Read / Write DPD Data Read Sampling Configuration RAM Read / Write

[0095] The FPGA sequentially completes the register reading and writing, data acquisition and feedback, and table configuration functions according to the message control word of the DPD module.

[0096] Optionally, before performing data communication between the DPD function core and the field programmable gate array (FPGA), the method further includes:

[0097] Configure the data transmission format between the DPD function core and the FPGA.

[0098] In this embodiment, when the data transmission format is the Ethernet data format, configuring the data transmission format between the DPD function core and the FPGA further includes configuring a cooperative transmission identifier, which is used for data transmission within the chip by the DPD function core.

[0099] Specifically, in this embodiment, the DPD module and the FPGA under the multi-core SMP architecture use a high-speed path, such as Figure 4 As shown, between the multi-core DPD module and the FPGA, a cooperative data transmission path is used inside the chip, and a high-speed Ethernet link is used outside.

[0100] The data definition between the FPGA and the DPD function of the multi-core SMP architecture is as follows.

[0101] The IP data format and length for the DPD module to communicate with the FPGA are as follows:

[0102] MAC Header IP Header Key Header Payload 14Byte 20Byte 32Byte 1448Byte

[0103] Define the cooperative data transmission key value and Link ID used by the DPD module to receive data. Currently, the first 4 bytes are used in the 32-byte cooperative data transmission header above.

[0104] The first byte is the device type. Currently, the multi-core processor uniformly uses 0x02.

[0105] The second byte is the subsystem number. Currently, it is defined as 0x71.

[0106] The third and fourth bytes are customized according to the extension. Currently, they are 0x01 0x00.

[0107] Therefore, the key value of the cooperative data transfer header is: 0x02 0x71 0x01 0x00.

[0108] The Link ID used by DPD. From the Link ID table, an unused space is planned for DPD to use. For example, the Link ID used in this embodiment is 0xC000.

[0109] The key value of the cooperative data transfer header used by the FPGA to receive data is defined according to the foregoing rules as:

[0110] 0x02 0x72 0x01 0x00

[0111] The first 9 bytes in the Payload are the interaction control information between the DPD module and the FPGA, and the following X bytes are the valid data. The specific structure is defined as follows:

[0112]

[0113] Command: 0 means read, 1 means write.

[0114] Address: The starting address for register or RAM access.

[0115] Length: The data length, in bytes.

[0116] The valid data of this packet: For the four types of operations of single register read / write, DPD table read / write, Trapping table read / write, and sampling configuration RAM read / write, the valid data length is within 1448 bytes.

[0117] Register Read and Write 2Bytes DPD Table Read and Write 64 * 8Bytes Trapping Table Read and Write 32 * 2Bytes Sampling Configuration RAM Read and Write 4Bytes

[0118] For the DPD data read operation, since the data length read at one time is 8192 * 2 bytes, which is greater than 1448 bytes, in this embodiment, it is directly divided into 1024 bytes per packet, and a total of 16 packets are transmitted to complete.

[0119] Requirement Data Length DPD Data Read 1024Bytes * 16 Packets

[0120] Optionally, the system function initialization based on the DPD functional core includes:

[0121] Setting an interrupt handler based on the DPD functional core;

[0122] After the interrupt handler is triggered, the DPD functional core reads the communication data returned by the FPGA.

[0123] As Figure 4 shown, in this embodiment, the system kernel adds an interrupt handler for core 11 in the initialization process. When the DPD module (DPD functional core) needs data, it sends a message through the high-speed link, which can be an Ethernet link in this embodiment, to notify the FPGA to report data. After the data is returned, the system kernel triggers the interrupt handler, and core 11 retrieves the data from the cache.

[0124] Optionally, in an alternative embodiment of the present invention, the data communication between the DPD functional core and the field programmable gate array FPGA includes:

[0125] The DPD functional core notifies the FPGA to report data based on the data transmission format;

[0126] The communication data returned by the FPGA is intercepted to the DPD functional core through the interrupt handler;

[0127] Data processing is performed on the communication data by the DPD functional core;

[0128] The data processing result is sent to the FPGA by the DPD functional core based on the data transmission format.

[0129] Specifically, in this embodiment, when the DPD module needs data, it sends a message through the high-speed link (Ethernet link) to notify the FPGA to report data; after the data is returned, an interrupt is triggered to core 11, and a timed query task is started; after it is queried that the required data has been received, a thread is started to complete the DPD algorithm calculation, and after completion, the data is sent to the FPGA.

[0130] Furthermore, in this embodiment, when the data transmission format is the Ethernet data format, data is transmitted inside the processing chip MSC0 through the cooperative transmission identifier and externally through the use of a high-speed Ethernet link. In this embodiment, as Figure 2 、 Figure 4As shown in the figure, a hardware switching unit SW is also provided between the processing chip MSC0 and the FPGA for high-speed link communication. When the DPD functional core core11 needs data, it notifies the FPGA through the Ethernet link. The FPGA reports data through the Ethernet link and transmits it to the transceiver interface DXGE of the processing chip MSC0. Then, the transceiver interface DXGE transmits the data to the accelerator RDM / XC. The accelerator RDM / XC places the data in the corresponding cache BUF according to the key value of the data. The cooperative transmission identifier is used for high-speed data transmission between the DPD functional core, the transceiver interface DXGE, the accelerator RDM / XC and other internal chip structures. Then, the system kernel triggers an interrupt handler and notifies the DPD functional core core11. The DPD functional core core11 retrieves the data from the cache BUF. At the same time, core11 starts a timed query task. After querying that the required data has been received, core11 starts a thread to run the calculation program to complete the DPD algorithm calculation. On the basis of the foregoing embodiment, further illustrate. For example, if a certain processor is a 16-core 32-thread processor, the selected core 11 can simulate two logical cores, that is, dual threads. During operation, one thread of core11 can be selected to complete the algorithm calculation. After completion, the calculated data is sent to the transceiver interface DXGE of the processing chip MSC0. See Figure 4 the XC data transmission in it. Finally, the system sends the data to the FPGA through the hardware switching unit SW through the transceiver interface DXGE of the processing chip MSC0.

[0131] In this embodiment, the FPGA completes data acquisition and uses the defined key value to complete data transceiver processing through the high-speed path. Under the multi-core SMP architecture, one core receives data, completes the DPD operation, and uses the defined data transceiver flag to send the data back to the FPGA through the high-speed path for control. Compared with the first embodiment, the transmission delay can be further reduced, and the processing efficiency of DPD is provided.

[0132] In a third aspect, a digital pre-distortion implementation device is proposed in the third embodiment of the present invention. The device includes:

[0133] A core allocation module, configured to allocate a fixed digital pre-distortion DPD functional core after the system is powered on;

[0134] An initialization module, configured to perform system function initialization based on the DPD functional core;

[0135] After the system function initialization, data communication with the field programmable gate array FPGA is performed based on the DPD functional core.

[0136] In this embodiment, see Figure 3, the core allocation module and the initialization module can be integrated at the system level to implement the above functions through the system.

[0137] Specifically, as Figure 2 shown, during system power-on, the system modifies the function of core 11 of the multi-core processor to change it from the original load sharing mode to the DPD exclusive mode. The DPD module is bound to core 11 of the multi-core processor to complete the initialization of memory application and related tasks.

[0138] Through the above technical solution, the method of the present invention overcomes the problems of large resource consumption and high power consumption in FPGA implementation, and at the same time solves the problems of low transmission rate and low processing efficiency in the DSP-FPGA architecture, achieving positive technical effects.

[0139] Optionally, the device further includes: a configuration module for configuring the DPD function of the system.

[0140] Optionally, the configuration module is further used to configure the data transmission format between the DPD function core and the FPGA.

[0141] Among them, optionally, the data transmission format is a serial port transmission format or an Ethernet data format;

[0142] In an optional embodiment of the present invention, the data transmission format is a serial port transmission format.

[0143] The configuration module is further used to configure the serial port transceiver identifier, and the serial port transceiver identifier is used for data transmission between the DPD function core and the FPGA.

[0144] Specifically, in this embodiment, between the DPD module and the FPGA in the multi-core SMP architecture, a serial port transceiver data format is defined for data transceiver transmission, and the configuration module can also be integrated at the system level.

[0145] Optionally, the initialization module is further used to set an interrupt handling program based on the DPD function core;

[0146] After the interrupt handling program is triggered, the DPD function core reads the communication data returned by the FPGA.

[0147] Optionally, the data communication between the DPD function core and the field programmable gate array FPGA based on the DPD function core includes:

[0148] The DPD function core notifies the FPGA to report data based on the data transmission format;

[0149] After the interrupt handling program is triggered, the DPD function core reads the communication data returned by the FPGA;

[0150] The DPD functional core processes data according to the communication data;

[0151] The DPD functional core sends the data processing result to the FPGA based on the data transmission format.

[0152] Specifically, the management module of the system adds an interrupt handler for core 11 during the initialization process. When the DPD module needs data, it sends a message through a low-speed link (serial port) to notify the FPGA to report data; after the data is sent back, an interrupt is triggered to core 11 to start a periodic query task; after it is queried that the required data has been received, a thread is started to complete the DPD algorithm calculation, and after completion, the data is sent to the FPGA.

[0153] Furthermore, in this embodiment, the core allocation module, the initialization module, and the configuration module can all be integrated within the system level. The processing chip MSC0 is directly connected to the FPGA through a serial port, as Figure 2 , Figure 3 shown. When core 11 needs data, it notifies the FPGA through the serial port. The FPGA reports data through the serial port and transmits it to the buffer BUF of the processing chip. The system kernel triggers the interrupt handler and notifies the DPD functional core core11. The DPD functional core core11 retrieves the data from the buffer BUF. At the same time, core11 starts a periodic query task. After it is queried that the required data has been received, core11 starts a thread to run the calculation program to complete the DPD algorithm calculation. On the basis of the foregoing embodiment, further illustrate. For example, if a certain processor has 16 cores and 32 threads, the selected core 11 can simulate two logical cores, that is, dual threads. During operation, one thread of core11 can be selected to complete the algorithm calculation, and after completion, the calculated data is sent to the FPGA through the serial port. See Figure 3 for the XC data transmission in

[0154] Fourthly, a digital pre-distortion implementation device is proposed in the fourth embodiment of the present invention. The device includes:

[0155] A core allocation module, configured to allocate a fixed digital pre-distortion (DPD) functional core after the system is powered on;

[0156] An initialization module, configured to initialize the system functions based on the DPD functional core;

[0157] After the system functions are initialized, data communication with a field programmable gate array (FPGA) is performed based on the DPD functional core.

[0158] In this embodiment, see Figure 4, the core allocation module and the initialization module can be integrated into the system level (such as the Linux system), so as to implement the above functions through the system.

[0159] Specifically, as Figure 2 shown, during system power-on, the function of core 11 of the multi-core processor is modified to change from the original load sharing mode to the DPD exclusive mode. The DPD module is bound to core 11 of the multi-core processor, and the initialization of memory application and related tasks is completed.

[0160] Through the above technical solution, the method of the present invention overcomes the problems of large resource consumption and high power consumption in FPGA implementation, and at the same time solves the problems of low transmission rate and low processing efficiency under the DSP-FPGA architecture, achieving positive technical effects.

[0161] Optionally, the device further includes: a configuration module for configuring the DPD function of the system.

[0162] Optionally, the configuration module is further used to configure the data transmission format between the DPD function core and the FPGA.

[0163] In an optional embodiment of the present invention, the data transmission format is an Ethernet data format.

[0164] The configuration module is further used to configure a cooperative transmission identifier, and the cooperative transmission identifier is used for data transmission inside the chip by the DPD function core.

[0165] In this embodiment, between the DPD module and the FPGA under the multi-core SMP architecture, an Ethernet standard data format is defined, and a cooperative data transmission field is added for data sending and receiving transmission.

[0166] Optionally, the initialization module is further used to set an interrupt handling program based on the DPD function core;

[0167] After the interrupt handling program is triggered, the DPD function core reads the communication data returned by the FPGA.

[0168] Optionally, the data communication between the DPD function core and the field programmable gate array FPGA based on the DPD function core includes:

[0169] The DPD function core notifies the FPGA to report data based on the data transmission format;

[0170] After the interrupt handling program is triggered, the DPD function core reads the communication data returned by the FPGA;

[0171] The DPD function core processes the data according to the communication data;

[0172] The data processing result is sent to the FPGA based on the data transmission format through the DPD function core.

[0173] Furthermore, in the case where the data transmission format is the Ethernet data format, in this embodiment, the core allocation module, the initialization module, and the configuration module can all be integrated into the system level. Inside the processing chip MSC0, data is transmitted through the cooperative transmission identifier, and externally through the use of a high-speed Ethernet link. In this embodiment, as Figure 2 , Figure 4 shown, a hardware switching unit SW is also provided between the processing chip MSC0 and the FPGA. When core 11 needs data, it notifies the FPGA through the Ethernet link. The FPGA reports data through the Ethernet link and transmits it to the transceiver interface DXGE of the processing chip MSC0. Then, the transceiver interface DXGE transmits the data to the accelerator RDM / XC. The accelerator RDM / XC places the data in the corresponding cache BUF according to the key value of the data. The cooperative transmission identifier is used for high-speed data transmission between the internal structures of chips such as the DPD function core, the transceiver interface DXGE, and the accelerator RDM / XC. Then, the system kernel triggers an interrupt program and notifies the DPD function core core11. The DPD function core core11 retrieves the data from the cache BUF. At the same time, core11 starts a timed query task. After querying that the required data has been received, core11 starts a thread to run the calculation program to complete the DPD algorithm calculation. On the basis of the foregoing embodiment, further illustrate that, for example, if a certain processor has 16 cores and 32 threads, the selected core 11 can simulate two logical cores, that is, two threads. During operation, one thread of core11 can be selected to complete the algorithm calculation. After completion, the calculated data is sent to the transceiver interface DXGE of the processing chip MSC0. See Figure 4 for the XC data transmission in . Finally, the transceiver interface DXGE of the processing chip MSC0 sends the data to the FPGA through the hardware switching unit SW.

[0174] The above transceiver interface DXGE, accelerator RDM / XC, and cache BUF can also be integrated into the processing chip MCS0. In the case where the data transmission format is the Ethernet data format, by modifying the function of core 11 of the processor, its mode changes from the original load sharing mode to the DPD exclusive mode, and external data communication with the FPGA is achieved through the hardware switching unit SW.

[0175] In this embodiment, the management module of the system adds an interrupt handler for core 11 during the initialization process. When the DPD module needs data, it sends a message through a high-speed link (Ethernet link) to instruct the FPGA to report data. After the data is transmitted back, an interrupt is triggered to core 11 to start a periodic query task. After it is queried that the required data has been received, a thread is started to complete the DPD algorithm calculation, and after completion, the data is sent to the FPGA.

[0176] In a fifth aspect, a fifth embodiment of the present invention provides a computer-readable storage medium, on which an implementation program for information transmission is stored. When the program is executed by a processor, the steps of the method according to the first embodiment or the second embodiment are implemented.

[0177] In a sixth aspect, a sixth embodiment of the present invention provides a DPD device, including: a memory, a processor, and a computer program stored on the memory and executable on the processor. When the computer program is executed by the processor, the steps of the method according to the first embodiment or the second embodiment are implemented.

[0178] It should be noted that in this article, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, article or device including the element.

[0179] The serial numbers of the above embodiments of the present invention are only for description and do not represent the superiority or inferiority of the embodiments.

[0180] Through the description of the above embodiments, those skilled in the art can clearly understand that the above-described embodiment methods can be implemented by means of software plus a necessary general hardware platform. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. The computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disc), including several instructions for causing a terminal (which can be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to execute the methods described in various embodiments of the present invention.

[0181] The embodiments of the present invention have been described above in conjunction with the accompanying drawings. However, the present invention is not limited to the above specific embodiments. The above specific embodiments are merely illustrative and not restrictive. Under the inspiration of the present invention, those of ordinary skill in the art can also make many forms without departing from the purpose of the present invention and the scope protected by the claims. All of these are within the protection scope of the present invention.

Claims

1. A method for implementing digital predistortion, characterized in that The method includes the following steps: After the system is powered on, allocate a fixed digital pre-distortion (DPD) function core, and initialize the system functions based on the DPD function core; Among them, the initialization of the system functions based on the DPD function core includes: Set the interrupt handler of the DPD function core; After the interrupt handler is triggered, the DPD function core reads the communication data returned by the FPGA; Configure the data transmission format between the DPD function core and the FPGA; After the system functions are initialized, the DPD function core notifies the FPGA to report data based on the data transmission format between the DPD function core and the FPGA; After the interrupt handler is triggered, read the communication data returned by the FPGA through the DPD function core; Perform data processing on the communication data through the DPD function core; Send the data processing result to the FPGA based on the data transmission format through the DPD function core.

2. The method according to claim 1, wherein Before allocating a fixed digital pre-distortion (DPD) function core, the method further includes: configuring the DPD function of the system.

3. The method according to claim 1, wherein The data transmission format is a serial port transmission format or an Ethernet data format; In the case where the data transmission format is a serial port transmission format: Configuring the data transmission format between the DPD function core and the FPGA further includes configuring a serial port transceiver identifier, which is used for data transmission between the DPD function core and the FPGA; In the case where the data transmission format is an Ethernet data format: Configuring the data transmission format between the DPD function core and the FPGA further includes configuring a cooperative transmission identifier, which is used for data transmission inside the processing chip by the DPD function core.

4. A digital pre-distortion implementation system, characterized in that, The system is used to allocate a fixed digital pre-distortion (DPD) function core after being powered on; Initialize the system functions based on the DPD function core; Among them, the initialization of the system functions based on the DPD function core includes: Set the interrupt handler of the DPD function core; After the interrupt handler is triggered, the DPD function core reads the communication data returned by the FPGA; Configure the data transmission format between the DPD function core and the FPGA; After the system functions are initialized, the DPD function core notifies the FPGA to report data based on the data transmission format between the DPD function core and the FPGA; After the interrupt handler is triggered, read the communication data returned by the FPGA through the DPD function core; Perform data processing on the communication data through the DPD function core; Send the data processing result to the FPGA based on the data transmission format through the DPD function core.

5. The system according to claim 4, wherein The system is further used to configure the data transmission format between the DPD function core and the FPGA.

6. The system according to claim 5, wherein The data transmission format is a serial port transmission format or an Ethernet data format; In the case where the data transmission format is a serial port transmission format: Configuring the data transfer format between the DPD function core and the FPGA further includes configuring a serial port transceiver identifier for data transfer between the DPD function core and the FPGA; In the case where the data transfer format is an Ethernet data format: Configuring the data transfer format between the DPD function core and the FPGA further includes configuring a collaborative transfer identifier for data transfer within the processing chip by the DPD function core.

7. A computer-readable storage medium, characterized in that, An implementation program for information transfer is stored on the computer-readable storage medium, and when the program is executed by a processor, the steps of the method according to any one of claims 1 to 3 are implemented.

8. A DPD device, characterized in that, Comprising: A memory, a processor, and a computer program stored on the memory and executable on the processor, and when the computer program is executed by the processor, the steps of the method according to any one of claims 1 to 3 are implemented.

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