Integrated clock gating cell and integrated circuit including integrated clock gating cell

Abstract

The clock gating cell includes an input logic / latch circuit, a keeper logic / signal generation circuit, and an output driver. The input logic / latch circuit generates an internal enable signal based on a first input enable signal and a second input enable signal, and generates a first internal signal provided to a first node based on the internal enable signal and an input clock signal. The keeper logic / signal generation circuit is connected between the first node and a second node, includes a feedback path that feeds back the first internal signal, generates a second internal signal provided to the second node based on the first internal signal and the input clock signal, and includes a first path and a second path that discharge the second node. The first path and the second path are different. The second path is connected to the feedback path. The output driver generates an output clock signal based on the second internal signal.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0120432, filed on September 30, 2019, with the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference. Technical Field

[0003] Exemplary embodiments generally relate to semiconductor integrated circuits, and more specifically, to an integrated clock gating unit and an integrated circuit including the integrated clock gating unit. Background Technology

[0004] As manufacturing processes miniaturize and more logic circuits are integrated onto a single chip, the use of sequential logic units (such as flip-flops and clock-gated units) is increasing. Clock gating is a common technique used to reduce clock power by interrupting the clock for digital circuit modules with a clock enable signal. Recently, most systems include flip-flops and clock-gated units that provide clock signals to the flip-flops, and because these logic units have relatively high power consumption, reducing the power consumption of flip-flops and clock-gated units is desirable. Furthermore, with increasing operating frequencies, the operating speed of flip-flops and clock-gated units has an increasing impact on the overall chip operating speed. Summary of the Invention

[0005] At least one exemplary embodiment of this disclosure provides an integrated clock gating unit with relatively low power consumption and relatively high operating speed.

[0006] At least one exemplary embodiment of this disclosure provides an integrated circuit including an integrated clock gating unit.

[0007] According to an exemplary embodiment, the integrated clock gating unit includes input logic and latching circuitry, hold logic and signal generation circuitry, and an output driver. The input logic and latching circuitry generates an internal enable signal based on a first input enable signal and a second input enable signal, and generates a first internal signal provided to a first node based on the internal enable signal and an input clock signal. The hold logic and signal generation circuitry is connected between the first node and a second node, includes a feedback path for feeding back the first internal signal, generates a second internal signal provided to the second node based on the first internal signal and the input clock signal, and includes a first path and a second path for discharging the second node. The first path and the second path are different paths, and the second path is connected to the feedback path. The output driver generates an output clock signal based on the second internal signal.

[0008] According to an exemplary embodiment, the integrated circuit includes combinational logic circuitry and an integrated clock gating unit. The combinational logic circuitry performs logical operations on data based on an output clock signal. The integrated clock gating unit selectively provides an output clock signal to the combinational logic circuitry based on at least one input enable signal and an input clock signal. The integrated clock gating unit includes input logic and latching circuitry, hold logic and signal generation circuitry, and an output driver. The input logic and latching circuitry generates an internal enable signal based on a first input enable signal and a second input enable signal, and generates a first internal signal provided to a first node based on the internal enable signal and the input clock signal. The hold logic and signal generation circuitry is connected between the first node and a second node, includes a feedback path for feeding back the first internal signal, generates a second internal signal provided to the second node based on the first internal signal and the input clock signal, and includes a first path and a second path for discharging the second node. The first path and the second path are different paths, and the second path is connected to the feedback path. The output driver generates an output clock signal based on the second internal signal.

[0009] According to an exemplary embodiment, the integrated clock gating unit includes a NOR gate, a latch, a NAND gate, a feedback inverter, a tri-state inverter, a feedback and discharge circuit, and an output driver. The NOR gate generates an internal enable signal based on a first input enable signal and a second input enable signal. The latch generates a first internal signal provided to a first node based on the internal enable signal and an input clock signal. The NAND gate is connected between the first node and a second node, generates a second internal signal provided to the second node based on the first internal signal and the input clock signal, and includes a first path for discharging the second node. The feedback inverter includes an input terminal connected to the first node and an output terminal connected to a third node, and includes a feedback path for feeding back the first internal signal. The tri-state inverter includes an input terminal connected to the third node and an output terminal connected to the first node, forming a feedback path. The feedback and discharge circuit is connected between the second node and the third node and includes a second path for discharging the second node. The output driver generates an output clock signal based on the second internal signal. The first path and the second path are different paths, the second path is connected to the feedback path, and the second path is configured to perform both feedback and discharge functions simultaneously.

[0010] The integrated clock gating unit and integrated circuit according to exemplary embodiments may include multiple (e.g., two or more) discharge paths. Furthermore, at least one of the multiple discharge paths may be formed or implemented using a feedback inverter forming a hold logic device, and feedback and discharge functions may be performed simultaneously. Therefore, the integrated clock gating unit and integrated circuit can have relatively low power consumption and relatively high operating speed. Moreover, as the number of discharge paths increases, the time required to activate the output clock signal after activating the input clock signal (e.g., CK to ECK) can be improved. Attached Figure Description

[0011] The above and other features of this disclosure will become more apparent from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings, in which:

[0012] Figure 1 This is a block diagram illustrating an integrated clock gating unit according to an exemplary embodiment.

[0013] Figure 2 It shows Figure 1 A circuit diagram of an example of an integrated clock gating unit.

[0014] Figure 3A and Figure 3B It shows that it includes Figure 2 A schematic diagram illustrating an example of the layout of components in an integrated clock gating unit.

[0015] Figure 4 It shows Figure 1 A circuit diagram of an example of an integrated clock gating unit.

[0016] Figure 5A and Figure 5B It shows that it includes Figure 4 A schematic diagram illustrating an example of the layout of components in an integrated clock gating unit.

[0017] Figure 6A and Figure 6B It shows Figure 2 and Figure 4 Timing diagram of the operation of the integrated clock gating unit.

[0018] Figure 6C and Figure 6D It shows Figure 1 A circuit diagram of an example of an integrated clock gating unit.

[0019] Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13, Figure 14 , Figure 15 and Figure 16 It shows Figure 1 A circuit diagram of an example of an integrated clock gating unit.

[0020] Figure 17 This is a block diagram illustrating an integrated circuit including an integrated clock gating unit according to an exemplary embodiment.

[0021] Figure 18 This is a block diagram illustrating a computing system including an integrated clock gating unit according to an exemplary embodiment. Detailed Implementation

[0022] Exemplary embodiments of the present disclosure will now be described more fully with reference to the accompanying drawings. Similar reference numerals throughout the drawings may denote similar elements.

[0023] It should be understood that the terms "first," "second," "third," etc., are used herein to distinguish one element from another, and the elements are not limited by these terms. Therefore, a "first" element in an exemplary embodiment may be described as a "second" element in another exemplary embodiment.

[0024] It should be understood that the description of a feature or aspect in each exemplary embodiment should generally be considered as applicable to other similar features or aspects in other exemplary embodiments, unless the context explicitly indicates otherwise.

[0025] As used herein, the singular forms “a,” “one,” and “the” are intended to also include the plural forms unless the context explicitly indicates otherwise.

[0026] Here, those skilled in the art will understand that when two or more elements or values ​​are described as substantially the same or substantially equal to each other, it should be understood that the elements or values ​​are identical to each other, indistinguishable from each other, or distinguishable from each other but functionally identical. Furthermore, those skilled in the art will understand that when two or more processes or events are described as being performed or occurring at substantially the same time or substantially simultaneously, it should be understood that the process or event may be performed or occurring at exactly the same time or substantially at the same time. For example, those skilled in the art will understand that the process or event may be performed or occurring at substantially the same time within the measurement error range.

[0027] Figure 1 This is a block diagram illustrating an integrated clock gating unit according to an exemplary embodiment.

[0028] refer to Figure 1The integrated clock gating unit 1000 includes an input logic and latch unit 100, a hold logic and signal generation unit 200, and an output driver 300. The integrated clock gating unit 1000 can also be referred to as an integrated clock gating circuit, the input logic and latch unit 100 as an input logic and latch circuit, the hold logic and signal generation unit 200 as a hold logic and signal generation circuit, and the output driver 300 as an output driver circuit.

[0029] The input logic and latch unit 100 generates an internal enable signal EN based on a first input enable signal SE and a second input enable signal E, and generates a first internal signal VFB provided to the first node FB based on the internal enable signal EN and the input clock signal CK. For example, the first input enable signal SE may be a scan enable signal associated with a scan test, and the second input enable signal E may be a data enable signal or a normal enable signal, and may generally be referred to as an enable signal associated with normal or general data processing. For example, the first node FB may be a feedback node.

[0030] The input logic and latch unit 100 may include a NOR gate 120 and a latch unit 140.

[0031] NOR gate 120 may include: a first input terminal receiving a first input enable signal SE; a second input terminal receiving a second input enable signal E; and an output terminal outputting an internal enable signal EN. NOR gate 120 may perform a NOR operation on the first input enable signal SE and the second input enable signal E to generate the internal enable signal EN.

[0032] The latch unit 140 may include: a first input terminal that receives an internal enable signal EN; a second input terminal that receives an input clock signal CK; and an output terminal that is connected to a first node FB. The latch unit 140 may generate a first internal signal VFB based on the internal enable signal EN and the input clock signal CK.

[0033] The hold logic and signal generation unit 200 are connected between the first node FB and the second node ZZ1. It includes a feedback path PFB for feeding back the first internal signal VFB, generates a second internal signal VZZ1 based on the first internal signal VFB and the input clock signal CK, and includes a first path P1 and a second path P2 for discharging the second node ZZ1. The first path P1 and the second path P2 are different paths, and the second path P2 is connected to the feedback path PFB. For example, the second node ZZ1 may be an internal node for generating the output clock signal ECK, such as a node immediately preceding or before the output clock signal ECK.

[0034] In an exemplary embodiment, the second path P2 can perform both feedback and discharge functions simultaneously, and therefore can be referred to as a feedback and discharge path. For example, the second path P2 can perform a feedback function because it is directly connected to the feedback path PFB, and can perform a discharge function because it is directly connected to the second node ZZ1. Conversely, the first path P1 can only perform a discharge function because it is only directly connected to the second node ZZ1, and therefore can be referred to as a discharge path.

[0035] The hold logic and signal generation unit 200 may include a feedback inverter 220, a tri-state inverter 240, a NAND gate 260, and a feedback and discharge unit 280. The feedback and discharge unit 280 may also be referred to as a feedback and discharge circuit.

[0036] The feedback inverter 220 may include an input terminal connected to the first node FB and an output terminal connected to the third node FBN, forming a feedback path PFB, and inverting the first internal signal VFB. For example, the third node FBN may be an inverted feedback node.

[0037] The tri-state inverter 240 may include an input terminal connected to a third node FBN and an output terminal connected to a first node FB, can form a feedback path PFB, and can operate based on an input clock signal CK and an inverted input clock signal NCK.

[0038] For example, the feedback path PFB can be formed or implemented using feedback inverter 220 and tri-state inverter 240. Furthermore, feedback inverter 220 and tri-state inverter 240 can form a hold logic device.

[0039] NAND gate 260 may include a first input terminal for receiving the input clock signal CK, a second input terminal connected to the first node FB, and an output terminal connected to the second node ZZ1, and may form a first path P1. NAND gate 260 may perform a NAND operation on the input clock signal CK and the first internal signal VFB to generate a second internal signal VZZ1. NAND gate 260 may form a signal generation unit.

[0040] The feedback and discharge unit 280 can be connected between the second node ZZ1 and the third node FBN to form a second path P2, and can operate based on the input clock signal CK.

[0041] The output driver 300 generates the output clock signal ECK based on the second internal signal VZZ1.

[0042] References include Figure 2 and Figure 4The following figures illustrate the detailed configuration and various exemplary embodiments of the input logic and latch unit 100, the hold logic and signal generation unit 200, and the output driver 300.

[0043] Unlike conventional integrated clock gating units that include a single discharge path, the integrated clock gating unit 1000 according to an exemplary embodiment may include multiple (e.g., two or more) discharge paths (e.g., a first path P1 and a second path P2). Furthermore, at least one of the multiple discharge paths (e.g., the second path P2) may be formed or implemented using a feedback inverter 220 forming a hold logic device, and both feedback and discharge functions may be performed simultaneously. Therefore, the integrated clock gating unit 1000 can have relatively low power consumption and relatively high operating speed. Moreover, as the number of discharge paths used for the second node ZZ1 as an internal node increases, the time required to activate the output clock signal ECK after activating the input clock signal CK (e.g., CK to ECK) can be improved.

[0044] Figure 2 It shows Figure 1 A circuit diagram of an example of an integrated clock gating unit.

[0045] refer to Figure 2 The integrated clock gating unit 1000A may include a NOR gate 120A, a latch unit 140A, a feedback inverter 220A, a tri-state inverter 240A, a NAND gate 260A, a feedback and discharge unit 280A, and inverters INVA1 and INVA2.

[0046] In such Figure 2 In the circuit diagram, a horizontal line (e.g., -) connected to one electrode of the transistor represents the power supply voltage (e.g., VDD), and an inverted triangle (e.g., ...) connected to one electrode of the transistor represents the power supply voltage. ) represents the ground voltage (e.g., GND or VSS).

[0047] NOR gate 120A may include p-type metal-oxide-semiconductor (PMOS) transistors PA1 and PA2, and n-type metal-oxide-semiconductor (NMOS) transistors NA1 and NA2. PMOS transistors PA1 and PA2 may be connected in series between the power supply voltage and node N1. The control electrode (e.g., the gate electrode) of PMOS transistor PA1 may receive a first input enable signal SE, and the control electrode of PMOS transistor PA2 may receive a second input enable signal E. NMOS transistors NA1 and NA2 may be connected in parallel between node N1 and ground. The control electrode of NMOS transistor NA1 may receive the first input enable signal SE, and the control electrode of NMOS transistor NA2 may receive the second input enable signal E. Node N1 may correspond to the output terminal of NOR gate 120A.

[0048] The latch unit 140A may include PMOS transistors PA3 and PA4, and NMOS transistors NA3 and NA4. PMOS transistors PA3 and PA4 may be connected in series between the power supply voltage and the first node FB. The control electrode of PMOS transistor PA3 may be connected to node N1 to receive an internal enable signal EN, and the control electrode of PMOS transistor PA4 may receive an input clock signal CK. NMOS transistors NA3 and NA4 may be connected in series between the first node FB and ground. The control electrode of NMOS transistor NA3 may receive an inverted input clock signal NCK, and the control electrode of NMOS transistor NA4 may be connected to node N1 to receive the internal enable signal EN.

[0049] NOR gate 120A and latch unit 140A can form input logic and latch unit (e.g., Figure 1 (Input logic and latch unit 100 in the middle).

[0050] The tri-state inverter 240A may include PMOS transistors PA5 and PA6, and NMOS transistors NA5 and NA6. PMOS transistors PA5 and PA6 may be connected in series between the power supply voltage and the first node FB. The control electrode of PMOS transistor PA5 may be connected to the third node FBN, and the control electrode of PMOS transistor PA6 may receive an inverted input clock signal NCK. NMOS transistors NA5 and NA6 may be connected in series between the first node FB and ground. The control electrode of NMOS transistor NA5 may be connected to the third node FBN, and the control electrode of NMOS transistor NA6 may receive an input clock signal CK.

[0051] NAND gate 260A may include PMOS transistors PA7 and PA8, and NMOS transistors NA7 and NA8. PMOS transistors PA7 and PA8 may be connected in parallel between the power supply voltage and the second node ZZ1. The control electrode of PMOS transistor PA7 may be connected to the first node FB, and the control electrode of PMOS transistor PA8 may receive the input clock signal CK. NMOS transistors NA7 and NA8 may be connected in series between the second node ZZ1 and ground. The control electrode of NMOS transistor NA7 may be connected to the first node FB, and the control electrode of NMOS transistor NA8 may receive the input clock signal CK. NMOS transistors NA7 and NA8 may form a first path P1 for discharging the second node ZZ1.

[0052] The feedback inverter 220A may include a PMOS transistor PA9 and an NMOS transistor NA9. The PMOS transistor PA9 may be connected between the power supply voltage and the third node FBN, and may include a control electrode connected to the first node FB. The NMOS transistor NA9 may be connected between the third node FBN and ground, and may include a control electrode connected to the first node FB.

[0053] The feedback and discharge unit 280A may include an NMOS transistor NA10. The NMOS transistor NA10 may include a first electrode connected to the second node ZZ1, a control electrode receiving the input clock signal CK, and a second electrode connected to the third node FBN. The NMOS transistor NA10 may form a second path P2 for discharging the second node ZZ1 (e.g., for performing a discharge function). Furthermore, the second path P2 may be directly connected to the feedback path PFB to perform a feedback function. The feedback and discharge functions can be performed substantially simultaneously. The second path P2 can be implemented relatively simply using a single transistor NA10.

[0054] Feedback inverter 220A, tri-state inverter 240A, NAND gate 260A, and feedback and discharge unit 280A can form hold logic and signal generation unit (e.g., Figure 1 (The hold logic and signal generation unit 200 in the middle).

[0055] Inverter INVA1 can receive the input clock signal CK and invert it to output the inverted input clock signal NCK. Inverter INVA2 can be connected to the second node ZZ1 to receive the second internal signal VZZ1 and invert it to output the output clock signal ECK. Inverter INVA2 can form an output driver (e.g., ...). Figure 1 Output driver 300 in the middle.

[0056] Reference Figure 3A and Figure 3B Further description Figure 2 The regions RA1 and RA2 are shown.

[0057] According to the exemplary embodiment, it is possible to change Figure 2 The configuration of the latch unit 140A, feedback inverter 220A, and tri-state inverter 240A will refer to... Figure 6C , Figure 7 , Figure 9 , Figure 11 , Figure 13 and Figure 15 Describe it.

[0058] Figure 3A and Figure 3B It shows that it includes Figure 2 A schematic diagram illustrating an example of the layout of components in an integrated clock gating unit.

[0059] exist Figure 3A and Figure 3B In this diagram, GL represents the gate line, V0 represents the via, and AR represents the active region. M1 represents the first metal line associated with the power supply voltage VDD and the ground voltage VSS, MB represents the second metal line connecting the gate line GL to the via V0, and MA represents the third metal line connecting the active region AR to the via V0. BR represents the fractured region including the active fin or active region cutout. Furthermore, FB, ZZ1, and FBN indicated at the via V0 represent... Figure 2 The integrated clock gating unit 1000A includes a first node FB, a second node ZZ1, and a third node FBN. CK and ECK, indicated at the via V0, represent... Figure 2 The integrated clock gating unit 1000A includes a node that receives the input clock signal CK and a node that outputs the output clock signal ECK.

[0060] refer to Figure 3A and Figure 3B , showed Figure 2 The layout of the holding logic and signal generation unit RA1 and the output driver RA2 in the integrated clock gating unit 1000A.

[0061] exist Figure 3A In the example, the NMOS transistor NA10 included in the feedback and discharge unit 280A can be implemented relatively simply by adding a gate line, a second metal line, and a CK via connected to it between the FBN via and the ZZ1 via located in the lower part of region RA1. With Figure 3A Compared to the example, in Figure 3B In the example, the gate line in the fracture region BR can be omitted. Figure 3A and Figure 3B In the example, the order of the lines and vias in region RA1 can be changed from left to right. For example, the layout can be changed so that the leftmost line and via are placed on the rightmost side, and the rightmost line and via are placed on the leftmost side.

[0062] Figure 4 It shows Figure 1 A circuit diagram of an example integrated clock gating unit. For ease of explanation, further descriptions of the previously described components and aspects will be omitted.

[0063] refer to Figure 4 The integrated clock gating unit 1000B may include a NOR gate 120B, a latch unit 140B, a feedback inverter 220B, a tri-state inverter 240B, a NAND gate 260B, a feedback and discharge unit 280B, and inverters INVB1 and INVB2.

[0064] Apart from partially changing the configuration of the tri-state inverter 240B and the NAND gate 260B, Figure 4 The integrated clock gating unit 1000B can be used with Figure 2 The integrated clock gating unit 1000A is basically the same. For example, Figure 4 The NOR gate 120B, latch unit 140B, feedback inverter 220B, and feedback and discharge unit 280B include transistors PB1, PB2, NB1, NB2, PB3, PB4, NB3, NB4, PB9, NB9, and NB10, which can be respectively connected to the NOR gate 120B, latch unit 140B, feedback inverter 220B, and feedback and discharge unit 280B. Figure 2 The transistors PA1, PA2, NA1, NA2, PA3, PA4, NA3, NA4, PA9, NA9, and NA10 included in the NOR gate 120A, latch unit 140A, feedback inverter 220A, and feedback and discharge unit 280A are basically the same, and Figure 4 The inverters INVB1 and INVB2 in the circuit can be connected to... Figure 2 The inverters INVA1 and INVA2 in the diagram are basically the same.

[0065] The tri-state inverter 240B may include PMOS transistors PB5 and PB6, and NMOS transistors NB5 and NB8. PMOS transistors PB5 and PB6 may be connected in series between the power supply voltage and the first node FB. The control electrode of PMOS transistor PB5 may be connected to the third node FBN, and the control electrode of PMOS transistor PB6 may receive an inverted input clock signal NCK. NMOS transistors NB5 and NB8 may be connected in series between the first node FB and ground. The control electrode of NMOS transistor NB5 may be connected to the third node FBN, and the control electrode of NMOS transistor NB8 may receive an input clock signal CK.

[0066] NAND gate 260B may include PMOS transistors PB7 and PB8, and NMOS transistors NB7 and NB8. PMOS transistors PB7 and PB8 may be connected in parallel between the power supply voltage and the second node ZZ1. The control electrode of PMOS transistor PB7 may be connected to the first node FB, and the control electrode of PMOS transistor PB8 may receive the input clock signal CK. NMOS transistors NB7 and NB8 may be connected in series between the second node ZZ1 and ground. The control electrode of NMOS transistor NB7 may be connected to the first node FB, and the control electrode of NMOS transistor NB8 may receive the input clock signal CK.

[0067] exist Figure 4 In the example, the tri-state inverter 240B and the NAND gate 260B can share at least one component (e.g., at least one circuit assembly). For example, the NMOS transistor NB8 can be shared by the tri-state inverter 240B and the NAND gate 260B. Figure 2 Compared to the example, it can be... Figure 2 The two NMOS transistors NA6 and NA8 that receive the input clock signal CK are combined into Figure 4 A single NMOS transistor NB8 in the array. For example. Figure 4 The first terminals of NMOS transistors NB5 and NB7 can be connected to each other to form a merge node MN, and only one NMOS transistor NB8 can be connected to the merge node MN, so it can be omitted. Figure 2 One of the two NMOS transistors NA6 and NA8 (e.g., NMOS transistor NA6). Therefore, Figure 4 The integrated clock gating unit 1000B can have a relatively small area, relatively low power consumption and relatively high operating speed.

[0068] According to the exemplary embodiment, it is possible to change Figure 4 The configuration of the latch unit 140B, feedback inverter 220B, and tri-state inverter 240B will refer to... Figure 6D , Figure 8 , Figure 10 , Figure 12 , Figure 14 and Figure 16 Describe it.

[0069] The following will refer to Figure 5A and Figure 5B describe Figure 4 The regions RB1 and RB2 are shown.

[0070] Figure 5A and Figure 5B It shows that it includes Figure 4A schematic diagram illustrating an example of the layout of components in an integrated clock gating unit. For ease of explanation, further descriptions of the previously described components and aspects may be omitted.

[0071] refer to Figure 5A and Figure 5B , showed Figure 4 The layout of the hold logic and signal generation unit portion RB1 and the output driver portion RB2 included in the integrated clock gating unit 1000B. Figure 5B In the middle, region RB1 can be divided into region RB12, which includes NMOS transistor NB8, and region RB11, which is the part of region RB1 excluding region RB12.

[0072] and Figure 3A Similar to the example, the NMOS transistor NB10 included in the feedback and discharge unit 280B can be controlled by setting... Figure 5A In the example, the second path P2 is implemented by adding a gate line, a second metal line, and a CK via connected to it between the FBN via and the ZZ1 via in the lower part of region RB1, thus making the implementation relatively simple. Figure 5A In the example, the order of the lines and vias in region RB1 can be changed from left to right. Figure 5A Compared to the example, in Figure 5B In the example, the positions of the CK via and the wires connected to it can be changed. Figure 5B In the example, according to the exemplary embodiment, region RB12 may be set to be adjacent to region RB11, but not located immediately adjacent to region RB11.

[0073] Figure 6A and Figure 6B It shows Figure 2 and Figure 4 Timing diagram of the operation of the integrated clock gating unit. Figure 6B yes Figure 6A An enlarged view of part of the "X" in the image.

[0074] refer to Figure 2 , Figure 4 , Figure 6A and Figure 6B The operation of the integrated clock gating units 1000A and 1000B is as follows.

[0075] When the input clock signal CK is at a logic low level, the second node ZZ1 can be set to a logic high value. The logic values ​​of the first node FB and the third node FBN can be determined based on the first input enable signal SE and the second input enable signal E.

[0076] For example, when both the first input enable signal SE and the second input enable signal E are at a logic low level, the first node FB can be set to a logic low value, and the third node FBN can be set to a logic high value. In this case, even if the input clock signal CK changes to a logic high level, the second node ZZ1 can remain at a logic high value. Furthermore, even if the internal enable signal EN changes to a logic low level based on either the first input enable signal SE or the second input enable signal E, the first node FB can remain at a logic low value, and the third node FBN can remain at a logic high value.

[0077] Conversely, when the input clock signal CK is logic low and one of the first input enable signal SE and the second input enable signal E is logic high, the first node FB can be set to a logic high value, and the third node FBN can be set to a logic low value. In this case, when the input clock signal CK changes to a logic high level, a discharge operation for the second node ZZ1 can be initiated through two paths P1 and P2, and the second node ZZ1 can change from a logic high value to a logic low value. As the number of discharge paths for the second node ZZ1 increases, the time required to activate the output clock signal ECK after activating the input clock signal CK (e.g., CK to ECK) can be improved.

[0078] Figure 6A and Figure 6B An example is shown where the second input enable signal E transitions from logic low to logic high. For example... Figure 6B As indicated by the arrows, compared to the output clock signal (shown by the dashed line) generated by a conventional integrated clock gating unit, the transition time of the output clock signal ECK (shown by the solid line) generated by the integrated clock gating units 1000A and 1000B according to the exemplary embodiment can be advanced or shifted forward, thus improving the CK-ECK transition time. Typically, CK-ECK can represent the time interval from a first point in time when the level of the input clock signal CK rises to approximately half of its high level to a second point in time when the level of the output clock signal ECK rises to approximately half of its high level.

[0079] Figure 6C and Figure 6D It shows Figure 1 A circuit diagram of an example integrated clock gating unit. For ease of explanation, further descriptions of the previously described components and aspects may be omitted.

[0080] refer to Figure 6C The integrated clock gating unit 1000A-1 may include a NOR gate 120A, a latch unit 140A, a feedback inverter 220A-1, a tri-state inverter 240A, a NAND gate 260A, a feedback and discharge unit 280A, and inverters INVA1 and INVA2.

[0081] Apart from some changes to the configuration of the feedback inverter 220A-1, Figure 6C The integrated clock gating unit 1000A-1 can be used with Figure 2 It is basically the same as the integrated clock gating unit 1000A.

[0082] The feedback inverter 220A-1 may include a PMOS transistor PA9 and an NMOS transistor NA9. The PMOS transistor PA9 may be connected between the second node ZZ1 and the third node FBN, and may include a control electrode connected to the first node FB. The NMOS transistor NA9 may be connected between the third node FBN and ground, and may include a control electrode connected to the first node FB. Figure 6C In the example, the feedback inverter 220A-1 can be connected to the second node ZZ1 instead of the power supply voltage.

[0083] refer to Figure 6D The integrated clock gating unit 1000B-1 may include a NOR gate 120B, a latch unit 140B, a feedback inverter 220B-1, a tri-state inverter 240B, a NAND gate 260B, a feedback and discharge unit 280B, and inverters INVB1 and INVB2.

[0084] Apart from some changes to the configuration of the feedback inverter 220B-1, Figure 6D The integrated clock gating unit 1000B-1 can be used with Figure 4 It is basically the same as the integrated clock gating unit 1000B. Figure 6D The feedback inverter 220B-1 in the middle can be used with Figure 6C The feedback inverter 220A-1 in this example is basically the same. Figure 6D The transistors PB9 and NB9 included in the feedback inverter 220B-1 can be respectively connected to... Figure 6C The transistors PA9 and NA9 included in the feedback inverter 220A-1 are basically the same.

[0085] Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 and Figure 16 It shows Figure 1 A circuit diagram of an example integrated clock gating unit. For ease of explanation, further descriptions of the previously described components and aspects may be omitted.

[0086] Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 and Figure 16 This illustrates a latching unit (e.g.,) among the elements included in an integrated clock gating unit. Figure 2 The latch unit 140A and / or Figure 4 The latch unit 140B in the middle), tri-state inverter (e.g., Figure 2 The three-state inverter 240A and / or Figure 4 Examples of altered components are shown, such as the three-state inverter 240B and / or its associated parts. Therefore, for ease of illustration, a block diagram rather than a circuit diagram is shown with the NOR gate 120 and the feedback inverter 220 unchanged.

[0087] refer to Figure 7 The integrated clock gating unit 1000A-a may include NOR gate 120, inverters INVA3, 220 and INVA2, PMOS transistors PA11, PA12, PA7 and PA8 and NMOS transistors NA11, NA12, NA13, NA14, NA10, NA7 and NA8. Figure 7 It shows in Figure 2 The example shows an instance where the configuration of latch unit 140A and tri-state inverter 240A has been changed.

[0088] Inverter INVA3 may include an input terminal and an output terminal for receiving an internal enable signal EN. PMOS transistor PA11 may be connected between the output terminal of inverter INVA3 and the first node FB, and may include a control electrode for receiving an input clock signal CK. NMOS transistors NA11 and NA12 may be connected in series between the output terminal of inverter INVA3 and the first node FB, and may also be connected in parallel with PMOS transistor PA11 between the output terminal of inverter INVA3 and the first node FB. The control electrode of NMOS transistor NA11 may be connected to the input terminal of inverter INVA3, and the control electrode of NMOS transistor NA12 may be connected to the second node ZZ1.

[0089] Inverter INVA3, PMOS transistor PA11, and NMOS transistors NA11 and NA12 can form a latching cell (e.g., Figure 1 (Latch unit 140 in the middle).

[0090] PMOS transistor PA12 can be connected between the power supply voltage and the first node FB, and may include a control electrode connected to the second node ZZ1. NMOS transistors NA13 and NA14 can be connected in series between the first node FB and ground. The control electrode of NMOS transistor NA13 can be connected to the third node FBN, and the control electrode of NMOS transistor NA14 can receive the input clock signal CK.

[0091] PMOS transistor PA12 and NMOS transistors NA13 and NA14 can form a tri-state inverter (e.g., Figure 1 (The three-state inverter 240 in the middle).

[0092] Figure 7 The PMOS transistors PA7 and PA8, NMOS transistors NA7, NA8 and NA10, and inverter INVA2 can be respectively connected to... Figure 2 The PMOS transistors PA7 and PA8, NMOS transistors NA7, NA8 and NA10, and inverter INVA2 are basically the same. PMOS transistors PA7 and PA8, and NMOS transistors NA7 and NA8 can form... Figure 2 The NAND gate 260A and NMOS transistor NA10 in the middle can form Figure 2 The feedback and discharge unit 280A is included, and the inverter INVA2 can form an output driver (e.g., Figure 1 Output driver 300 in the middle.

[0093] refer to Figure 8 The integrated clock gating unit 1000B-a may include NOR gate 120, inverters INVB3, 220 and INVB2, PMOS transistors PB11, PB12, PB7 and PB8 and NMOS transistors NB11, NB12, NB13, NB10, NB7 and NB8. Figure 8 It shows in Figure 4 The example shows an instance where the configuration of latch unit 140B and tri-state inverter 240B has been modified.

[0094] Figure 8 The inverter INVB3, PMOS transistor PB11, and NMOS transistors NB11 and NB12 in the circuit can be respectively connected to... Figure 7 The inverter INVA3, PMOS transistor PA11, and NMOS transistors NA11 and NA12 are basically the same and can form a latching unit (e.g., Figure 1 (Latch unit 140 in the middle). Figure 8 The PMOS transistor PB12 and NMOS transistors NB13 and NB8 in the diagram can be respectively connected to... Figure 7The PMOS transistor PA12 and NMOS transistors NA13 and NA14 are basically the same and can form a three-state inverter (e.g., Figure 1 (The three-state inverter 240 in the middle). Figure 8 It shows Figure 7 An example of combining two NMOS transistors, NA14 and NA8, into a single NMOS transistor, NB8.

[0095] Figure 8 The PMOS transistors PB7 and PB8, NMOS transistors NB7, NB8 and NB10, and inverter INVB2 can be respectively connected to... Figure 4 The PMOS transistors PB7 and PB8, NMOS transistors NB7, NB8 and NB10, and inverter INVB2 are basically the same.

[0096] refer to Figure 9 The integrated clock gating unit 1000A-b may include NOR gate 120, inverters INVA3, 220 and INVA2, PMOS transistors PA13, PA12, PA7 and PA8 and NMOS transistors NA15, NA16, NA13, NA14, NA10, NA7 and NA8. Figure 9 It shows in Figure 2 The example shows an instance where the configuration of latch unit 140A and tri-state inverter 240A has been changed.

[0097] Inverter INVA3 may include an input terminal and an output terminal for receiving an internal enable signal EN. PMOS transistor PA13 may be connected between the output terminal of inverter INVA3 and the first node FB, and may include a control electrode for receiving the input clock signal CK. NMOS transistors NA15 and NA16 may be connected in series between the first node FB and ground. The control electrode of NMOS transistor NA15 may be connected to the second node ZZ1, and the control electrode of NMOS transistor NA16 may be connected to the input terminal of inverter INVA3.

[0098] Inverter INVA3, PMOS transistor PA13, and NMOS transistors NA15 and NA16 can form a latching cell (e.g., Figure 1 (Latch unit 140 in the middle).

[0099] Figure 9 The PMOS transistor PA12 and NMOS transistors NA13 and NA14 in the diagram can be respectively connected to... Figure 7 The PMOS transistor PA12 and NMOS transistors NA13 and NA14 are basically the same. Figure 9The PMOS transistors PA7 and PA8, NMOS transistors NA7, NA8 and NA10, and inverter INVA2 can be respectively connected to... Figure 2 The PMOS transistors PA7 and PA8, NMOS transistors NA7, NA8 and NA10, and inverter INVA2 are basically the same.

[0100] refer to Figure 10 The integrated clock gating unit 1000B-b may include NOR gate 120, inverters INVB3, 220 and INVB2, PMOS transistors PB13, PB12, PB7 and PB8 and NMOS transistors NB15, NB16, NB13, NB10, NB7 and NB8. Figure 10 It shows in Figure 4 The example shows an instance where the configuration of latch unit 140B and tri-state inverter 240B has been modified.

[0101] Figure 10 The inverter INVB3, PMOS transistor PB13, and NMOS transistors NB15 and NB16 in the circuit can be respectively connected to... Figure 9 The inverter INVA3, PMOS transistor PA13, and NMOS transistors NA15 and NA16 are basically the same. Figure 10 The PMOS transistor PB12 and NMOS transistors NB13 and NB8 in the diagram can be respectively connected to... Figure 9 The PMOS transistor PA12 and NMOS transistors NA13 and NA14 are basically the same. Figure 10 It shows Figure 9 An example of combining two NMOS transistors, NA14 and NA8, into a single NMOS transistor, NB8.

[0102] Figure 10 The PMOS transistors PB7 and PB8, NMOS transistors NB7, NB8 and NB10, and inverter INVB2 can be respectively connected to... Figure 4 The PMOS transistors PB7 and PB8, NMOS transistors NB7, NB8 and NB10, and inverter INVB2 are basically the same.

[0103] refer to Figure 11 The integrated clock gating unit 1000A-c may include NOR gate 120, inverter 220 and INVA2, PMOS transistors PA14, PA15, PA12, PA7 and PA8 and NMOS transistors NA17, NA18, NA13, NA14, NA10, NA7 and NA8. Figure 11 It shows in Figure 2 The example shows an instance where the configuration of latch unit 140A and tri-state inverter 240A has been changed.

[0104] PMOS transistors PA14 and PA15 can be connected in series between the power supply voltage and the first node FB. The control electrode of PMOS transistor PA14 can receive the internal enable signal EN, and the control electrode of PMOS transistor PA15 can receive the input clock signal CK. NMOS transistors NA17 and NA18 can be connected in series between the first node FB and the ground voltage. The control electrode of NMOS transistor NA17 can be connected to the second node ZZ1, and the control electrode of NMOS transistor NA18 can receive the internal enable signal EN.

[0105] PMOS transistors PA14 and PA15, and NMOS transistors NA17 and NA18, can form latching cells (e.g., Figure 1 (Latch unit 140 in the middle).

[0106] Figure 11 The PMOS transistor PA12 and NMOS transistors NA13 and NA14 in the diagram can be respectively connected to... Figure 7 The PMOS transistor PA12 and NMOS transistors NA13 and NA14 are basically the same. Figure 11 The PMOS transistors PA7 and PA8, NMOS transistors NA7, NA8 and NA10, and inverter INVA2 can be respectively connected to... Figure 2 The PMOS transistors PA7 and PA8, NMOS transistors NA7, NA8 and NA10, and inverter INVA2 are basically the same.

[0107] refer to Figure 12 The integrated clock gating unit 1000B-c may include NOR gate 120, inverter 220 and INVB2, PMOS transistors PB14, PB15, PB12, PB7 and PB8 and NMOS transistors NB17, NB18, NB13, NB10, NB7 and NB8. Figure 12 It shows in Figure 4 The example shows an instance where the configuration of latch unit 140B and tri-state inverter 240B has been modified.

[0108] Figure 12 The PMOS transistors PB14 and PB15 and the NMOS transistors NB17 and NB18 can be respectively connected to Figure 11 The PMOS transistors PA14 and PA15 and the NMOS transistors NA17 and NA18 are basically the same. Figure 12 The PMOS transistor PB12 and NMOS transistors NB13 and NB8 in the diagram can be respectively connected to... Figure 11The PMOS transistor PA12 and NMOS transistors NA13 and NA14 are basically the same. Figure 12 It shows Figure 11 An example of combining two NMOS transistors, NA14 and NA8, into a single NMOS transistor, NB8.

[0109] Figure 12 The PMOS transistors PB7 and PB8, NMOS transistors NB7, NB8 and NB10, and inverter INVB2 can be respectively connected to... Figure 4 The PMOS transistors PB7 and PB8, NMOS transistors NB7, NB8 and NB10, and inverter INVB2 are basically the same.

[0110] refer to Figure 13 The integrated clock gating unit 1000A-d may include NOR gate 120, inverters INVA3, 220 and INVA2, PMOS transistors PA11, PA16, PA7 and PA8 and NMOS transistors NA11, NA12, NA19, NA20, NA10, NA7 and NA8. Figure 13 It shows in Figure 2 The example shows an instance where the configuration of latch unit 140A and tri-state inverter 240A has been changed.

[0111] Figure 13 The inverter INVA3, PMOS transistor PA11, and NMOS transistors NA11 and NA12 in the circuit can be respectively connected to... Figure 7 The inverter INVA3, PMOS transistor PA11, and NMOS transistors NA11 and NA12 are basically the same.

[0112] PMOS transistor PA16 can be connected between the power supply voltage and the first node FB, and may include a control electrode connected to the second node ZZ1. NMOS transistors NA19 and NA20 can be connected in series between node N2 included in the input logic and latch unit and ground. For example, node N2 can be the node between NMOS transistors NA11 and NA12 included in the latch unit. The control electrode of NMOS transistor NA19 can be connected to the third node FBN, and the control electrode of NMOS transistor NA20 can receive the input clock signal CK.

[0113] PMOS transistor PA16 and NMOS transistors NA19 and NA20 can form a tri-state inverter (e.g., Figure 1 (The three-state inverter 240 in the middle).

[0114] Figure 13The PMOS transistors PA7 and PA8, NMOS transistors NA7, NA8 and NA10, and inverter INVA2 can be respectively connected to... Figure 2 The PMOS transistors PA7 and PA8, NMOS transistors NA7, NA8 and NA10, and inverter INVA2 are basically the same.

[0115] refer to Figure 14 The integrated clock gating unit 1000B-d may include NOR gate 120, inverters INVB3, 220 and INVB2, PMOS transistors PB11, PB16, PB7 and PB8 and NMOS transistors NB11, NB12, NB19, NB10, NB7 and NB8. Figure 14 It shows in Figure 4 The example shows an instance where the configuration of latch unit 140B and tri-state inverter 240B has been modified.

[0116] Figure 14 The inverter INVB3, PMOS transistor PB11, and NMOS transistors NB11 and NB12 in the circuit can be respectively connected to... Figure 13 The inverter INVA3, PMOS transistor PA11, and NMOS transistors NA11 and NA12 are basically the same. Figure 14 The PMOS transistor PB16 and NMOS transistors NB19 and NB8 in the diagram can be respectively connected to... Figure 13 The PMOS transistor PA16 and NMOS transistors NA19 and NA20 are basically the same. Figure 14 It shows Figure 13 An example of combining two NMOS transistors, NA20 and NA8, into a single NMOS transistor, NB8.

[0117] Figure 14 The PMOS transistors PB7 and PB8, NMOS transistors NB7, NB8 and NB10, and inverter INVB2 can be respectively connected to... Figure 4 The PMOS transistors PB7 and PB8, NMOS transistors NB7, NB8 and NB10, and inverter INVB2 are basically the same.

[0118] refer to Figure 15 The integrated clock gating unit 1000A-e may include NOR gate 120, inverter 220 and INVA2, PMOS transistors PA14, PA15, PA17, PA7 and PA8 and NMOS transistors NA17, NA18, NA21, NA22, NA10, NA7 and NA8. Figure 15 It shows in Figure 2 The example shows an instance where the configuration of latch unit 140A and tri-state inverter 240A has been changed.

[0119] Figure 15 The PMOS transistors PA14 and PA15 and the NMOS transistors NA17 and NA18 in the diagram can be respectively connected to... Figure 11 The PMOS transistors PA14 and PA15 and the NMOS transistors NA17 and NA18 are basically the same.

[0120] PMOS transistor PA17 can be connected between the power supply voltage and the first node FB, and may include a control electrode connected to the second node ZZ1. NMOS transistors NA21 and NA22 can be connected in series between node N3 included in the input logic and latch unit and ground. For example, node N3 can be the node between NMOS transistors NA17 and NA18 included in the latch unit. The control electrode of NMOS transistor NA21 can be connected to the third node FBN, and the control electrode of NMOS transistor NA22 can receive the input clock signal CK.

[0121] PMOS transistor PA17 and NMOS transistors NA21 and NA22 can form a tri-state inverter (e.g., Figure 1 (The three-state inverter 240 in the middle).

[0122] Figure 15 The PMOS transistors PA7 and PA8, NMOS transistors NA7, NA8 and NA10, and inverter INVA2 can be respectively connected to... Figure 2 The PMOS transistors PA7 and PA8, NMOS transistors NA7, NA8 and NA10, and inverter INVA2 are basically the same.

[0123] refer to Figure 16 The integrated clock gating unit 1000B-e may include NOR gate 120, inverter 220 and INVB2, PMOS transistors PB14, PB15, PB17, PB7 and PB8 and NMOS transistors NB17, NB18, NB21, NB10, NB7 and NB8. Figure 16 It shows in Figure 4 The example shows an instance where the configuration of latch unit 140B and tri-state inverter 240B has been modified.

[0124] Figure 16 The PMOS transistors PB14 and PB15 and the NMOS transistors NB17 and NB18 can be respectively connected to Figure 15 The PMOS transistors PA14 and PA15 and the NMOS transistors NA17 and NA18 are basically the same. Figure 16 The PMOS transistor PB17 and NMOS transistors NB21 and NB8 in the diagram can be respectively connected to... Figure 15 The PMOS transistor PA17 and NMOS transistors NA21 and NA22 are basically the same. Figure 16 It shows Figure 15 An example of combining two NMOS transistors, NA22 and NA8, into a single NMOS transistor, NB8.

[0125] Figure 16 The PMOS transistors PB7 and PB8, NMOS transistors NB7, NB8 and NB10, and inverter INVB2 can be respectively connected to... Figure 4 The PMOS transistors PB7 and PB8, NMOS transistors NB7, NB8 and NB10, and inverter INVB2 are basically the same.

[0126] In short, Figures 7 to 16 In the integrated clock gating units shown, those whose reference numerals include the same capital letter "A" (e.g., Figure 7 , Figure 9 , Figure 11 , Figure 13 and Figure 15 The integrated clock gating units 1000A-a, 1000A-b, 1000A-c, 1000A-d, and 1000A-e can have Figure 2 A portion of the integrated clock gating unit 1000A has been configured differently. Similarly, in Figures 7 to 16 In the integrated clock gating units shown, those with the same capital letter "B" in the reference numerals (e.g., Figure 8 , Figure 10 , Figure 12 , Figure 14 and Figure 16 The integrated clock gating units 1000B-a, 1000B-b, 1000B-c, 1000B-d, and 1000B-e can have Figure 4 A portion of the integrated clock gating unit 1000B has been configured differently. Furthermore, besides the two NMOS transistors receiving the input clock signal CK being merged into a single NMOS transistor, the integrated clock gating unit (e.g., with the same lowercase letters in the reference numerals) has also been modified. Figure 7 and Figure 8 The integrated clock gating units 1000A-a and 1000B-a, which share the same lowercase letter "a", can have essentially the same configuration.

[0127] Although it has been referenced Figures 7 to 16Various examples of integrated clock gating units are described, but exemplary embodiments are not limited thereto, and exemplary embodiments may be modified to the extent that two or more discharge paths for the second node ZZ1 are implemented and at least one of the discharge paths performs both feedback and discharge functions simultaneously.

[0128] Figure 17 This is a block diagram illustrating an integrated circuit including an integrated clock gating unit according to an exemplary embodiment.

[0129] refer to Figure 17 The integrated circuit 2000 includes an integrated clock gating unit 2100 and a combinational logic circuit 2200.

[0130] The integrated clock gating unit 2100 selectively provides the output clock signal ECK to the combinational logic circuit 2200 based on at least one of the input enable signal SE and the input enable signal E and the input clock signal CK.

[0131] The integrated clock gating unit 2100 can be based on a reference. Figures 1 to 16 The exemplary embodiment described above describes an integrated clock gating unit. The integrated clock gating unit 2100 may include multiple (e.g., two or more) discharge paths. Furthermore, at least one of the multiple discharge paths can be formed or implemented using a feedback inverter 220, and the feedback function and discharge function can be performed substantially simultaneously. Therefore, the integrated clock gating unit 2100 can have relatively low power consumption and relatively high operating speed. Moreover, as the number of discharge paths increases, the time required to activate the output clock signal ECK after activating the input clock signal CK (e.g., CK to ECK) can be improved.

[0132] The combinational logic circuit 2200 performs various logical operations on data based on the output clock signal ECK. For example, the combinational logic circuit 2200 can perform a logical operation on the first input data SIN based on the output clock signal ECK to generate the first output data SOUT, or it can perform a logical operation on the second input data DIN based on the output clock signal ECK to generate the second output data DOUT. For example, the first input data SIN and the first output data SOUT can be input / output data used for scan testing, and the second input data DIN and the second output data DOUT can be input / output data used for normal or general data processing.

[0133] In an exemplary embodiment, the integrated circuit 2000 may be designed to include a scan chain circuit as a design-for-test (DFT) circuit to facilitate efficient testing of the integrated circuit 2000. For example, the scan chain circuit can be used to perform scan tests on the integrated circuit 2000. For example, a shift-in operation can be performed to sequentially input a predetermined test pattern as scan input SIN into the scan chain circuit. Furthermore, a capture operation can be performed such that the test pattern loaded into the scan chain circuit is provided to the combinational logic circuit 2200 to generate observations based on the test pattern, and the observations of the combinational logic circuit 2200 are stored in the scan chain circuit. Additionally, a shift-out operation can be performed to sequentially output the observations stored in the scan chain circuit as scan output SOUT.

[0134] In exemplary embodiments, multiple similar or different test patterns can be used. In one case, the shift-out operation, which outputs an observation for one test pattern, and the shift-in operation, which inputs the next test pattern, can be performed substantially simultaneously. In other cases, the shift-out operation, which outputs an observation for one test pattern, and the shift-in operation, which inputs the next test pattern, can be performed at different times. For example, the shift-out operation can be performed before the shift-in operation of the next test pattern. Alternatively, as another example, the shift-in operation of the next test pattern can be performed before the shift-out operation.

[0135] Figure 18 This is a block diagram illustrating a computing system including an integrated clock gating unit according to an exemplary embodiment.

[0136] refer to Figure 18 The computing system 3000 may include a clock 3100, random access memory (RAM) 3200, a user interface 3300, a solid-state drive / disk (SSD) 3400, an integrated clock gating unit 1000, a modem 3500 (e.g., a baseband chipset), a battery 3600, and / or a memory controller 3700, any one or all of which may be electrically connected to the system bus 3005. The integrated clock gating unit 1000 may be, according to reference... Figures 1 to 16 The exemplary embodiment described above includes an integrated clock gating unit. A computing system 3000 including the integrated clock gating unit 1000 can correspond to the exemplary embodiment described in detail above, and can also be electrically connected to the system bus 3005.

[0137] If the computing system 3000 is a mobile device, the battery 3600 can power the computing system 3000. The computing system 3000 may also include an application chipset, a camera image processor (CIS), mobile DRAM, etc.

[0138] In an exemplary embodiment, the computing system 3000 may be used as, for example, a computer, a computer server, a server rack, a portable computer, an ultra-mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a network tablet computer, a wireless telephone, a mobile phone, a smartphone, an e-book reader, a portable multimedia player (PMP), a digital camera, a digital recorder / player, a digital photo / video recorder / player, a portable game console, a navigation system, a black box, a 3D television, a device capable of transmitting and receiving information wirelessly, one of various electronic devices constituting a home network, one of various electronic devices constituting a computer network, one of various electronic devices constituting a telematics network, RFID, one of various electronic devices constituting a computing system, etc.

[0139] This document describes functional blocks, units, and / or modules and illustrates exemplary embodiments in the accompanying drawings. Those skilled in the art will understand that these blocks, units, and / or modules can be physically implemented using electronic (or optical) circuitry such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wiring connections, etc., which can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques.

[0140] When blocks, units, and / or modules are implemented by microprocessors or the like, they can be programmed using software (e.g., microcode) to perform the various functions discussed herein, and may optionally be driven by firmware and / or software. Alternatively, each block, unit, and / or module may be implemented by dedicated hardware or as a combination of dedicated hardware performing some functions and processors (e.g., one or more programmed microprocessors and associated circuitry) performing other functions. Furthermore, without departing from the scope of this disclosure, each block, unit, and / or module of the exemplary embodiments may be physically divided into two or more interactive and discrete blocks, units, and / or modules. Furthermore, without departing from the scope of this disclosure, the blocks, units, and / or modules of the exemplary embodiments may be physically combined into more complex blocks, units, and / or modules.

[0141] This disclosure can be applied to a variety of electronic devices and systems, including those with integrated clock gating units. For example, this disclosure can be applied to systems such as personal computers (PCs), server computers, data centers, workstations, mobile phones, smartphones, tablet computers, laptop computers, PDAs, PMPs, digital cameras, portable game consoles, music players, camcorders, video players, navigation devices, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-book readers, virtual reality (VR) devices, augmented reality (AR) devices, robotic devices, drones, and the like.

[0142] While this disclosure has been specifically shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and detail may be made herein without departing from the spirit and scope of this disclosure as defined by the appended claims.

Claims

1. An integrated clock gating unit, comprising: The input logic and latching circuit generates an internal enable signal based on a first input enable signal and a second input enable signal, and generates a first internal signal to be provided to the first node based on the internal enable signal and the input clock signal. The hold logic and signal generation circuit are connected between the first node and the second node. The hold logic and signal generation circuit includes a feedback path that feeds back the first internal signal, generates a second internal signal to be provided to the second node based on the first internal signal and the input clock signal, and further includes a first path and a second path that discharge the second node. Wherein, the first path and the second path are different paths, and the second path is connected to the feedback path; and The output driver generates an output clock signal based on the second internal signal. The hold logic and signal generation circuit include: A feedback inverter, including an input terminal connected to the first node and an output terminal connected to the third node, and forming the feedback path; and The three-state inverter includes an input terminal connected to the third node and an output terminal connected to the first node, and forms the feedback path.

2. The integrated clock gating unit according to claim 1, wherein, The second path performs both feedback and discharge functions simultaneously.

3. The integrated clock gating unit according to claim 1, wherein, The hold logic and signal generation circuitry also include: A NAND gate, comprising a first input terminal receiving the input clock signal, a second input terminal connected to the first node, and an output terminal connected to the second node, and forming the first path; and A feedback and discharge circuit is connected between the second node and the third node, forming the second path.

4. The integrated clock gating unit according to claim 3, wherein, The feedback and discharge circuit includes: An n-type metal-oxide-semiconductor (NMOS) transistor includes a first electrode connected to the second node, a control electrode that receives the input clock signal, and a second electrode connected to the third node.

5. The integrated clock gating unit according to claim 3, wherein, The NAND gate and the tri-state inverter share at least one element.

6. The integrated clock gating unit according to claim 5, wherein, The NAND gate includes: First p-type metal-oxide-semiconductor PMOS transistor; The second PMOS transistor is connected in parallel to the first PMOS transistor between the power supply voltage and the second node. The first PMOS transistor includes a control electrode connected to the first node, and the second PMOS transistor includes a control electrode for receiving the input clock signal. The first n-type metal-oxide-semiconductor NMOS transistor; and The second NMOS transistor is connected in series with the first NMOS transistor between the second node and ground voltage. The first NMOS transistor includes a control electrode connected to the first node, and the second NMOS transistor includes a control electrode for receiving the input clock signal. The second NMOS transistor that receives the input clock signal is shared by the NAND gate and the tri-state inverter.

7. The integrated clock gating unit according to claim 3, wherein, The tri-state inverter includes: First p-type metal-oxide-semiconductor PMOS transistor; The second PMOS transistor is connected in series with the first PMOS transistor between the power supply voltage and the first node. The first PMOS transistor includes a control electrode connected to the third node, and the second PMOS transistor includes a control electrode that receives an inverted input clock signal. The first n-type metal-oxide-semiconductor NMOS transistor; and The second NMOS transistor is connected in series with the first NMOS transistor between the first node and ground voltage. The first NMOS transistor includes a control electrode connected to the third node, and the second NMOS transistor includes a control electrode for receiving the input clock signal.

8. The integrated clock gating unit according to claim 3, wherein, The tri-state inverter includes: A p-type metal-oxide-semiconductor PMOS transistor is connected between a power supply voltage and the first node, and includes a control electrode connected to the second node. The first n-type metal-oxide-semiconductor NMOS transistor; and The second NMOS transistor is connected in series between the first node and ground voltage. The first NMOS transistor includes a control electrode connected to the third node, and the second NMOS transistor includes a control electrode for receiving the input clock signal.

9. The integrated clock gating unit according to claim 3, wherein, The tri-state inverter includes: A p-type metal-oxide-semiconductor PMOS transistor is connected between a power supply voltage and the first node, and includes a control electrode connected to the second node. The first n-type metal-oxide-semiconductor NMOS transistor; and The second NMOS transistor is connected in series between the fourth node and ground. The fourth node is included in the input logic and latch circuit, the first NMOS transistor includes a control electrode connected to the third node, and the second NMOS transistor includes a control electrode for receiving the input clock signal.

10. The integrated clock gating unit according to claim 3, wherein, The feedback inverter includes: A p-type metal-oxide-semiconductor (PMOS) transistor is connected between a power supply voltage and the third node, and includes a control electrode connected to the first node; and An n-type metal-oxide-semiconductor (NMOS) transistor is connected between the third node and ground voltage, and includes a control electrode connected to the first node.

11. The integrated clock gating unit according to claim 3, wherein, The feedback inverter includes: A p-type metal-oxide-semiconductor (PMOS) transistor is connected between the second node and the third node, and includes a control electrode connected to the first node; and An n-type metal-oxide-semiconductor (NMOS) transistor is connected between the third node and ground voltage, and includes a control electrode connected to the first node.

12. The integrated clock gating unit according to claim 1, wherein, The input logic and latch circuitry include: A NOR gate includes a first input terminal for receiving the first input enable signal, a second input terminal for receiving the second input enable signal, and an output terminal for outputting the internal enable signal; and The latch includes a first input terminal for receiving the internal enable signal, a second input terminal for receiving the input clock signal, and an output terminal connected to the first node.

13. The integrated clock gating unit according to claim 12, wherein, The latch includes: First p-type metal-oxide-semiconductor PMOS transistor; The second PMOS transistor is connected in series with the first PMOS transistor between the power supply voltage and the first node. Wherein, the first PMOS transistor includes a control electrode that receives the internal enable signal, and the second PMOS transistor includes a control electrode that receives the input clock signal; The first n-type metal-oxide-semiconductor NMOS transistor; and The second NMOS transistor is connected in series with the first NMOS transistor between the first node and ground voltage. The first NMOS transistor includes a control electrode that receives an inverted input clock signal, and the second NMOS transistor includes a control electrode that receives the internal enable signal.

14. The integrated clock gating unit according to claim 12, wherein, The latch includes: An inverter, including an input terminal and an output terminal for receiving the internal enable signal; A p-type metal-oxide-semiconductor PMOS transistor is connected between the output terminal of the inverter and the first node, and includes a control electrode for receiving the input clock signal; The first n-type metal-oxide-semiconductor NMOS transistor; and The second NMOS transistor is connected in series with the first NMOS transistor between the output terminal of the inverter and the first node. The first NMOS transistor includes a control electrode connected to the input terminal of the inverter, and the second NMOS transistor includes a control electrode connected to the second node.

15. The integrated clock gating unit according to claim 12, wherein, The latch includes: An inverter, including an input terminal and an output terminal for receiving the internal enable signal; A p-type metal-oxide-semiconductor PMOS transistor is connected between the output terminal of the inverter and the first node, and includes a control electrode for receiving the input clock signal; The first n-type metal-oxide-semiconductor NMOS transistor; and The second NMOS transistor is connected in series with the first NMOS transistor between the first node and ground voltage. The first NMOS transistor includes a control electrode connected to the second node, and the second NMOS transistor includes a control electrode connected to the input terminal of the inverter.

16. The integrated clock gating unit according to claim 12, wherein, The latch includes: First p-type metal-oxide-semiconductor PMOS transistor; The second PMOS transistor is connected in series with the first PMOS transistor between the power supply voltage and the first node. Wherein, the first PMOS transistor includes a control electrode that receives the internal enable signal, and the second PMOS transistor includes a control electrode that receives the input clock signal; The first n-type metal-oxide-semiconductor NMOS transistor; and The second NMOS transistor is connected in series with the first NMOS transistor between the first node and ground voltage. The first NMOS transistor includes a control electrode connected to the second node, and the second NMOS transistor includes a control electrode that receives the internal enable signal.

17. The integrated clock gating unit according to claim 12, wherein, The NOR gate includes: First p-type metal-oxide-semiconductor PMOS transistor; The second PMOS transistor is connected in series with the first PMOS transistor between the power supply voltage and the third node. Wherein, the first PMOS transistor includes a control electrode that receives the first input enable signal, and the second PMOS transistor includes a control electrode that receives the second input enable signal; The first n-type metal-oxide-semiconductor NMOS transistor; and The second NMOS transistor is connected in parallel to the first NMOS transistor between the third node and ground voltage. The first NMOS transistor includes a control electrode that receives the first input enable signal, and the second NMOS transistor includes a control electrode that receives the second input enable signal.

18. The integrated clock gating unit according to claim 1, wherein, The output driver includes: An inverter includes an input terminal connected to the second node and an output terminal that outputs the output clock signal.

19. An integrated circuit, comprising: Combinational logic circuits are configured to perform logical operations on data based on an output clock signal; as well as An integrated clock gating unit is configured to selectively provide the output clock signal to the combinational logic circuit based on at least one input enable signal and an input clock signal. The integrated clock gating unit includes: The input logic and latching circuit generates an internal enable signal based on a first input enable signal and a second input enable signal, and generates a first internal signal to be provided to the first node based on the internal enable signal and the input clock signal; The hold logic and signal generation circuit are connected between the first node and the second node. The hold logic and signal generation circuit includes a feedback path that feeds back the first internal signal, generates a second internal signal to be provided to the second node based on the first internal signal and the input clock signal, and further includes a first path and a second path that discharge the second node. Wherein, the first path and the second path are different paths, and the second path is connected to the feedback path; and The output driver generates the output clock signal based on the second internal signal. The hold logic and signal generation circuit include: A feedback inverter, including an input terminal connected to the first node and an output terminal connected to the third node, and forming the feedback path; and The three-state inverter includes an input terminal connected to the third node and an output terminal connected to the first node, and forms the feedback path.

20. An integrated clock gating unit, comprising: The NOR gate generates an internal enable signal based on the first input enable signal and the second input enable signal; The latch generates a first internal signal to be provided to the first node based on the internal enable signal and the input clock signal; A NAND gate is connected between the first node and the second node. The NAND gate generates a second internal signal for the second node based on the first internal signal and the input clock signal, and forms a first path for the second node to discharge. The feedback inverter includes an input terminal connected to the first node and an output terminal connected to the third node, and includes a feedback path for feeding back the first internal signal; A three-state inverter includes an input terminal connected to the third node and an output terminal connected to the first node, and forms the feedback path; A feedback and discharge circuit is connected between the second node and the third node, and forms a second path for discharging the second node; as well as The output driver generates an output clock signal based on the second internal signal. The first path and the second path are different paths. The second path is connected to the feedback path and performs both feedback and discharge functions simultaneously.

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