Memory error discrimination device and computer-readable recording medium

Abstract

The present invention provides a memory error discrimination device and a computer program for memory error discrimination, which can discriminate whether an error occurring in a three-dimensionally stacked memory is a soft error caused by radiation incident on the memory. The memory error discrimination device includes: an error detection unit (22) that detects memory elements in each of multiple layers included in a three-dimensionally stacked memory (2) in which an error has occurred; an error position determination unit (23) that determines the positions of the memory elements in which errors have occurred in the multiple layers; and a determination unit (24) that, when the positions of the memory elements in which errors have occurred are arranged in a straight line across two or more predetermined numbers of layers among the multiple layers, determines that the error occurring in the memory is a soft error caused by radiation incident on the memory.

Description

Technical Field

[0001] The present invention relates to a memory error determination device and a computer program for memory error determination that determine, for example, the cause of an error occurring in a three-dimensionally stacked memory. Background Art

[0002] It is known that when radiation enters a three-dimensionally stacked memory, secondary ions are generated by collision with silicon atoms in the memory, and electrons emitted from the silicon atoms in the flight path of the secondary ions reverse the charge in the memory cell, thereby causing a soft error in the memory. Therefore, a technique for improving resistance to such soft errors caused by radiation has been proposed (for example, see Japanese Unexamined Patent Application Publication No. 2019-67469 (hereinafter referred to as Patent Document 1)). In this technique, when writing N data in a memory system in which N memory circuits having the same structure are respectively mounted and N core chips are stacked in the vertical direction, the data is stored at different write addresses for each memory circuit.

[0003] In addition, the following technique has been proposed (for example, see Japanese Unexamined Patent Application Publication No. 2018-128820 (hereinafter referred to as Patent Document 2)). In an FPGA, when the detected position of the soft error is an unused part of the functional unit, the operation of the control device is continued. On the other hand, when the position of the soft error is a specification part of the functional unit, a predetermined process is executed to prevent unnecessary stoppage. Further, the following technique has been proposed (for example, see Japanese Patent Application Laid-Open No. 5-225077 (hereinafter referred to as Patent Document 3)). In a memory having ECC, when a 1-bit error occurs in the memory, it is determined whether it is a hard error or a soft error, and if a hard error occurs, a report is made to the CPU by interruption.

[0004] When a certain error occurs in a memory, it is preferable to be able to accurately determine the cause of the error. This is because if the cause of the error can be accurately determined, appropriate measures can be taken for the memory in which the error has occurred. In particular, for soft errors caused by radiation, they occur even if the memory itself does not malfunction, so it is useful to determine whether the generated error is a soft error caused by radiation. However, the techniques described in Patent Document 1 and Patent Document 2 do not determine the cause even when a certain error occurs in the memory. In addition, in the technique described in Patent Document 3, although it is determined whether the 1-bit error occurring in the memory is caused by a hard error or a software error, the cause of the error cannot be determined. Summary of the Invention

[0005] An object of one aspect of the present invention is to provide a memory error discrimination device capable of discriminating whether an error generated in a three-dimensionally stacked memory is a soft error caused by radiation incident on the memory.

[0006] According to one embodiment, there is provided a memory error discrimination device. The memory error discrimination device includes: an error detection unit 22 that detects memory elements in which an error has occurred in each of multiple layers included in a three-dimensionally stacked memory 2; an error position determination unit 23 that determines the positions of the memory elements in which an error has occurred in each of the multiple layers; and a determination unit 24 that, when the positions of the memory elements in which an error has occurred are arranged in a straight line over two or more predetermined numbers of layers among the multiple layers, determines that the error generated in the memory 2 is a soft error caused by radiation incident on the memory 2.

[0007] According to another aspect, there is provided a computer program for memory error discrimination. The computer program for memory error discrimination includes commands for causing a computer to perform the following steps: detecting memory elements in which an error has occurred in each of multiple layers included in a three-dimensionally stacked memory 2, determining the positions of the memory elements in which an error has occurred in each of the multiple layers, and when the positions of the memory elements in which an error has occurred are arranged in a straight line over two or more predetermined numbers of layers among the multiple layers, determining that the error generated in the memory 2 is a soft error caused by radiation incident on the memory 2.

[0008] According to one aspect, it is possible to discriminate whether an error generated in a three-dimensionally stacked memory is a soft error caused by radiation incident on the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a schematic structural diagram of a memory error discrimination device.

[0010] Figure 2 is a functional block diagram of a processor associated with memory error discrimination processing.

[0011] Figure 3A is a schematic diagram showing an example of the distribution of memory elements that become in error in the case of a soft error being generated in the memory due to radiation.

[0012] Figure 3B is a schematic diagram showing an example of the distribution of memory elements that become in error in the case of an error being generated in the memory for other reasons.

[0013] Figure 4 is a flowchart of the operation of memory error discrimination processing.

[0014] Figure 5It is a schematic diagram for explaining the outline of the memory error discrimination process of the modification example. Summary of the Invention

[0016] Hereinafter, with reference to the drawings, a memory error discrimination device and a computer program for memory error discrimination that operates using the memory error discrimination device will be described. This memory error discrimination device discriminates whether an error that occurs in a three-dimensionally stacked memory, that is, a memory having multiple layers in which memory elements are two-dimensionally arranged, is caused by radiation (for example, α-rays, β-rays, γ-rays, neutron rays, X-rays) incident on the memory. The inventors of the present application have noticed that when radiation is incident on a memory, an error may occur in the memory elements along the flight path of the radiation. Therefore, when writing data to each layer of the three-dimensionally stacked memory, this memory error discrimination device encodes the data using an error correction code or an error detection code. If an error is detected by the error correction code or the error detection code in multiple layers of the memory, this memory error discrimination device discriminates whether the memory elements in which the error has occurred are linearly arranged. And, when the memory elements in which the error has occurred are linearly arranged, this memory error discrimination device determines that the error is a soft error caused by radiation incident on the memory.

[0017] Figure 1 It is a schematic structural diagram of the memory error discrimination device. The memory error discrimination device 1 is installed, for example, in a machine device such as a numerically controlled machine tool or a robot, or a computer. And, the memory error discrimination device 1 has a memory controller 11, a general memory controller 12, a built-in memory 13, an interrupt controller 14, a communication interface 15, and a processor 16 for controlling the three-dimensionally stacked memory 2 that is the object of discrimination for the cause of the error. These parts of the memory error discrimination device 1 are installed, for example, as dedicated circuits for executing the processing of these parts in an integrated circuit. That is, the memory error discrimination device 1 itself is configured as a processor unit. Or, these parts of the memory error discrimination device 1 may also be configured as separate circuits. Further, these parts of the memory error discrimination device 1 are communicably connected to each other via signal lines such as a bus, for example.

[0018] In the present embodiment, the memory 2 that is the object of discrimination of the error cause and is stacked in a three-dimensional shape is a three-dimensional dynamic random access memory (3D-Dynamic Random Access Memory, 3D-DRAM) having layers of a plurality of memory elements arranged in a two-dimensional shape. For example, it stores various data used by applications executed in the device equipped with the memory error discrimination device 1. In addition, the memory 2 is not limited to 3D-DRAM, and any memory stacked in a three-dimensional shape may be used. For example, it may also be a three-dimensionally stacked NAND flash memory (registered trademark).

[0019] The memory controller 11 is connected to the memory 2 and controls the memory 2 according to an instruction from the processor 16. That is, the memory controller 11 writes the data received from the processor 16 and encoded by an error detection code or an error correction code into the memory 2. Alternatively, the memory controller 11 reads the encoded data from the memory 2 and transmits the read data to the processor 16. Further, the memory controller 11 executes a refresh process of the memory 2. In addition, in the present embodiment, the processor 16 encodes the data stored in the memory 2, but the memory controller 11 may also encode the data stored in the memory 2.

[0020] The general-purpose memory controller 12 is connected to the non-volatile memory 3 and controls the non-volatile memory 3 according to an instruction from the processor 16. In addition, the non-volatile memory 3 is an example of a storage unit, and stores, for example, a computer program for memory error discrimination processing and various information used in the processing. In addition, the information used in the memory error discrimination processing includes, for example, a position table indicating the correspondence between the bit address of each memory element of the memory 2 and the position coordinates of the memory element in the three-dimensional space. Further, the non-volatile memory 3 may also store a computer program for startup and information referred to by the computer program for startup. That is, the general-purpose memory controller 12 reads a computer program for startup or the like from the non-volatile memory 3 according to an instruction from the processor 16 or the interrupt controller 14, and transmits the read program or the like to the processor 16.

[0021] The built-in memory 13 is another example of a storage unit, and is, for example, a static random access memory (Static Random Access Memory, SRAM), and temporarily stores data used by an application program executed by the processor 16, or data generated during the memory error discrimination processing, or information read from the non-volatile memory 3.

[0022] The interrupt controller 14 performs interrupt processing. In the present embodiment, for example, when the processor 16 executes an application running on the processor 16 and the interrupt controller 14 detects an uncorrectable error (hereinafter referred to as a non-correctable error) generated in the memory 2, the interrupt controller 14 performs interrupt processing. At this time, the interrupt controller 14 instructs the processor 16 to execute a memory error determination process. In addition, the interrupt controller 14 itself may also execute the memory error determination process described later.

[0023] The communication interface 15 is an interface for connecting the memory error determination device 1 to a display device 4 such as a liquid crystal display as an example of a notification unit, an input device (not shown) such as a keyboard, and an external storage device (not shown) such as a hard disk device. The communication interface 15 outputs, for example, information (such as a message indicating the determination result) indicating the cause of the error generated in the memory 2 received from the processor 16 to the display device 4 or the external storage device. In addition, the communication interface 15 transmits an operation signal or the like received from the input device to the interrupt controller 14 or the processor 16.

[0024] In addition, the external storage device may also store a location table. In this case, the external storage device is another example of a storage unit, and the communication interface 15 reads the location table from the external storage device according to an instruction from the processor 16 and transmits the read location table to the processor 16.

[0025] The processor 16 has, for example, one or more microprocessor units (MPUs) and executes various application programs related to the device in which the memory error determination device 1 is installed. Further, the processor 16 executes a memory error determination process for the memory 2. Further, when executing various processes, the processor 16 writes data or the like used in the process to the memory 2 or the built-in memory 13 as needed, or reads data or the like used in the process from the memory 2, the non-volatile memory 3, or the built-in memory 13. In addition, the memory controller 11 may also execute the memory error determination process described later.

[0026] Figure 2 is a functional block diagram of the processor 16 related to the memory error determination process. The processor 16 includes an encoding unit 21, an error detection unit 22, an error location determination unit 23, and a determination unit 24. Each of these units included in the processor 16 is, for example, a software module implemented by a computer program executed on the processor 16. Alternatively, each of these units included in the processor 16 may be a dedicated arithmetic circuit provided in the processor 16. In addition, the error detection unit 22, the error location determination unit 23, and the determination unit 24 among these units included in the processor 16 execute the memory error determination process.

[0027] When the encoding unit 21 writes data to the memory 2 according to an application program running on the processor 16, the data is divided into bit strings having a predetermined bit length, and each of the bit strings is encoded using an error correction code (ECC) or an error detection code (OCR) to generate codewords. In the present embodiment, the encoding unit 21 uses a SECDED (Single-bit Error Correction Double-bit Error Detection) code such as an extended Hamming code having a 2-bit error detection capability and a 1-bit error correction capability for encoding the bit strings. Then, the encoding unit 21 writes each codeword into the memory 2 via the memory controller 11.

[0028] When the execution of the memory error determination process is instructed from the interrupt controller 14, the error detection unit 22 determines whether an error has occurred in the memory 2. For this purpose, the error detection unit 22 reads in each codeword written to each layer of the memory 2 via the memory controller 11, and determines whether there is an error in each codeword. Since the processor 16 can grasp the address of the memory being accessed, the error detection unit 22 can grasp the storage address of the codeword in which the error has occurred. In the present embodiment, since the SECDED code is used for generating the codewords, the error detection unit 22 can detect a 1-bit correctable error or a 2-bit error in the codeword of interest by calculating the bit string obtained by multiplying the codeword of interest by the check matrix. The error detection unit 22 determines the bit address of the memory element (hereinafter, sometimes referred to as the memory element in which the error has occurred or the memory element in which the error has been detected) storing the detected bit in the codeword in which a 1-bit correctable error has been detected in each codeword, and the address of the memory area storing the codeword in which a 2-bit error has been detected.

[0029] The error detection unit 22 notifies the bit address of the memory element in which the error has occurred to the error position determination unit 23 for each layer of the memory 2. Further, the error detection unit 22 may also notify the address of the memory area storing the codeword in which a 2-bit error has been detected to the error position determination unit 23.

[0030] The error position determination unit 23 determines the coordinates in the three-dimensional space, i.e., the error position, of the memory element in which an error has occurred for each layer of the memory 2. In the present embodiment, the error position determination unit 23 reads in a position table from the non-volatile memory 3 via the general memory controller 12, determines the position coordinates in the three-dimensional space corresponding to the bit address of the memory element in which an error has occurred by referring to this position table, and sets the determined position coordinates as the error position. Then, the error position determination unit 23 notifies the determination unit 24 of the error positions of the respective memory elements in which an error has occurred. Similarly, the error position determination unit 23 can also determine the error positions of the respective memory elements included in the memory area storing the codeword in which a 2-bit error has been detected. Further, the error position determination unit 23 can also notify the determination unit 24 of the error positions of the respective memory elements included in the memory area storing the codeword in which a 2-bit error has been detected.

[0031] Based on the error positions of the respective memory elements in which an error has occurred, the determination unit 24 determines whether the error that has occurred in the memory 2 is a soft error caused by radiation incident on the memory 2.

[0032] Figure 3A FIG. is a schematic diagram showing an example of the distribution of the memory elements that become in error in the case where a soft error occurs in the memory 2 due to radiation. Figure 3B FIG. is a schematic diagram showing an example of the distribution of the memory elements that become in error in the case where an error occurs in the memory 2 for other reasons.

[0033] As Figure 3A shown, in the case where radiation is incident on the memory 2, the incident path 301 of the radiation generally becomes a straight line. Therefore, in the case where a soft error occurs in the memory 2 due to the radiation incident on the memory 2, the memory elements 302 in which an error has occurred are arranged linearly along the incident path 301 of the radiation.

[0034] On the other hand, as Figure 3B shown, in the case where an error occurs in the memory 2 for other reasons, the memory elements 302 in which an error has occurred are not limited to a linear arrangement.

[0035] Therefore, the determination unit 24 determines the positions of the respective memory elements in which an error has occurred, that is, whether each error position extends linearly through the multiple layers of the memory 2. In the case of a linear arrangement, it is determined that the error occurring in the memory 2 is a soft error caused by radiation incident on the memory 2. In the present embodiment, when two-bit errors are detected for any one codeword stored in at least one layer of the memory 2, and for three or more of the other layers of the multiple layers of the memory 2 (hereinafter, for ease of explanation, referred to as single-bit error layers), when one-bit errors are detected in any one codeword, the determination unit 24 calculates a straight line connecting the error positions of two of the single-bit error layers. And when there are a predetermined number or more of error positions on this straight line among the error positions in each single-bit error layer, the determination unit 24 determines that the respective memory elements in which an error has occurred are linearly arranged in the multiple layers of the memory 2. That is, the determination unit 24 determines that the error occurring in the memory 2 is a soft error caused by radiation incident on the memory 2. In addition, the predetermined number can be set, for example, to the total number of single-bit error layers or a number obtained by multiplying the total number of single-bit error layers by a predetermined number less than 1 (for example, 0.5 to 0.9). Further, when the distance between the error position and the straight line is equal to or less than a predetermined distance (for example, a distance corresponding to the pitch between memory elements), the determination unit 24 may also determine that the error position is on this straight line. For example, in Figure 3A the example shown, in the layers 311 to 314 of the memory 2, only one memory element 302 in which an error has occurred in the layers 311, 313, and 314 is detected. In addition, since errors have occurred in multiple memory elements in the layer 312, the bits that have become errors cannot be determined for the codewords stored in these memory elements (that is, for the codewords stored in the layer 312, an error that cannot be corrected is detected). Therefore, since the error positions of the memory elements 302 in the layers 311, 313, and 314 are linearly arranged, the determination unit 24 can determine that the error occurring in the memory 2 is a soft error caused by radiation incident on the memory 2.

[0036] According to a modified example, the determination unit 24 performs a Hough transform on the set of error positions of each single-bit error layer to obtain the straight line with the largest number of error positions located on it. When the number of error positions on this straight line is equal to or more than a predetermined number, the determination unit 24 determines that the error occurring in the memory 2 is a soft error caused by radiation incident on the memory 2.

[0037] In addition, when the error generated in the memory 2 is an error caused by radiation incident on the memory 2, there is a high possibility that the memory area storing the codeword that is the cause of the error that cannot be corrected, that is, the codeword in which 2-bit errors are detected, is located on the straight line on which the error positions are arranged. Therefore, the determination unit 24 may also determine that the error generated in the memory 2 is a soft error caused by radiation incident on the memory 2 only when the straight line on which the error positions are arranged passes through the memory area storing the codeword that is the cause of the error that cannot be corrected. Further, in this case, the determination unit 24 can determine whether the straight line on which the error positions are arranged passes through this memory area based on the position in the three-dimensional space of the memory area storing the codeword that is the cause of the error that cannot be corrected, which is notified from the error position determination unit 23.

[0038] When the determination unit 24 determines that the error generated in the memory 2 is a soft error caused by radiation incident on the memory 2, it causes the display device 4 to display a message indicating the determination result via the communication interface 15. Thus, the determination result is notified to the user. And the determination unit 24 can also cause the display device 4 to display a message indicating that there is no need to replace the hardware.

[0039] Figure 4 is the operation flowchart of the memory error discrimination process. When the processor 16 is instructed by the interrupt controller 14 to execute the memory error discrimination process, it executes the memory error discrimination process according to the following operation flowchart.

[0040] The error detection unit 22 of the processor 16 detects the codewords in which 1-bit correctable errors have occurred among the codewords stored in each layer of the memory 2, and for each detected codeword, determines the bit address of the memory element in which the error has occurred (step S101).

[0041] The error position determination unit 23 of the processor 16 determines the error position in the three-dimensional space for each memory element in which an error has occurred, based on the bit address (step S102).

[0042] The determination unit 24 of the processor 16 determines whether the determined error positions extend linearly across multiple layers of the memory 2 (step S103). When the determined error positions extend linearly across multiple layers of the memory 2 (step S103 - Yes), the determination unit 24 determines that the error generated in the memory 2 is a soft error caused by radiation incident on the memory 2. Then, the determination unit 24 causes a message indicating the determination result to be displayed on the display device 4 via the communication interface 15 (step S104).

[0043] After step S104, or when the error positions determined in step S103 do not cover the multi-layers of the memory 2 arranged linearly (step S103 - No), the processor 16 ends the memory error determination process.

[0044] As described above, the memory error determination device determines the positions of the memory elements where errors have occurred based on the data encoded by error detection codes or error correction codes stored in each layer of the three-dimensionally stacked memory. The memory error determination device determines whether the memory elements where errors have occurred cover multiple layers arranged linearly based on the positions of the memory elements where errors have occurred. Further, when the memory elements where errors have occurred cover multiple layers arranged linearly, the memory error determination device determines that the error occurring in the memory is a soft error caused by radiation incident on the memory. Therefore, the memory error determination device can determine whether the error occurring in the three-dimensionally stacked memory is caused by radiation. As a result, when an uncorrectable error occurs in the memory, it is easy for the user to determine whether it is necessary to replace the memory.

[0045] According to the modified example, the determination unit 24 may also set one block for a predetermined number (for example, 3×3 or 5×5) of memory elements for each layer of the memory 2. Further, when an error occurs in any one of the memory elements within the block, the determination unit 24 may also determine whether the error positions cover multiple layers arranged linearly by determining that all the memory elements within the block to which the memory element where the error has occurred belongs have had an error.

[0046] Figure 5It is a schematic diagram for explaining the outline of the memory error determination process of this modification example. In this example, for layers 511 to 514 of the memory 2, one block is set for every three memory elements. And, in this example, an error occurs in each of the memory elements 501 to 504. Therefore, in layer 511, each memory element within block 521 containing memory element 501 is regarded as having an error. Similarly, each of block 522 containing memory element 502 in layer 512, block 523 containing memory element 503 in layer 513, and block 524 containing memory element 504 in layer 514 is regarded as having an error in each memory element contained in that block. And, in this case, as shown by arrow 321, the memory elements within blocks 521 to 524 are arranged linearly, so the determination unit 24 determines that the error occurring in the memory 2 is a soft error caused by radiation incident on the memory. According to this modification example, even when the positions of the respective memory elements in which errors occur due to the relationship between the radiation incident on the memory 2 and the positions of the collided silicon atoms are distributed with some deviation relative to the flight path of the radiation, the determination unit 24 can accurately determine whether the error occurring in the memory is caused by radiation incident on the memory.

[0047] In addition, in the above modification example, the determination unit 24 may also regard each block as a memory area for writing one codeword. Furthermore, in this case, the encoding unit 21 may also apply an error detection code such as a parity check code or a Cyclic Redundancy Check (CRC) code to each bit string instead of the SECDED code. When each block is set as a memory area for writing one codeword, the determination unit 24 may also use the layer containing the memory area storing the codeword in which an uncorrectable error has occurred for the determination of whether the error positions are arranged linearly in multiple layers. Therefore, even when the number of layers containing the memory elements in which errors have occurred is three layers, the determination unit 24 can determine whether the error occurring in the memory 2 is a soft error caused by radiation incident on the memory.

[0048] In addition, it is rare for multiple radiation rays to simultaneously enter the memory 2. Therefore, in the above-described embodiments or modified examples, when errors occur at multiple different positions in each of a predetermined number (for example, 2 to 3) or more layers, that is, when errors occur in multiple different memory elements, the determination unit 24 determines that the error occurring in the memory 2 is not caused by radiation. However, since there are also cases where errors occur in multiple memory elements that are close to each other within the same layer due to radiation, when errors occur in multiple memory elements within the same block or in two adjacent blocks, the errors occurring in these multiple memory elements may be errors occurring at one location. Moreover, the determination unit 24 may also cause the display device 4 to display, via the communication interface 15, a message indicating that the error occurring in the memory 2 is not an error caused by radiation. According to this modified example, the determination unit 24 can suppress misjudging an error occurring in the memory due to a cause other than radiation as an error caused by radiation.

[0049] In addition, according to another modified example, in the case of assuming the range of the direction in which radiation enters the memory 2, information indicating this range (hereinafter referred to as the incident direction range) may also be pre-stored in the non-volatile memory 3 or an external storage device. Moreover, the determination unit 24 may determine whether the error positions are arranged in a straight line in multiple layers only for the straight lines in the directions included in the incident direction range. In addition, in this case, even when the number of layers including the memory elements in which errors have occurred is only 2 layers, the determination unit 24 may determine that the error positions are arranged in a straight line in multiple layers, that is, the error occurring in the memory 2 is a soft error caused by radiation entering the memory, only when the direction of the straight line connecting the respective error positions in these 2 layers is included in the incident direction range.

[0050] In addition, if alpha rays, which are a type of radiation, enter the memory 2 and collide with silicon atoms in any layer, secondary ions are generated from the collision position, so errors may sometimes occur in multiple memory elements around the collision site. In this case, it is highly likely that the layer including the multiple memory elements in which errors have occurred is at the end of the flight path of the alpha rays. Therefore, according to another modified example, when the determination unit 24 detects multiple memory elements in which errors have occurred in the layer at either end of the straight line in which the error positions in multiple layers are arranged, it may also determine that the error occurring in the memory 2 is a soft error caused by alpha rays entering the memory 2. Moreover, the determination unit 24 may also cause a message indicating the determination result to be displayed on the display device 4 via the communication interface 15.

[0051] Further, according to another modification example, when the determination unit 24 determines that the error generated in the memory 2 is a soft error caused by radiation incident on the memory 2, the determination result and the determination date and time may be stored in an external storage device as error history information. Thereby, the user can investigate the occurrence frequency of soft errors caused by radiation by referring to the error history information.

[0052] Further, according to another modification example, when the determination unit 24 determines that the error generated in the memory 2 is a soft error caused by radiation incident on the memory 2, regarding the memory area of the memory 2 that stores the codeword for which an uncorrectable error has occurred, it is determined whether the bit string corresponding to the codeword written to the memory area remains in the internal memory 13. Moreover, when the bit string remains in the internal memory 13, the determination unit 24 may also encode the bit string again and write it to the memory area of the memory 2.

[0053] Further, according to another modification example, the processor 16 may also perform a memory error determination process on the memory 2 at a predetermined cycle or at a predetermined timing. In this case, even if no uncorrectable error has occurred in the memory 2, the processor 16 can detect a soft error caused by radiation incident on the memory 2.

[0054] In addition, a computer program for each function of the processor 16 of the memory error determination device 1 that implements the above-described embodiment or modification example may also be provided in a form recorded on a computer-readable removable recording medium such as a semiconductor memory, a magnetic recording medium, or an optical recording medium.

[0055] All examples and specific terms listed herein are for the purpose of helping the reader understand the present invention and the teachings of the concepts contributed by the inventor to advance the technology, and should be construed as not limited to the structure of any example in this specification related to the advantages and disadvantages of the present invention, such specific examples listed, and conditions. Although the embodiments of the present invention have been described in detail, it should be understood that various changes, substitutions, and modifications can be made without departing from the gist and scope of the present invention.

Claims

1. A memory error discrimination device, characterized in that: The memory error discrimination device includes: An error detection unit that detects memory elements in which errors have occurred in each of multiple layers included in a three-dimensionally stacked memory; An error position determination unit that determines the positions of the memory elements in which the errors have occurred in each of the multiple layers; And A determination unit that, when the positions of the memory elements in which the errors have occurred are arranged in a straight line over 2 or more predetermined numbers of layers among the multiple layers, determines that the error occurring in the memory is a soft error caused by radiation incident on the memory; Data stored in the memory is divided into bit strings having a predetermined bit length, and for each of the bit strings, a codeword obtained by encoding the bit string using a code having an error correction ability of 1 bit and an error detection ability of 2 bits is stored in the memory; When the error detection unit detects 2-bit errors in the codewords stored in any layer of the multiple layers, for the other layers of the multiple layers, it determines the codewords in which 1-bit errors are detected according to the above code, and determines the memory elements storing the bits that are the errors as the memory elements in which the above errors have occurred.

2. The memory error discrimination device according to claim 1, characterized in that: When the determination unit determines that the error occurring in the memory is a soft error caused by radiation incident on the memory, it notifies the result of the determination via a notification unit.

3. The memory error discrimination device according to claim 1 or 2, characterized in that: The determination unit sets blocks for a predetermined number of memory elements in each of the multiple layers, regards each memory included in the block to which the memory element in which the error has occurred belongs as the memory element in which the error has occurred, and determines whether the positions of the memory elements in which the error has occurred are arranged in a straight line over the predetermined number of layers.

4. The memory error discrimination device according to claim 1 or 2, characterized in that: When there are multiple memory elements in which the error has occurred in the layer at one end of the straight line where the positions of the memory elements in which the error has occurred are arranged in the multiple layers, the determination unit determines that the error occurring in the memory is a soft error caused by α-rays incident on the memory.

5. A computer-readable recording medium recording a computer program for memory error discrimination, characterized in that: The computer program causes a computer to perform the following steps: Detect memory elements in which errors have occurred in each of multiple layers included in a three-dimensionally stacked memory; Determine the positions of the memory elements in which the errors have occurred in each of the multiple layers; When the positions of the memory elements in which the errors have occurred are arranged in a straight line over 2 or more predetermined numbers of layers among the multiple layers, determine that the error occurring in the memory is a soft error caused by radiation incident on the memory. The data stored in the above-mentioned memory is divided into bit strings having a predetermined bit length. For each of the above-mentioned bit strings, a codeword obtained by encoding the bit string using a code having an error correction capability of 1 bit and an error detection capability of 2 bits is stored in the above-mentioned memory. The memory element in which the above error has occurred is detected as follows: when 2-bit errors are detected in the codewords stored in any layer of the above-mentioned multi-layer, for the other layers of the above-mentioned multi-layer, codewords in which 1-bit errors are detected are determined according to the above code, and the memory element storing the bit that has become the error is determined as the memory element in which the above error has occurred.

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