Pre-emphasis circuit, method and display device
By using a pre-emphasis circuit in the source driver IC, it determines whether to pre-emphasis voltage based on the change of data bits and input signals, the problem of slowing voltage slewing rate in high-resolution display screens is solved, and a more stable IC temperature and Higher picture quality.
Patent Information
- Application Number
- CN202011475365.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2020-12-14
- Publication Date
- 2025-02-07
- Estimated Expiration
- 2040-12-14
AI Technical Summary
In high-resolution displays, the source driver IC needs to drive a large number of pixels, resulting in slower output voltage conversion rate, resulting in abnormal picture quality and increased IC temperature.
Pre-emphasis circuit is adopted, including latch, level shifter, decoder, gamma voltage supply and amplifier input pre-emphasis module. By judging the specified number of bits of data and input pre-emphasis signal, it determines whether to make gray scale The voltage is pre-emphasized, thereby increasing the voltage slewing rate.
Without increasing the quiescent current of the amplifier, the rapid conversion of the output voltage is achieved, ensuring the stability of the IC temperature and improving the picture quality of the high-resolution display.
Smart Images

Figure CN112615616B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of display driving, and in particular to a pre-emphasis circuit, method and display device. Background Art
[0002] The source driver IC of the display screen reconstructs the input digital signal into an analog signal through a digital-analog converter (DAC) to drive the pixels of the panel. The higher the resolution of the display screen, the more pixels there are, so the number of pixels that need to be driven in the same time increases, resulting in a shorter driving time for each pixel; and the larger the screen, the greater the capacitance of the screen, and the longer the time to drive the pixel; this will slow down the conversion rate of the output voltage in the source driver IC of the display panel, resulting in abnormal image quality and increased IC temperature.
[0003] In ordinary display source driver IC circuits, a commonly used method is to increase the quiescent current of the amplifier to improve the voltage conversion rate. If the display screen has a resolution of 8k or above, simply increasing the current to increase the voltage conversion rate has a limited effect, and increasing the current in this way will cause the temperature of the IC to rise. In high-definition and large display devices above 8k, this problem becomes more and more obvious. Summary of the invention
[0004] The present invention provides a pre-emphasis circuit, method and display device, which can realize rapid conversion of output voltage without increasing the quiescent current of the amplifier and ensure the stability of IC temperature.
[0005] In order to achieve the above object, the present invention adopts the following scheme:
[0006] On the one hand, an embodiment of the present invention provides a pre-emphasis circuit, including:
[0007] A first latch, a second latch, a first level shifter, a decoder, a gamma voltage supplier, and an amplifier input pre-emphasis module;
[0008] The first latch is used to store the received first data and output the first data;
[0009] The second latch is used to store the received second data and output the second data, where the second data is the next data of the first data;
[0010] The first level shifter is used to boost the first data and use the high-voltage data signal obtained by boosting as current input data of the decoder;
[0011] The amplifier input pre-emphasis module is connected to the gamma voltage supplier, the decoder, the input pre-emphasis signal IPE terminal, the first latch and the second latch, and is used to determine whether to pre-emphasize the grayscale voltage corresponding to the current input data according to the values of the first data and the specified number of bits of the second data, the IPE value input by the input pre-emphasis signal IPE terminal and the grayscale value corresponding to the current input data:
[0012] If it is necessary to pre-emphasize the voltage of the gray scale corresponding to the current input data, output the pre-emphasized voltage of the gray scale corresponding to the current input data to the decoder;
[0013] If it is not necessary to pre-emphasize the voltage of the gray scale corresponding to the current input data, the voltage of the gray scale corresponding to the current input data is output to the decoder.
[0014] Optionally, the amplifier input pre-emphasis module includes:
[0015] A mode detection module, the mode detection module is connected to the first latch and the second latch, and is used to determine whether it is possible to pre-emphasize the grayscale voltage corresponding to the current input data based on the values of the specified bits of the first data and the second data and the IPE value, and output a control signal;
[0016] A pre-emphasis module is connected to the output end of the mode detection module, the output end of the gamma voltage supplier and the input end of the decoder, and is used to determine whether to pre-emphasize the current input data according to the control signal provided by the mode detection module and the grayscale value corresponding to the current input data.
[0017] Optionally, the mode detection module includes:
[0018] XOR gate circuit, AND gate circuit, D flip-flop and second level shifter;
[0019] The input end of the XOR gate circuit is connected to the first latch and the second latch, and is used to determine whether the values of the specified number of bits of the first data and the second data input are equal, and output the determination result;
[0020] The output end of the XOR gate circuit is connected to the D end of the D flip-flop, the input end of the AND gate circuit is connected to the Q end of the D flip-flop, and the input end of the AND gate circuit is also connected to the input pre-emphasis signal IPE end, and is used to judge whether it is possible to pre-emphasize the grayscale voltage corresponding to the current input data according to the judgment result of the XOR gate circuit and the IPE value, including:
[0021] When the values of the designated bits of the first data and the second data are not equal, and IPE=1, a determination result that a voltage corresponding to the gray scale of the current input data may need to be pre-emphasized is obtained and output;
[0022] When the values of the designated bits of the first data and the second data are equal or IPE=0, a determination result that it is not necessary to pre-emphasize the voltage corresponding to the gray scale of the current input data is obtained and outputted;
[0023] The second level shifter is connected to the output end of the AND gate circuit and is used to provide a control signal for the pre-emphasis module.
[0024] Optionally, the values of the specified number of bits of the first data and the second data include:
[0025] The value D1 of the xth bit of the first data <x>, the value D2 of the xth bit of the second data <x>.
[0026] Optionally, the xth bit is the most significant bit of the first data and / or the second data.
[0027] Optionally, the pre-emphasis circuit includes:
[0028] The gamma voltage supplier includes a plurality of different grayscale voltage output ports, and the decoder includes a plurality of grayscale voltage input ports corresponding to the different grayscale voltage output ports;
[0029] The pre-emphasis module includes n sub-control modules, where n≥1, and each sub-control module is connected between a designated grayscale voltage output port and an input port, and is used to perform pre-emphasis control on the output of the designated grayscale voltage.
[0030] Optionally, the sub-control module includes a first switch and a second switch;
[0031] One end of the first switch is connected to a designated grayscale voltage output port in the gamma voltage supplier, and the other end is connected to a pre-emphasis output port of the designated grayscale voltage;
[0032] The first switch is controlled to be closed and opened by the value of the control signal;
[0033] One end of the second switch is connected to the pre-emphasis input voltage, and the other end is connected to the pre-emphasis output port of the specified grayscale voltage;
[0034] The second switch is controlled to be closed and opened by the value of the control signal;
[0035] The pre-emphasis output terminal of the designated gray-scale voltage is connected to an input port of the decoder corresponding to the designated gray-scale voltage.
[0036] Optionally, the sub-control module includes a multiplexer:
[0037] The input end of the multiplexer is respectively connected to the designated grayscale voltage output port and the pre-emphasis input voltage end of the gamma voltage supplier, and the output end is the pre-emphasis output end of the designated grayscale voltage, and the pre-emphasis output end of the designated grayscale voltage is connected to the input port corresponding to the designated grayscale voltage in the decoder;
[0038] The multiplexer selects whether the output voltage of a specified gray scale needs to be emphasized according to the value of the control signal.
[0039] On the one hand, an embodiment of the present invention provides a pre-emphasis method, which is applied to the pre-emphasis circuit described in the embodiment of the present invention, including:
[0040] Receiving and storing first data and second data, wherein the second data is the last bit of the first data;
[0041] Determine whether to pre-emphasize the grayscale voltage corresponding to the current input data according to the values of the specified number of bits of the first data and the second data, the IPE value inputted by the pre-emphasis signal IPE terminal, and the grayscale value corresponding to the current input data;
[0042] If it is necessary to pre-emphasize the grayscale voltage corresponding to the current input data, output the pre-emphasized grayscale voltage corresponding to the current input data;
[0043] If there is no need to pre-emphasize the grayscale voltage corresponding to the current input data, the grayscale voltage corresponding to the current input data is output.
[0044] Optionally, the determining whether to pre-emphasize the grayscale voltage corresponding to the current input data according to the value of the specified number of bits of the first data and the second data, the IPE value input by the pre-emphasis signal IPE terminal, and the grayscale value of the current input data comprises:
[0045] When the values of the designated bits of the first data and the second data are not equal, and IPE=1, it may be necessary to pre-emphasize the grayscale voltage corresponding to the current input data;
[0046] When the values of the designated bits of the first data and the second data are equal or IPE=0, there is no need to pre-emphasize the grayscale voltage corresponding to the current input data.
[0047] Optionally, the pre-emphasis of the grayscale voltage corresponding to the current input data may include:
[0048] If the grayscale value corresponding to the current input data belongs to the pre-emphasis grayscale range, outputting the pre-emphasis voltage of the grayscale corresponding to the current input data;
[0049] If the grayscale value corresponding to the current input data does not belong to the pre-emphasized grayscale range, a voltage of the grayscale corresponding to the current input data is output.
[0050] On the one hand, an embodiment of the present invention provides a pre-emphasis device, comprising:
[0051] A first processing module, used for receiving and storing first data and second data, wherein the second data is the last bit of the first data;
[0052] A second processing module, configured to determine whether to perform pre-emphasis on the current input data according to the values of the specified number of bits of the first data and the second data, the IPE value input by the pre-emphasis signal IPE terminal, and the grayscale value corresponding to the current input data;
[0053] The second processing module comprises:
[0054] If it is necessary to pre-emphasize the grayscale voltage corresponding to the current input data, output the pre-emphasized grayscale voltage corresponding to the current input data;
[0055] If there is no need to pre-emphasize the grayscale voltage corresponding to the current input data, the grayscale voltage corresponding to the current input data is output.
[0056] On the one hand, an embodiment of the present invention provides a source driver chip, comprising any one of the pre-emphasis circuits provided by the embodiments of the present invention.
[0057] On the one hand, an embodiment of the present invention provides a display device, including the source driver chip provided by an embodiment of the present invention.
[0058] On the one hand, an embodiment of the present invention provides an electronic device, characterized in that it includes a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein when the computer program is executed by the processor, any pre-emphasis enhancement method provided by the embodiment of the present invention is implemented.
[0059] The beneficial effects brought about by the technical solution provided by the embodiment of the present invention include at least: the pre-emphasis circuit provided by the present invention can determine whether to output the pre-emphasis voltage of the gray scale corresponding to the current input data to the amplifier input terminal according to the data inputted by the data input terminal by adding the amplifier input pre-emphasis module, and can realize the rapid conversion of the output voltage without increasing the quiescent current of the amplifier, while ensuring the stability of the IC temperature. BRIEF DESCRIPTION OF THE DRAWINGS
[0060] Figure 1 A schematic diagram of a pre-emphasis circuit structure provided by an embodiment of the present invention;
[0061] Figure 2 A schematic diagram of a pre-emphasis circuit structure provided by an embodiment of the present invention;
[0062] Figure 3 A schematic diagram of a pre-emphasis circuit structure provided by an embodiment of the present invention;
[0063] Figure 4 A schematic diagram of the structure of a mode detection module of a pre-emphasis circuit provided by an embodiment of the present invention;
[0064] Figure 5 A schematic structural diagram of a pre-emphasis module of a pre-emphasis circuit provided in an embodiment of the present invention;
[0065] Figure 6 A schematic structural diagram of a pre-emphasis module of a pre-emphasis circuit provided in an embodiment of the present invention;
[0066] Figure 7 A schematic structural diagram of a pre-emphasis module of a pre-emphasis circuit provided in an embodiment of the present invention;
[0067] Figure 8 A schematic structural diagram of a pre-emphasis module of a pre-emphasis circuit provided in an embodiment of the present invention;
[0068] Fig. 9 A flow chart of a pre-emphasis method provided by an embodiment of the present invention;
[0069] Fig.10 A schematic diagram of the structure of a pre-emphasis device provided in an embodiment of the present invention;
[0070] Fig.11 A schematic diagram of the structure of a pre-emphasis device provided in an embodiment of the present invention;
[0071] Fig.12 A schematic diagram of the structure of an electronic device provided by an embodiment of the present invention;
[0072] Description of reference numerals:
[0073] 101 - first latch, 102 - second latch, 103 - first level shifter, 104 - decoder, 105 - gamma voltage supplier, 106 - amplifier input pre-emphasis module, 107 - amplifier, 1061 - mode detection module, 1062 - pre-emphasis module. DETAILED DESCRIPTION
[0074] In order to make the purpose, technical solution and advantages of the embodiment of the present invention clearer, the technical solution of the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings of the embodiment of the present invention. Obviously, the described embodiment is a part of the embodiment of the present invention, not all of the embodiments. Based on the described embodiment of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.
[0075] The terms "first", "second", etc. in the specification and claims of the present invention are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present invention can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.
[0076] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.
[0077] refer to Figure 1 The schematic diagram of the pre-emphasis circuit provided by the embodiment of the present invention is shown. The pre-emphasis circuit provided by the present invention adds an amplifier input pre-emphasis module. The added module circuit is based on the data Data input by the DAC (digital analog converter). <n:0>The data input to the amplifier is pre-emphasized to achieve fast voltage transitions.
[0078] refer to Figure 1 , the pre-emphasis circuit comprises:
[0079] A first latch 101, a second latch 102, a first level shifter 103, a decoder 104, a gamma voltage supplier 105 and an amplifier input pre-emphasis module 106;
[0080] The first latch 101 is used to store the received first data and output the first data;
[0081] The second latch 102 is used to store the received second data and output the second data, where the second data is the next data of the first data;
[0082] The first level shifter 103 is used to boost the first data and use the high-voltage data signal obtained by boosting as current input data of the decoder 104;
[0083] The amplifier input pre-emphasis module 106 is connected to the gamma voltage supplier 105, the decoder 104, the input pre-emphasis signal IPE terminal, the first latch 101 and the second latch 102, and is used to determine whether to pre-emphasize the grayscale voltage corresponding to the current input data according to the values of the first data and the specified number of bits of the second data, the IPE value input by the input pre-emphasis signal IPE terminal and the grayscale value corresponding to the current input data:
[0084] If it is necessary to pre-emphasize the voltage of the gray scale corresponding to the current input data, output the pre-emphasized voltage of the gray scale corresponding to the current input data to the decoder 104;
[0085] If there is no need to pre-emphasize the voltage of the gray scale corresponding to the current input data, the voltage of the gray scale corresponding to the current input data is output to the decoder 104 .
[0086] Through the pre-emphasis module in the above pre-emphasis circuit, it is possible to realize the digital signal Data at the DAC input end. <n:0>The output voltage can be quickly converted without increasing the quiescent current of the amplifier, and the voltage at the input of the amplifier can be controlled to change the gamma voltage within a specific range, while ensuring the stability of the IC temperature.
[0087] Specifically, taking the data input end as an 8-bit DAC (digital-to-analog converter) as an example, refer to Figure 2 The structure diagram of the pre-emphasis circuit of the 8-bit source code driver IC is used to illustrate the working mode of the pre-emphasis circuit provided by the present invention:
[0088] The first latch 101 outputs the first data D1<7:0> in binary form, the second latch 102 outputs the second data D2<7:0> in binary form, the first level shifter 103 pressurizes the input data D1<7:0> to obtain a high-voltage data signal DH<7:0> and an inverted signal DHB<7:0>, and outputs DH<7:0> and DHB<7:0> to the decoder 104.
[0089] Taking the first data and the second data specifying the 7th bit as an example, the amplifier input pre-emphasis module 106 obtains the value D1 of the 7th bit of the first data <7> and the value D2 of the 7th bit of the second data <7> , according to the IPE value and the grayscale value of the current input data, determine whether to pre-emphasize the grayscale voltage corresponding to the current input data; for IPE (Input Pre-Emphasis, input pre-emphasis signal), 1 or 0 can be input according to the specific needs of the actual use environment.
[0090] It is worth noting that Figure 2 The <7:0> marked in the figure (same as in other figures) are all binary data. Figure 2 The example is 8 bits, so the binary data involved is 8 bits, from bit 0 to bit 7, so D1 <x>and D2 <x>The calculation also starts from position 0.
[0091] It is worth noting that the value of the specified number of bits of the first data and the second data can specify multiple bits of data for comparison. For example, while specifying the 7th bit of the first data and the second data, the 5th bit of the first data and the second data is also specified, and the comparison is performed through two groups of values of the specified number of bits. That is, the comparison conditions of these two groups of specified number of bits need to be met at the same time to meet the pre-emphasis circuit enabling conditions.
[0092] Optional, reference Figure 3 , the amplifier input pre-emphasis module 106 comprises:
[0093] The mode detection module 1061 is connected to the first latch 101 and the second latch 102, and is used to determine whether it is possible to pre-emphasize the grayscale voltage corresponding to the current input data based on the value of the specified number of bits of the first data and the second data and the IPE value, and output a control signal.
[0094] A pre-emphasis module 1062, which is connected to the output end of the mode detection module 1061, the output end of the gamma voltage supplier 105 and the input end of the decoder 104, and is used to determine whether to pre-emphasize the current input data based on the control signal provided by the mode detection module 1061 and the grayscale value corresponding to the current input data. Figure 3 The value of the first data and the second data bit x is specified in D1 <x>and D2 <x>.
[0095] Specifically, Figure 2 As shown, in the pre-emphasis circuit provided by the present invention, the amplifier input pre-emphasis module 106 is composed of two modules: a mode detection module 1061 and a pre-emphasis module 1062;
[0096] The mode detection module 1061 is used to determine the current display mode according to the value of the specified number of bits of the first data and the second data. When the grayscale change of the display output exceeds a specific value, the voltage conversion rate needs to be accelerated. The specific value of the change is determined by the setting.
[0097] After the mode detection module 1061 outputs the control signal, the pre-emphasis module 1062 is required to further determine whether it is necessary to pre-emphasize the grayscale voltage corresponding to the current input data;
[0098] Therefore, the enabling ranges of the mode detection module 1061 and the pre-emphasis module 1062 must be met at the same time in order to achieve rapid voltage conversion through the pre-emphasis circuit.
[0099] Optional, reference Figure 4 The mode detection module 1061 includes:
[0100] XOR gate circuit 10611, AND gate circuit 10613, D flip-flop 10612 and second level shifter 10614;
[0101] The input end of the XOR gate circuit 10611 is connected to the first latch 101 and the second latch 102, and is used to determine whether the values of the specified number of bits of the first data and the second data input are equal, and output the determination result;
[0102] The output end of the XOR gate circuit 10611 is connected to the D end of the D flip-flop 10612, the input end of the AND gate circuit 10613 is connected to the Q end of the D flip-flop 10612, and the input end of the AND gate circuit 10613 is also connected to the input pre-emphasis signal IPE end, and is used to determine whether it is possible to pre-emphasize the grayscale voltage corresponding to the current input data according to the judgment result of the XOR gate circuit 10611 and the IPE value, including:
[0103] When the values of the designated bits of the first data and the second data are not equal, and IPE=1, a determination result that a voltage corresponding to the gray scale of the current input data may need to be pre-emphasized is obtained and output;
[0104] When the values of the designated bits of the first data and the second data are equal or IPE=0, a determination result that it is not necessary to pre-emphasize the voltage corresponding to the gray scale of the current input data is obtained and outputted;
[0105] The second level shifter 10614 is connected to the output end of the AND gate circuit 10613 and is used to provide a control signal for the pre-emphasis module.
[0106] The Rb terminal of the D flip-flop is connected to the inverted signal RSTB of the low-level effective reset signal, which is used to reset the mode detection circuit.
[0107] The trigger terminal of the D flip-flop is connected to the inverted signal of the OENB output enable.
[0108] Specifically, the mode detection module 1061 is used to compare whether the values of the specified bits of the first data and the second data are the same, for example, the value D1 of the specified xth bit is <x>and D2 <x>, if the two are the same, it means that the change between the first data and the second data is not large, and no rapid voltage conversion is required, so there is no need to pre-emphasize the input data;
[0109] If the values of the designated bits of the first data and the second data are different, it means that the change between the first data and the second data is too large, and the output voltage needs to be quickly converted, and pre-emphasis may be required.
[0110] Specifically, the input terminal provides 8-bit data Data<7:0>, taking the 7th bit as an example, D1 <7> It is exactly the MSB (Most Significant Bit) value of the first data, D2 <7> It is the MSB value of the second data, that is, D1 is the data driving the current display IC, and D2 is the next data driving the display IC. When these two values are different, it means that the display mode changes greatly, and it may be necessary to quickly implement voltage conversion. Specifically, through the XOR gate circuit 10611, D1 <7> and D2 <7> Make a judgment.
[0111] Specifically, when the OENB signal is at a rising edge (changes from "0" to "1"), the mode detection module 1061 detects D1 <7> and D2 <7> Make comparisons;
[0112] If D1 <7> =D2 <7> , then the XOR gate circuit 10611 and the AND gate circuit 10613 will both output "0". At this time, IPEH outputs "0" and IPEHB outputs "1";
[0113] If IPE=0, the AND gate circuit 10613 will output "0". At this time, IPEH outputs "0" and IPEHB outputs "1".
[0114] Only when D1 <x> ≠D2 <x>And when IPE=1, the AND gate circuit 10613 will output "1". At this time, IPEH outputs "1" and IPEHB outputs "0". Only in this case does it belong to the enabling range of the mode detection module 1061.
[0115] At this time, the control signals output by the mode detection module 1061 to the pre-emphasis module 1062 are the IPEH and IPEHB signals.
[0116] In the above example, the first data and the second data are compared in the case where the designated bit number is the 7th bit. <7> 、D2 <7> Whether they are equal, it is judged whether the input data belongs to the enabling range of the mode detection module 1061, exemplarily:
[0117] Take x=7, that is, compare the most significant bit of the 8-bit data Data<7:0>. When IPE=1,
[0118] D1∈(0,127), D2∈(0,127), D1 <7> =D2 <7> , the input data Data does not belong to the enabled range of the mode detection module 1061;
[0119] D1∈(0,127), D2∈(128,255), D1 <7> ≠D2 <7> , the input data Data belongs to the enabled range of the mode detection module 1061;
[0120] D1∈(128,255), D2∈(0,127), D1 <7> ≠D2 <7> , the input data Data belongs to the enabled range of the mode detection module 1061;
[0121] D1∈(128,255), D2∈(128,255), D1 <7> =D2 <7> , the input data Data does not belong to the enabled range of the mode detection module 1061.
[0122] Optionally, the pre-emphasis circuit provided by the present invention can be set to accelerate the voltage conversion rate only when the grayscale change of the display output exceeds a specific value. Through this setting, it can effectively avoid the situation where the difference between D1 and D2 is very small, but D1 <x> ≠D2 <x>In this case, pre-emphasize the input data.
[0123] Exemplarily, the specific values of grayscale changes may be as follows:
[0124] 1) When only D1 is compared <7> and D2 <7> When , the specific value of grayscale change = total grayscale number / 2.
[0125] Example 1: 8-bit resolution, a total of 256 gray levels.
[0126] Grayscale change specific value = 256 / 2 = 128 grayscales;
[0127] If D1 <7> ≠D2 <7> , and the change between D1 and D2 exceeds 128 gray levels, the conversion rate needs to be accelerated.
[0128] Example 2: 10-bit resolution, a total of 1024 gray levels.
[0129] Grayscale change specific value = 1024 / 2 = 512 grayscales;
[0130] If D1 <7> ≠D2 <7> , and the change between D1 and D2 exceeds 512 gray levels, speeding up the conversion rate.
[0131] 2) When comparing D1 <7> and D2 <7> , D1 <6> and D2 <6> , the specific value of grayscale change = total grayscale number / 4.
[0132] Example 1: 8-bit resolution, a total of 256 gray levels.
[0133] Grayscale change specific value = 256 / 4 = 64 grayscales;
[0134] If (D1 <7> and D2 <7> ) or (D1 <6> and D2 <6> ) changes more than 64 gray levels, the conversion rate needs to be increased.
[0135] Example 2: 10-bit resolution: 1024 gray levels in total.
[0136] Grayscale change specific value = 1024 / 4 = 256 grayscales;
[0137] If (D1 <7> and D2 <7> ) or (D1 <6> and D2 <6> ) changes over 256 gray levels, speeding up the conversion rate.
[0138] Using different first data, second data, the value of the specified number of bits D1 <x>and D2 <x>, or by using the values of specified bits of multiple sets of first data and second data, more precise pattern changes can be detected.
[0139] Specifically, for 8-bit data, x=6 can be set, and for D1 <6> and D2 <6> By comparison, this can change the variation range of the first data and the second data when the mode detection circuit is enabled;
[0140] It can also be set to only meet D1 <7> =D2 <7> , and D1 <6> =D2 <6> , the input data belongs to the enabling range of the mode detection module 1061. For example, for 8-bit data, when IPE=1, compare D1 <7> and D2 <7> , and D1 <6> and D2 <6> ; At this time, D1 needs to be satisfied at the same time <7> ≠D2 <7> , and D1 <6> ≠D2 <6> , in order to meet the enabling conditions.
[0141] When D1 <7> =0,D2 <7> =1, D1∈(0,127), D2∈(128,255);
[0142] When D1 <6> =0,D2 <6> =1, D1∈(0,63)∪(128,191), D2∈(64,127)∪(192,255);
[0143] When D1 <7> =1,D2 <7> =0, D1∈(128,255), D2∈(0,127);
[0144] When D2 <7> =1,D2 <6> When =0, D1∈(64,127)∪(192,255), D2∈(0,63)∪(128,191).
[0145] therefore:
[0146] D1∈(0,63), D2∈(0,191), D1 <7> =D2 <7> or D1 <6> =D2 <6> , the input data Data does not belong to the enabled range of the mode detection module 1061;
[0147] D1∈(0,63), D2∈(192,255), D1 <7> ≠D2 <7> , and D1 <6> ≠D2 <6> , the input data Data belongs to the enabled range of the mode detection module 1061;
[0148] D1∈(192,255), D2∈(0,63), D1 <7> ≠D2 <7> , and D1 <6> ≠D2 <6> , the input data Data belongs to the enabled range of the mode detection module 1061;
[0149] D1∈(192,255), D2∈(0,191), D1 <7> =D2 <7> or D1 <6> =D2 <6> , the input data Data does not belong to the enabled range of the mode detection module 1061.
[0150] D1∈(0,63), D2∈(0,63), D1 <7> =D2 <7> or D1 <6> =D2 <6> , the input data Data does not belong to the enabled range of the mode detection module 1061;
[0151] D1∈(0,63), D2∈(64,255), D1 <7> ≠D2 <7> , and D1 <6> ≠D2 <6> , the input data Data belongs to the enabled range of the mode detection module 1061;
[0152] D1∈(192,255), D2∈(0,191), D1 <7> ≠D2 <7> , the input data Data belongs to the enabled range of the mode detection module 1061;
[0153] D1∈(192,255), D2∈(192,255), D1 <7> =D2 <7> , the input data Data does not belong to the enabled range of the mode detection module 1061.
[0154] Optionally, the pre-emphasis circuit includes:
[0155] The gamma voltage supplier 105 includes a plurality of different grayscale voltage output ports, and the decoder 104 includes a plurality of grayscale voltage input ports corresponding to the different grayscale voltage output ports;
[0156] The pre-emphasis module 1062 includes n sub-control modules, where n≥1, and each sub-control module is connected between a designated grayscale voltage output port and an input port, and is used to perform pre-emphasis control on the output of the designated grayscale voltage.
[0157] Specifically, the pre-emphasis module 1062 receives the grayscale voltage corresponding to the current input data output by the gamma voltage supplier 105, determines whether to pre-emphasize the grayscale voltage corresponding to the current input data according to the control signal and the grayscale value of the current input data, and outputs it to the input interface of the grayscale voltage corresponding to the current input data in the decoder 104.
[0158] Figure 5 FIG. 1 shows a schematic diagram of the structure of the pre-emphasis module 1062 in the case of an 8-bit input signal. Figure 5 As shown, the gamma voltage supply 105 has a voltage output port G corresponding to 255 gray levels of 8-bit input data. <0> ~G <255> The decoder 104 has a voltage input port GO corresponding to 255 gray levels. <0> ~GO <255> According to the configuration, there is at least one sub-control module in the pre-emphasis module, exemplarily, Figure 5 The pre-emphasis module shown has a G corresponding to 0 grayscale. <0> and GO <0> The sub-control module 106210 between the corresponding 255 grayscale G <255> and GO <255> Sub-control module 10621 between 255 .
[0159] Specifically, Figure 3 , Figure 5 In the embodiment, when the input data D1<7:0> is boosted by the first level shifter 103, the high-voltage data signal DH<7:0> and the inverted signal DHB<7:0> of the input data are obtained and output to the decoder 104, and the gamma voltage supplier 105 provides 255 grayscale voltages, which correspond to 255 grayscale values. For example, DH<7:0> = "11111111", which corresponds to 255 grayscales, and the corresponding gamma voltage supplier G <255> port, DH<7:0> = "00000000", corresponding to grayscale 0, corresponding to the G of the gamma voltage supply 105 <0> port; DH<7:0> = "10000000", corresponding to 128 grayscale, corresponding to the gamma voltage supply 105 output port G <128> Afterwards, the pre-emphasis module 1062 determines whether to pre-emphasize the input data according to the grayscale voltage provided by the gamma voltage supply voltage port and the control signal provided by the mode detection module 1061. For example, Figure 5 In the case of DH<7:0>="11111111", G <255> and GO <255> Sub-control module 10621 between 255 Therefore, when the control signal, IPEH = "1", IPEHB = "0", the output is to GO <255> The voltage is the pre-emphasis voltage corresponding to the gray scale of the current input data. Figure 5 When DH<7:0>="10000000", 128 gray scale is not in Figure 5 The pre-emphasis module is within the pre-emphasis range shown in the figure. Therefore, no matter what the control signal is, GO <255> All equal to G <255> , no pre-emphasis is required.
[0160] The following table shows the case where DH<7:0> = "11111111", DH<7:0> = "00000000", and DH<7:0> = "10000000". Figure 5 In the example, the voltage value output by the pre-emphasis module 1062 is:
[0161]
[0162] The above sub-control module is only one implementation mode provided by the present invention. Specifically, it can be configured in different G <x>Japanese GO <x>A sub-control module 10621 is set between them.
[0163] Optionally, the sub-control module includes a first switch and a second switch;
[0164] One end of the first switch is connected to a designated grayscale voltage output port in the gamma voltage supplier 105, and the other end is connected to a pre-emphasis output port of the designated grayscale voltage;
[0165] The first switch is controlled to be closed and opened by the value of the control signal;
[0166] One end of the second switch is connected to the pre-emphasis input voltage, and the other end is connected to the pre-emphasis output port of the specified grayscale voltage;
[0167] The second switch is controlled to be closed and opened by the value of the control signal;
[0168] The pre-emphasis output terminal of the designated gray-scale voltage is connected to an input port of the decoder corresponding to the designated gray-scale voltage.
[0169] Specifically, refer to Figure 6 , the first switch in the figure is a, the second switch is b, and the sub-control module 10621 shown in the figure controls the first switch and the second switch through the IPEH and IPEHB signals to directly output the voltage corresponding to the gray scale of the current input data, or output the pre-emphasized voltage corresponding to the gray scale of the current input data. Exemplary, Figure 6 The amplifier input pre-emphasis module 106 has sub-control modules set at 255 gray scale and 0 gray scale to G <255> and GO <255> For example, the first switch is 10621 255a , the second switch is 10621 255b When the first switch control signal IPEH=1, the first switch is closed, and when IPEH=0, the first switch is opened; when the second switch control signal IPEHB=1, the second switch is closed, and when IPEHB=0, the second switch is opened; through the above method, the amplifier input pre-emphasis module 106 can determine whether to pre-emphasize the grayscale voltage corresponding to the current input data according to the control signal.
[0170] Optionally, the sub-control module may also be a multiplexer:
[0171] The input end of the multiplexer is respectively connected to the designated grayscale voltage output port and the pre-emphasis input voltage end of the gamma voltage supplier, and the output end is the pre-emphasis output end of the designated grayscale voltage, and the pre-emphasis output end of the designated grayscale voltage is connected to the input port corresponding to the designated grayscale voltage in the decoder;
[0172] The multiplexer selects whether the output voltage of a specified gray scale needs to be emphasized according to the value of the control signal.
[0173] Specifically, refer to Figure 5 In the example, the sub-control module used is a multiplexer. <255> and GO <255> Multiplexer 10621 between 255 For example:
[0174] When IPEH = 1, IPEHB = 0, the output terminal PRE_OUT of the multiplexer is connected to the PRE terminal, that is, at this time, G <255> The output voltage is increased before output, GO <255> The voltage VDD received by the end is the 255 gray scale amplified voltage;
[0175] When IPEH=0, IPEHB=1, the output terminal PRE_OUT of the multiplexer is connected to the ORI terminal, directly to GO <255> Output voltage G corresponding to 255 grayscale <255> .
[0176] The pre-emphasis circuit provided by the present invention can be used in different G <x>Japanese GO <x>Sub-control module 10621 is set between Figure 7-8 Two other pre-emphasis output settings of the pre-emphasis module are listed.
[0177] refer to Figure 7 , multiplexers are set on the output circuits corresponding to 0, 1, 254 and 255 gray levels respectively, Figure 7 In the example, the pre-emphasis module is set to (G <255> -VDD) / (G <254> -VDD) / (G <1> -VSS) / (G <0> -VSS), for example, the following lists different input data values and the corresponding output results (& represents sum):
[0178] Example 1)DH<7:0>='11111111'&IPEH='0':PRE_OUT=G <255> ;
[0179] Example 2) DH<7:0>='11111111'&IPEH='1':PRE_OUT=VDD;
[0180] Example 3)DH<7:0>='11111110'&IPEH='0':PRE_OUT=G <254> ;
[0181] Example 4) DH<7:0>='11111110'&IPEH='1':PRE_OUT=VDD;
[0182] Example 5)DH<7:0>='11111101'&IPEH='0':PRE_OUT=G <253> ;
[0183] Example 6)DH<7:0>='11111101'&IPEH='1':PRE_OUT=G <253> ;
[0184] Example 7)DH<7:0>='00000010'&IPEH='0':PRE_OUT=G <2> ;
[0185] Example 8)DH<7:0>='00000010'&IPEH='1':PRE_OUT=G <2> ;
[0186] Example 9)DH<7:0>='00000001'&IPEH='0':PRE_OUT=G <1> ;
[0187] Example 10) DH<7:0>='00000001'&IPEH='1':PRE_OUT=VSS;
[0188] Example 11)DH<7:0>='00000000'&IPEH='0':PRE_OUT=G <0> ;
[0189] Example 12) DH<7:0>='00000000'&IPEH='1':PRE_OUT=VSS.
[0190] refer to Figure 8 , multiplexers are set on the output circuits corresponding to 1 and 254 gray levels respectively, Figure 8 In the example, the pre-emphasis module is set to (G <254> -G <255> ) / (G <1> -G <0> ), for example, the following lists different input data values and the corresponding output results (& represents sum):
[0191] Example 1)DH<7:0>='11111111'&IPEH='0':PRE_OUT=G <255> ;
[0192] Example 2)DH<7:0>='11111111'&IPEH='1':PRE_OUT=G <255> ;
[0193] Example 3)DH<7:0>='11111110'&IPEH='0':PRE_OUT=G <254> ;
[0194] Example 4)DH<7:0>='11111110'&IPEH='1':PRE_OUT=G <255> ;
[0195] Example 5)DH<7:0>='11111101'&IPEH='0':PRE_OUT=G <253> ;
[0196] Example 6)DH<7:0>='11111101'&IPEH='1':PRE_OUT=G <253> ;
[0197] Example 7)DH<7:0>='00000010'&IPEH='0':PRE_OUT=G <2> ;
[0198] Example 8)DH<7:0>='00000010'&IPEH='1':PRE_OUT=G <2> ;
[0199] Example 9)DH<7:0>='00000001'&IPEH='0':PRE_OUT=G <1> ;
[0200] Example 10)DH<7:0>='00000001'&IPEH='1':PRE_OUT=G <0> ;
[0201] Example 11)DH<7:0>='00000000'&IPEH='0':PRE_OUT=G <0> ;
[0202] Example 12)DH<7:0>='00000000'&IPEH='1':PRE_OUT=G <0> .
[0203] On the one hand, reference Fig. 9 The embodiment of the present invention provides a pre-emphasis method, which is applied to the pre-emphasis circuit described in the embodiment of the present invention, comprising:
[0204] Step 901, receiving and storing first data and second data, where the second data is the last bit of the first data;
[0205] Step 902, determining whether to pre-emphasize the grayscale voltage corresponding to the current input data according to the values of the specified number of bits of the first data and the second data, the IPE value input by the pre-emphasis signal IPE terminal, and the grayscale value corresponding to the current input data;
[0206] Step 903: if the grayscale voltage corresponding to the current input data needs to be pre-emphasized, output the pre-emphasized grayscale voltage corresponding to the current input data;
[0207] Step 904: if it is not necessary to pre-emphasize the grayscale voltage corresponding to the current input data, output the grayscale voltage corresponding to the current input data.
[0208] By comparing the values of the specified number of bits of the first data and the second data, the difference between the first data and the second data can be determined. By comparing the values of the different number of bits of the first data and the second data, the difference threshold of the first data and the second data can be expanded or reduced, and the enabling range of the pre-emphasis module can be adjusted. Only when the IPE signal is a pre-emphasis enabling indication and the grayscale value of the current input data also belongs to the pre-emphasis range, the current input data needs to be pre-emphasized.
[0209] Optionally, step 102, the step of determining whether to pre-emphasize the grayscale voltage corresponding to the current input data according to the value of the specified number of bits of the first data and the second data, the IPE value input by the pre-emphasis signal IPE terminal, and the grayscale value corresponding to the current input data, comprises:
[0210] When the values of the designated bits of the first data and the second data are not equal, and IPE=1, it may be necessary to pre-emphasize the grayscale voltage corresponding to the current input data;
[0211] When the values of the designated bits of the first data and the second data are equal or IPE=0, there is no need to pre-emphasize the grayscale voltage corresponding to the current input data.
[0212] Only when IPE=1 and the values of the designated bits of the first data and the second data are not equal, that is, the difference between the first data and the second data is large and the display mode changes greatly, it is possible to pre-emphasize the current input data.
[0213] Optionally, the step of pre-emphasizing the current input data may include:
[0214] If the grayscale value corresponding to the current input data belongs to the pre-emphasis grayscale range, outputting the pre-emphasis voltage of the grayscale corresponding to the current input data;
[0215] If the grayscale value corresponding to the current input data does not belong to the pre-emphasized grayscale range, a voltage of the grayscale corresponding to the current input data is output.
[0216] When the grayscale voltage corresponding to the current input data may be pre-emphasized, the grayscale value corresponding to the current input data needs to belong to the pre-emphasized grayscale range before the current data is pre-emphasized and the pre-emphasized voltage corresponding to the grayscale of the current input data is output. According to the description of the implementation method of the pre-emphasis circuit, the pre-emphasis grayscale range can be adjusted.
[0217] refer to Fig.10 , an embodiment of the present invention provides a pre-emphasis device 100, comprising:
[0218] The first processing module 1001 is used to receive and store first data and second data, where the second data is the last bit of the first data;
[0219] The second processing module 1002 is used to determine whether to pre-emphasize the grayscale voltage corresponding to the current input data according to the value of the specified number of bits of the first data and the second data, the IPE value input by the pre-emphasis signal IPE terminal and the grayscale value corresponding to the current input data;
[0220] The third processing module 1003 is used for outputting the pre-emphasized voltage of the gray scale corresponding to the current input data if it is necessary to pre-emphasize the gray scale voltage corresponding to the current input data;
[0221] The fourth processing module 1004 is configured to output a grayscale voltage corresponding to the current input data if pre-emphasis is not required for the grayscale voltage corresponding to the current input data.
[0222] Optional, reference Fig.11 , the second processing module 1002 includes:
[0223] The first processing submodule 10021 is used for, when the values of the designated bits of the first data and the second data are not equal and IPE=1, pre-emphasizing the grayscale voltage corresponding to the current input data;
[0224] The second processing submodule 10022 is configured to, when the values of the designated bits of the first data and the second data are equal or IPE=0, not to pre-emphasize the grayscale voltage corresponding to the current input data.
[0225] Optional, reference Fig.11 , the device 100 further includes:
[0226] The fifth processing module 1005 is used for, when the values of the designated bits of the first data and the second data are not equal, possibly pre-emphasizing the grayscale voltage corresponding to the current input data, and comprises:
[0227] If the grayscale value corresponding to the current input data belongs to the pre-emphasis grayscale range, outputting the pre-emphasis voltage of the grayscale corresponding to the current input data;
[0228] If the grayscale value corresponding to the current input data does not belong to the pre-emphasized grayscale range, a voltage of the grayscale corresponding to the current input data is output.
[0229] On the one hand, an embodiment of the present invention further provides a source driver chip, comprising any one of the pre-emphasis circuits provided by the embodiments of the present invention.
[0230] On the one hand, an embodiment of the present invention further provides a display device, including the source driver chip provided by the embodiment of the present invention.
[0231] Please refer to Fig.12 An embodiment of the present invention further provides an electronic device 1200, including a processor 1201, a memory 1202, and a computer program stored in the memory 1202 and executable on the processor 1201. When the computer program is executed by the processor 1201, the computer program implements the various processes of the above-mentioned pre-emphasis method embodiment and can achieve the same technical effect. To avoid repetition, it will not be described here.
[0232] The embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, each process of the embodiment of the above-mentioned pre-emphasis method is implemented, and the same technical effect can be achieved. To avoid repetition, it is not repeated here. The computer-readable storage medium is, for example, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.
[0233] It should be noted that, in this article, the term "includes", "comprising" or any other variation thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprising a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.
[0234] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, a magnetic disk, or an optical disk), and includes a number of instructions for enabling a terminal (which can be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to execute the methods described in each embodiment of the present invention.
[0235] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection of the invention.< / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x>
Claims
1. A pre-emphasis circuit, characterized in that: include: A first latch, a second latch, a first level shifter, a decoder, a gamma voltage supplier, and an amplifier input pre-emphasis module; The first latch is used to store the received first data and output the first data, wherein the first data is in binary form; The second latch is used to store the received second data and output the second data, wherein the second data is the next data of the first data, and the second data is in binary form; The first level shifter is used to boost the first data and use the high-voltage data signal obtained by boosting as current input data of the decoder; The amplifier input pre-emphasis module is connected to the gamma voltage supplier, the decoder, the input pre-emphasis signal IPE terminal, the first latch and the second latch, and is used to determine whether to pre-emphasize the grayscale voltage corresponding to the current input data according to the values of the first data and the specified number of bits of the second data, the IPE value input by the input pre-emphasis signal IPE terminal and the grayscale value corresponding to the current input data: If it is necessary to pre-emphasize the voltage of the gray scale corresponding to the current input data, output the pre-emphasized voltage of the gray scale corresponding to the current input data to the decoder; If it is not necessary to pre-emphasize the voltage of the gray scale corresponding to the current input data, the voltage of the gray scale corresponding to the current input data is output to the decoder.
2. The pre-emphasis circuit according to claim 1, characterized in that: The amplifier input pre-emphasis module comprises: A mode detection module, the mode detection module is connected to the first latch and the second latch, and is used to determine whether it is possible to pre-emphasize the grayscale voltage corresponding to the current input data according to the values of the specified number of bits of the first data and the second data and the IPE value, and output a control signal; A pre-emphasis module is connected to the output end of the mode detection module, the output end of the gamma voltage supplier and the input end of the decoder, and is used to determine whether to pre-emphasize the current input data according to the control signal provided by the mode detection module and the grayscale value corresponding to the current input data.
3. The pre-emphasis circuit according to claim 2, characterized in that: The mode detection module comprises: XOR gate circuit, AND gate circuit, D flip-flop and second level shifter; The input end of the XOR gate circuit is connected to the first latch and the second latch, and is used to determine whether the values of the specified number of bits of the first data and the second data input are equal, and output the determination result; The output end of the XOR gate circuit is connected to the D end of the D flip-flop, the input end of the AND gate circuit is connected to the Q end of the D flip-flop, and the input end of the AND gate circuit is also connected to the input pre-emphasis signal IPE end, and is used to judge whether it is possible to pre-emphasize the grayscale voltage corresponding to the current input data according to the judgment result of the XOR gate circuit and the IPE value, including: When the values of the designated bits of the first data and the second data are not equal, and IPE=1, a determination result that a voltage corresponding to the gray scale of the current input data may need to be pre-emphasized is obtained and output; When the values of the designated bits of the first data and the second data are equal or IPE=0, a determination result that it is not necessary to pre-emphasize the voltage corresponding to the gray scale of the current input data is obtained and outputted; The second level shifter is connected to the output end of the AND gate circuit and is used to provide a control signal for the pre-emphasis module.
4. The pre-emphasis circuit according to claim 1, characterized in that: The values of the specified number of bits of the first data and the second data include: The value D1 of the xth bit of the first data <x>, the value D2 of the xth bit of the second data <x> 。< / x> < / x> 5. The pre-emphasis circuit according to claim 4, characterized in that: The xth bit is the most significant bit of the first data and / or the second data.
6. The pre-emphasis circuit according to claim 2, characterized in that: include: The gamma voltage supplier includes a plurality of different grayscale voltage output ports, and the decoder includes a plurality of grayscale voltage input ports corresponding to the different grayscale voltage output ports; The pre-emphasis module includes n sub-control modules, where n≥1, and each sub-control module is connected between a designated grayscale voltage output port and an input port, and is used to perform pre-emphasis control on the output of the designated grayscale voltage.
7. The pre-emphasis circuit according to claim 6, characterized in that: The sub-control module includes a first switch and a second switch; One end of the first switch is connected to a designated grayscale voltage output port in the gamma voltage supplier, and the other end is connected to a pre-emphasis output port of the designated grayscale voltage; The first switch is controlled to be closed and opened by the value of the control signal; One end of the second switch is connected to the pre-emphasis input voltage, and the other end is connected to the pre-emphasis output port of the specified grayscale voltage; The second switch is controlled to be closed and opened by the value of the control signal; The pre-emphasis output terminal of the designated gray-scale voltage is connected to an input port of the decoder corresponding to the designated gray-scale voltage.
8. The pre-emphasis circuit according to claim 6, characterized in that: The sub-control module includes a multiplexer: The input end of the multiplexer is respectively connected to the designated grayscale voltage output port and the pre-emphasis input voltage end of the gamma voltage supplier, and the output end is the pre-emphasis output end of the designated grayscale voltage, and the pre-emphasis output end of the designated grayscale voltage is connected to the input port corresponding to the designated grayscale voltage in the decoder; The multiplexer selects whether the output voltage of a specified gray scale needs to be emphasized according to the value of the control signal.
9. A pre-emphasis method, applied to the pre-emphasis circuit according to any one of claims 1 to 8, characterized in that: include: Receiving and storing first data and second data, wherein the second data is the last bit of the first data; Determine whether to pre-emphasize the grayscale voltage corresponding to the current input data according to the values of the specified number of bits of the first data and the second data, the IPE value inputted by the pre-emphasis signal IPE terminal, and the grayscale value corresponding to the current input data; If it is necessary to pre-emphasize the grayscale voltage corresponding to the current input data, output the pre-emphasized grayscale voltage corresponding to the current input data; If there is no need to pre-emphasize the grayscale voltage corresponding to the current input data, the grayscale voltage corresponding to the current input data is output.
10. The pre-emphasis method according to claim 9, characterized in that: The determining whether to pre-emphasize the grayscale voltage corresponding to the current input data according to the values of the specified bits of the first data and the second data, the IPE value inputted by the pre-emphasis signal IPE terminal and the grayscale value of the current input data comprises: When the values of the designated bits of the first data and the second data are not equal, and IPE=1, it may be necessary to pre-emphasize the grayscale voltage corresponding to the current input data; When the values of the designated bits of the first data and the second data are equal or IPE=0, there is no need to pre-emphasize the grayscale voltage corresponding to the current input data.
11. The pre-emphasis method according to claim 10, characterized in that: The step of pre-emphasizing the grayscale voltage corresponding to the current input data may include: If the grayscale value corresponding to the current input data belongs to the pre-emphasis grayscale range, outputting the pre-emphasis voltage of the grayscale corresponding to the current input data; If the grayscale value corresponding to the current input data does not belong to the pre-emphasized grayscale range, a voltage of the grayscale corresponding to the current input data is output.
12. A pre-emphasis device, characterized in that: include: A first processing module, used for receiving and storing first data and second data, wherein the second data is the last bit of the first data; A second processing module, configured to determine whether to perform pre-emphasis on the current input data according to the values of the specified number of bits of the first data and the second data, the IPE value input by the pre-emphasis signal IPE terminal, and the grayscale value corresponding to the current input data; The second processing module comprises: If the current input data needs to be pre-emphasized, output a pre-emphasized voltage corresponding to the grayscale of the current input data; If the current input data does not need to be pre-emphasized, a voltage corresponding to the gray scale of the current input data is output.
13. A source driver chip, characterized in that: The method comprises a pre-emphasis circuit as claimed in any one of claims 1 to 8.
14. A display device, characterized in that: Comprising the source driver chip as claimed in claim 13.
15. An electronic device, characterized in that: The invention comprises a processor, a memory and a computer program stored in the memory and executable on the processor, wherein the computer program implements the pre-emphasis method according to any one of claims 9 to 11 when executed by the processor.
Citation Information
Patent Citations
Pre-emphasis circuit, source electrode driving chip and display device
CN214205496U