Interface circuit devices, memory devices and memory systems

Abstract

An interface circuit device, a memory device, and a memory system are provided. The memory system includes: a memory device comprising a plurality of non-volatile memories and an interface circuit connected to each of the plurality of non-volatile memories; and a memory controller connected to the interface circuit and configured to transmit / receive data according to a first clock, wherein the interface circuit is configured to divide the first clock into a second clock according to the number of the plurality of non-volatile memories, and transmit / receive data to / from each of the plurality of non-volatile memories according to the second clock.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0123961, filed with the Korean Intellectual Property Office on October 7, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The exemplary embodiments of the present invention relate to memory devices. For example, at least some exemplary embodiments relate to memory devices including interface circuitry for adaptively adjusting internal operating frequencies and / or methods of operating the memory device. Background Technology

[0004] Semiconductor memory devices can be divided into volatile memory devices, which lose stored data when power is interrupted, and non-volatile memory devices, which retain stored data even when power is interrupted. Volatile memory devices can be read and written at high speeds, but their stored content is lost when the external power is turned off. In contrast, non-volatile memory devices have slower read and write speeds than volatile memory devices, but they retain their content even when the external power is turned off.

[0005] Furthermore, due to their advantages of high capacity, low noise, and low power consumption, non-volatile memory such as flash memory is widely used as storage devices in various fields. In particular, flash-based solid-state drives (SSDs) are used as high-capacity storage devices in personal computers, laptops, workstations, server systems, and so on. General-purpose SSD devices connect to computing systems via Serial AT Attachment (SATA) interfaces or Peripheral Component Interconnect (PCI) fast interfaces. However, with the recent increase in data processed in computing systems, data throughput may exceed the data bandwidth or communication speed of the interface connected to non-volatile memory, leading to data bottlenecks. This phenomenon can degrade the performance of computing systems, and various performance enhancement methods have been developed to address this problem. Summary of the Invention

[0006] The exemplary embodiments of the present invention provide a method and / or apparatus, memory device, memory system, and / or method of operation thereof that can operate stably in an interface circuit at a maximum operating frequency.

[0007] According to an exemplary embodiment of the present invention, a memory system is provided, comprising: a memory controller configured to exchange data according to a first clock, the data including one or more of read data and write data; and a memory device including a plurality of non-volatile memories and an interface circuit connected to the memory controller and the plurality of non-volatile memories, the interface circuit being configured to divide the first clock into a second clock based on the number of the plurality of non-volatile memories, and to exchange data with the plurality of non-volatile memories according to the second clock.

[0008] According to another exemplary embodiment of the present invention, an interface circuit device is provided, comprising: a frequency divider configured to divide a first clock received from a memory controller into a second clock and send the second clock to a first non-volatile memory and a second non-volatile memory; and a serializer including a first buffer register connected to the first non-volatile memory, a second buffer register connected to the second non-volatile memory, and a combiner configured to receive read data from each of the first and second buffer registers based on the first clock and output the read data to the memory controller.

[0009] According to another exemplary embodiment of the present invention, a memory device is provided, comprising: a plurality of non-volatile memories; and a plurality of interface circuits, including: a first interface circuit of a first layer connected to a memory controller, the first interface circuit being configured to exchange data with the memory controller according to a first clock; and a second interface circuit of a second layer connecting the first interface circuit to the plurality of non-volatile memories, the second interface circuit being configured to exchange data with the first interface circuit based on a second clock and to exchange data with the plurality of non-volatile memories based on a third clock, wherein the second clock is generated by dividing the first clock according to the number of the second interface circuits, and the third clock is generated by dividing the second clock according to the number of the plurality of non-volatile memories. Attached Figure Description

[0010] Exemplary embodiments of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 This is a diagram illustrating a data processing system according to an example embodiment of the concept of the present invention;

[0012] Figure 2 This is a diagram illustrating a memory device according to an example embodiment of the concept of the present invention;

[0013] Figure 3 This is a diagram illustrating a memory device for outputting read data according to an exemplary embodiment of the present invention;

[0014] Figure 4 This is a timing diagram illustrating an example embodiment of a memory device according to a concept of the present invention;

[0015] Figure 5 This is a diagram illustrating a memory device for outputting read data according to another example embodiment of the concept of the present invention;

[0016] Figure 6 This is a timing diagram illustrating an example embodiment of a memory device according to a concept of the present invention;

[0017] Figure 7 This is a flowchart illustrating the operation sequence of a memory device according to an exemplary embodiment of the present invention;

[0018] Figure 8 This is a diagram illustrating a memory device with a hierarchical structure according to an exemplary embodiment of the present invention; and

[0019] Figure 9 This is a diagram illustrating a solid-state drive (SSD) system according to an example embodiment of the concept of the present invention. Detailed Implementation

[0020] Exemplary embodiments of the inventive concept will now be described more fully with reference to the accompanying drawings, in which some exemplary embodiments of the inventive concept are illustrated.

[0021] Figure 1 This is a diagram illustrating a memory system 10 according to an exemplary embodiment of the present invention.

[0022] The memory system 10 can be implemented as an electronic device, such as a personal computer (PC), laptop computer, mobile phone, smartphone, tablet PC, personal digital assistant (PDA), enterprise digital assistant (EDA), digital still camera, digital video camera, audio device, portable multimedia player (PMP), personal navigation device (PND), MP3 player, handheld game console, or e-reader. Furthermore, the memory system 10 can be implemented as an electronic device such as a wearable device, such as a wristwatch or head-mounted display (HMD).

[0023] refer to Figure 1The memory system 10 may include a host 100 and a storage device 400. The storage device 400 may include a memory controller 200 and a memory device 300. The memory device 300 may include interface circuitry 310 and a plurality of non-volatile memories (e.g., first non-volatile memories 320_1 to Nth non-volatile memories 320_N (NVM#1 to NVM#N)).

[0024] According to various example embodiments, host 100 can send a data access request (REQ) to storage device 400. For example, host 100 can provide a data write request or a data read request to storage device 400, and storage device 400 can write data to or read data from the first non-volatile memory 320_1 to the Nth non-volatile memory 320_N according to the access request from host 100, and can also send data to host 100. Furthermore, according to a data erase request from host 100, storage device 400 can perform an erase operation on data in a region indicated by host 100.

[0025] According to various example embodiments, host 100 can communicate with storage device 400 through various interfaces. Host 100 may include various types of devices capable of performing data access on storage device 400. For example, host 100 may be an application processor (AP) that communicates with storage device 400 based on flash memory.

[0026] According to various example embodiments, storage device 400 may be internal memory embedded in an electronic device. For example, storage device 400 may be an embedded universal flash storage (UFS) memory device, an embedded multi-media card (eMMC), or a solid-state drive (SSD). Storage device 400 may be embedded in the same substrate as host 100. In some example embodiments, storage device 400 may be external memory removable from the electronic device. For example, storage device 400 may include at least one of a UFS memory card, a compact flash (CF) card, a secure digital (SD) card, a micro-secure digital (SD) card, a mini-secure digital (SD) card, an extreme digital (xD) card, and a Memory Stick.

[0027] According to various example embodiments, storage device 400 may include memory controller 200 and memory device 300, and memory device 300 may include interface circuitry 310 and first non-volatile memory 320_1 to Nth non-volatile memory 320_N.

[0028] According to various example embodiments, the memory controller 200 may write write data to the first non-volatile memory 320_1 to the Nth non-volatile memory 320_N in response to a write request received from the host 100, or may receive read data from the first non-volatile memory 320_1 to the Nth non-volatile memory 320_N in response to a read request received from the host 100.

[0029] According to various example embodiments, interface circuit 310 can connect the first non-volatile memory 320_1 to the Nth non-volatile memory 320_N to memory controller 200. For example, interface circuit 310 can temporarily store data signals output from the first non-volatile memory 320_1 to the Nth non-volatile memory 320_N, and can output these data signals as read data through memory controller 200. That is, interface circuit 310 can be configured to buffer read data output to host 100 to cover the difference between the operating speed between interface circuit 310 and host 100 and the operating speed between interface circuit 310 and the first non-volatile memory 320_1 to the Nth non-volatile memory 320_N. Based on this buffering, interface circuit 310 can reduce the load between the first non-volatile memory 320_1 to the Nth non-volatile memory 320_N and memory controller 200. Interface circuit 310 can be referred to as a buffer chip or buffer circuit.

[0030] According to various example embodiments, the memory controller 200 may include a training control unit 210. The training control unit 210 may perform training on the memory device 300, and this training may be an operation to determine a delayed clock value for continuous operation frequency switching of the interface circuitry 310. For example, the training control unit 210 may control a clock signal including a clock cycle and skew information to be obtained based on a response signal, wherein the clock signal is to be applied to the first non-volatile memory 320_1 to the Nth non-volatile memory 320_N via the interface circuitry 310. The training control unit 210 will now be described in detail.

[0031] Each of the first non-volatile memory 320_1 to the Nth non-volatile memory 320_N may include a memory cell array comprising a plurality of memory cells. For example, the plurality of memory cells may be flash memory cells. The following exemplary embodiments of the inventive concept will be described assuming that the plurality of memory cells are NAND flash memory cells. However, the inventive concept is not limited thereto. According to various exemplary embodiments, the plurality of memory cells may be various types of non-volatile memory cells. In exemplary embodiments, the plurality of memory cells may be resistive memory cells, such as resistive random-access memory (RRAM) cells, phase-change random-access memory (PRAM) cells, or magnetoresistive random-access memory (MRAM) cells. In exemplary embodiments, the plurality of memory cells may be ferroelectric random-access memory (FRAM) cells or spin-transfer torque random-access memory (STT-RAM) cells. Each of the first non-volatile memory 320_1 to the Nth non-volatile memory 320_N can have a three-dimensional (3D) array structure. For example, a three-dimensional array structure can be applied to a charge trap flash (CTF) including an insulating film as a charge storage layer and a flash memory device including a conductive floating gate as a charge storage layer. In an example embodiment, each of the first non-volatile memory 320_1 to the Nth non-volatile memory 320_N can be based on a vertical stacking structure. For example, each of the first non-volatile memory 320_1 to the Nth non-volatile memory 320_N can correspond to a stacking structure including 100 layers or more. When each of the first non-volatile memory 320_1 to the Nth non-volatile memory 320_N is based on a vertical stacking structure, each of the first non-volatile memory 320_1 to the Nth non-volatile memory 320_N can be referred to as a vertical NAND (V-NAND) flash memory. In another embodiment, each of the first non-volatile memory 320_1 to the Nth non-volatile memory 320_N may have a cell-on-peri or cell-over-peri (CoP) structure.

[0032] Figure 2This is a diagram illustrating a memory device according to an example embodiment of the concept of the present invention.

[0033] refer to Figure 2 The memory device 300 may include interface circuitry 310 and first non-volatile memories 320_1 to Nth non-volatile memories 320_N. (References omitted) Figure 1 The same description was made.

[0034] According to various example embodiments, interface circuitry 310 may include deserializer 330 and serializer 340.

[0035] The deserializer 330 can divide the data received from the memory controller 200 according to the input clock signal. The deserializer 330 can receive the transmitted write data according to the external input clock signal EXT.input CLK. The deserializer 330 can divide the write data and write the write data separately to N non-volatile memories (i.e., the first non-volatile memory 320_1 to the Nth non-volatile memory 320_N). In this case, the operation frequency of writing data to each of the non-volatile memories 320_1 to 320_N can be reduced to the frequency of the external input clock signal EXT.input CLK multiplied by 1 / N. In the example embodiment, when the first non-volatile memory 320_1 to the Nth non-volatile memory 320_N is NAND flash memory, N is one of the following: (i) the number of NAND flash memories, or (ii) the multiple of 8 when the number of input / output structures in a single NAND flash memory is a multiple of 8. For example, suppose the deserializer 330 divides the write data into a first non-volatile memory 320_1 and a second non-volatile memory 320_2. The first non-volatile memory 320_1 and the second non-volatile memory 320_2 can receive the write data based on a 500MHz clock (which is half the external input clock signal EXT.input CLK). In this case, the write data can be obtained by adding the data received by the first non-volatile memory 320_1 and the data received by the second non-volatile memory 320_2 together. For example, the data received by the first non-volatile memory 320_1 may include packets corresponding to odd-numbered clocks in the write data, and the data received by the second non-volatile memory 320_2 may include packets corresponding to even-numbered clocks in the write data.

[0036] The serializer 340 can combine data received from the first non-volatile memory 320_1 to the Nth non-volatile memory 320_N according to the output clock signal. The serializer 340 can also receive data from the first non-volatile memory 320_1 to the Nth non-volatile memory 320_N according to an internal clock signal. In this case, the internal clock signal can be a clock signal divided by the deserializer 330 as described above. For example, since the clocks of the signals input to and output from the interface circuit 310 are the same, the frequencies of the external input clock signal EXT.input CLK input to the deserializer 330 and the external output clock signal EXT.output CLK to be output can be the same. Therefore, the first non-volatile memory 320_1 to the Nth non-volatile memory 320_N can send the read divided data to the serializer 340 according to the internal output clock signal output CLK (which is the external output clock signal EXT.output CLK to be output multiplied by 1 / N). For example, assuming that the deserializer 330 divides the data into the first non-volatile memory 320_1 and the second non-volatile memory 320_2, the first non-volatile memory 320_1 and the second non-volatile memory 320_2 can send the divided data to the serializer 340, and can output the data as read data.

[0037] Based on the above example embodiments, it was found that the frequency of the clock signal between the interface circuit 310 and the memory controller 200 is different from the frequency of the clock signal between the interface circuit 310 and the first non-volatile memory 320_1 to the Nth non-volatile memory 320_N. That is, it was found that the memory device 300 can perform operating frequency conversion using the interface circuit 310. When the first non-volatile memory 320_1 to the Nth non-volatile memory 320_N sends read divided data (Read Div Data) to the serializer 340, and the serializer 340 combines the read divided data (Read Div Data) to generate and output read data, the timing of the serializer 340 receiving the read divided data (Read Div Data) may be important. However, since each of the first non-volatile memories 320_1 to the Nth non-volatile memories 320_N independently transmits pre-stored frequency-divided data in response to a read request signal, and the time taken for the first non-volatile memories 320_1 to the Nth non-volatile memories 320_N to transmit data may not be exactly the same, a synchronization method for this time may be required, which will refer to Figure 3 and Figure 4 Please describe this in detail.

[0038] Figure 3This is a diagram illustrating a memory device for outputting read data according to an exemplary embodiment of the concept of the present invention. The same description as above will be omitted.

[0039] The following will be described assuming that the plurality of non-volatile memories include a first non-volatile memory 320_1 and a second non-volatile memory 320_2. However, the inventive concept is not limited thereto.

[0040] refer to Figure 3 The memory device 300 can output read data. The memory controller 200 can, in response to a data read request from the host 100, send an external output clock signal EXT.output CLK to the interface circuit 310. Specifically, the external output clock signal EXT.output CLK can be input to the frequency divider 350 and the time-to-digital converter (TDC) 360 in the interface circuit 310.

[0041] Frequency divider 350 can correspond to Figure 2 The deserializer 330. That is, the frequency divider 350 can divide the external output clock signal EXT.output CLK and send the internal output clock signal output CLK to the first non-volatile memory 320_1 and the second non-volatile memory 320_2. The TDC 360 can perform a toggle operation in response to the external output clock signal EXT.output CLK.

[0042] In response to the internal output clock signal output CLK, the first non-volatile memory 320_1 and the second non-volatile memory 320_2 can output the stored data and the data strobe signal.

[0043] In response to the internal output clock signal output CLK, the first non-volatile memory 320_1 can send a first data signal DQ_1 and a first data strobe signal DQS_1 to the serializer 340. Furthermore, to identify the time difference between the transmission timings of the non-volatile memories, the first non-volatile memory 320_1 can send the first data strobe signal DQS_1 to the TDC 360. In response to the internal output clock signal output CLK, the second non-volatile memory 320_2 can send a second data signal DQ_2 and a second data strobe signal DQS_2 to the serializer 340. Furthermore, to identify the time difference between the transmission timings of the non-volatile memories, the second non-volatile memory 320_2 can send the second data strobe signal DQS_2 to the TDC 360.

[0044] The TDC 360 can receive a first data strobe signal DQS_1 and a second data strobe signal DQS_2, and can generate offset information based on the first data strobe signal DQS_1 and the second data strobe signal DQS_2. For example, it can be assumed that the TDC 360 receives the first data strobe signal DQS_1 at a first time and receives the second data strobe signal DQS_2 at a second time, which is later than the first time. In this case, the TDC 360 can calculate the first time, the second time, and the clock between the first time and the second time.

[0045] As described above, since the toggle operation begins at the time the external output clock signal EXT.output CLK is received, the TDC 360 can identify the first time based on the number of toggles at the time the first data strobe signal DQS_1 is received. In other words, the first time can be an inherent delay parameter used by the first non-volatile memory 320_1 to receive a read request and output data in response to that read request.

[0046] Similarly, TDC 360 can identify the second time based on the number of toggles until the second data strobe signal DQS_2 is received. Therefore, the second time can be an inherent delay parameter used by the second non-volatile memory 320_2 to receive a read request and output the second data signal DQ_2 in response to the read request.

[0047] Furthermore, the TDC 360 can calculate the difference in the number of flips between the first and second times, and can obtain offset information. The term "offset information" can refer to the difference in time taken for output data between non-volatile memories.

[0048] According to various example embodiments, the serializer 340 may include a plurality of buffer registers and a combiner 380. The plurality of buffer registers may each correspond to a plurality of non-volatile memories. Therefore, the following will be described assuming that the plurality of buffer registers includes a first buffer register 370_1 and a second buffer register 370_2. However, the inventive concept is not limited thereto, and according to various example embodiments, the plurality of buffer registers may include more than two buffer registers.

[0049] The first buffer register 370_1 (buffer register #1) and the second buffer register 370_2 (buffer register #2) can correspond to the first non-volatile memory 320_1 and the second non-volatile memory 320_2, respectively. For example, the first buffer register 370_1 can receive the first data signal DQ_1 from the first non-volatile memory 320_1 and can temporarily store the first data signal DQ_1. The second buffer register 370_2 can receive the second data signal DQ_2 from the second non-volatile memory 320_2 and can temporarily store the second data signal DQ_2.

[0050] According to various example embodiments, based on control signals, buffer registers can output temporarily stored data at a time delayed by a desired (or alternatively, predetermined) time, or they can simultaneously receive and output data. For example, when no delay clock is set for data output, first buffer register 370_1 and second buffer register 370_2 can receive first data signal DQ_1 and second data signal DQ_2 respectively, and can directly output first data signal DQ_1 and second data signal DQ_2 to combiner 380. In this case, because first data signal DQ_1 is output earlier than second data signal DQ_2 at the first time, combiner 380 may output read data by using only first data signal DQ_1, at a clock time corresponding to the offset information. However, because first data signal DQ_1 includes data packets corresponding to odd-numbered clock signals in the written data, the output read data may correspond to inappropriate data.

[0051] Therefore, in some example embodiments, to prevent (or alternatively, to prevent) the output of inappropriate read data, the buffer registers can delay the data output by a desired (or alternatively, predetermined) clock cycle. Alternatively, in other example embodiments, the first buffer register 370_1 and the second buffer register 370_2 can output the first data signal DQ_1 and the second data signal DQ_2 to the combiner 380 at a time delayed by a delayed clock cycle, respectively. The delayed clock can correspond to the minimum clock cycle that ensures the simultaneous output of the first data signal DQ_1 and the second data signal DQ_2 by compensating for the clock difference between the first and second times. For example, the delayed clock can be the same as the second time at which the second data signal DQ_2 (which is the later-output data signal) is output, and can also include a margin clock that takes into account the size of the buffer memory of each of the first buffer register 370_1 and the second buffer register 370_2. In example embodiments, the length of the margin clock can be the reciprocal of the buffer memory size of the first buffer register 370_1 and the second buffer register 370_2. However, the inventive concept is not limited thereto.

[0052] Figure 4 This is a timing diagram illustrating a memory device according to an example embodiment of the concept of the present invention. The same description as above will be omitted.

[0053] refer to Figure 4 The external output clock signal EXT.output CLK can be toggled. The frequency of the external output clock signal EXT.output CLK can correspond to the maximum operating frequency. For example, the maximum operating frequency can be 1 GHz. However, the maximum operating frequency is not limited to 1 GHz, and according to various example embodiments, the maximum operating frequency can include high frequencies exceeding 1 GHz.

[0054] The external output clock signal EXT.output CLK can be generated by... Figure 3 350 or frequency divider Figure 2 The deserializer 330 sends the data to the first non-volatile memory 320_1 and the second non-volatile memory 320_2. For ease of explanation, it is assumed that there is no delay time or clock when the external output clock signal EXT.output CLK is divided by the frequency divider 350 or the deserializer 330. Therefore, when the external output clock signal EXT.output CLK toggles, the internal output clock signal output@NVM#1 sent to the first non-volatile memory 320_1 and the internal output clock signal output@NVM#2 sent to the second non-volatile memory 320_2 can be toggled simultaneously.

[0055] refer to Figure 3 The TDC 360 can receive the external output clock signal EXT.output CLK and can initiate a toggle operation in response to it. Because the TDC 360 performs the trigger operation synchronously with the rising edge, the period for the TDC 360 toggle operation can be twice the period of the external output clock signal EXT.output CLK, and can be the same as the period of the internal output clock signal output@NVM#1 or output@NVM#2.

[0056] The first non-volatile memory 320_1 can receive an internal output clock signal output@NVM#1, and in response to the internal output clock signal output@NVM#1, can send a first data signal DQ_1 to the serializer 340 or the first buffer register 370_1 of the serializer 340. In this case, a first data strobe signal DQS_1 is also generated and can be sent to the TDC 360.

[0057] TDC 360 can receive the first data strobe signal DQS_1 from the first non-volatile memory 320_1 and can identify the first time tDQ_Delay#1. TDC 360 can determine that the time taken for the first non-volatile memory 320_1 to output data is 3 clock cycles. In addition, TDC 360 can determine that the first data signal DQ_1 is temporarily stored in the first buffer register 370_1.

[0058] The second non-volatile memory 320_2 can receive an internal output clock signal output@NVM#2, and in response to the internal output clock signal output@NVM#2, can send a second data signal DQ_2 to the serializer 340 or the second buffer register 370_2 of the serializer 340. Similar to the first non-volatile memory 320_1, a second data strobe signal DQS_2 is also generated and can be sent to the TDC 360.

[0059] TDC 360 can receive the second data strobe signal DQS_2 from the second non-volatile memory 320_2 and can identify the second time tDQ_Delay#2. TDC 360 can determine that the time taken for the second non-volatile memory 320_2 to output data is 6 clock cycles, and the second data signal DQ_2 is temporarily stored in the second buffer register 370_2.

[0060] TDC 360 can generate offset information. Since the second time tDQ_Delay#2 corresponds to 6 clock cycles and the first time tDQ_Delay#1 corresponds to 3 clock cycles, the offset information can indicate 3 clock cycles, and therefore can indicate that the second non-volatile memory 320_2 outputs data 3 clock cycles later than the first non-volatile memory 320_1.

[0061] According to various example embodiments, when no delay clock is set for the first buffer register 370_1 and the second buffer register 370_2 (data is read without delay), inappropriate read data is found to be output. Starting after 3 clock cycles, the first buffer register 370_1 can output stored data at the frequency of the external output clock signal EXT.output CLK. Because the second buffer register 370_2 can output the second data signal DQ_2 starting after 6 clock cycles, there may be no data stored in the second buffer register 370_2. Figure 4 In the process, it was found that the data read without setting a delay clock is [0, null (empty), 2, null, 4, null, 6, 1, 8, 3, 10, 5, ...].

[0062] According to various example embodiments, when a delayed clock is set to the first buffer register 370_1 and the second buffer register 370_2 (data is read with a delay), normal read data is found to be output. The first buffer register 370_1 and the second buffer register 370_2 can output and temporarily store the first data signal DQ_1 and the second data signal DQ_2 respectively, starting from the elapsed time of the delayed clock. Because the clock delay time by each buffer register is the same, it is guaranteed that the second data signal DQ_2 will be temporarily stored in the second buffer register 370_2 regardless of how late the data output from the second non-volatile memory 320_2 appears. (Reference) Figure 4 When a delay clock is set, the read data is found to be [0,1,2,3,4,5,6,7,…].

[0063] According to various example embodiments, the delay clock may also include a delay time corresponding to the tolerance clock. The operation frequency of data input from the non-volatile memory is only half the operation frequency of data output from the buffer register to the combiner 380. Therefore, when the size of the buffer register is large enough, no problem arises; however, when the size of the buffer register is not large enough, it may be preferable to provide an additional tolerance clock corresponding to the desired (or alternatively, predetermined) number of clocks in order to prevent (or alternatively, prevent) the buffer register from being empty.

[0064] Figure 5 This is a diagram illustrating a memory device for outputting read data according to another exemplary embodiment of the concept of the present invention. (The references are omitted.) Figure 3 The same description was made.

[0065] refer to Figure 5 The interface circuit 310 may not include the TDC 360. Alternatively, the memory controller 200 may not include the training control unit 210. In this case, since offset data may not be generated, synchronization may not depend on a reference, etc. Figure 3 and Figure 4 The aforementioned delay clock based on offset information. However, in some example embodiments, normal read data can be output at the maximum operating frequency even when the memory controller 200 does not include the training control unit 210 or the interface circuit 310 does not include the TDC 360.

[0066] According to various example embodiments, the memory controller 200 can provide a maximum delay value tDQSRE to the interface circuit 310 or the first non-volatile memory 320_1 and the second non-volatile memory 320_2, where tDQSRE is a timing parameter indicating the data access time of the memory. The maximum delay value, which must be satisfied by the first non-volatile memory 320_1 and the second non-volatile memory 320_2, can refer to the maximum delay clock time that guarantees data output. That is, after the maximum delay time has elapsed, the first non-volatile memory 320_1 and the second non-volatile memory 320_2 must output the first data signal DQ_1 and the second data signal DQ_2, respectively.

[0067] According to the example embodiment, the memory controller 200 can send the maximum delay value tDQSRE to the buffer register. That is, in response to the maximum delay value tDQSRE, until the clock corresponding to the maximum delay value has elapsed, the first buffer register 370_1 and the second buffer register 370_2 can temporarily store the data received from the first non-volatile memory 320_1 and the second non-volatile memory 320_2, and can wait to output the data as read data through the combiner 380.

[0068] According to another example embodiment, the memory controller 200 can send the maximum delay value tDQSRE to the non-volatile memory. That is, from the time the internal output clock signal output CLK is received, the first non-volatile memory 320_1 and the second non-volatile memory 320_2 can wait until the clock corresponding to the maximum delay value tDQSRE has elapsed before outputting the data signal or data strobe signal.

[0069] In other words, when the clock corresponding to the maximum delay value used to guarantee the output data of the non-volatile memory is delayed, it is possible to prevent the storage and output of only one of the data signals in the first buffer register 370_1 and the second buffer register 370_2. Therefore, the TDC 360 or the training control unit 210 can be omitted.

[0070] Figure 6 This is a timing diagram illustrating an example embodiment of a memory device according to a concept of the present invention. (Note: The last part, "omitted," appears to be a typo and can be left as is.) Figure 4 The same description was made.

[0071] refer to Figure 6 Since the interface circuit 310 does not include TDC 360, no waveform related to TDC 360 was found.

[0072] Because TDC 360 is not provided, the memory controller 200 may not count the clock tDQ_Delay#1 required for the output data of the first non-volatile memory 320_1 or the clock tDQ_Delay#2 required for the output data of the second non-volatile memory 320_2.

[0073] According to the example embodiment, after the maximum delay value tDQSRE has elapsed, the memory controller 200 may request the first non-volatile memory 320_1 or the second non-volatile memory 320_2 to output a data signal and a data strobe signal.

[0074] According to another embodiment, the memory controller 200 can send a maximum delay value tDQSRE to a first buffer register 370_1 and a second buffer register 370_2, and can request the first buffer register 370_1 and the second buffer register 370_2 to temporarily store a first data signal DQ_1 or a second data signal DQ_2, and wait until the maximum delay value tDQSRE has elapsed. After the maximum delay value tDQSRE has elapsed, the first buffer register 370_1 and the second buffer register 370_2 can output data to the combiner 380. During the time elapsed by the maximum delay value tDQSRE, data is stored in all buffer registers, and therefore normal read data can be output.

[0075] Figure 7 This is a flowchart illustrating the operational sequence of a memory device according to an exemplary embodiment of the present invention.

[0076] refer to Figure 7 In operation S110, the memory device 300 can receive training control signals. These training control signals can be generated and transmitted by the training control unit 210 of the memory controller 200. That is, when the training control unit 210 generates the training control signals, the memory controller 200 can transmit a clock signal, including a single clock signal, along with the training control signals to the interface circuit 310.

[0077] In operation S120, memory device 300 can read the TDC output value. The clock signal is not a signal used for the process of writing or reading actual data, but rather a signal used to obtain the clock response waveforms of the first non-volatile memory 320_1 and the second non-volatile memory 320_2, and to obtain the first time required for the first non-volatile memory 320_1 to output data, the second time required for the second non-volatile memory 320_2 to output data, and offset information between the first and second times. Therefore, when the clock signal is applied, memory device 300 can obtain the values ​​of the first time, the second time, and the offset information as the TDC output value of TDC 360.

[0078] In operation S130, memory device 300 can set the delay value of interface circuit 310 based on the TDC output value of TDC 360. Memory device 300 can further set the delay clock value by using a time delay tolerance clock value from a second time. The tolerance clock value can be variably set based on the memory size of the first buffer register 370_1 and the second buffer register 370_2.

[0079] In operation S140, memory device 300 may determine whether to repeat training at a desired (or alternatively, at a predefined) time interval. According to various example embodiments, training using a clock signal may be performed at a desired (or alternatively, at a predefined) time interval, or may be performed only once at memory-driven time.

[0080] When the memory device 300 is continuously driven, the surrounding environment (such as internal temperature or voltage) may differ from the initial stage of operation. In this case, the time for the first non-volatile memory 320_1 to output data and the time for the second non-volatile memory 320_2 to output data may vary depending on changes in internal temperature or voltage. Therefore, the memory device 300 can perform training using a clock signal at desired (or alternatively, in a predefined) time interval, continuously update the first time, second time, and offset information, and variably set the delay clock value based on the updated information. Although training is performed at a predefined time interval in the above exemplary embodiments, the inventive concept is not limited thereto. In another example embodiment, when the internal temperature of the memory device 300 exceeds a set (or alternatively, preset) critical temperature, the time required for output data may change, so the memory device 300 can perform updates by performing training using a clock signal.

[0081] Figure 8 This is a diagram illustrating a memory device with a layered structure according to an example embodiment of the concept of the present invention.

[0082] refer to Figure 8 The memory device 300 may include interface circuitry with a hierarchical structure. The first interface circuitry 310_1 of layer 1, and the second and third interface circuitry 310_21 of layer 2 will be discussed in detail below. However, the inventive concept is not limited thereto, and the number of layers and the number of interface circuits included in each layer can be modified in various ways.

[0083] According to various example embodiments, the first interface circuit 310_1 can be located in layer 1. As the top layer, layer 1 can directly receive the external clock signal EXT.CLK and the data signal DATA from the memory controller 200. The first interface circuit 310_1 can divide the external clock signal EXT.CLK received from the memory controller 200 into a first internal clock signal INT.CLK#1, and can send the first internal clock signal INT.CLK#1 to the second interface circuit 310_21 and the third interface circuit 310_22 located in layer 2. Because the external clock signal EXT.CLK is divided into two first internal clock signals INT.CLK#1, the frequency of the first internal clock signal INT.CLK#1 can be the frequency of the external clock signal EXT.CLK multiplied by 1 / 2.

[0084] According to various example embodiments, the second interface circuit 310_21 and the third interface circuit 310_22 may be located in layer 2. Layer 2, as an intermediate layer, can perform signaling between the upper and lower layers. The second interface circuit 310_21 may be connected to N non-volatile memories 320_1 to 320_N (NVM#1 to NVM#N), and the third interface circuit 310_22 may be connected to M non-volatile memories 320_1 to 320_M (NVM#1 to NVM#M). The second interface circuit 310_21 may divide the first internal clock signal INT.CLK#1 to generate a divided clock signal, and send the divided clock signal to the first non-volatile memory 320_1 to the Nth non-volatile memory 320_N in layer 3. For example, the second interface circuit 310_21 can divide the received first internal clock signal INT.CLK#1 into N second internal clock signals INT.CLK#2, and the frequency of these N second internal clock signals INT.CLK#2 can be the frequency of the first internal clock signal INT.CLK#1 multiplied by 1 / N. For example, assuming that the frequency of the external clock signal EXT.CLK is the maximum operating frequency, and that the maximum operating frequency is 1GHz, then the operating frequency sensed by each non-volatile memory can simply be 1GHz multiplied by 1 / 2N.

[0085] According to various example embodiments, the memory controller 200 can control the opening / closing of the interface circuitry between Layer 1 and Layer 2 using training switching signals. For example, the training switching signals may be as shown in Table 1.

[0086] [Table 1]

[0087] Training switching signal Layer 1 Layer 2 11 Frequency division Frequency division 10 Frequency division Bypassing 01 Bypass Frequency division 00 Bypass Bypass

[0088] Referring to Table 1, although the training switching signal is a 2-bit signal, this is only an example. The number of bits allocated to the training switching signal can increase as the number of layers increases.

[0089] Based on the bits indicated by the training switching signal, the frequency changes for each layer can be shown in Table 2. (Where N and M are limited to 2).

[0090] [Table 2]

[0091] Training signal bit External – Layer 1 Layer 1–Layer 2 Layer 2–Layer 3 11 1 0.5 0.25 10 1 0.5 0.5 01 1 1 0.5 00 1 1 1

[0092] In other words, when the input operation frequency is low, the memory controller 200 can set the training switching signal to "00" to avoid reducing the frequency and thus avoid wasting extra processing time. Furthermore, when the input operation frequency is closer to the maximum operating frequency, the memory controller 200 can adaptively control the training switching signal to change to "01" or "10", or set the training switching signal to "11", to minimize the operating frequency sensed by the non-volatile memory.

[0093] Figure 9 This is a diagram illustrating a solid-state drive (SSD) system according to an example embodiment of the concept of the present invention.

[0094] refer to Figure 9 The SSD system 900 may include a host 1000 and an SSD 1100. The SSD 1100 can send / receive signals to / from the host 1000 via a signal connector and can receive power via a power connector. The SSD 1100 may include an SSD controller 1110, an auxiliary power supply 1120, and multiple memory devices 1130, 1140, and 1150. The multiple memory devices 1130, 1140, and 1150 may be vertically stacked NAND flash memory devices. In this case, at least one of the multiple memory devices 1130, 1140, and 1150 can be connected via a reference... Figures 1 to 8 The aforementioned delay clock value operates with the host 1000 at the maximum operating frequency, and transmits / receives data between the SSD controller 1110 and the plurality of memory devices 1130, 1140 and 1150 at a lower operating frequency.

[0095] The memory controller 200 and interface circuitry 310, along with their sub-components (including the training control unit 210, deserializer 330, and serializer 340), may include processing circuitry, including but not limited to a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a programmable logic unit, a microprocessor, and an application-specific integrated circuit (ASIC). Furthermore, buffer registers 370_1 and 370_2 may include volatile memory, such as dynamic random access memory (DRAM) or static RAM (SRAM). The processing circuitry can execute instructions that configure the processing circuitry to adaptively adjust its internal operating frequency.

[0096] While the inventive concept has been specifically shown and described with reference to some exemplary embodiments thereof, it should be understood that various changes in form and detail may be made without departing from the spirit and scope of the appended claims.

Claims

1. A memory system, comprising: A memory controller is configured to exchange data with an interface circuit according to a first clock, the data including one or more read data and write data; and A memory device includes a plurality of non-volatile memories and an interface circuit connected to the memory controller and the plurality of non-volatile memories, the interface circuit being configured to, The first clock is divided into a second clock based on the number of the plurality of non-volatile memories. According to the second clock, the data is exchanged with the plurality of non-volatile memories. Receive data strobe signals from the plurality of non-volatile memories, and Offsets are detected based on the time difference between receiving the data strobe signals from the plurality of non-volatile memories. The interface circuit includes multiple buffer registers. The interface circuit is also configured to variably determine tolerances based on the memory size of the plurality of buffer registers.

2. The memory system according to claim 1, wherein, The interface circuit includes: A deserializer is configured to receive the write data from the memory controller, divide a first clock into a second clock based on the number of the plurality of non-volatile memories, divide the write data to generate divided write data, and send the divided write data to the corresponding non-volatile memories among the plurality of non-volatile memories based on the second clock; and A serializer is configured to receive partitioned read data from the plurality of non-volatile memories based on a second clock, buffer the partitioned read data, generate read data based on the partitioned read data, and send the read data to the memory controller based on a first clock, wherein... The interface circuitry is configured to increase the operating frequency of the memory system by dividing the write data into the divided write data via the deserializer, and to reduce the load between the memory controller and the plurality of nonvolatile memories by buffering the divided read data output from each of the plurality of nonvolatile memories in the serializer.

3. The memory system according to claim 2, wherein, The serializer includes: The plurality of buffer registers are connected to corresponding non-volatile memories in the plurality of non-volatile memories, and the plurality of buffer registers are configured to buffer the partitioned read data received from the corresponding non-volatile memories in the plurality of non-volatile memories; and A combiner is configured to generate the read data from the divided read data.

4. The memory system according to claim 3, wherein, The interface circuitry is also configured to determine the delay time associated with the partitioned read data based on the offset, such that the partitioned read data buffered in different buffer registers among the plurality of buffer registers correspond to each other.

5. The memory system according to claim 4, wherein, The interface circuitry is configured to determine the delay time based on the tolerance and the maximum delay among the plurality of non-volatile memories.

6. The memory system according to claim 3, wherein, The interface circuitry is configured to determine the delay time associated with the partitioned read data based on a set maximum delay, such that the partitioned read data buffered in different buffer registers among the plurality of buffer registers correspond to each other.

7. The memory system according to claim 6, wherein, The maximum latency set corresponds to the data access time tDQSRE parameter.

8. The memory system according to claim 1, in, The plurality of non-volatile memories are one of NAND flash memory, vertical NAND flash memory, vertical NAND flash memory based on peripheral cell CoP structure, and vertical NAND flash memory having a stacked structure including 100 or more layers. Wherein, the frequency of the first clock corresponds to the maximum operating frequency of the plurality of non-volatile memories, and the maximum operating frequency is greater than or equal to 1 GHz, and Wherein, the frequency of the second clock is 1 / N of the frequency of the first clock, and N is one of the following: (i) the number of NAND flash memory, or (ii) the multiple of 8 when the number of input / output structures in a single NAND flash memory is a multiple of 8.

9. An interface circuit device, comprising: The frequency divider is configured to divide a first clock received from the memory controller into a second clock and send the second clock to a first non-volatile memory and a second non-volatile memory. Serializer, the serializer comprising, The first buffer register is connected to the first non-volatile memory. The second buffer register connected to the second non-volatile memory, and The combiner is configured to receive read data from each of the first buffer register and the second buffer register based on the first clock, and to output the read data to the memory controller; and The time-to-digital converter (TDC) is configured to delay the first buffer register and the second buffer register by means of the following steps: The toggle operation begins when the first clock is received from the memory controller. According to the second clock, the first data strobe signal output from the first non-volatile memory is received, and According to the second clock, in response to receiving a second data strobe signal output from the second non-volatile memory, the toggle operation is stopped to identify that both the first buffer register and the second buffer register store data, wherein... The interface circuitry is configured to reduce the load between the memory controller and the first non-volatile memory and the second non-volatile memory by buffering data output from the first non-volatile memory and the second non-volatile memory in the serializer.

10. The interface circuit device according to claim 9, wherein, The interface circuitry is configured to increase the latency tolerance based on the memory size of the first buffer register and the second buffer register.

11. The interface circuit device according to claim 10, wherein, The length of the tolerance is the reciprocal of the memory size of the first buffer register and the second buffer register.

12. The interface circuit device according to claim 9, wherein, The frequency of the second clock is half the frequency of the first clock.

13. The interface circuit device according to claim 9, wherein, The interface circuitry is configured to determine the delay time associated with the output data of the first buffer register and the second buffer register based on a set maximum delay.

14. The interface circuit device according to claim 13, wherein, The maximum latency set corresponds to the data access time tDQSRE parameter.

15. The interface circuit device according to claim 9, in, The first non-volatile memory and the second non-volatile memory are one of NAND flash memory, vertical NAND flash memory, vertical NAND flash memory based on peripheral cell CoP structure, and vertical NAND flash memory having a stacked structure including 100 or more layers. The frequency of the first clock corresponds to the maximum operating frequency of the first non-volatile memory and the second non-volatile memory, and the maximum operating frequency is greater than or equal to 1 GHz.

Images