Method for manufacturing semiconductor element

Abstract

The present invention provides a method for manufacturing a semiconductor element, which can improve the yield rate. The method for manufacturing a semiconductor element comprises: a process of preparing a wafer (10), wherein the wafer includes a first region (11) and a second region (12) on an upper surface (15), wherein the second region is arranged around the first region and is located at a lower position than the first region; and a process of forming a semiconductor layer (20) composed of a nitride semiconductor on the upper surface of the wafer. When viewed from above, the first region has an extended protrusion (11b) at an end in a first direction, wherein the first direction is a direction passing through the center of the wafer and parallel to the m-axis of the semiconductor layer, and the extended protrusion extends in a direction from the center of the wafer toward the end edge of the wafer. The extended protrusion has a first side surface (12c) parallel to a third direction, wherein the third direction is a direction inclined at an angle of 5° or more and 55° or less relative to a second direction parallel to a first tangent line to the end edge of the wafer in the first direction.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor element. Background Art

[0002] As a method for manufacturing semiconductor devices such as light-emitting diodes (LEDs), Patent Document 1 discloses a method in which a semiconductor layer is grown on a wafer serving as a growth substrate, such as a sapphire substrate, and then bonded to a support substrate. In this method for manufacturing semiconductor devices, cracks may sometimes form in the semiconductor layer during growth. Furthermore, the flatness of the upper surface of the semiconductor layer may be impaired, resulting in a reduction in the yield of the semiconductor device manufacturing method.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: International Publication No. 2011 / 161975 Summary of the Invention

[0006] Technical problem to be solved by the invention

[0007] One embodiment of the present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a method for manufacturing a semiconductor element that can reduce the influence of cracks generated in a semiconductor layer and improve the yield by flattening the upper surface of the semiconductor layer.

[0008] Means for solving technical problems

[0009] A method for manufacturing a semiconductor device according to one embodiment of the present invention comprises: preparing a wafer having a first region and a second region on its top surface, the second region being disposed around the first region and located lower than the first region; and forming a semiconductor layer composed of a nitride semiconductor on the top surface of the wafer. When viewed from above, the first region has an extended protrusion at its end in a first direction, the first direction being a direction passing through the center of the wafer and parallel to the m-axis of the semiconductor layer, the extended protrusion extending in a direction from the center of the wafer toward the edge of the wafer. The extended protrusion has a first side surface parallel to a third direction, the third direction being a direction inclined at an angle of not less than 5° and not more than 55° relative to a second direction parallel to a tangent line to the edge of the wafer in the first direction.

[0010] A method for manufacturing a semiconductor device according to one embodiment of the present invention comprises: preparing a wafer having a first region and a second region on its upper surface, the second region being disposed around the first region and located lower than the first region; and forming a semiconductor layer composed of a nitride semiconductor on the upper surface of the wafer. When viewed from above, the second region has an extended protrusion at its end in a first direction, the first direction being a direction passing through the center of the wafer and parallel to the m-axis of the semiconductor layer, and the extended protrusion extends in a direction from the edge of the wafer toward the center of the wafer. The extended protrusion has a first side surface parallel to a third direction, the third direction being a direction inclined at an angle of not less than 5° and not more than 55° relative to a second direction parallel to a tangent line to the edge of the wafer in the first direction.

[0011] Effects of the Invention

[0012] According to one embodiment of the present invention, a method for manufacturing a semiconductor element can be realized that can reduce the influence of cracks generated in a semiconductor layer and improve yield by flattening the upper surface of the semiconductor layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 This is a flowchart showing the method for manufacturing a semiconductor device according to the first embodiment.

[0014] Figure 2A It is a top view showing the wafer according to the first embodiment.

[0015] Figure 2B It is along Figure 2A Partial end view of the first direction shown.

[0016] Figure 2C It is along Figure 2A Partial end view of the fifth direction shown.

[0017] Figure 3 This is a partially enlarged plan view of the wafer according to the first embodiment.

[0018] Figure 4A It is a plan view showing the wafer and semiconductor layer in the first embodiment.

[0019] Figure 4B It is along Figure 4A Partial end view of the first direction shown.

[0020] Figure 4C It is along Figure 4A Partial end view of the fifth direction shown.

[0021] Figure 5AIt is a plan view showing the crystal orientation of the semiconductor layer.

[0022] Figure 5B It is a perspective view showing the crystal orientation of the semiconductor layer.

[0023] Figure 6 It is a top view of a wafer showing a modification of the first embodiment.

[0024] Figure 7 This is a partially enlarged plan view of a wafer showing a modification of the first embodiment.

[0025] Figure 8 It is a top view of a wafer showing the second embodiment.

[0026] Figure 9 It is a partially enlarged plan view of a wafer showing the second embodiment.

[0027] Figure 10 It is a plan view showing a method for manufacturing a semiconductor element according to a comparative example.

[0028] Figure 11A It is a top view showing a method for manufacturing a semiconductor element according to a reference example.

[0029] Figure 11B It is a partial end view showing a method for manufacturing a semiconductor element according to a reference example.

[0030] Figure 12A 1 is a top view showing a wafer and a semiconductor layer in a test example.

[0031] Figure 12B The horizontal axis is the radial position, and the vertical axis is the height of the upper surface of the semiconductor layer. Figure 12A The diagram shows the shape of the line segment AA'.

[0032] Figure 12C The angle θ is taken on the horizontal axis and the protrusion H is taken on the vertical axis to show the semiconductor layer along the Figure 12A The shape of circle B is shown in the diagram.

[0033] Description of Reference Numerals

[0034] 10, 10a: Wafer

[0035] 11: First Area

[0036] 11a: Circular part

[0037] 11b: Extended protrusion

[0038] 11c: First side

[0039] 11d: Second side

[0040] 12: Second Area

[0041] 12a: Ring part

[0042] 12b: Extended protrusion

[0043] 12c: First side

[0044] 12d: Second side

[0045] 15: Upper surface

[0046] 16: Stairs

[0047] 17: End edge

[0048] 18: Bevel face

[0049] 19: Oriented Plane

[0050] 20: Semiconductor layer

[0051] 41: First tangent

[0052] 42: Second tangent

[0053] 43: Third Tangent

[0054] 50: Wafer

[0055] 55: Upper surface

[0056] 110: Wafer

[0057] 120: Semiconductor layer

[0058] 120a: Thick film part

[0059] 120b: end

[0060] 120c: Other parts

[0061] 121: Crack

[0062] 210: Wafer

[0063] 211: First Area

[0064] 212: Second Area

[0065] 215: Upper surface

[0066] 216: Stairs

[0067] 220: Semiconductor layer

[0068] 220a: Thick film part

[0069] 230: Support wafer

[0070] 231: Lower surface

[0071] 232: Flat part

[0072] 233: Inclined part

[0073] A: Line segment

[0074] B: Circle

[0075] C: Center

[0076] D1: First distance

[0077] D2: Second distance

[0078] G: Height

[0079] H: Protrusion

[0080] V1: First direction

[0081] V2: Second direction

[0082] V3: Third direction

[0083] V4: The fourth direction

[0084] V5: The fifth direction

[0085] θ, θ1, θ2: angles DETAILED DESCRIPTION

[0086] The following describes embodiments of the present invention with reference to the accompanying drawings. Note that the figures are schematic or conceptual, and appropriate emphasis and omissions have been made to facilitate understanding. The shapes and dimensional ratios of the various components shown in the figures are not necessarily the same as in reality. In the figures, the dimensional ratios and shapes of the various components may not strictly match. In the following description, components that have already appeared will be marked with the same reference numerals, and detailed descriptions will be omitted.

[0087] <First embodiment>

[0088] First, a method for manufacturing a semiconductor element according to a first embodiment of the present invention will be briefly described.

[0089] The method for manufacturing a semiconductor device according to the present embodiment includes a step of preparing a wafer 10 (step S1 ) and a step of forming a semiconductor layer 20 made of a nitride semiconductor on the wafer 10 (step S2 ).

[0090] The upper surface 15 of the wafer 10 includes a first region 11 and a second region 12. The second region 12 is provided around the first region 11 and is located lower than the first region 11. When viewing the wafer 10 from above, the first region 11 has an extended portion 11b at its end in a first direction V1, which is a direction passing through the center C of the wafer 10 and parallel to the m-axis of the semiconductor layer 20. The extended portion 11b extends from the center C of the wafer 10 toward the edge 17 of the wafer 10. The extended portion 11b has a first side surface 11c parallel to a third direction V3, which is inclined at an angle θ1 of 5° to 55° relative to a second direction V2 parallel to a first tangent line 41 to the edge of the wafer 10 in the first direction V1.

[0091] Hereinafter, the method for manufacturing the semiconductor element according to the present embodiment will be described in detail.

[0092] <Step of Preparing Wafer 10>

[0093] First, if Figure 1 As shown in step S1 , a wafer 10 is prepared.

[0094] The wafer 10 is, for example, a sapphire substrate, and is made of, for example, single crystal sapphire. Figure 2A As shown, the shape of the wafer 10 is roughly circular, with a diameter of about 70 mm to 300 mm. The thickness of the wafer 10 is, for example, 100 μm to 800 μm, preferably 100 μm to 300 μm. The thickness of the wafer 10 can also be reduced to a thin film by grinding, polishing, etc. as needed. An orientation plane 19 that is chord-shaped when viewed from above can be provided on the wafer 10. An inclined portion 18 is provided on the outer periphery of the wafer 10. As shown Figure 2B and Figure 2C As shown, the thickness of bevel portion 18 decreases as it approaches edge 17 of wafer 10. Unlike first region 11 and second region 12, bevel portion 18 is formed from a crystal plane of wafer 10 where semiconductor layer 20 is not formed. The edge of bevel portion 18 corresponds to edge 17 of wafer 10.

[0095] The upper surface 15 of the wafer 10 is the portion excluding the bevel portion 18. For example, the upper surface 15 is the c-plane of the sapphire constituting the wafer 10. For example, the angle formed between the upper surface 15 and the c-plane of the sapphire is 5° or less. Note that the upper surface 15 may also be inclined relative to the c-plane of the sapphire.

[0096] The following describes a case where a sapphire substrate is used as the wafer 10, and a semiconductor layer 20 composed of a nitride semiconductor is formed on the upper surface 15 of the wafer 10, which is the c-plane of the sapphire substrate. A first direction V1 and a fifth direction V5 are set on the upper surface 15 of the wafer 10. Both the first direction V1 and the fifth direction V5 are directions parallel to the upper surface 15. In this embodiment, six directions are set for each. As described later, when the semiconductor layer 20 is formed on the upper surface 15 of the wafer 10, the first direction V1 is a direction passing through the center C of the wafer 10 and parallel to the m-axis of the semiconductor layer 20. Furthermore, when the semiconductor layer 20 is formed on the upper surface 15 of the wafer 10, the fifth direction V5 is a direction passing through the center C and parallel to the a-axis of the semiconductor layer 20. The center C of the wafer 10 is the center of the circumscribed circle of the wafer 10 when viewed from above. For example, the angle formed by the first directions V1 is 60°. For example, the angle formed by the fifth directions V5 is 60°. For example, the angle formed by the adjacent first direction V1 and fifth direction V5 is 30°.

[0097] The upper surface 15 of the wafer 10 includes a first region 11 and a second region 12. The first region 11 is surrounded by the second region 12 when viewed from above. The second region 12 is provided around the first region 11 when viewed from above and is located at a lower position than the first region 11. Therefore, a step 16 is formed between the first region 11 and the second region 12. The height G of the step 16 can be appropriately changed according to the total film thickness of the semiconductor layer 20 formed on the upper surface 15 of the wafer 10. The height of the step 16 is the distance between the first region 11 and the second region 12 in the thickness direction of the wafer 10. For example, the second region 12 is located at a position lower than the first region 11 by more than 2 μm. In other words, the height G of the step 16 is, for example, more than 2 μm. In addition, the height G of the step 16 is, for example, less than 30 μm. The height G of the step 16 is, for example, more than 4 μm and less than 8 μm.

[0098] By setting the height G of the step 16 to be 2 μm or more, it is easy to obtain the effect of suppressing the crack generated in the second region 12 of the wafer 10 described later from spreading to the central portion of the wafer 10. By setting the height G of the step 16 to be 30 μm or less, the time required for processing the wafer 10 can be shortened. Figure 2B and Figure 2C In the figure, the surface constituting the step 16 is a surface perpendicular to the upper surface 15 of the wafer 10 , but may be a surface inclined with respect to the upper surface 15 of the wafer 10 .

[0099] The first region 11 includes a circular portion 11a and an extended portion 11b extending from the circular portion 11a toward the edge of the wafer 10. When viewed from above, the first region 11 has six extended portions 11b extending from the outer edge of one circular portion 11a toward the edge 17 of the wafer 10 in the first direction V1. For example, the center of the circular portion 11a coincides with the center C of the wafer 10. The extended length of each extended portion 11b is, for example, 0.1 mm to 10 mm, preferably 0.5 mm to 5 mm. By setting the extended length of the extended portion 11b to 0.1 mm or greater, the area where the semiconductor layer 20 is thicker than that of the semiconductor layer 20 in other areas of the first region 11 can be effectively reduced. Setting the extended length of the extended portion 11b to 10 mm or less ensures the area of ​​the second region 12 provided along the first direction V1, thereby effectively suppressing crack propagation from the second region 12 toward the first region 11.

[0100] Therefore, a first distance D1 between the edge 17 of the wafer 10 and the first region 11 in the first direction V1 is shorter than a second distance D2 between the edge 17 of the wafer 10 and the first region 11 in the fifth direction V5 by the length of the extended protrusion 11b. In other words, the relationship between the first distance D1 and the second distance D2 is: first distance D1 < second distance D2. The first distance D1 is, for example, 0.1 mm to 5 mm, preferably 0.2 mm to 3 mm. The second distance D2 is, for example, 1 mm to 10 mm.

[0101] The second distance D2 between the end edge 17 of the wafer 10 and the first region 11 in the fifth direction V5 parallel to the a-axis of the semiconductor layer 20 is preferably less than 1 / 10 of the diameter of the wafer 10. By setting the second distance D2 in this way, the area of ​​the first region 11 can be ensured, and cracks generated in the semiconductor layer 20 in the second region 12 can be effectively suppressed from propagating to the central portion of the wafer 10. For example, if the diameter of the wafer 10 is 100 mm, the second distance D2 is less than 10 mm. If the diameter of the wafer 10 is 150 mm, the second distance D2 is less than 15 mm. If the diameter of the wafer 10 is 200 mm, the second distance D2 is less than 20 mm. If the diameter of the wafer 10 is 300 mm, the second distance D2 is less than 30 mm.

[0102] In this embodiment, the second region 12 is provided between the circular portion 11a and the inclined surface portion 18 in a plan view. In contrast, there may be a portion between the extended protrusion 11b and the inclined surface portion 18 where the second region 12 is not provided. Figure 2A and Figure 2BIn the illustrated example, the extended portion 11 b does not reach the inclined portion 18 , and the second region 12 is provided between the extended portion 11 b and the inclined portion 18 .

[0103] like Figure 3 As shown, the extended protrusion 11b has a first side surface 11c and a second side surface 11d. The first side surface 11c is parallel to the third direction V3. The third direction V3 is inclined at an angle θ1 relative to the second direction V2. The second direction V2 is parallel to the first tangent line 41 of the end edge 17 of the wafer 10 in the first direction V1. The angle θ1 is greater than or equal to 55° and less than or equal to 5°, preferably greater than or equal to 30°, and more preferably greater than or equal to 5° and less than or equal to 20°. By setting the angle θ1 to greater than or equal to 55°, it is possible to reduce the area in which the semiconductor layer 20 formed near the end portion of the first region 11 in the first direction V1 is thicker than the semiconductor layer 20 in other areas.

[0104] The second side surface 11d is parallel to the fourth direction V4. The fourth direction V4 is a direction different from the third direction V3 and is inclined at an angle θ2 relative to the second direction V2. The angle θ2 is greater than or equal to 5° and less than or equal to 55°, preferably greater than or equal to 5° and less than or equal to 30°, and more preferably greater than or equal to 5° and less than or equal to 20°. By making the angle θ2 greater than or equal to 5° and less than or equal to 55°, the same effect as the first side surface 11c can be obtained. The first side surface 11c is continuous with the second side surface 11d. That is, a portion of the first side surface 11c is connected to a portion of the second side surface 11d. Thus, the above-mentioned effect can be efficiently obtained, that is, the increase in film thickness around the end portion of the first region 11 in the first direction V1 can be suppressed by the first side surface 11c and the second side surface 11d.

[0105] In addition, if Figure 2A and Figure 3 As shown, in a top view, a second tangent line 42 at the edge of the first region 11 in the fifth direction V5, which passes through the center C of the wafer 10 and is parallel to the a-axis of the semiconductor layer 20, is parallel to a third tangent line 43 at the edge 17 of the wafer 10 in the fifth direction V5. The end of the first region 11 in the fifth direction V5 is not provided with the extended protrusion 11b provided at the end of the first region 11 in the first direction V1. In other words, the extended protrusion 11b is provided only at the end of the first region 11 in the first direction V1. This ensures the area of ​​the second region 12 in the first direction V1, thereby preventing cracks generated in the semiconductor layer 20 in the second region 12 from propagating to the center of the wafer 10.

[0106] <Step of Forming the Semiconductor Layer 20>

[0107] Next, if Figure 1 As shown in step S2 , a semiconductor layer 20 composed of a nitride semiconductor is formed on the wafer 10 .

[0108] like Figures 4A to 4C As shown, the semiconductor layer 20 is epitaxially grown on the upper surface 15 of the wafer 10 by a vapor phase growth method such as MOCVD (Metal Organic Chemical Vapor Deposition) using the wafer 10 as a substrate for crystal growth. The semiconductor layer 20 is formed in both the first region 11 and the second region 12. Figure 5A and Figure 5B As shown, the (0001) c-plane of the semiconductor layer 20 is parallel to the upper surface 15 of the wafer 10. In addition, the first direction V1 is parallel to the m-axis of the semiconductor layer 20, and the fifth direction V5 is parallel to the a-axis of the semiconductor layer 20. The first direction V1 is the direction from the center C of the wafer 10 toward the edge 17 of the wafer 10, as shown in FIG. Figure 2A As shown, there are six first directions V1. The fifth direction V5 is the direction from the center C of the wafer 10 toward the edge 17 of the wafer 10, as shown in FIG. Figure 2A As shown, there are six directions of the fifth direction V5.

[0109] The semiconductor layer 20 includes, for example, a group III-V nitride semiconductor (In X Al Y Ga 1－X－Y N(0≤X, 0≤Y, X+Y≤1)) The semiconductor layer 20 includes, for example, an n-type semiconductor layer, a p-type semiconductor layer, and a light emitting layer located between the n-type semiconductor layer and the p-type semiconductor layer.

[0110] The peak wavelength of light emitted from the light emitting layer is, for example, not less than 330 nm and not more than 400 nm. In the case where the peak wavelength of light emitted from the light emitting layer is not less than 330 nm and not more than 400 nm, when the semiconductor layer 20 is a semiconductor layer that does not contain aluminum (Al), for example, is composed of gallium nitride (GaN), the light from the light emitting layer is easily absorbed by the semiconductor layer. For example, by making the semiconductor layer 20 have an AlGaN layer containing aluminum, the light from the light emitting layer is not easily absorbed by the semiconductor layer. For example, by including an AlGaN layer that accounts for, for example, 20% or more relative to the total film thickness of the semiconductor layer 20 in the semiconductor layer 20, it is difficult for the semiconductor layer 20 to absorb the light emitted from the light emitting layer compared to the case where most of the semiconductor layer 20 is composed of GaN. The semiconductor layer 20 preferably contains AlGaN, for example. x1 Ga 1－x1 N(0.03≤x1≤0.08).

[0111] As another example of the peak wavelength of light emitted from the light emitting layer, it is, for example, 250 nm or more and 330 nm or less. Even in the case where the peak wavelength of light emitted from the light emitting layer is 250 nm or more and 330 nm or less, when the semiconductor layer 20 is a semiconductor layer that does not contain aluminum (Al), for example, is composed of gallium nitride (GaN), the light from the light emitting layer is easily absorbed by the semiconductor layer. By making the semiconductor layer 20 have an AlGaN layer containing aluminum, the light from the light emitting layer is less likely to be absorbed by the semiconductor layer. For example, by including an AlGaN layer that accounts for, for example, 20% or more relative to the total film thickness of the semiconductor layer 20 in the semiconductor layer 20, it is less likely for the semiconductor layer 20 to absorb the light emitted from the light emitting layer compared to the case where most of the semiconductor layer 20 is composed of GaN. The semiconductor layer 20 preferably contains AlGaN, for example. x1 Ga 1－x1 N(0.5≤x1≤1).

[0112] In this embodiment, when viewed from the center C of the wafer 10, an extended protrusion 11b having a first side surface 11c and a second side surface 11d is provided at the end of the semiconductor layer 20 in the first direction V1. A third direction V3 parallel to the first side surface 11c and a fourth direction V4 parallel to the second side surface 11d are inclined relative to the second direction V2. This suppresses local increases in the thickness of the semiconductor layer 20 in the first region 11, compared to a configuration without the extended protrusion 11b. This is presumably because the provision of the first side surface 11c and the second side surface 11d causes the semiconductor layer 20 to grow near the end of the semiconductor layer 20 in the first direction V1, thereby suppressing increases in thickness. As a result, the upper surface 15 of the semiconductor layer 20 can be made flat in the first region 11, resulting in a uniform thickness of the semiconductor layer 20. Preferably, the film thickness of the semiconductor layer 20 in the first region 11 is made uniform so that the difference between the maximum film thickness and the minimum film thickness of the semiconductor layer 20 is approximately 2 μm or less.

[0113] The wafer 10 and semiconductor layer 20 thus fabricated are processed into a semiconductor device, for example, through the following steps. For example, a support wafer is bonded to the wafer 10 via the semiconductor layer 20. The support wafer is, for example, a silicon wafer. At this time, since the semiconductor layer 20 formed on the first region 11 has a substantially uniform film thickness, the support wafer can be bonded with high precision using a bonding member or the like.

[0114] Next, the structure comprising the wafer 10, semiconductor layer 20, and support wafer is processed using the support wafer as a support substrate. For example, the wafer 10, which serves as a substrate for crystal growth, can be peeled off from the semiconductor layer 20. In this way, a semiconductor element is manufactured. Examples of semiconductor elements include light-emitting diodes (LEDs) and laser diodes (LDs).

[0115] Next, the effects of the method for manufacturing a semiconductor device according to this embodiment will be described.

[0116] In the semiconductor device manufacturing method of this embodiment, a first region 11 and a second region 12 are provided on the upper surface 15 of a wafer 10. Consequently, when a semiconductor layer 20 is formed on the upper surface 15, the semiconductor layer 20 is formed in both the first region 11 and the second region 12. Because a step 16 is formed between the first region 11 and the second region 12, cracks generated in the semiconductor layer 20 formed in the second region 12 are prevented from propagating by the step 16 and are less likely to enter the semiconductor layer 20 formed in the first region 11. This reduces the occurrence of cracks in the semiconductor layer 20, enabling semiconductor device manufacturing with a high yield.

[0117] Furthermore, according to this embodiment, an extended protrusion 11b having a first side surface 11c and a second side surface 11d is provided at the end of the semiconductor layer 20 in the first direction V1 when viewed from the center C. This prevents local increases in the thickness of the semiconductor layer 20, thereby making the thickness of the semiconductor layer 20 uniform. Consequently, processing accuracy is improved in subsequent steps. For example, a support wafer can be bonded to the wafer 10 with high precision via the semiconductor layer 20.

[0118] Therefore, according to the method for manufacturing a semiconductor element of this embodiment, the yield of the semiconductor element can be improved.

[0119] <Modification of First Embodiment>

[0120] Next, a modification of this embodiment will be described.

[0121] This modification differs from the first embodiment in the structure of the wafer. The structure other than the wafer in this modification is the same as that of the first embodiment.

[0122] like Figure 6 and Figure 7As shown, in this variation, in wafer 10a, the extended protrusion 11b of the first region 11 reaches the edge of the upper surface 15 of wafer 10a. That is, the extended protrusion 11b reaches the bevel portion 18, and no second region 12 is provided between the extended protrusion 11b and the bevel portion 18. This variation also achieves the same effects as the first embodiment, but achieves local effects different from those of the first embodiment. For example, compared to the first embodiment, this variation is less effective in suppressing the extension of cracks in the second region 12 in the first direction V1. On the other hand, since the area of ​​the first region 11 can be increased, it is easier to suppress local increases in the film thickness of the semiconductor layer 20.

[0123] <Second embodiment>

[0124] Next, a method for manufacturing a semiconductor element according to a second embodiment of the present invention will be briefly described.

[0125] The method for manufacturing a semiconductor device according to the present embodiment includes a step of preparing a wafer 50 (step S1 ) and a step of forming a semiconductor layer 20 made of a nitride semiconductor on the wafer 50 (step S2 ).

[0126] The upper surface 55 of the wafer 50 includes a first region 11 and a second region 12. The second region 12 is provided around the first region 11 and is located lower than the first region 11. When viewing the wafer 50 from above, the second region 12 has an extended portion 12b at its end in a first direction V1, which is a direction passing through the center C of the wafer 50 and parallel to the m-axis of the semiconductor layer 20. The extended portion 12b extends from the edge 17 of the wafer 50 toward the center C of the wafer 50. The extended portion 12b has a first side surface 12c parallel to a third direction V3, which is inclined at an angle θ1 of 5° to 55° relative to a second direction V2 parallel to a first tangent line 41 to the edge 17 of the wafer 50 in the first direction V1.

[0127] Hereinafter, the method for manufacturing the semiconductor element according to the present embodiment will be described in detail.

[0128] The present embodiment differs from the first embodiment in the structure of the wafer. The structure and effects other than the wafer in the present embodiment are the same as those in the first embodiment.

[0129] like Figure 8 and Figure 9 As shown, the upper surface 55 of the wafer 50 has a first region 11 and a second region 12. The second region 12 is provided around the first region 11 and is located lower than the first region 11. The second region 12 has an annular portion 12a and an extended protrusion 12b.

[0130] When the wafer 50 is viewed from above, the annular portion 12a is roughly annular and is continuous with the inclined portion 18. The end of the annular portion 12a is in contact with the inclined portion 18. The extended protrusion 12b is provided at an end portion in a first direction V1 that passes through the center C of the wafer 50 and is parallel to the m-axis of the semiconductor layer 20. The extended protrusion 12b extends from the annular portion 12a toward the inside of the wafer 50. That is, the extended protrusion 12b extends in a direction from the end edge 17 of the wafer 50 toward the center C of the wafer 50. As described in the first embodiment, the first direction V1 is a direction corresponding to the m-axis of the semiconductor layer 20, and there are a total of six directions. Therefore, six extended protrusions 12b are provided corresponding to the first direction V1.

[0131] like Figure 9 As shown, the extended protrusion 12b has a first side surface 12c and a second side surface 12d. The first side surface 12c is parallel to the third direction V3, and the second side surface 12d is parallel to the fourth direction V4. The definitions of the third direction V3 and the fourth direction V4 are the same as those in the first embodiment. That is, the third direction V3 is inclined at an angle θ1 of 5° to 55° relative to the second direction V2. In addition, the fourth direction V4 is a direction different from the third direction V3 and is inclined at an angle θ2 of 5° to 55° relative to the second direction V2. The first side surface 12c is continuous with the second side surface 12d. That is, a portion of the first side surface 12c is connected to a portion of the second side surface 12d. As a result, it is possible to effectively suppress the increase in film thickness around the end portion of the first region 11 in the first direction V1 due to the first side surface 12c and the second side surface 12d.

[0132] Furthermore, in a plan view, a second tangent line 42 to the edge of the first region 11 in the fifth direction V5, which passes through the center C of the wafer 50 and is parallel to the a-axis of the semiconductor layer, is parallel to a third tangent line 43 to the edge 17 in the fifth direction V5 of the wafer 50. The structure of the wafer 50 other than the above is the same as that of the wafer 10.

[0133] According to this embodiment as well, the same effects as those of the first embodiment can be obtained.

[0134] Comparative Example

[0135] Next, comparative examples will be described.

[0136] Figure 10 It is a plan view showing a method for manufacturing a semiconductor element according to this comparative example.

[0137] like Figure 10As shown, in this comparative example, no regions with varying heights are provided on the upper surface of wafer 110. Therefore, the upper surface of wafer 110 is entirely flat. Furthermore, semiconductor layer 120 is formed on the upper surface of wafer 110. In this case, the film thickness of semiconductor layer 120 is relatively thicker at its periphery. In particular, a thick film portion 120a is formed at the end portion of semiconductor layer 120 located in the first direction V1 when viewed from center C, where the film thickness is thicker than at the end portions in other directions.

[0138] When the semiconductor layer 120 contains aluminum (Al), the film thickness of the outer periphery of the semiconductor layer 120 tends to be thicker than that of other regions, compared to when the semiconductor layer 120 does not contain aluminum. This is believed to be because, when the semiconductor layer 120 contains aluminum, the semiconductor layer 120 is more likely to undergo undesirable growth at the outer periphery of the semiconductor layer 120. Furthermore, the film thickness of the outer periphery of the semiconductor layer 120 depends on the direction from the center C, with the film thickness at the end located in the first direction V1 when viewed from the center C being thicker than the film thickness at the end located in the fifth direction V5 when viewed from the center C. The portion of the semiconductor layer 120 formed on the first region 11 that is located at the end in the first direction V1 when viewed from the center C is referred to as a thick film portion 120a. Thick film portions 120a are present at six ends of the semiconductor layer 120 in the first direction V1 when viewed from the center C.

[0139] The reason why the film thickness becomes uneven in this way is not necessarily clear, but it can be inferred as follows. As described above, the first direction V1 is along the m-axis of the semiconductor layer 120, and the fifth direction V5 is along the a-axis of the semiconductor layer 120. Moreover, the (0001) c-plane of the semiconductor layer 120 is parallel to the upper surface of the wafer 110. In this case, the growth rate of the semiconductor layer 120 along the m-axis of the semiconductor layer 120 (the first direction V1) relative to the (0001) c-plane of the semiconductor layer 120 is slower than the growth rate of the semiconductor layer 120 along the a-axis of the semiconductor layer 120 (the fifth direction V5). Therefore, it can be inferred that the film thickness at the end of the semiconductor layer 120 in the first direction V1, where the growth rate is slow relative to the (0001) c-plane of the semiconductor layer 120, is accelerated because the growth rate in the fifth direction V5, which is faster than the first direction V1, also affects the growth rate in the first direction V1, resulting in the film being thicker than the surrounding area.

[0140] Therefore, at the end of the semiconductor layer 120, undesirable growth of the semiconductor layer occurs, and cracks 121 may sometimes occur from this portion. Here, the so-called undesirable growth of the semiconductor layer refers to the formation of a semiconductor layer having a composition or crystallinity different from that of the semiconductor layer desired to be grown on the wafer 10. Moreover, in this comparative example, the upper surface of the wafer 110 is flat, and no steps are formed on the upper surface of the wafer 110. Therefore, the cracks 121 generated at the end of the semiconductor layer 120 are likely to propagate to the central portion of the semiconductor layer 120. As a result, the yield of the semiconductor layer 120 is reduced. Note that in the case where the semiconductor layer 120 includes a semiconductor layer containing aluminum, cracks 121 are likely to occur at the end of the semiconductor layer 120. This is inferred to be because, as described above, in the case where the semiconductor layer 120 includes a semiconductor layer containing aluminum, undesirable growth of the semiconductor layer is likely to occur at the end of the semiconductor layer 120, and cracks 121 are likely to occur in this portion.

[0141] Reference Example

[0142] Next, a reference example will be described.

[0143] like Figure 11A and Figure 11B As shown, in this reference example, a first region 211 and a second region 212 are provided on the upper surface 215 of the wafer 210. However, no extensions are provided in the first region 211 or the second region 212, and the outer edge of the first region 211 is circular when viewed from above. Therefore, the thick film portion 220a of the semiconductor layer 220 is formed on the outer periphery of the portion of the semiconductor layer 220 provided in the first region 211 and is formed at a position in the first direction V1 when viewed from the center C.

[0144] In this reference example, since the second region 212 is provided on the upper surface 215 of the wafer 210, even if a crack occurs at the end of the semiconductor layer 220, the propagation of the crack is prevented by the step 216 between the first region 211 and the second region 212. Therefore, a crack generated at the end of the semiconductor layer 220 is unlikely to propagate to the center of the semiconductor layer 220.

[0145] However, in this reference example, there is a possibility of defects occurring when the support wafer 230 is bonded to the wafer 210 via the semiconductor layer 220. The outer shape of the wafer 210 is substantially the same as that of the support wafer 230. In this case, since no extended protrusion is provided in the first region 211, the thick film portion 220a abuts against the flat portion 232 of the lower surface 231 of the support wafer 230. Since the thick film portion 220a of the semiconductor layer 220 contacts the flat portion 232 of the support wafer 230, portions of the semiconductor layer 220 other than the thick film portion 220a no longer abut against the support wafer 230, resulting in bonding defects and a reduction in the yield rate.

[0146] Furthermore, since the thick film portion 220 a is formed in the semiconductor layer 220 , high-precision processing becomes difficult in subsequent steps even when the support wafer 230 is not used, thus causing a decrease in the yield of semiconductor devices.

[0147] Test Example

[0148] Next, a test example will be described.

[0149] Figure 12A 1 is a plan view showing the wafer 110 and the semiconductor layer 120 in this experimental example.

[0150] Figure 12B The horizontal axis is the radial position, and the vertical axis is the height of the upper surface of the semiconductor layer 120 to show the position of the semiconductor layer 120 along the Figure 12A The diagram shows the shape of the line segment AA'.

[0151] Figure 12C The angle θ is taken on the horizontal axis and the protrusion amount H is taken on the vertical axis to show the semiconductor layer 120 along the Figure 12A The shape of circle B is shown in the diagram.

[0152] Note that angle θ is the angle viewed from the center C of wafer 110, and a direction of θ = 0° coincides with one of the fifth directions V5. Furthermore, the protrusion amount H is the difference between the height of the edge of semiconductor layer 120 and the height of a position 70 μm away from the edge of semiconductor layer 120 toward center C. Figure 12B and Figure 12C For example, it is the measurement result measured with a surface roughness meter.

[0153] In this experimental example, a semiconductor layer 120 comprising a gallium nitride-based semiconductor was epitaxially grown on a sapphire wafer 110 using MOCVD. Semiconductor layer 120 included an n-type semiconductor layer, a p-type semiconductor layer, and a light-emitting layer positioned between the n-type and p-type semiconductor layers. Note that this experimental example used the same conditions as those used in the comparative and reference examples. The average thickness of semiconductor layer 120 formed on wafer 110 was 10 μm.

[0154] like Figure 12B As shown, the end portion 120b of the semiconductor layer 120 is thicker than the other portion 120c.

[0155] like Figure 12CAs shown, the thickness of the semiconductor layer 120 at the end has an angle dependency. When viewed from the center C, the portion in the fifth direction V5 has a protrusion amount H of approximately 1.5 to 3 μm, while the portion in the first direction V1 has a protrusion amount H of approximately 4 to 5 μm. In other words, the end portion in the first direction V1 is thicker than the end portion in the fifth direction V5.

[0156] Therefore, as in the aforementioned reference example, if the outer shape of the first region 211 is made circular, the thick film portion 220a of the semiconductor layer 220 contacts the flat portion 232 of the supporting wafer 230, resulting in poor bonding. Note that it is also possible to consider widening the width of the inclined portion 233 of the supporting wafer 230 to avoid contact between the thick film portion 220a and the flat portion 232. In addition, it is also possible to consider making the wafer 210 larger than the supporting wafer 230 to avoid contact between the thick film portion 220a and the flat portion 232. However, the size and shape of the wafer are standardized. If they are changed, it is necessary to change the specifications of most of the processing equipment used in the manufacture of semiconductor elements, which will result in a significant reduction in the yield of semiconductor elements. In addition, there is a hidden danger that the number of semiconductor elements that can be manufactured in a single manufacturing process will be reduced.

[0157] In contrast, according to the first and second embodiments described above, the use of existing standard wafers can suppress the propagation of cracks and the generation of thick film portions in the semiconductor layer 20, thereby enabling the manufacture of semiconductor devices with a higher yield.

[0158] Industrial Applicability

[0159] The present invention can be used, for example, to manufacture semiconductor devices such as light emitting diodes (LEDs) and laser diodes (LDs).

Claims

1. A method for manufacturing a semiconductor element, characterized in that: have: A step of preparing a wafer, the wafer being made of sapphire and including a first region and a second region on an upper surface thereof, wherein the second region is provided around the first region and is located at a lower position than the first region; a step of epitaxially growing a semiconductor layer composed of a nitride semiconductor on the upper surface of the wafer; When viewed from above, the first region has an extended protrusion at an end in a first direction, the first direction being a direction passing through the center of the wafer and parallel to the m-axis of the semiconductor layer, the extended protrusion extending in a direction from the center of the wafer toward an edge of the wafer. The extended protrusion has a first side surface parallel to a third direction, which is a direction inclined at an angle of 5° to 55° with respect to a second direction parallel to a tangent line to the edge of the wafer in the first direction.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: When viewed from above, the extended protrusion further has a second side surface extending along a fourth direction, where the fourth direction is a direction different from the third direction and is inclined at an angle of 5° to 55° with respect to the second direction.

3. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein: The extended protrusion reaches an edge of the upper surface of the wafer.

4. The method for manufacturing a semiconductor element according to claim 1 or 2, wherein: When viewed from above, a tangent line to an edge of the first region in a fifth direction is parallel to a tangent line to an edge of the wafer in the fifth direction. The fifth direction is a direction passing through the center of the wafer and parallel to the a-axis of the semiconductor layer.

5. A method for manufacturing a semiconductor element, characterized in that: have: A step of preparing a wafer, the wafer being made of sapphire and including a first region and a second region on an upper surface thereof, wherein the second region is provided around the first region and is located at a lower position than the first region; a step of epitaxially growing a semiconductor layer composed of a nitride semiconductor on the upper surface of the wafer; When viewed from above, the second region has an extended protrusion at an end in a first direction, the first direction being a direction passing through the center of the wafer and parallel to the m-axis of the semiconductor layer, the extended protrusion extending in a direction from the edge side of the wafer toward the center of the wafer. The extended protrusion has a first side surface parallel to a third direction, which is a direction inclined at an angle of 5° to 55° with respect to a second direction parallel to a tangent line to the edge of the wafer in the first direction.

6. The method for manufacturing a semiconductor device according to claim 5, wherein: When viewed from above, the extended protrusion further has a second side surface extending along a fourth direction, where the fourth direction is a direction different from the third direction and is inclined at an angle of 5° to 55° with respect to the second direction.

7. The method for manufacturing a semiconductor device according to claim 6, wherein: The first side surface is continuous with the second side surface.

8. The method for manufacturing a semiconductor device according to any one of claims 5 to 7, wherein: When viewed from above, a tangent line to an edge of the first region in a fifth direction is parallel to a tangent line to an edge of the wafer in the fifth direction. The fifth direction is a direction passing through the center of the wafer and parallel to the a-axis of the semiconductor layer.

9. The method for manufacturing a semiconductor device according to any one of claims 5 to 7, wherein: The second region is located at a position lower than the first region by 2 μm or more.

10. The method for manufacturing a semiconductor element according to any one of claims 5 to 7, wherein: A distance between an edge of the wafer in a fifth direction and the first region is less than 1 / 10 of a diameter of the wafer, and the fifth direction is a direction parallel to an a-axis of the semiconductor layer.

Images