IGBT drive circuit and power conversion equipment

Abstract

The present disclosure relates to an IGBT drive circuit and a power conversion device, wherein the IGBT drive circuit comprises: a drive chip (10) having a first drive signal port (Vo); a drive resistance adjustment circuit (20) connected between the first drive signal port (Vo) and a gate (G) of the IGBT, wherein the drive resistance formed by the drive resistance adjustment circuit (20) is adjustable; a peak voltage detection circuit (30) connected to the gate (G) of the IGBT that is conductive to the first drive signal port (Vo), wherein the peak voltage detection circuit (30) is configured to monitor whether a peak voltage occurs when the IGBT is turned off; and a resistance adjustment control circuit (40) connected between the peak voltage detection circuit (30) and the drive resistance adjustment circuit (20), wherein the resistance formed by the drive resistance adjustment circuit (20) is reduced when a peak voltage is detected when the IGBT is turned off.

Description

Technical Field

[0001] The present disclosure relates to the technical field of power equipment, and in particular, to an IGBT drive circuit and a power conversion device. Background Art

[0002] In a power conversion device, an Insulated Gate Bipolar Transistor (IGBT) is one of the most core devices, which determines whether the power conversion proceeds normally. However, during the turn-off process of the IGBT, the gate is often affected by other parasitic capacitances and stray inductances and accumulates charges, forming a spike voltage, which poses a risk of mis-conduction. That is, if the spike voltage exceeds the turn-on voltage threshold of the IGBT, it will cause the IGBT to conduct during the turn-off period. At this time, it will conduct simultaneously with other working IGBTs in the same bridge arm, resulting in a short circuit and damaging the IGBT.

[0003] Therefore, in order to ensure the normal operation of the IGBT, suppressing the gate spike voltage and eliminating the mis-conduction problem are the key. Summary of the Invention

[0004] Embodiments of the present disclosure provide an IGBT drive circuit and a power conversion device, which can prevent the IGBT drive circuit from conducting during the turn-off period.

[0005] According to a first aspect of the present disclosure, there is provided an IGBT drive circuit, including:

[0006] A drive chip having a first drive signal port;

[0007] A drive resistance adjustment circuit connected between the first drive signal port and the gate of the IGBT, and the drive resistance formed by the drive resistance adjustment circuit is adjustable;

[0008] A spike voltage detection circuit connected to the gate of the IGBT that conducts with the first drive signal port, and the spike voltage detection circuit is configured to monitor whether a spike voltage appears when the IGBT is turned off; and

[0009] A resistance adjustment control circuit connected between the spike voltage detection circuit and the drive resistance adjustment circuit, and is configured to reduce the resistance formed by the drive resistance adjustment circuit when a spike voltage is detected during the turn-off of the IGBT.

[0010] In some embodiments, the drive resistance adjustment circuit includes: a first drive resistance, a first MOS transistor, a second drive resistance, and a third anti-reverse diode;

[0011] Among them, the first end of the first driving resistor is electrically connected to the first driving signal port, the second end of the first driving resistor is electrically connected to the gate of the IGBT, and the first MOS transistor, the second driving resistor, and the third anti - reverse diode are connected in series and then connected in parallel with the first driving resistor.

[0012] In some embodiments, the driving chip has a forward - bias output port, and the first gate of the first MOS transistor is connected to the forward - bias output port and the resistance - regulating control circuit.

[0013] Among them, the resistance - regulating control circuit is configured to turn off the first MOS transistor by grounding the first gate of the first MOS transistor when the voltage is normal after the IGBT is turned off, so that the driving resistor is the first driving resistor; and when a spike voltage is detected, the voltage at the connection between the first gate of the first MOS transistor and the resistance - regulating control circuit is made lower than the voltage of the forward - bias output port to turn on the first MOS transistor, so that the driving resistor is the resistance formed by the parallel connection of the first driving resistor and the second driving resistor.

[0014] In some embodiments, the driving chip has a forward - bias output port, and the first gate of the first MOS transistor is connected to the forward - bias output port through a first protection resistor.

[0015] In some embodiments, the spike - voltage detection circuit includes: a PNP - type triode, a breakdown diode, a first anti - reverse diode, a second protection resistor, and a third protection resistor.

[0016] Among them, the breakdown diode, the first anti - reverse diode, and the second protection resistor are connected in series in sequence, the second protection resistor is connected to the resistance - regulating control circuit, the emitter of the PNP - type triode is connected to the breakdown diode, the collector of the PNP - type triode is directly connected to the gate of the IGBT, and the base of the PNP - type triode is connected to the gate of the IGBT through the third protection resistor.

[0017] In some embodiments, the driving chip has a second driving signal port electrically connected to the emitter of the IGBT, and the connection between the spike - voltage detection circuit and the resistance - regulating control circuit is connected to the second driving signal port through a fourth protection resistor.

[0018] In some embodiments, the driving chip has a second driving signal port electrically connected to the emitter of the IGBT, and the resistance - regulating control circuit includes:

[0019] A second anti - reverse diode and a free - wheeling capacitor connected in series, the positive pole of the second anti - reverse diode is connected to the circuit connecting the first driving signal port and the gate of the IGBT, and the connection point is located between the driving - resistance regulating circuit and the spike - voltage detection circuit, and one end of the free - wheeling capacitor is connected to the second driving signal port.

[0020] A second MOS transistor, having a second source connected to the driving resistor adjusting circuit, a second drain connected to the second driving signal port, and a second gate connected between the second anti - reverse diode and the free - wheeling capacitor; and

[0021] An NPN - type triode, having a collector connected to the second gate, an emitter connected to the second driving signal port, and a base connected to one end where the peak voltage detection circuit is connected to the emitter of the IGBT.

[0022] In some embodiments, the driving resistor adjusting circuit includes: a first driving resistor, a first MOS transistor, a second driving resistor, and a third anti - reverse diode; a first end of the first driving resistor is electrically connected to the first driving signal port, a second end of the first driving resistor is electrically connected to the gate of the IGBT, and the first MOS transistor, the second driving resistor, and the third anti - reverse diode are connected in series and then connected in parallel with the first driving resistor;

[0023] wherein, a first gate of the first MOS transistor is connected to a second source of the second MOS transistor.

[0024] In some embodiments, the resistor adjusting control circuit further includes:

[0025] A fifth protection resistor, connected between the driving resistor adjusting circuit and the second source;

[0026] A sixth protection resistor, connected between the second gate and the collector of the NPN - type triode; and / or

[0027] A seventh protection resistor, having one end connected between the second anti - reverse diode and the free - wheeling capacitor and the other end connected between the second gate and the collector of the NPN - type triode.

[0028] According to a second aspect of the present disclosure, there is provided a power conversion device including the IGBT driving circuit of the above - mentioned embodiment.

[0029] The IGBT driving circuit according to the embodiments of the present disclosure, when the IGBT is turned off, monitors whether there is a peak voltage through the peak voltage detection circuit 30, so as to select a resistance value of the driving resistor that is smaller than that in the normal working state. When a peak voltage appears, by reducing the driving resistor during turn - off, an additional rapid discharge channel is provided for the accumulated charge on the IGBT gate, thereby suppressing the gate peak voltage, ensuring that the IGBT is not mis - turned on, and realizing the function of protecting the IGBT during turn - off. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The drawings described herein are used to provide a further understanding of the present disclosure, and constitute a part of this application. The illustrative embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation of the present disclosure. In the drawings:

[0031] Figure 1Schematic diagram of the module composition of some embodiments of the IGBT drive circuit of the present disclosure;

[0032] Figure 2 Circuit schematic diagram of some embodiments of the IGBT drive circuit of the present disclosure. Detailed implementation manners

[0033] The present disclosure is described in detail below. In the following paragraphs, different aspects of the embodiments are defined in more detail. Each aspect so defined can be combined with any other one or more aspects, unless explicitly stated that they cannot be combined. In particular, any feature considered to be preferred or advantageous can be combined with any other one or more features considered to be preferred or advantageous.

[0034] As Figure 1 and Figure 2 shown, the present disclosure provides an IGBT drive circuit, including: a drive chip 10, a drive resistance adjustment circuit 20, a spike voltage detection circuit 30, and a resistance adjustment control circuit 40.

[0035] Among them, the drive chip 10 has a first drive signal port Vo, a second drive signal port V E and a forward bias output port Vcc. The first drive signal port Vo is conducted with the gate G of the IGBT, and the second drive signal port V E is conducted with the emitter E of the IGBT. The first drive signal port Vo and the second drive signal port V E are used to output drive signals, and the forward bias output port Vcc is used to output a forward voltage.

[0036] The drive resistance adjustment circuit 20 is connected between the first drive signal port Vo and the gate G of the IGBT, and the magnitude of the drive resistance formed by the drive resistance adjustment circuit 20 is adjustable.

[0037] The spike voltage detection circuit 30 is connected to the gate G of the IGBT that is conducted with the first drive signal port Vo, and the spike voltage detection circuit 30 is configured to monitor whether a spike voltage appears when the IGBT is turned off.

[0038] The resistance adjustment control circuit 40 is connected between the spike voltage detection circuit 30 and the drive resistance adjustment circuit 20, and is configured to reduce the resistance formed by the drive resistance adjustment circuit 20 when a spike voltage is detected during the turn-off of the IGBT.

[0039] In the IGBT drive circuit according to the embodiments of the present disclosure, when the IGBT is turned off, the peak voltage detection circuit 30 monitors whether there is a peak voltage, so as to select a resistance value of the drive resistor that is smaller than that in the normal operating state. When a peak voltage appears, the drive resistor during turn-off is reduced to provide an additional rapid discharge path for the accumulated charge at the IGBT gate, thereby suppressing the gate peak voltage, ensuring that the IGBT is not mis-triggered, and realizing the function of protecting the IGBT during turn-off.

[0040] Among them, "mis-triggering" means that two IGBTs in the same bridge arm connected to the positive and negative poles of the busbar are turned on simultaneously. At this time, it is equivalent to a short circuit between the positive and negative poles of the busbar, and a large amount of current will pass through the IGBTs, causing short-circuit damage. Then the power conversion device will stop working. Preventing mis-triggering can prevent the IGBTs from being damaged by short circuit and ensure the normal operation of the device.

[0041] In some embodiments, as Figure 2 shown, the drive resistor adjustment circuit 20 includes: a first drive resistor R1, a first MOS transistor Q1, a second drive resistor R2, and a third anti-reverse diode D3. The first drive resistor R1 and the second drive resistor R2 are used to drive the IGBT switch to control the current magnitude.

[0042] Among them, the first end of the first drive resistor R1 is connected to the first drive signal port Vo, the second end of the first drive resistor R1 is connected to the gate G of the IGBT, and the first MOS transistor Q1, the second drive resistor R2, and the third anti-reverse diode D3 are connected in series and then connected in parallel with the first drive resistor R1. The positive pole of the third anti-reverse diode D3 is connected to the first drive resistor R1, and the negative pole is connected to the second drive resistor R2. The MOS transistor is an insulated gate field effect transistor, and its full English name is "metal oxide semiconductor".

[0043] In this embodiment, when the IGBT is turned off, if the voltage at the gate G of the IGBT is normal, the first gate g1 of the first MOS transistor Q1 is turned off through the resistor adjustment control circuit 40, and the drive resistor is the first drive resistor R1; if a peak voltage is detected through the peak voltage detection circuit 30, the first MOS transistor Q1 is turned on through the resistor adjustment control circuit 40, and the drive resistor is the resistor formed by the parallel connection of the first drive resistor R1 and the second drive resistor R2. The resistance of the parallel connection is smaller than the resistance of R1. Thus, an additional rapid discharge path can be provided for the accumulated charge at the gate G of the IGBT, thereby suppressing the gate peak voltage, ensuring that the IGBT is not mis-triggered, and realizing the function of protecting the IGBT during turn-off.

[0044] In some embodiments, as Figure 2As shown, the driving chip 10 has a forward bias output port Vcc, and the first gate g1 of the first MOS transistor Q1 is connected to the forward bias output port Vcc and the resistance adjustment control circuit 40.

[0045] Among them, the resistance adjustment control circuit 40 is configured to ground the first gate g1 of the first MOS transistor Q1 to turn it off and make the driving resistance be the first driving resistance R1 when the voltage is normal after the IGBT is turned off; and when a spike voltage is detected, make the voltage at the connection between the first gate g1 of the first MOS transistor Q1 and the resistance adjustment control circuit 40 lower than the voltage of the forward bias output port Vcc to turn on the first MOS transistor Q1 so that the driving resistance is the resistance formed by the parallel connection of the first driving resistance R1 and the second driving resistance R2.

[0046] This embodiment can control the voltage applied to the first gate g1 of the first MOS transistor Q1 through the resistance adjustment control circuit 40 to control the on / off of the first MOS transistor Q1, so that when there is a spike voltage after the IGBT is turned off, the driving resistance is reduced by turning on the first MOS transistor Q1 to make the driving resistance be the resistance formed by the parallel connection of the first driving resistance R1 and the second driving resistance R2 compared with the normal voltage of the gate G of the IGBT. Thus, an additional rapid discharge channel can be provided for the accumulated charge of the gate G of the IGBT, thereby suppressing the gate spike voltage, ensuring that the IGBT is not mis-triggered, and realizing the function of protecting the IGBT when it is turned off.

[0047] In some embodiments, the driving chip 10 has a forward bias output port Vcc, and the first gate g1 of the first MOS transistor Q1 is connected to the forward bias output port Vcc through a first protection resistor R3. This embodiment can play a current limiting role when the first gate g1 of the first MOS transistor Q1 is grounded, preventing the voltage applied by the forward bias output port Vcc to the first MOS transistor Q1 from being too large, so as to avoid damaging the driving chip 10 or the first MOS transistor Q1.

[0048] In some embodiments, as Figure 2 shown, the spike voltage detection circuit 30 includes: a PNP type triode Q4, a breakdown diode Z1, a first anti-reverse diode D1, a second protection resistor R7, and a third protection resistor R9. If the gate G voltage of the IGBT exceeds the IGBT turn-on threshold, the breakdown diode Z1 conducts; the first anti-reverse diode D1 is configured to only allow the accumulated charge of the gate G of the IGBT to be released outward and prevent the charge from flowing reversely toward the gate G of the IGBT. The positive electrode of the first anti-reverse diode D1 is connected to the breakdown diode Z1, and the negative electrode is connected to the second protection resistor R7. The second protection resistor R7 can prevent the gate G and the emitter E of the IGBT from being short-circuited; the third protection resistor R9 is used to prevent the gate G voltage of the IGBT from being too large and damaging the PNP type triode Q4.

[0049] Among them, the breakdown diode Z1, the first anti-reverse diode D1, and the second protection resistor R7 are connected in series in sequence. The second protection resistor R7 is connected to the resistance adjustment control circuit 40 and is also connected to the emitter E of the IGBT. The emitter of the PNP transistor Q4 is connected to the breakdown diode Z1, the collector of the PNP transistor Q4 is directly connected to the gate G of the IGBT, and the base of the PNP transistor Q4 is connected to the gate G of the IGBT through the third protection resistor R9.

[0050] In this embodiment, by setting the breakdown diode Z1 in the spike voltage detection circuit 30, reliable detection can be performed when there is a spike voltage after the IGBT is turned off, so as to timely reduce the driving resistance to release excess charge.

[0051] In some embodiments, as Figure 2 shown, the driving chip 10 has a second driving signal port V E that is electrically connected to the emitter E of the IGBT. The connection point between the spike voltage detection circuit 30 and the resistance adjustment control circuit 40 is connected to the second driving signal port V E through the fourth protection resistor R8. By setting the fourth protection resistor R8, protection can be formed for the spike voltage detection circuit 30 and the resistance adjustment control circuit 40, especially to prevent damage to the NPN transistor Q3 in the adjustment control circuit 40 due to excessive voltage. Moreover, the fourth protection resistor R8 can prevent the gate G and the emitter E of the IGBT from being short-circuited.

[0052] In some embodiments, as Figure 2 shown, the driving chip 10 has a second driving signal port V E that is electrically connected to the emitter E of the IGBT. The resistance adjustment control circuit 40 includes: a second anti-reverse diode D2 and a freewheeling capacitor C1 connected in series, a second MOS transistor Q2, and an NPN transistor Q3.

[0053] Among them, the positive electrode of the second anti-reverse diode D2 is connected to the circuit where the first driving signal port Vo is connected to the gate G of the IGBT, and the connection point is located between the driving resistance adjustment circuit 20 and the spike voltage detection circuit 30. One end of the freewheeling capacitor C1 far from the second anti-reverse diode D2 is connected to the second driving signal port V E .

[0054] The second source electrode s2 of the second MOS transistor Q2 is connected to the driving resistance adjustment circuit 20. Specifically, the second source electrode s2 is connected to the first gate g1 of the first MOS transistor Q1; the second drain electrode d2 of the second MOS transistor Q2 is connected to the second driving signal port V E and the second gate g2 of the second MOS transistor Q2 is connected between the second anti-reverse diode D2 and the freewheeling capacitor C1.

[0055] The NPN bipolar transistor Q3 has its collector connected to the second gate g2, its emitter connected to the second drive signal port V E and its base connected to one end where the peak voltage detection circuit 30 is connected to the emitter E of the IGBT.

[0056] In this embodiment, when the peak voltage detection circuit 30 detects a peak voltage, the voltage at the connection between the first gate g1 of the first MOS transistor Q1 and the resistance adjustment control circuit 40 can be adjusted through the cooperation of various components to control the on / off of the first MOS transistor Q1, so that different drive resistances are adopted after the IGBT is turned off and a peak appears and under normal voltage, to ensure the reliable operation of the IGBT drive circuit.

[0057] In some embodiments, the drive resistance adjustment circuit 20 includes: a first drive resistance R1, a first MOS transistor Q1, a second drive resistance R2, and a third anti - reverse diode D3; the first end of the first drive resistance R1 is electrically connected to the first drive signal port Vo, the second end of the first drive resistance R1 is electrically connected to the gate G of the IGBT, and the first MOS transistor Q1, the second drive resistance R2, and the third anti - reverse diode D3 are connected in series and then connected in parallel with the first drive resistance R1. Among them, the first gate g1 of the first MOS transistor Q1 is connected to the second source s2 of the second MOS transistor Q2.

[0058] In some embodiments, as Figure 2 shown, the resistance adjustment control circuit 40 further includes:

[0059] A fifth protection resistance R4, connected between the drive resistance adjustment circuit 20 and the second source s2;

[0060] A sixth protection resistance R6, connected between the second gate g2 and the collector of the NPN bipolar transistor Q3; and / or

[0061] A seventh protection resistance R5, one end of which is connected between the second anti - reverse diode D2 and the free - wheeling capacitor C1, and the other end is connected between the second gate g2 and the collector of the NPN bipolar transistor Q3.

[0062] In this embodiment, both the fifth protection resistance R4 and the first protection resistance R3 can play a current - limiting protection role when the second MOS transistor Q2 is turned on and the gate g1 of the first MOS transistor Q1 is grounded, preventing excessive current from damaging the first MOS transistor Q1, the second MOS transistor Q2, or the drive chip 10. Both the seventh protection resistance R5 and the sixth protection resistance R6 can play a current - limiting protection role when the second gate g1 of the second MOS transistor Q2 is connected to one end of the free - wheeling capacitor C1 or through, and after the gate g2 of Q2 is connected to one end of C1 or grounded through the NPN bipolar transistor Q3.

[0063] Next, the specific structure of the IGBT drive circuit of the present disclosure will be described in conjunction with Figure 2 to illustrate.

[0064] The driving chip 10 has a first driving signal port Vo, a second driving signal port V E and a forward bias output port Vcc, and the IGBT has a gate G and an emitter E. The first driving signal port Vo is connected to the gate G of the IGBT, and the second driving signal port V E is connected to the emitter E of the IGBT.

[0065] The devices used include a first driving resistor R1 and a second driving resistor R2, a breakdown diode Z1, a first reverse protection diode D1, a second reverse protection diode D2, a third reverse protection diode D3, a freewheeling capacitor C1, protection resistors R3, R4, R5, R6, R7, R8, R9, an N-type first MOS transistor Q1, an N-type second MOS transistor Q2, an NPN-type triode Q3, and a PNP-type triode Q4.

[0066] As Figure 2 shown, a first driving resistor R1 is provided between the first driving signal port Vo and the gate G of the IGBT, and the second driving resistor R2, the N-type first MOS transistor Q1, and the third reverse protection diode D3 are connected in series and then connected in parallel with both ends of the first driving resistor R1.

[0067] The first drain d1 of the first MOS transistor Q1 and one end of the first driving resistor R1 are connected to the first driving signal port Vo, and the first source s1 of the first MOS transistor Q1 is connected to the second driving resistor R2. The first gate g1 of the first MOS transistor Q1 is connected to the forward bias output port Vcc, and the first gate g1 of the first MOS transistor Q1 is connected to the second source s2 of the N-type second MOS transistor Q2 through a fifth protection resistor R4. The second drain d2 of the second MOS transistor Q2 is connected to the second driving signal port V E connection, and the second gate g2 of the second MOS transistor Q2 is connected between the freewheeling capacitor C1 and the second reverse diode D2 through a seventh protection resistor R5. The positive electrode of the second reverse diode D2 is connected between the first driving signal port Vo and the second driving signal port V E and is located between the third reverse diode D3 and the connection point between the collector of the PNP-type triode Q4 and the gate G of the IGBT. One end of the freewheeling capacitor C1 far from the second reverse diode D2 is connected to the second driving signal port V E connection.

[0068] The collector of the NPN-type triode Q3 is between the second gate g2 of the second MOS transistor Q2 and a sixth protection resistor R6, and one end of the seventh protection resistor R5 is connected between the second gate g2 and the sixth protection resistor R6. The emitter of the NPN-type triode Q3 is connected to the second driving signal port V EOn the connection line between the emitter E of the IGBT and is located between the connection points of the freewheeling capacitor C1 and the fourth protection resistor R8 with the connection line. The base of the NPN transistor Q3 is connected to the emitter of the PNP transistor Q4 in series through the second protection resistor R7, the first anti-reverse diode D1, and the breakdown diode Z1 in sequence. The collector of the PNP transistor Q4 is directly connected and conducts with the gate G of the IGBT. The base of the PNP transistor Q4 is connected to the gate G of the IGBT through the third protection resistor R9, and the voltage of the gate G of the IGBT can be monitored in real time when the IGBT is turned off.

[0069] The working principle of this IGBT drive circuit is as follows:

[0070] 1. The gate G voltage of the IGBT is normal

[0071] When the first drive signal port Vo outputs the turn-on signal Von, the PNP transistor Q4 does not work. Therefore, the NPN transistor Q3 is not conducting, and the second anti-reverse diode D2 conducts. The freewheeling capacitor C1 is charged, and at the same time, a voltage is applied to the second MOS transistor Q2 through the seventh protection resistor R5 to make it conduct, pulling down the potential at the front end of the fifth protection resistor R4. The voltage of the first gate g1 of the first MOS transistor Q1 is grounded and turned off. At this time, the driving resistance value is the resistance value of R1.

[0072] When Vo outputs the turn-off signal -Voff, the PNP transistor Q4 conducts and starts to work. Since the gate G voltage of the IGBT is normal, the breakdown diode Z1 is not broken down, and the NPN transistor Q3 still does not conduct. At this time, the second reverse diode D2 does not work. The freewheeling capacitor C1 applies a voltage to turn on the second MOS transistor Q2, and the voltage of the first gate g1 of the first MOS transistor Q1 is grounded and turned off. At this time, the driving resistance value is the resistance value of R1.

[0073] 2. When the IGBT is turned off, a voltage spike appears at the gate

[0074] When the first drive signal port Vo outputs the negative turn-off signal -Voff and a spike voltage appears at the gate, if the spike voltage exceeds the IGBT turn-on threshold, the breakdown diode Z1 is broken down, the first anti-reverse diode D1, and the NPN transistor Q3 start to work, pulling down the potential at the front end of the sixth protection resistor R6, making the voltage of the second gate g2 of the second MOS transistor Q2 grounded and turned off. Therefore, the positive bias output port Vcc continuously applies a positive bias to the first MOS transistor Q1, making the first MOS transistor Q1 conduct, and the second drive resistor R2 is connected into the circuit and is in parallel with R1. At this time, the driving resistance value is R1·R2 / (R1 + R2), and the driving resistance value becomes smaller. At this time, the charge of the gate G of the IGBT is quickly discharged through the low-impedance drive circuit, and the voltage spike is suppressed.

[0075] Secondly, the present disclosure also provides a power conversion device, including the IGBT drive circuit of the above embodiment. The power conversion from direct current to alternating current is an inversion process, and the power conversion from alternating current to direct current is a rectification process. Both of these processes are achieved by the alternating switching of several IGBTs, that is, no matter which working state, the IGBT is always constantly turned on and off.

[0076] Therefore, by adopting the IGBT drive circuit of the present disclosure, when the IGBT is turned off and a spike voltage appears, an additional rapid discharge channel is provided for the accumulated charge on the IGBT gate by reducing the drive resistance during turn-off, thereby suppressing the gate spike voltage, ensuring that the IGBT is not mis-triggered, realizing the function of protecting the IGBT during turn-off, preventing the IGBT from being short-circuited and damaged, and thus ensuring the normal operation of the power conversion device.

[0077] It should also be noted that the functional blocks, components, systems, devices, or circuits described herein can be implemented using hardware, software, or a combination of hardware and software. For example, one or more integrated circuits can be used to implement the disclosed embodiments, and the one or more integrated circuits are programmed to perform the functions, tasks, methods, actions, or other operational characteristics described herein for the disclosed embodiments. The one or more integrated circuits can include, for example, one or more processors or configurable logic devices (CLDs), or a combination thereof. The one or more processors can be, for example, one or more central processing units (CPUs), controllers, microcontrollers, microprocessors, hardware accelerators, ASICs (application specific integrated circuits), or other integrated processing devices. The one or more CLDs can be, for example, one or more CPLDs (complex programmable logic devices), FPGAs (field programmable gate arrays), PLAs (programmable logic arrays), reconfigurable logic circuits, or other integrated logic devices. Additionally, an integrated circuit including one or more processors can be programmed to execute software, firmware, code, or other program instructions embodied in one or more non-transitory tangible computer-readable media to perform the functions, tasks, methods, actions, or other operational characteristics described herein for the disclosed embodiments. An integrated circuit including one or more CLDs can also be programmed using logic code, logic definitions, hardware description languages, configuration files, or other logical instructions embodied in one or more non-transitory tangible computer-readable media to perform the functions, tasks, methods, actions, or other operational characteristics described herein for the disclosed embodiments. Further, the one or more non-transitory tangible computer-readable media can include, for example, one or more data storage devices, memory devices, flash memories, random access memories, read-only memories, programmable memory devices, reprogrammable storage devices, hard disk drives, floppy disks, DVDs, CD-ROMs, or any other non-transitory tangible computer-readable media. Other variations can also be implemented while still utilizing the techniques described herein.

[0078] Unless stated otherwise, terms such as “first” and “second” are used arbitrarily to distinguish the elements described by such terms. Therefore, these terms are not necessarily intended to indicate a temporal or other precedence of such elements.

[0079] The above has introduced in detail an IGBT driving circuit and a power conversion device provided by the present disclosure. Specific embodiments are applied in this text to elaborate on the principle and implementation manner of the present disclosure. The description of the above embodiments is only used to help understand the method and its core idea of the present disclosure. It should be noted that for those of ordinary skill in the art in this technical field, without departing from the principle of the present disclosure, several improvements and modifications can also be made to the present disclosure, and these improvements and modifications also fall within the protection scope of the claims of the present disclosure.

Claims

1. An IGBT driving circuit, characterized in that: include: A driving chip (10) having a first driving signal port (Vo); A drive resistance adjustment circuit (20) connected between the first drive signal port (Vo) and the gate (G) of the IGBT, wherein the drive resistance formed by the drive resistance adjustment circuit (20) is adjustable; A peak voltage detection circuit (30) connected to a gate (G) of an IGBT that is conductive with the first drive signal port (Vo), wherein the peak voltage detection circuit (30) is configured to monitor whether a peak voltage occurs when the IGBT is turned off; and A resistance adjustment control circuit (40) is connected between the peak voltage detection circuit (30) and the drive resistance adjustment circuit (20), and is configured to reduce the resistance formed by the drive resistance adjustment circuit (20) when the peak voltage is detected when the IGBT is turned off; The peak voltage detection circuit (30) comprises: a PNP transistor (Q4), a breakdown diode (Z1), a first anti-reverse diode (D1), a second protection resistor (R7) and a third protection resistor (R9); The breakdown diode (Z1), the first anti-reverse diode (D1) and the second protection resistor (R7) are connected in series in sequence, the second protection resistor (R7) is connected to the resistance adjustment control circuit (40), the emitter of the PNP transistor (Q4) is connected to the breakdown diode (Z1), the collector of the PNP transistor (Q4) is directly connected to the gate (G) of the IGBT, and the base of the PNP transistor (Q4) is connected to the gate (G) of the IGBT through the third protection resistor (R9).

2. The IGBT driving circuit according to claim 1, characterized in that: The driving resistance adjustment circuit (20) comprises: a first driving resistor (R1), a first MOS tube (Q1), a second driving resistor (R2) and a third anti-reverse diode (D3); The first end of the first drive resistor (R1) is connected to the first drive signal port (Vo), the second end of the first drive resistor (R1) is connected to the gate (G) of the IGBT, and the first MOS tube (Q1), the second drive resistor (R2) and the third anti-reverse diode (D3) are connected in series and then connected in parallel with the first drive resistor (R1).

3. The IGBT driving circuit according to claim 2, characterized in that: The driving chip (10) has a forward bias output port (Vcc), and the first gate (g1) of the first MOS tube (Q1) is connected to the forward bias output port (Vcc) and the resistance adjustment control circuit (40); The resistance adjustment control circuit (40) is configured to ground the first gate (g1) of the first MOS tube (Q1) and turn it off when the voltage is normal after the IGBT is turned off, so that the driving resistance is the first driving resistance (R1); and when a peak voltage is detected, the voltage at the connection point between the first gate (g1) of the first MOS tube (Q1) and the resistance adjustment control circuit (40) is lower than the voltage of the forward bias output port (Vcc), so as to turn on the first MOS tube (Q1) so that the driving resistance is the resistance formed by the first driving resistance (R1) and the second driving resistance (R2) connected in parallel.

4. The IGBT driving circuit according to claim 2, characterized in that: The driving chip (10) has a forward bias output port (Vcc), and the first gate (g1) of the first MOS tube (Q1) is connected to the forward bias output port (Vcc) via a first protection resistor (R3).

5. The IGBT driving circuit according to claim 1, characterized in that: The driving chip (10) has a second driving signal port (V E ), the connection point between the peak voltage detection circuit (30) and the resistance adjustment control circuit (40) is connected to the second drive signal port (V E )connect.

6. The IGBT driving circuit according to claim 1, characterized in that: The driving chip (10) has a second driving signal port (V E ), the resistance adjustment control circuit (40) comprises: A second anti-reverse diode (D2) and a freewheeling capacitor (C1) are connected in series, wherein the positive electrode of the second anti-reverse diode (D2) is connected to a circuit connecting the first drive signal port (Vo) and the gate (G) of the IGBT, and the connection point is located between the drive resistance adjustment circuit (20) and the peak voltage detection circuit (30), and one end of the freewheeling capacitor (C1) is connected to the second drive signal port (Vo). E )connect; A second MOS tube (Q2), a second source electrode (s2) of which is connected to the driving resistance adjustment circuit (20), and a second drain electrode (d2) of which is connected to the second driving signal port (V E ), the second gate (g2) is connected between the second anti-reverse diode (D2) and the freewheeling capacitor (C1); and An NPN transistor (Q3), whose collector is connected to the second gate (g2) and whose emitter is connected to the second drive signal port (V E ) is connected, and the base is connected to one end of the peak voltage detection circuit (30) and the emitter (E) of the IGBT.

7. The IGBT driving circuit according to claim 6, characterized in that: The driving resistance adjustment circuit (20) comprises: a first driving resistor (R1), a first MOS transistor (Q1), a second driving resistor (R2) and a third anti-reverse diode (D3); the first end of the first driving resistor (R1) is connected to the first driving signal port (Vo), the second end of the first driving resistor (R1) is connected to the gate (G) of the IGBT, and the first MOS transistor (Q1), the second driving resistor (R2) and the third anti-reverse diode (D3) are connected in series and then connected in parallel with the first driving resistor (R1); The first gate electrode (g1) of the first MOS transistor (Q1) is connected to the second source electrode (s2) of the second MOS transistor (Q2).

8. The IGBT driving circuit according to claim 6, characterized in that: The resistance adjustment control circuit (40) further includes: a fifth protection resistor (R4), connected between the driving resistance adjustment circuit (20) and the second source (s2); a sixth protection resistor (R6), connected between the second gate (g2) and the collector of the NPN transistor (Q3); and / or A seventh protection resistor (R5) has one end connected between the second anti-reverse diode (D2) and the freewheeling capacitor (C1), and the other end connected between the second gate (g2) and the collector of the NPN transistor (Q3).

9. A power conversion device, characterized in that: It comprises the IGBT driving circuit described in any one of claims 1 to 8.

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