Method of forming an integrated circuit device

Abstract

Methods of forming integrated circuit devices are provided. A method of forming an integrated circuit device can include forming a first insulating layer and a via contact on a substrate. The substrate can include an upper surface facing the via contact, the via contact can be in the first insulating layer and can include a lower surface facing the substrate and an upper surface opposite the lower surface. The method can also include forming a second insulating layer and a metal line on the via contact. The metal line can be in the second insulating layer and can include a lower surface facing the substrate and in contact with the upper surface of the via contact. The lower surface of the metal line and an interface between the metal line and the via contact can each have a first width in a horizontal direction parallel to the upper surface of the substrate.

Description

Technical Field

[0001] This disclosure generally relates to the field of electronics, and more specifically to integrated circuit devices. Background Technology

[0002] Fully-aligned wire structures have been introduced to provide a stable electrical connection between the via contact and the wire subsequently formed on the via contact. However, due to overlay error during wire formation, fully-aligned wire structures may not provide uniform surface resistance between the via contact and the wire. Summary of the Invention

[0003] According to some embodiments of the present invention, a method of forming an integrated circuit device may include sequentially forming via contacts and metal lines through separate processes. The via contact may be an enlarged via contact having a width wider than the width of the metal line. The difference between the width of the via contact and the width of the metal line may be greater than the coverage margin between the via contact and the metal line, such that the metal line may include portions that overlap and fully contact the underlying via contact even if coverage errors exist during the formation of the metal line. Furthermore, the method may include forming fully aligned metal lines by forming recesses above the via contacts prior to forming the metal lines.

[0004] According to some embodiments of the present invention, a method of forming an integrated circuit device may include forming a first insulating layer and a via contact on a substrate. The substrate may include an upper surface facing the via contact, and the via contact may be in the first insulating layer and may include a lower surface facing the substrate and an upper surface opposite to the lower surface. The method may further include forming a second insulating layer and a metal line on the via contact. The metal line may be in the second insulating layer and may include a lower surface facing the substrate and contacting the upper surface of the via contact. The lower surface of the metal line and the interface between the metal line and the via contact may both have a first width in a horizontal direction parallel to the upper surface of the substrate.

[0005] According to some embodiments of the present invention, a method of forming an integrated circuit device may include forming a first insulating layer and a via contact on a substrate. The substrate may include an upper surface facing the via contact, and the via contact may include a lower surface facing the substrate and an upper surface opposite to the lower surface that may be recessed toward the substrate relative to the first insulating layer. The method may further include forming a second insulating layer and a metal line on the via contact. The metal line may be in the second insulating layer and may contact a portion of the upper surface of the via contact. The via contact may be on opposite sides in a horizontal direction parallel to the upper surface of the substrate, and the metal line may not overlap the opposite side of the via contact.

[0006] According to some embodiments of the present invention, a method of forming an integrated circuit device may include forming a first insulating layer and a via contact on a substrate. The via contact may be in the first insulating layer, and the substrate may include an upper surface facing the via contact. The method may further include forming a first metal line and a second metal line on the via contact and the first insulating layer. The first metal line and the second metal line may be spaced apart from each other in a horizontal direction parallel to the upper surface of the substrate. The first metal line is spaced apart from the upper surface of the substrate by a first distance and may contact the via contact, and the second metal line is spaced apart from the upper surface of the substrate by a second distance and may contact the first insulating layer, the second distance being greater than the first distance. The first metal line may be included on a first opposite side in the horizontal direction, and the via contact may be included on a second opposite side in the horizontal direction, the first opposite side being between the second opposite sides. Attached Figure Description

[0007] Figure 1 This is a flowchart of a method for forming an integrated circuit device according to some embodiments of the inventive concept.

[0008] Figure 2 and Figure 4 This is a top view illustrating a method for forming an integrated circuit device according to some embodiments of the inventive concept.

[0009] Figure 3 and Figure 5A They are along Figure 2 and Figure 4 A cross-sectional view taken from line A-A'.

[0010] Figure 5B yes Figure 5A A magnified view of region R.

[0011] Figure 6 This is a flowchart of a method for forming an integrated circuit device according to some embodiments of the inventive concept.

[0012] Figure 7 and Figure 8 It shows along Figure 2 A cross-sectional view of the method for forming an integrated circuit device, taken from line A-A'.

[0013] Figure 9 This is a flowchart of a method for forming an integrated circuit device according to some embodiments of the inventive concept.

[0014] Figure 10 It shows along Figure 2 A cross-sectional view of the method for forming an integrated circuit device, taken from line A-A'.

[0015] Figure 11This is a flowchart of a method for forming an integrated circuit device according to some embodiments of the inventive concept.

[0016] Figure 12 and Figure 13 It shows along Figure 4 A cross-sectional view of the method for forming an integrated circuit device, taken from line A-A'.

[0017] Figure 14 This is a flowchart of a method for forming an integrated circuit device according to some embodiments of the inventive concept.

[0018] Figure 15 It shows along Figure 4 A cross-sectional view of the method for forming an integrated circuit device, taken from line A-A'. Detailed Implementation

[0019] Figure 1 This is a flowchart of a method for forming an integrated circuit device according to some embodiments of the inventive concept. Figure 2 and Figure 4 This is a top view illustrating a method for forming an integrated circuit device according to some embodiments of the inventive concept. Figure 3 and Figure 5A They are along Figure 2 and Figure 4 A cross-sectional view taken from line A-A'. Figure 5B yes Figure 5A A magnified view of region R.

[0020] Reference Figures 1 to 3 One approach may include forming a first insulating layer 22 and a via contact 24 (box 100) on a substrate 10. The via contact 24 may be within the first insulating layer 22. In some embodiments, a lower layer structure 12 may be formed on the substrate 10 prior to the formation of the first insulating layer 22 and the via contact 24. The lower layer structure 12 may include various elements of an integrated circuit device (e.g., source / drain regions, capacitors, word lines, and / or bit lines), and the via contact 24 may be electrically connected to one of the elements of the integrated circuit device. The substrate 10 may include an upper surface 10u facing the via contact 24.

[0021] The substrate 10 may include one or more semiconductor materials, such as Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, and / or InP. In some embodiments, the substrate 10 may be a bulk substrate (e.g., a bulk silicon substrate) or a semiconductor-on-insulator (SOI) substrate.

[0022] The pathway contact 24 may include a metal (e.g., Cu, Co, Ru, Mo, Mn, and / or Nb). Although Figure 3The diagram shows that the via contact 24 is formed of a single layer, but the via contact 24 may include multiple layers (e.g., a metal layer, a diffusion barrier layer, and / or an etch stop layer). In some embodiments, such as... Figure 2 In the top view shown, the via contact 24 may be surrounded by the first insulating layer 22. The via contact 24 may include opposite sides 24s in the first horizontal direction D1. The first horizontal direction D1 may be parallel to the upper surface 10u of the substrate 10.

[0023] In some implementations, such as Figure 3 As shown, the first insulating layer 22 may include an initial first insulating layer 20 and a cap insulating layer 21 sequentially formed on the substrate 10. In some embodiments, the cap insulating layer 21 may be omitted. Both the initial first insulating layer 20 and the cap insulating layer 21 may include an insulating material (e.g., SiO2, SiCOH, or SiOC). The first insulating layer 22 may be spaced apart from the substrate 10 in a third direction D3. The third direction D3 may be a vertical direction and may be perpendicular to the first horizontal direction D1.

[0024] The via contact 24 may include an upper surface 24u recessed toward the substrate 10 relative to the first insulating layer 22, and the recess 26 may be defined by the opposite side 22s of the first insulating layer 22 and the upper surface 24u of the via contact 24. The first insulating layer 22 may expose the upper surface 24u of the via contact 24.

[0025] Reference Figure 1 , Figure 4 , Figure 5A and Figure 5B The method may further include forming a second insulating layer 30 and metal wires 34_1 and 34_2 (box 200). Metal wires 34_1 and 34_2 may be in the second insulating layer 30. To illustrate the via contact 24 below, in Figure 4 The second insulating layer 30 is not shown. Each of the metal wires 34_1 and 34_2 may extend longitudinally in the second horizontal direction D2, as shown. Figure 4 As shown. The second horizontal direction D2 can be parallel to the upper surface 10u of the substrate 10. In some embodiments, the second horizontal direction D2 can be perpendicular to the first horizontal direction D1.

[0026] Metal wires 34_1 and 34_2 may include a first metal wire 34_1 and a second metal wire 34_2. The first metal wire 34_1 and the second metal wire 34_2 are spaced apart from each other in a first horizontal direction D1. The first metal wire 34_1 may contact the through contact 24, and the second metal wire 34_2 may contact the first insulating layer 22.

[0027] The first metal line 34_1 may have a first width W1 in the first horizontal direction D1. Although Figure 5AThe diagram shows that the first metal line 34_1 has a uniform width (i.e., a first width W1) along the third direction D3 in the first horizontal direction D1, but the first metal line 34_1 may have a varying width along the third direction D3 in the first horizontal direction D1. In some embodiments, the lower surface of the first metal line 34_1 may face the substrate 10 and may contact a portion of the upper surface 24u of the via contact 24. (Refer to...) Figure 5B The lower surface of the first metal line 34_1 may have a first width W1 in the first horizontal direction D1, and the interface between the first metal line 34_1 and the passage contact 24 may also have a first width W1 in the first horizontal direction D1.

[0028] The upper surface 24u of the passage contact 24 may have a second width W2 in the first horizontal direction D1, such as Figure 5B As shown. The second width W2 can be wider than the first width W1 of the lower surface of the first metal line 34_1. In some embodiments, the difference between the second width W2 and the first width W1 can be equal to or greater than the coverage margin between the via contact 24 and the first metal line 34_1, such that the entire lower surface of the first metal line 34_1 contacts the via contact 24 even in the event of coverage errors during the formation of the first metal line 34_1. For example, the difference between the second width W2 and the first width W1 can be approximately 6 nanometers (nm) or greater. In some embodiments, the second width W2 can be approximately 18 nm, and the first width W1 can be approximately 12 nm. Coverage margin can refer to the alignment margin between two individual stacked elements.

[0029] Each second metal wire 34_2 may have a third width W3 in the first horizontal direction D1. Although Figure 4 Figure 5 shows that the first width W1 and the third width W3 are equal, but in some embodiments, the first width W1 may be different from the third width W3.

[0030] Reference Figure 5B The lower portion of the first metal wire 34_1 may be located in a recess 26 defined by the opposite side 22s of the first insulating layer 22 and the upper surface 24u of the through contact 24. In some embodiments, the lower portion of the first metal wire 34_1 may be spaced apart from the opposite side 22s of the first insulating layer 22. In some embodiments, a second insulating layer 30 may be formed in the recess 26 and may separate the lower portion of the first metal wire 34_1 from the opposite side 22s of the first insulating layer 22.

[0031] In some embodiments, the first metal wire 34_1 may not overlap with the opposite side 24s of the path contact 24, such as... Figure 5BAs shown. In some embodiments, the opposite side of the first metal wire 34_1 in the first horizontal direction D1 may be between the opposite sides 24s of the passage contact 24, such as... Figure 5B As shown.

[0032] Refer again Figure 5A The lower surface of the first metal line 34_1 may be spaced from the substrate 10 by a first distance d1 in the third direction D3, and the lower surface of the second metal line 34_2 may be spaced from the substrate 10 by a second distance d2 in the third direction D3. The second distance d2 may be longer than the first distance d1. For example, the second distance d2 may be about 5 nm longer than the first distance d1 or greater. The upper surfaces of the first metal line 34_1 and the second metal line 34_2 may be coplanar with each other.

[0033] Each of metal lines 34_1 and 34_2 may include a diffusion barrier layer 31 and a metal layer 32 sequentially stacked on the substrate 10. The diffusion barrier layer 31 may include, for example, a metal and / or a metal nitride (e.g., tantalum (Ta), tantalum nitride (TaN), titanium (Ti), and / or titanium nitride (TiN)) and may be formed using, for example, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or plating processes (e.g., electroplating). The metal layer 32 may include a metal (e.g., Cu, Co, Ru, Mo, Mn, and / or Nb) and may be formed using, for example, PVD, ALD, CVD, and / or plating processes. In some embodiments, the metal layer 32 may include the same material as that included in the via contact 24. For example, both the via contact 24 and the metal layer 32 may include Cu.

[0034] The second insulating layer 30 may include an insulating material. In some embodiments, the second insulating layer 30 may include an insulating material having a low dielectric constant (k) (e.g., a dielectric constant below 3.0). In some embodiments, the second insulating layer 30 may be formed using a process capable of forming the second insulating layer 30 in a narrow space. For example, the second insulating layer 30 may be formed using a flowable CVD process and / or a spin-coating process. In some embodiments, the second insulating layer 30 may include a cavity 42 between one of the first metal line 34_1 and the second metal line 34_2. The cavity 42 may include, for example, air and / or an inert gas (e.g., argon, nitrogen, or helium). In some embodiments, the second insulating layer 30 may include a SiCOH layer that can be formed by a plasma-enhanced chemical vapor deposition (PECVD) process, and the SiCOH layer may have a dielectric constant of approximately 2.7.

[0035] Figure 6 This is a flowchart illustrating a method for forming an integrated circuit device according to some embodiments of the inventive concept, showing... Figure 1 An example of the specific steps in box 100, Figure 7 and Figure 8 It shows along Figure 2 A cross-sectional view of the method for forming an integrated circuit device, taken from line A-A'.

[0036] Reference Figure 1 and Figures 6 to 8 In some embodiments, a first insulating layer 22 and a via contact 24 are formed on the substrate 10. Figure 1 Box 100 in the middle can include, for example, Figure 7 As shown, a first insulating layer 22 and an initial via contact 24p are formed on the substrate 10. Figure 6 (in box 110) and remove a portion of the initial path contact 24p, thus as Figure 8 As shown, a via contact 24 is formed in the first insulating layer 22. Figure 6 (Box 120 in the middle).

[0037] Removing a portion of the initial via contact 24p can form a recess 26 above the upper surface 24u of the via contact 24. This portion of the initial via contact 24p can be removed using various processes (e.g., wet etching and / or dry etching). The depth of the recess 26 in the third direction D3 can be approximately 5 nm or greater.

[0038] Figure 9 This is a flowchart illustrating a method for forming an integrated circuit device according to some embodiments of the inventive concept, showing... Figure 1 Another example of the specific steps in box 100, Figure 10 It shows along Figure 2 A cross-sectional view of the method for forming an integrated circuit device, taken from line A-A'.

[0039] refer to Figure 1 , Figure 3 , Figure 9 and Figure 10 In some embodiments, a first insulating layer 22 and a via contact 24 are formed on the substrate 10. Figure 1 Box 100 in the middle can include, for example, Figure 10 As shown, an initial first insulating layer 20 and a via contact 24 are formed. Figure 9 (in box 150) and as Figure 3 As shown, a cover insulating layer 21 is formed on the initial first insulating layer 20. Figure 9 (Box 160 in the middle).

[0040] Reference Figure 10 In some embodiments, the initial first insulating layer 20 and the via contact 24 may have upper surfaces that are coplanar with each other. (See again...) Figure 3The cap insulating layer 21 can be selectively formed on the initial first insulating layer 20 using, for example, one or more region-selective atomic layer processes, and may not be formed on the via contact 24. After the cap insulating layer 21 is formed, it can be as follows: Figure 3 The recess 26 is defined by the upper surface 24u of the cover insulation layer 21 and the passage contact 24.

[0041] In some embodiments, the cap insulating layer 21 may include porous or dense SiCOH, an ultra-low k (ULK) material having a dielectric constant below 2.5, an extremely low k (ELK) material having a dielectric constant below 2.1, SiCN, SiCON, SiO2, SiN, SiON, AlO, AlN, AlON, HfO, HfN, and / or ZrO. In some embodiments, the cap insulating layer 21 may include a porous low-k material. Low-k materials have a dielectric constant lower than that of silicon dioxide. For example, the cap insulating layer 21 can be formed using processes described by Mackus et al. (From the Bottom-Up: Toward Area-Selective Atomic Layer Deposition with High Selectivity. Chem. Mater. 2019, 31, 2-12) or Bob-Semple et al. (Area-Selective Atomic Layer Deposition Assisted by Self-Assembled Monolayers: A Comparison of Cu, Co, W, and Ru. Chem. Mater. 2019, 31, 1635-1645). In some embodiments, the initial first insulating layer 20 and the cap insulating layer 21 may comprise different materials. For example, the initial first insulating layer 20 may comprise a SiO2 layer, and the cap insulating layer 21 may comprise a SiCOH layer.

[0042] Figure 11 This is a flowchart illustrating a method for forming an integrated circuit device according to some embodiments of the inventive concept, showing... Figure 1 An example of the specific steps in box 200. Figure 12 and Figure 13 It shows along Figure 4 A cross-sectional view of the method for forming an integrated circuit device, taken from line A-A'.

[0043] Reference Figure 1 and Figure 5 and Figures 11 to 13 In some embodiments, a second insulating layer and a metal wire are formed. Figure 1 Box 200 in the middle can include, for example, Figure 12A metal layer 34p is formed as shown. Figure 11 (in box 210) Figure 13 The patterned metal layer 34p shown is shown. Figure 11 (frame 220) and a second insulating layer 30 formed as shown in Figure 5. Figure 11 (Box 230 in the middle).

[0044] In some embodiments, forming the metal layer 34p may include sequentially forming an initial diffusion barrier layer 31p and an initial metal layer 32p. The metal layer 34p may contact the upper surface of the first insulating layer 22 and the upper surface 24u of the via contact 24, and may be as follows: Figure 12 As shown, it is formed in the depression (e.g.) Figure 3 In the recess 26). In some embodiments, the formation of the initial diffusion barrier layer 31p can be omitted, in which case the initial metal layer 32p can contact the upper surface of the first insulating layer 22 and the upper surface 24u of the passage contact 24.

[0045] In some embodiments, the patterned metal layer 34p may include sequentially etching an initial metal layer 32p and an initial diffusion barrier layer 31p until the first insulating layer 22 and the via contact 24 are exposed, thereby forming a first metal line 34_1 and a second metal line 34_2. The first metal line 34_1 may contact only a portion of the upper surface 24u of the via contact 24, and may expose the remaining portion of the upper surface 24u of the via contact 24.

[0046] In some embodiments, forming a second insulating layer 30 may include forming a second insulating layer 30 between the first metal wire 34_1 and the first insulating layer 22, so that the second insulating layer 30 can separate the first metal wire 34_1 from the first insulating layer 22.

[0047] Figure 14 This is a flowchart illustrating a method for forming an integrated circuit device according to some embodiments of the inventive concept, showing... Figure 1 An example of the specific steps in box 200. Figure 15 It shows along Figure 4 A cross-sectional view of the method for forming an integrated circuit device, taken from line A-A'.

[0048] Reference Figure 1 and Figure 5 and Figure 14 and Figure 15 In some embodiments, a second insulating layer 30 and a first metal wire 34_1 are formed. Figure 1 The frame 200 in the middle may include forming a second insulating layer 30. Figure 14 (in box 250), such as Figure 15 An opening 38_1 is formed in the second insulating layer 30 as shown. Figure 14(in the frame 260) and as shown in FIG5, the first metal wire 34_1 is formed in the opening 38_1 of the second insulating layer 30. Figure 14 (Box 270 in the middle).

[0049] In some embodiments, the etch stop layer 36 may be formed prior to the formation of the second insulating layer 30, and a portion of the etch stop layer 36 may be removed simultaneously with the formation of the opening 38_1. The etch stop layer 36 may be a single layer or multiple stacked layers. For example, the etch stop layer 36 may be a single layer comprising SiCN, two stacked layers comprising AlN / oxygen-doped carbide (ODC), AlOx / ODC, or SiCN / SiC, or three stacked layers comprising AlOx / ODC / AlOx. ODC comprises Si, O, and C. The opening 38_1 may be a first opening exposing a portion of the upper surface 24u of the via contact 24, and a second opening 38_2 may also be formed in the second insulating layer 30. The second opening 38_2 may expose the first insulating layer 22.

[0050] Referring back to Figure 5, the first metal wire 34_1 can be formed in the first opening 38_1, and the second metal wire 34_2 can be formed in the second opening 38_2 respectively.

[0051] Example embodiments are described herein with reference to the accompanying drawings. Many different forms and embodiments are possible without departing from the spirit and teachings of this disclosure, and therefore this disclosure should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will convey the scope of this disclosure to those skilled in the art. In the drawings, the dimensions and relative dimensions of layers and regions may be exaggerated for clarity. The same reference numerals always denote the same elements.

[0052] Example embodiments of the inventive concept are described herein with reference to cross-sectional or top views, which are schematic diagrams of intermediate structures between ideal and example embodiments. Thus, variations in the illustrated shape, for example due to manufacturing techniques and / or tolerances, are to be expected. Therefore, the example embodiments of the inventive concept should not be construed as limited to the specific shapes shown herein, but rather include, for example, deviations in shape caused by manufacturing processes.

[0053] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concept pertains. It will also be understood that terms such as those defined in common dictionaries shall be interpreted as having meanings consistent with their meanings in the context of the relevant field and shall not be interpreted in an idealized or overly formal manner unless expressly defined herein. As used herein, the term “and / or” includes any and all combinations of one or more of the related listed items.

[0054] It should be noted that in some alternative embodiments, the functions / actions indicated in the flowchart boxes herein may not occur in the order shown in the flowchart. For example, depending on the functions / actions involved, two boxes shown consecutively may actually be executed substantially simultaneously, or these boxes may sometimes be executed in reverse order. Furthermore, the function of a given box in the flowchart and / or block diagram may be divided into multiple boxes, and / or the functions of two or more boxes in the flowchart and / or block diagram may be at least partially integrated. Finally, other boxes may be added / inserted between the shown boxes, and / or boxes / operations may be omitted without departing from the scope of the inventive concept.

[0055] The subject matter disclosed above should be considered illustrative rather than restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments that fall within the true spirit and scope of the inventive concept. Therefore, to the maximum extent permitted by law, the scope will be determined by the broadest permissible interpretation of the following claims and their equivalents, and should not be limited or restricted by the foregoing detailed description.

[0056] This application claims priority to U.S. Provisional Application No. 62 / 913,865, filed October 11, 2019, with the United States Patent and Trademark Office (USPTO), entitled “METHODS OF FABRICATING FULLY ALIGNED METAL ON VIA”, and U.S. Application No. 16 / 785,732, filed February 10, 2020, with the USPTO, entitled “INTEGRATED CIRCUIT DEVICES INCLUDING ENLARGED VIA AND FULLY ALIGNED METALWIRE AND METHODS OF FORMING THE SAME”, the disclosures of which are incorporated herein by reference in their entirety.

Claims

1. A method for forming an integrated circuit device, the method comprising: A first insulating layer and a via contact are formed on a substrate, wherein the substrate includes an upper surface facing the via contact, the via contact is in the first insulating layer and includes a lower surface facing the substrate and an upper surface opposite to the lower surface; as well as A second insulating layer and a metal wire are formed on the via contact, wherein the metal wire is in the second insulating layer and includes a lower surface facing the substrate and contacting the upper surface of the via contact; The lower surface of the metal wire and the interface between the metal wire and the via contact both have a first width in the horizontal direction, which is parallel to the upper surface of the substrate. The metal wires include a first metal wire and a second metal wire spaced apart from each other in the horizontal direction. Wherein, the first metal wire includes a first lower surface facing the substrate and contacting the upper surface of the via contact, and the second metal wire includes a second lower surface facing the substrate and contacting the first insulating layer, and Wherein, the first lower surface of the first metal wire is spaced apart from the upper surface of the substrate by a first distance, and the second lower surface of the second metal wire is spaced apart from the upper surface of the substrate by a second distance, the second distance being longer than the first distance.

2. The method according to claim 1, wherein, The pathway contact includes opposite sides in the horizontal direction, and the metal wire does not overlap the opposite sides of the pathway contact.

3. The method according to claim 1, wherein, The first metal wire includes a first upper surface opposite to the first lower surface of the first metal wire, and the second metal wire includes a second upper surface opposite to the second lower surface of the second metal wire. The first upper surface of the first metal wire and the second upper surface of the second metal wire are coplanar.

4. The method according to claim 1, wherein, The first insulating layer includes an upper surface that contacts the second insulating layer, and The upper surface of the passage contact is recessed toward the substrate relative to the upper surface of the first insulating layer.

5. The method according to claim 4, wherein, The second insulating layer comprises a low-k dielectric material that is different from the material of the first insulating layer.

6. The method according to claim 4, wherein, The upper surface of the first insulating layer that contacts the passage defines a recess, and The first metal wire is included in the lower portion of the recess, and the lower portion of the first metal wire is spaced apart from the opposite side of the first insulating layer.

7. The method according to claim 4, wherein, The upper surface of the first insulating layer that contacts the passage defines a recess, and The first metal wire is included in the lower portion of the recess, and the second insulating layer separates the lower portion of the first metal wire from the opposite side of the first insulating layer.

8. The method according to claim 1, wherein, The metal wire comprises a diffusion barrier layer and a metal layer sequentially stacked on the via contact.

9. The method according to claim 1, wherein, The upper surface in contact with the passage has a second width in the horizontal direction, and the second width is wider than the first width.

10. A method for forming an integrated circuit device, the method comprising: A first insulating layer and a via contact are formed on a substrate, wherein the substrate includes an upper surface facing the via contact, and the via contact includes a lower surface facing the substrate and an upper surface opposite the lower surface and recessed toward the substrate relative to the first insulating layer. as well as A second insulating layer and a metal wire are formed on the via contact, wherein the metal wire is within the second insulating layer and contacts a portion of the upper surface of the via contact. The via contact is located on opposite sides in a horizontal direction parallel to the upper surface of the substrate, and the metal line does not overlap the opposite sides of the via contact. The metal wires include a first metal wire and a second metal wire spaced apart from each other in the horizontal direction. Wherein, the first metal wire includes a first lower surface that contacts a portion of the upper surface of the passage contact, and the second metal wire includes a second lower surface that contacts the upper surface of the first insulating layer, and Wherein, the first lower surface of the first metal wire is spaced apart from the upper surface of the substrate by a first distance, and the second lower surface of the second metal wire is spaced apart from the upper surface of the substrate by a second distance, the second distance being longer than the first distance.

11. The method according to claim 10, wherein, The first metal line includes a lower surface facing the substrate, and Wherein, the lower surface of the first metal wire has a first width in the horizontal direction, the upper surface of the passage contact has a second width in the horizontal direction, and the second width is wider than the first width.

12. The method according to claim 10, wherein, Forming the second insulating layer and the metal wire includes: A metal layer is formed at the contact between the first insulating layer and the passage; The metal lines are formed by patterning the metal layer; and The second insulating layer is formed on the metal wire.

13. The method according to claim 10, wherein, Forming the second insulating layer and the metal wire includes: A second insulating layer is formed at the contact between the first insulating layer and the passage; An opening is formed in the second insulating layer by removing a portion of the second insulating layer, the opening exposing the portion of the upper surface to which the passage contacts; and The metal wire is formed in the opening.

14. The method of claim 10, wherein, Forming the first insulating layer and the via contact includes: A first insulating layer and an initial via contact are formed on the substrate, wherein the initial via contact is within the first insulating layer; and By removing a portion of the initial path contact, a recess is formed by the upper surface of the first insulating layer and the path contact.

15. The method according to claim 10, wherein, Forming the first insulating layer and the via contact includes: An initial first insulating layer and the via contact are formed on the substrate, wherein the via contact is in the initial first insulating layer; and A cover insulating layer is selectively formed on the initial first insulating layer, wherein the first insulating layer includes the initial first insulating layer and the cover insulating layer, and the upper surface of the cover insulating layer in contact with the passage defines a recess.

16. A method of forming an integrated circuit device, the method comprising: A first insulating layer and a via contact are formed on a substrate, wherein the via contact is in the first insulating layer, and the substrate includes an upper surface facing the via contact; as well as A first metal line and a second metal line are formed on the via contact and the first insulating layer, wherein the first metal line and the second metal line are spaced apart from each other in a horizontal direction parallel to the upper surface of the substrate, wherein the first metal line is spaced apart from the upper surface of the substrate by a first distance and contacts the via contact, and the second metal line is spaced apart from the upper surface of the substrate by a second distance and contacts the first insulating layer, wherein the second distance is greater than the first distance. Wherein, the first metal wire is included on a first opposite side in the horizontal direction, the passage contact is included on a second opposite side in the horizontal direction, and the first opposite side is between the second opposite sides.

17. The method of claim 16, wherein forming the first metal wire and the second metal wire comprises: A metal layer is formed at the contact between the first insulating layer and the passage; as well as The first metal line and the second metal line are formed by patterning the metal layer, wherein the first metal line exposes a portion of the via contact. The method further includes forming a second insulating layer between the first metal wire and the second metal wire and contacting the portion of the passage exposed by the first metal wire.

18. The method of claim 16, further comprising: A second insulating layer is formed at the contact between the first insulating layer and the passage; as well as A first opening and a second opening are formed in the second insulating layer, wherein the first opening exposes a first portion of the passage contact, the second opening exposes a portion of the first insulating layer, wherein the second insulating layer contacts a second portion of the passage contact other than the first portion, and wherein a first metal wire is formed in the first opening and a second metal wire is formed in the second opening.

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