Chip packaging structure and forming method thereof

Abstract

According to some embodiments, a method for forming a chip packaging structure is provided. The method includes arranging a chip on a substrate. The method includes forming a heat dissipation wall structure on the substrate. The heat dissipation wall structure is adjacent to the chip, and there is a first gap between the chip and the heat dissipation wall structure. The method includes forming a first heat conduction layer in the first gap. The method includes forming a second heat conduction layer on the chip. The method includes arranging a heat dissipation cover on the substrate to cover the heat dissipation wall structure, the first heat conduction layer, the second heat conduction layer and the chip. The heat dissipation cover is bonded to the substrate, the heat dissipation wall structure, the first heat conduction layer and the second heat conduction layer. A chip packaging structure is also provided.

Description

Technical Field

[0001] Some embodiments of the present disclosure relate to semiconductor packages. Background Art

[0002] Semiconductor devices are used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. To form circuit components and elements, semiconductor devices are usually manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate and patterning the various material layers using photolithography and etching processes.

[0003] On a single semiconductor wafer, dozens or hundreds of integrated circuits are typically manufactured. Individual die are separated by cutting the integrated circuit (IC) along scribe lines. The individual die are then packaged separately. The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated in a given area. However, as the feature size continues to decrease, the manufacturing process continues to become more difficult to perform. Therefore, it is challenging to form a reliable package of electronic components with high integration density. Summary of the invention

[0004] According to some embodiments, a method for forming a chip packaging structure is provided. The method includes arranging a chip on a substrate. The method includes forming a heat dissipation wall structure on the substrate. The heat dissipation wall structure is adjacent to the chip, and there is a first gap between the chip and the heat dissipation wall structure. The method includes forming a first heat conduction layer in the first gap. The method includes forming a second heat conduction layer on the chip. The method includes arranging a heat dissipation cover on the substrate to cover the heat dissipation wall structure, the first heat conduction layer, the second heat conduction layer and the chip. The heat dissipation cover is bonded to the substrate, the heat dissipation wall structure, the first heat conduction layer and the second heat conduction layer.

[0005] According to some embodiments, a method for forming a chip packaging structure is provided. The method includes bonding a chip to a substrate. The method includes forming a heat dissipation wall structure on the substrate. The method includes forming a heat conduction layer on the chip and between the chip and the heat dissipation wall structure. The method includes bonding a heat dissipation cover to the substrate, the heat dissipation wall structure and the heat conduction layer.

[0006] According to some embodiments, a chip packaging structure is provided. The chip packaging structure includes a substrate, a chip, a heat dissipation wall structure, a first heat conduction layer, a second heat conduction layer, and a heat dissipation cover. The chip is on the substrate. The heat dissipation wall structure is on the substrate and is separated from the chip. The first heat conduction layer is between the heat dissipation wall structure and the chip. The second heat conduction layer is on the chip. The heat dissipation cover is on the substrate and covers the heat dissipation wall structure, the first heat conduction layer, the second heat conduction layer, and the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When reading the accompanying drawings of the specification, various aspects of the present disclosure can be best understood from the following detailed description. It should be noted that the various features are not necessarily drawn to scale. In fact, the size of the various features may be arbitrarily enlarged or reduced to make a clear description.

[0008] Figures 1A to 1E are cross-sectional views of various stages of a process for forming a chip package structure according to some embodiments.

[0009] Figure 1B-1 According to some embodiments Figure 1B A top view of a chip packaging structure.

[0010] Figure 1C-1 According to some embodiments Figure 1C A top view of a chip packaging structure.

[0011] Figure 1D-1 According to some embodiments Figure 1D A top view of a chip packaging structure.

[0012] Figure 1E-1 According to some embodiments Figure 1E A top view of a chip packaging structure.

[0013] Figure 2A is a top view of a chip packaging structure according to some embodiments.

[0014] Figure 2B is a diagram showing the Figure 2A A cross-sectional view of the chip packaging structure along the section line II' in FIG.

[0015] Figure 3 is a top view of a chip packaging structure according to some embodiments.

[0016] Figure 4 is a cross-sectional view of a chip packaging structure according to some embodiments.

[0017] Figure 5A is a cross-sectional view of a chip packaging structure according to some embodiments.

[0018] Figure 5BAccording to some embodiments Figure 5A A top view of a chip packaging structure.

[0019] Figure 6 is a cross-sectional view of a chip packaging structure according to some embodiments.

[0020] Figure 7 is a cross-sectional view of a chip packaging structure according to some embodiments.

[0021] Figure 8 is a cross-sectional view of a chip packaging structure according to some embodiments.

[0022] Fig. 9 is a cross-sectional view of a chip packaging structure according to some embodiments.

[0023] Fig.10 is a cross-sectional view of a chip packaging structure according to some embodiments.

[0024] Fig.11 is a cross-sectional view of a chip packaging structure according to some embodiments.

[0025] Fig.12 is a cross-sectional view of a chip packaging structure according to some embodiments.

[0026] Description of reference numerals:

[0027] 100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200: chip packaging structure

[0028] 110: Substrate

[0029] 111: Top surface of substrate

[0030] 112: Dielectric layer

[0031] 114: Conductive pad

[0032] 116: Circuit layer

[0033] 118: Conductive vias

[0034] 120: Chip

[0035] 120c: Corner part

[0036] 121: High performance device

[0037] 122: Substrate

[0038] 122a: front surface

[0039] 122b: rear surface

[0040] 122c, 122d, 122e, 122f: Side

[0041] 124: Redistribution layer

[0042] 126, 228: Interfacial layer

[0043] 128: Sidewall of chip

[0044] 129: Top surface of chip

[0045] 130: Bump

[0046] 140: Bottom filling layer

[0047] 150, 170, 210: Adhesive layer

[0048] 152, 154, 172, 174: Strip-shaped portion of adhesive layer

[0049] 160: Heat dissipation wall structure

[0050] 162, 164: Strip-shaped part of the heat dissipation wall structure

[0051] 166: Side wall of heat dissipation wall structure

[0052] 166a: Groove

[0053] 180, 190, 1010: thermal conductive layer

[0054] 182: Top part of the thermal conductive layer

[0055] 184, 192: Top surface of the thermal conductive layer

[0056] 186, 188: Strip-shaped part of the heat-conducting layer

[0057] 194: Edge of the thermal conductive layer

[0058] 220: Radiator cover

[0059] 222: Top plate

[0060] 222a: Lower surface of top plate

[0061] 224: Hood side wall structure

[0062] 224a: Outer side wall of the cover side wall structure

[0063] 226: Outer edge

[0064] A1, A2, A3: Distance

[0065] D1, D2, D3, D4: Depth

[0066] G1, G2, G3: Clearance

[0067] T1: Thickness

[0068] W1, W2, W3, W4: Width DETAILED DESCRIPTION

[0069] The following disclosure provides many different embodiments or examples to implement different features of the present disclosure. Specific examples of various components and arrangements are described below to simplify the present disclosure. Of course, the examples are for illustrative purposes only and are not intended to be limited thereto. For example, if the specification describes that a first feature is formed on a second feature, it means that an embodiment in which the first feature and the second feature are in direct contact may be included, and an embodiment in which an additional feature is formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact may be included. In addition, in various examples, the present disclosure may use repeated reference symbols and / or letters. Such repetition is for the purpose of simplicity and clarity and does not represent the relationship between the various embodiments and / or configurations discussed.

[0070] In addition, the spatially related words used, such as "below", "below", "lower", "above", "higher", etc., are for the convenience of describing the relationship between one element or feature and another element or features in the drawings. In addition to the orientation shown in the drawings, these spatially related words are intended to include different orientations of the device in use or operation. The device can be turned to different orientations (rotated 90 degrees or other orientations), and the spatially related words used herein can also be interpreted in the same way. It should be understood that additional operations may be provided before, during, and after the method described in the present disclosure, and in other embodiments of the method described in the present disclosure, some of the described operations may be replaced or deleted.

[0071] Some embodiments of the present disclosure are described below. Additional operations may be provided before, during, and / or after the stages described in these embodiments. In different embodiments, some of the stages described may be replaced or eliminated. Additional features may be added to the semiconductor device structure. In different embodiments, some of the features described below may be replaced or eliminated. Although some embodiments are discussed below with operations performed in a particular order, these operations may also be performed in other logical orders.

[0072] Figures 1A to 1E is a cross-sectional view of various stages of a process for forming a chip package structure according to some embodiments. Figure 1A As shown, according to some embodiments, a substrate 110 is provided. The substrate 110 includes a printed circuit board (PCB), a chip, or other suitable structures having a circuit layer and a pad.

[0073] According to some embodiments, the substrate 110 includes a dielectric layer 112, a plurality of conducting pads 114, a plurality of circuit layers 116, and a plurality of conducting vias 118. According to some embodiments, the conducting pads 114 are formed on the dielectric layer 112.

[0074] According to some embodiments, a circuit layer 116 and a conductive via 118 are formed in the dielectric layer 112. According to some embodiments, the conductive via 118, the circuit layer 116, and the conductive pad 114 are electrically connected to each other.

[0075] According to some embodiments, the dielectric layer 112 is made of an insulating material, such as an oxide, for example, silicon dioxide. According to some embodiments, the conductive pad 114, the wiring layer 116 and the conductive via 118 are made of metal (eg, copper, aluminum, gold, silver or tungsten) or alloys thereof.

[0076] like Figure 1A As shown, according to some embodiments, a chip 120 is provided. According to some embodiments, the chip 120 includes a substrate 122, a redistribution layer 124, and an interfacial layer 126. According to some embodiments, the substrate 122 has a front surface 122a and a back surface 122b.

[0077] The substrate 122 includes, for example, a semiconductor substrate. In some embodiments, the substrate 122 is made of an elemental semiconductor material including silicon or germanium in a single crystal, polycrystalline, or amorphous structure.

[0078] In some other embodiments, the substrate 122 is made of a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, an alloy semiconductor such as SiGe or GaAsP, or a combination of SiGe and GaAsP. The substrate 122 may also include a multilayer semiconductor, a semiconductor-on-insulator (SOI) (e.g., silicon-on-insulator or germanium-on-insulator), or a combination of a multilayer semiconductor and a semiconductor-on-insulator.

[0079] In some embodiments, substrate 122 includes various device elements. In some embodiments, various device elements are formed in substrate 122 and / or on substrate 122. For the purpose of simplicity and clear display, device elements are not shown in the drawings. Examples of various device elements include active devices, passive devices, other suitable devices, or combinations of the foregoing devices. Active devices may include transistors or diodes (not shown) formed at front surface 122a. Passive devices include resistors, capacitors, or other suitable passive devices.

[0080] For example, transistors include metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJT), high voltage transistors, high frequency transistors, p-channel field-effect transistors (PFETs) and / or n-channel field-effect transistors (NFETs), etc.

[0081] To form various device elements, various processes are performed, such as front-end-of-line (FEOL) semiconductor manufacturing processes, which may include deposition, etching, implantation, photolithography, annealing, planarization, one or more other suitable processes, or a combination of the foregoing processes.

[0082] In some embodiments, isolation features (not shown) are formed in the substrate 122. The isolation features are used to define the active region and electrically isolate various device elements formed in and / or on the substrate 122 in the active region. In some embodiments, the isolation features include shallow trench isolation (STI) features, local oxidation of silicon (LOCOS) features, other suitable isolation features, or combinations of the foregoing features.

[0083] According to some embodiments, a redistribution layer 124 is formed over the front surface 122a. According to some embodiments, the redistribution layer 124 includes a dielectric layer (not shown) and a wiring layer (not shown) in the dielectric layer. According to some embodiments, the wiring layer is electrically connected to a device (not shown) formed at the front surface 122a.

[0084] According to some embodiments, the interface layer 126 is formed over the rear surface 122b of the substrate 122. According to some embodiments, the interface layer 126 includes a titanium layer (not shown), a nickel-vanadium (NiV) layer (not shown), and a gold layer (not shown) sequentially stacked over the rear surface 122b.

[0085] like Figure 1AAs shown, according to some embodiments, a chip 120 is bonded to a substrate 110 via a plurality of bumps 130. According to some embodiments, the bumps 130 are respectively bonded to the conductive pads 114. According to some embodiments, there is a gap G1 between the chip 120 and the substrate 110.

[0086] The chip 120 includes a chip with high thermal performance, for example, a central processing unit (CPU) chip, a server chip, a system on chip, or a high-power chip. According to some embodiments, the power of the chip 120 is greater than 500 W. According to some embodiments, the bump 130 is in the gap G1. According to some embodiments, the bump 130 is made of a conductive material, for example, a solder material (e.g., tin).

[0087] like Figure 1A As shown, according to some embodiments, an underfill layer 140 is formed in the gap G1. According to some embodiments, the underfill layer 140 further extends onto a plurality of sidewalls 128 of the chip 120. According to some embodiments, the underfill layer 140 surrounds the bump 130. According to some embodiments, the underfill layer 140 surrounds the chip 120. According to some embodiments, the underfill layer 140 includes an insulating material (e.g., a polymer material).

[0088] Figure 1B-1 According to some embodiments Figure 1B A top view of a chip packaging structure. Figure 1B is a diagram showing the Figure 1B-1 A cross-sectional view of the chip packaging structure along the section line II' in FIG. Figure 1B as well as Figure 1B-1 As shown, according to some embodiments, an adhesive layer 150 is formed on the substrate 110 .

[0089] According to some embodiments, the adhesive layer 150 has a ring shape. According to some embodiments, the adhesive layer 150 is made of a polymer, for example, epoxy resin or silicone resin. According to some embodiments, the adhesive layer 150 is formed using a dispensing process.

[0090] like Figure 1B as well as Figure 1B-1 As shown, according to some embodiments, a heat dissipation wall structure 160 is formed on the adhesive layer 150. According to some embodiments, the heat dissipation wall structure 160 is adjacent to the chip 120. According to some embodiments, there is a gap G2 between the chip 120 and the heat dissipation wall structure 160. According to some embodiments, the heat dissipation wall structure 160 has a ring shape.

[0091] According to some embodiments, the heat dissipation wall structure 160 is made of a material with good thermal conductivity, for example, a metal material (for example, aluminum, copper and / or nickel) or an alloy material (for example, stainless steel). In some embodiments, the heat dissipation wall structure 160 is an annular structure, and the heat dissipation wall structure 160 (or annular structure) is bonded to the substrate 110 through the adhesive layer 150 so that the heat dissipation wall structure 160 is formed on the substrate 110. In some embodiments, the heat dissipation wall structure 160 is formed using an electroplating process.

[0092] like Figure 1B as well as Figure 1B-1 As shown, according to some embodiments, an adhesive layer 170 is formed on the heat dissipation wall structure 160. According to some embodiments, the adhesive layer 170 is made of a polymer, such as epoxy resin or silicone resin. According to some embodiments, the adhesive layer 170 is formed by a dispensing process.

[0093] Figure 1C-1 According to some embodiments Figure 1C A top view of a chip packaging structure. Figure 1C is a diagram showing the Figure 1C-1 A cross-sectional view of the chip packaging structure along the section line II' in FIG. Figure 1C as well as Figure 1C-1 As shown, according to some embodiments, a heat conducting layer 180 is formed in the gap G2.

[0094] According to some embodiments, the heat conducting layer 180 fills the gap G2. According to some embodiments, the heat conducting layer 180 is used to conduct heat from the chip 120 to the heat dissipation wall structure 160. According to some embodiments, the heat conducting layer 180 has a top portion 182 extending from the gap G2. According to some embodiments, the top portion 182 flows to a top surface 129 of the chip 120.

[0095] According to some embodiments, thermal conductive layer 180 directly contacts underfill layer 140, heat dissipation wall structure 160, substrate 110, adhesive layer 150, adhesive layer 170, and chip 120. According to some embodiments, thermal conductive layer 180 is between underfill layer 140 and heat dissipation wall structure 160.

[0096] In some embodiments, the lower portion of the thermal conductive layer 180 is between the bottom filling layer 140 and the adhesive layer 150. In some embodiments, a width W1 of the thermal conductive layer 180 decreases toward the substrate 110. According to some embodiments, the width W1 decreases continuously toward the substrate 110. Figure 1C-1 As shown, according to some embodiments, the heat conducting layer 180 surrounds the chip 120. According to some embodiments, the heat dissipation wall structure 160 surrounds the heat conducting layer 180.

[0097] According to some embodiments, the thermal conductivity of the heat conductive layer 180 is greater than the thermal conductivity of air. That is, according to some embodiments, the heat conductive layer 180 is made of a material having a thermal conductivity greater than the thermal conductivity of air. In some embodiments, the material includes a flowable material, for example, a polymer material (e.g., silicone) or a combination of a polymer and a metal (e.g., silver paste). According to some embodiments, the heat conductive layer 180 is formed using a dispensing process.

[0098] Figure 1D-1 According to some embodiments Figure 1D A top view of a chip packaging structure. Figure 1D is a diagram showing the Figure 1D-1 A cross-sectional view of the chip packaging structure along the section line II' in FIG. Figure 1D as well as Figure 1D-1 As shown, according to some embodiments, a heat conducting layer 190 is formed on the chip 120. Figure 1D as well as Figure 1D-1 As shown, according to some embodiments, the top portion 182 of the thermally conductive layer 180 is between the thermally conductive layer 190 and the heat dissipating wall structure 160 (or the adhesive layer 170 ).

[0099] like Figure 1D as well as Figure 1D-1 As shown, according to some embodiments, a top surface 192 of the heat conducting layer 190 is substantially coplanar with a top surface 184 of the heat conducting layer 180. The term "substantially coplanar" in the present application may include situations where there are slight deviations from the coplanar geometry. The deviation may occur due to the manufacturing process. According to some embodiments, in some other embodiments, the top surface 192 is slightly higher than the top surface 184. According to some embodiments, the heat conducting layer 190 directly contacts the interface layer 126 between the chip 120 and the heat conducting layer 180.

[0100] like Figure 1D as well as Figure 1D-1 As shown, according to some embodiments, the heat conductive layer 180 continuously surrounds the entire heat conductive layer 190 , and the heat dissipation wall structure 160 (or the adhesive layer 170 or the adhesive layer 150 ) continuously surrounds the entire heat conductive layer 180 and the entire heat conductive layer 190 .

[0101] According to some embodiments, the heat conductive layer 190 is a sheet structure. Therefore, according to some embodiments, the heat conductive layer 190 is also called a heat conductive sheet. According to some embodiments, the heat conductive layer 190 is made of a metal material (e.g., tin, silver, gold, or indium), an alloy material of the aforementioned metals, or a polymer material doped with a material with a high thermal conductivity (e.g., graphite, graphene, or metal).

[0102] In some embodiments, the thermal conductivity of the heat-conducting layer 190 is greater than the thermal conductivity of the heat-conducting layer 180. In some embodiments, the thermal conductivity of the heat-dissipating wall structure 160 is greater than the thermal conductivity of the heat-conducting layer 180.

[0103] According to some embodiments, thermal conductive layer 180 is softer than thermal conductive layer 190. According to some embodiments, thermal conductive layer 190 is formed by a deposition process. According to some embodiments, because thermal conductive layer 180 is softer than thermal conductive layer 190, the (softer) thermal conductive layer 180 (e.g., Figure 1C 129 is squeezed out of the top surface 129 by the (harder) thermally conductive layer 190 .

[0104] Figure 1E-1 According to some embodiments Figure 1E A top view of a chip packaging structure. Figure 1E is a diagram showing the Figure 1E-1 A cross-sectional view of the chip packaging structure along the section line II' in FIG. Figure 1E as well as Figure 1E-1 As shown, according to some embodiments, an adhesive layer 210 is formed on the substrate 110. According to some embodiments, the adhesive layer 210 continuously surrounds the heat dissipation wall structure 160, the heat conductive layer 180 and the heat conductive layer 190 (or the chip 120).

[0105] According to some embodiments, the adhesive layer 210 has a ring shape. According to some embodiments, the adhesive layer 210 is made of a polymer, such as epoxy resin or silicone resin. According to some embodiments, the adhesive layer 210 is formed using a dispensing process.

[0106] like Figure 1E as well as Figure 1E-1 As shown, according to some embodiments, a heat dissipation cover (lid) 220 is disposed on the substrate 110 to cover the heat dissipation wall structure 160, the heat conductive layer 180, the heat conductive layer 190 and the chip 120. According to some embodiments, the heat dissipation cover 220 is bonded to the substrate 110 through the adhesive layer 210.

[0107] According to some embodiments, the heat dissipation cover 220 is also bonded to the heat dissipation wall structure 160 through the adhesive layer 170. According to some embodiments, the heat dissipation cover 220 is further bonded to the thermal conductive layer 180 and the thermal conductive layer 190. According to some embodiments, after the heat dissipation cover 220 is disposed on the substrate 110, the thermal conductive layer 180 directly contacts the heat dissipation cover 220, the thermal conductive layer 190, the bottom filling layer 140, the substrate 110, the heat dissipation wall structure 160, the adhesive layer 150, and the adhesive layer 170.

[0108] According to some embodiments, the thermally conductive layer 190 directly contacts the heat dissipation cover 220. According to some embodiments, the thermally conductive layer 190 has a thickness T1 in the range of about 200 microns to about 400 microns. According to some embodiments, the heat dissipation cover 220 includes a top plate 222, a cover sidewall structure 224, an outer edge portion 226, and an interface layer 228. According to some embodiments, the cover sidewall structure 224 is below the top plate 222.

[0109] According to some embodiments, the cover sidewall structure 224 is between the top plate 222 and the outer edge portion 226. According to some embodiments, the cover sidewall structure 224 is connected to the top plate 222 and the outer edge portion 226. According to some embodiments, the outer edge portion 226 is bonded to the adhesive layer 210. According to some embodiments, the interface layer 228 is on a lower surface 222a of the top plate 222.

[0110] According to some embodiments, the interface layer 228 is between the top plate 222 and the thermally conductive layer 190 and is connected to the top plate 222 and the thermally conductive layer 190. According to some embodiments, the interface layer 228 includes a nickel layer (not shown) and a gold layer (not shown) sequentially stacked on the lower surface 222a of the top plate 222.

[0111] According to some embodiments, the heat dissipation wall structure 160 is between the chip 120 and the cover sidewall structure 224. In some embodiments, a distance A1 between the chip 120 and the heat dissipation wall structure 160 is smaller than a distance A2 between the heat dissipation wall structure 160 and the cover sidewall structure 224.

[0112] According to some embodiments, a distance A3 is used to separate the chip 120 from the cover sidewall structure 224. In some embodiments, the ratio (A1 / A3) of the distance A1 to the distance A3 is in the range of about 0.15 to about 0.35. In some examples, if the ratio (A1 / A3) is less than 0.15, the gap G2 may be too narrow to be successfully filled with the thermal conductive layer 180.

[0113] In some examples, if the ratio (A1 / A3) is greater than 0.35, the heat conduction path between the chip 120 and the heat dissipation wall structure 160 may be too long and may result in that the heat from the chip 120 may not be effectively transferred to the heat dissipation wall structure 160. In some embodiments, the ratio (A1 / T1) of the distance A1 to the thickness T1 of the heat conduction layer 190 is in the range of about 1 to about 5.

[0114] According to some embodiments, there is an air gap G3 between the heat dissipation wall structure 160 and the cover sidewall structure 224. According to some embodiments, the heat dissipation cover 220 is made of a material with high thermal conductivity, such as a metal material (aluminum or copper), an alloy material (such as stainless steel), or aluminum-silicon carbide (AlSiC).

[0115] According to some embodiments, an annealing process is performed after the heat dissipation cover 220 is disposed on the substrate 110. During the annealing process, the thermal conductive layer 190 is melted, which improves the adhesion of the thermal conductive layer 190 to the interface layer 126 of the chip 120 and the adhesion of the thermal conductive layer 190 to the interface layer 228 of the heat dissipation cover 220. According to some embodiments, after the annealing process, the melted thermal conductive layer 190 is solidified.

[0116] In some embodiments, a width W2 of the heat conducting layer 190 is substantially equal to a width W3 of the chip 120. According to some embodiments, the term "substantially equal to" in the present application means "within 10%". For example, according to some embodiments, the term "substantially equal to" means that the difference between the width W2 and the width W3 is within 10% of the average width of the heat conducting layer 190 and the chip 120. The difference may occur due to the manufacturing process.

[0117] According to some embodiments, after the annealing process, the junction layer 126 includes a titanium layer (not shown), a nickel-vanadium layer (not shown), an indium-nickel-gold (InNiAu) layer (not shown), and an indium-gold (InAu) layer (not shown) sequentially stacked on the rear surface 122b.

[0118] According to some embodiments, after the annealing process, the junction layer 228 includes a nickel layer (not shown), an indium-nickel-gold layer (not shown), and an indium-gold layer (not shown) sequentially stacked on the lower surface 222 a of the top plate 222 .

[0119] According to some embodiments, the heat conducting layer 180 is solidified by an annealing process. According to some embodiments, after the annealing process, the heat conducting layer 180 is still softer than the heat conducting layer 190. According to some embodiments, the Young's modulus of the heat conducting layer 190 is greater than the Young's modulus of the heat conducting layer 180. According to some embodiments, in this step, a chip package structure 100 is substantially formed.

[0120] According to some embodiments, the heat dissipation wall structure 160 has a width W4. According to some embodiments, the chip 120 and the cover sidewall structure 224 are separated by a distance A3. According to some embodiments, in some embodiments, the ratio of the width W4 to the distance A3 (W4 / A3) is in the range of about 0.05 to about 0.2.

[0121] In some examples, if the ratio ( W4 / A3 ) is less than 0.05, the thermal path between the heat dissipation wall structure 160 and the heat dissipation cover 220 may be too narrow to effectively transfer the heat from the chip 120 to the heat dissipation cover 220 .

[0122] In some examples, if the ratio (W4 / A3) is greater than 0.2, the thermal stress between the heat dissipation wall structure 160 and the substrate 110 may be too large, which may affect the stability of the heat dissipation wall structure 160. According to some embodiments, the heat dissipation wall structure 160 and the substrate 110 have different thermal expansion coefficients.

[0123] According to some embodiments, the heat conducting layer 190 creates a heat conducting path between the chip 120 and the heat dissipation cover 220, and the heat conducting layer 180 together with the heat dissipation wall structure 160 creates an additional heat conducting path between the chip 120 and the heat dissipation cover 220. Therefore, according to some embodiments, the additional heat conducting path improves the heat dissipation efficiency of the chip packaging structure 100, which improves the reliability of the chip packaging structure 100.

[0124] According to some embodiments, because the heat conductive layer 180 is softer than the heat conductive layer 190, the heat conductive layer 180 can alleviate the thermal stress generated between the chip 120 (e.g., the multiple corner portions 120c of the chip 120) and the heat conductive layer 190 in the subsequent annealing process. Therefore, according to some embodiments, the softer heat conductive layer 180 prevents the harder heat conductive layer 190 (e.g., the heat conductive layer 190 adjacent to the corner portion 120c) from cracking in the subsequent annealing process. Therefore, according to some embodiments, the reliability of the chip package structure 100 is improved.

[0125] Figure 2A is a top view of a chip package structure 200 according to some embodiments. Figure 2B is a diagram showing the Figure 2A FIG. 2 is a cross-sectional view of the chip package structure 200 along the section line II′ in FIG. Figure 2A as well as Figure 2B As shown, according to some embodiments, except that the heat dissipation wall structure 160 has a U-shape, the chip packaging structure 200 is similar to Figure 1E-1 Chip package structure 100. According to some embodiments, adhesive layer 150 and adhesive layer 170 have a U-shape. According to some embodiments, heat conducting layer 180 has a U-shape.

[0126] According to some embodiments, the chip 120 has a plurality of high-performance devices 121 formed on the front surface 122a. According to some embodiments, the high-performance devices 121 include high-speed integrated circuits, memory devices, high operating frequency devices, or high current devices.

[0127] According to some embodiments, the high-performance device 121 is disposed on the side 122c, the side 122d, and the side 122e closer to the chip 120, and on the side 122f farther from the chip 120. Therefore, according to some embodiments, the heat dissipation wall structure 160 and the heat conductive layer 180 adjacent to the side 122c, the side 122d, and the side 122e can quickly conduct the heat from the high-performance device 121 to the heat dissipation cover 220.

[0128] The U-shaped design of the heat dissipation wall structure 160 , the heat conductive layer 180 , the adhesive layer 150 , and the adhesive layer 170 can reduce the material costs of the heat dissipation wall structure 160 , the heat conductive layer 180 , the adhesive layer 150 , and the adhesive layer 170 .

[0129] Figure 3 FIG. 3 is a top view of a chip package structure 300 according to some embodiments. Figure 3 As shown, according to some embodiments, the chip packaging structure 300 is similar to the chip packaging structure 300 except that the heat dissipation wall structure 160 has a strip-shaped portion 162 and a strip-shaped portion 164 separated from each other. Figure 2A A chip packaging structure 200 is provided.

[0130] According to some embodiments, the adhesive layer 150 has a strip portion 152 and a strip portion 154 separated from each other. According to some embodiments, the adhesive layer 170 has a strip portion 172 and a strip portion 174 separated from each other. According to some embodiments, the heat conducting layer 180 has a strip portion 186 and a stripe portion 188 separated from each other.

[0131] In accordance with some embodiments, strip portions 152 , 162 , 172 , and 186 are adjacent to side 122 c of chip 120 . In accordance with some embodiments, strip portions 154 , 164 , 174 , and 188 are adjacent to side 122 e of chip 120 .

[0132] According to some embodiments, the high-performance device 121 of the chip 120 is disposed on the side 122c and the side 122e closer to the chip 120, and farther from the side 122d and the side 122f of the chip 120. Therefore, according to some embodiments, the heat dissipation wall structure 160 and the heat conductive layer 180 adjacent to the side 122c and the side 122e can quickly conduct the heat from the high-performance device 121 to the heat dissipation cover 220.

[0133] Figure 4 FIG. 4 is a top view of a chip package structure 400 according to some embodiments. Figure 4 As shown, according to some embodiments, the chip package structure 400 is similar to the chip package structure 400 except that the heat conducting layer 190 is wider than the chip 120. Figure 1EThat is, according to some embodiments, the width W2 of the heat conducting layer 190 is greater than the width W3 of the chip 120 .

[0134] According to some embodiments, thermally conductive layer 190 is partially formed over thermally conductive layer 180. In some embodiments, a plurality of edge portions 194 of thermally conductive layer 190 are buried in thermally conductive layer 180.

[0135] In some embodiments, the thermal conductivity of the heat conductive layer 190 is greater than the thermal conductivity of the heat conductive layer 180. According to some embodiments, the (wider) heat conductive layer 190 may increase the contact area between the heat conductive layer 190 and the heat dissipation cover 220, which improves the heat conduction efficiency between the heat conductive layer 190 and the heat dissipation cover 220. Therefore, according to some embodiments, the heat dissipation efficiency of the chip packaging structure 400 is improved.

[0136] Figure 5A is a cross-sectional view of a chip package structure 500 according to some embodiments. Figure 5B According to some embodiments Figure 5A FIG. 5 is a top view of a chip packaging structure 500 . Figure 5A is a diagram showing the Figure 5B FIG. 5 is a cross-sectional view of the chip package structure 500 taken along a cross-sectional line II′ in FIG.

[0137] like Figure 5A as well as Figure 5B As shown, according to some embodiments, the chip package structure 500 is similar to the chip package structure 100 except that the heat conducting layer 190 is narrower than the chip 120. Figure 1E as well as Figure 1E-1 That is, according to some embodiments, the width W2 of the heat conducting layer 190 is smaller than the width W3 of the chip 120 . According to some embodiments, the heat conducting layer 180 partially extends onto the top surface 129 of the chip 120 .

[0138] According to some embodiments, thermal stress tends to concentrate in the corner portion 120c of the chip 120. Because the (soft) thermal conductive layer 180 covers the corner portion 120c, the (soft) thermal conductive layer 180 can relieve most of the thermal stress in the corner portion 120c and prevent the (harder) thermal conductive layer 190 from cracking during a subsequent annealing process.

[0139] Figure 6 FIG. 6 is a cross-sectional view of a chip package structure 600 according to some embodiments. Figure 6 As shown, according to some embodiments, the chip packaging structure 600 is similar to the chip packaging structure 600 except that the heat dissipation wall structure 160 has a side wall 166 facing the chip 120, and the side wall 166 has a groove 166a. Figure 1EAccording to some embodiments, the heat conducting layer 180 fills the groove 166 a.

[0140] According to some embodiments, the groove 166 a can increase the contact area between the heat conductive layer 180 and the heat dissipation wall structure 160 , which improves the heat conduction efficiency between the heat conductive layer 180 and the heat dissipation wall structure 160 .

[0141] According to some embodiments, the groove 166a has a depth D1. According to some embodiments, the heat dissipation wall structure 160 has a width W4. In some embodiments, the ratio of the depth D1 to the width W4 of the heat dissipation wall structure 160 (D1 / W4) is in the range of about 0.3 to about 0.6.

[0142] In some examples, if the ratio (D1 / W4) is less than 0.3, the increase in the contact area between the heat conductive layer 180 and the heat dissipation wall structure 160 may not be significant. In some examples, if the ratio (D1 / W4) is greater than 0.6, the groove 166a may cause the structural strength of the heat dissipation wall structure 160 to be damaged.

[0143] Figure 7 FIG. 7 is a cross-sectional view of a chip package structure 700 according to some embodiments. Figure 7 As shown, according to some embodiments, the chip packaging structure 700 is similar to the chip packaging structure 700 except that the side wall 166 of the heat dissipation wall structure 160 has a plurality of grooves 166a. Figure 6 A chip packaging structure 600 is provided.

[0144] According to some embodiments, the heat conductive layer 180 fills the grooves 166a. According to some embodiments, the grooves 166a have the same depth D1. In some embodiments, the ratio (D1 / W4) of the depth D1 to the width W4 of the heat dissipation wall structure 160 is in the range of about 0.3 to about 0.6.

[0145] Figure 8 FIG. 8 is a cross-sectional view of a chip package structure 800 according to some embodiments. Figure 8 As shown, according to some embodiments, the chip packaging structure 800 is similar to the chip packaging structure 800 except that the groove 166a of the side wall 166 of the heat dissipation wall structure 160 has different depths D1, D2, D3 and D4. Figure 7 A chip packaging structure 700 is provided.

[0146] In some embodiments, the ratio of the depth D1 to the width W4 of the heat dissipation wall structure 160 (D1 / W4) is in the range of about 0.3 to about 0.6. In some embodiments, the ratio of the depth D2 to the width W4 (D2 / W4) is in the range of about 0.3 to about 0.6. In some embodiments, the ratio of the depth D3 to the width W4 (D3 / W4) is in the range of about 0.3 to about 0.6. In some embodiments, the ratio of the depth D4 to the width W4 (D4 / W4) is in the range of about 0.3 to about 0.6.

[0147] Fig. 9 FIG. 9 is a cross-sectional view of a chip package structure 900 according to some embodiments. Fig. 9 As shown, according to some embodiments, the chip package structure 900 is similar to the chip package structure 900 except that the heat conductive layer 180 extends to the gap G1 between the chip 120 and the substrate 110. Figure 1E According to some embodiments, the heat conductive layer 180 in the gap G1 surrounds the bump 130. According to some embodiments, in the chip package structure 900, no bottom filling layer is formed.

[0148] Fig.10 is a cross-sectional view of a chip package structure 1000 according to some embodiments. Figure 1B After the steps, Fig.10 As shown, according to some embodiments, a heat conducting layer 1010 is formed in the gap G2 between the chip 120 and the heat dissipation wall structure 160 and on the chip 120. According to some embodiments, the heat conducting layer 1010 directly contacts the heat dissipation cover 220, the chip 120, the heat dissipation wall structure 160, the substrate 110, the bottom filling layer 140, the adhesive layer 150 and the adhesive layer 170.

[0149] According to some embodiments, the thermally conductive layer 1010 is made of a material having a thermal conductivity greater than that of air. In some embodiments, the material includes a flowable material, such as a polymer material (eg, silicone) or a combination of a polymer and a metal (eg, silver paste).

[0150] According to some embodiments, the thermal conductive layer 1010 is formed by a dispensing process. Then, according to some embodiments, Figure 1E In this step, according to some embodiments, the chip package structure 1000 is substantially formed.

[0151] Fig.11 FIG. 1 is a cross-sectional view of a chip package structure 1100 according to some embodiments. Fig.11 As shown, according to some embodiments, the chip package structure 1100 is similar to the chip package structure 1100 except that the heat conducting layer 1010 of the chip package structure 1100 further extends into the gap G1 between the chip 120 and the substrate 110. Fig.10 Chip packaging structure 1000.

[0152] According to some embodiments, the heat conductive layer 1010 surrounds the bump 130. According to some embodiments, in the chip package structure 1100, no underfill layer is formed.

[0153] Fig.12 FIG. 1 is a cross-sectional view of a chip package structure 1200 according to some embodiments. Fig.12 As shown, according to some embodiments, the chip package structure 1200 is similar to the chip package structure 1200 except that the heat dissipation cover 220 does not have the outer edge portion 226. Figure 1E A chip packaging structure 100 is provided.

[0154] According to some embodiments, the cover sidewall structure 224 is bonded to the adhesive layer 210. According to some embodiments, the cover sidewall structure 224 has an outer sidewall 224a substantially perpendicular to a top surface 111 of the substrate 110.

[0155] According to some embodiments, the processes and materials for forming the chip packaging structure 200, the chip packaging structure 300, the chip packaging structure 400, the chip packaging structure 500, the chip packaging structure 600, the chip packaging structure 700, the chip packaging structure 800, the chip packaging structure 900, the chip packaging structure 1000, the chip packaging structure 1100 and the chip packaging structure 1200 may be equivalent to or similar to the processes and materials for forming the aforementioned chip packaging structure 100.

[0156] According to some embodiments, a chip packaging structure and a method for forming the same are provided. The method (for forming the chip packaging structure) forms a heat dissipation wall structure adjacent to a chip, the heat dissipation wall structure is connected to a heat dissipation cover thereon, and a heat conduction layer is formed between the chip and the heat dissipation wall structure. The heat dissipation wall structure and the heat conduction layer conduct heat from a side wall of the chip to the heat dissipation cover. Therefore, the heat dissipation efficiency of the chip packaging structure is improved. Therefore, the reliability of the chip packaging structure is improved.

[0157] According to some embodiments, a method for forming a chip packaging structure is provided. The method includes arranging a chip on a substrate. The method includes forming a heat dissipation wall structure on the substrate. The heat dissipation wall structure is adjacent to the chip, and there is a first gap between the chip and the heat dissipation wall structure. The method includes forming a first heat conduction layer in the first gap. The method includes forming a second heat conduction layer on the chip. The method includes arranging a heat dissipation cover on the substrate to cover the heat dissipation wall structure, the first heat conduction layer, the second heat conduction layer and the chip. The heat dissipation cover is bonded to the substrate, the heat dissipation wall structure, the first heat conduction layer and the second heat conduction layer.

[0158] In some embodiments, after the heat dissipation cover is set on the substrate, the first heat conductive layer directly contacts the heat dissipation cover, the second heat conductive layer, the heat dissipation wall structure and the substrate. In some embodiments, the second heat conductive layer directly contacts the heat dissipation cover, the first heat conductive layer and the chip. In some embodiments, a first thermal conductivity of the second heat conductive layer is greater than a second thermal conductivity of the first heat conductive layer, and the second thermal conductivity is greater than a third thermal conductivity of air. In some embodiments, the heat dissipation wall structure has a side wall facing the chip, the side wall has a groove, and the first heat conductive layer fills the groove. In some embodiments, the chip is bonded to the substrate through a bump, there is a second gap between the chip and the substrate, and the bump is in the second gap. And the method also includes forming a bottom filling layer in the second gap before forming the heat dissipation wall structure on the substrate. The bottom filling layer surrounds the bump. In some embodiments, the first heat conductive layer directly contacts the bottom filling layer. In some embodiments, forming the heat dissipation wall structure on the substrate includes bonding the heat dissipation wall structure to the substrate through an adhesive layer. In some embodiments, the chip is bonded to the substrate through a bump, there is a second gap between the chip and the substrate, the bump is in the second gap, and the first heat conductive layer extends into the second gap and surrounds the bump. In some embodiments, the first heat-conducting layer is softer than the second heat-conducting layer. In some embodiments, the first heat-conducting layer surrounds the chip, and the heat-dissipating wall structure surrounds the first heat-conducting layer.

[0159] According to some embodiments, a method for forming a chip packaging structure is provided. The method includes bonding a chip to a substrate. The method includes forming a heat dissipation wall structure on the substrate. The method includes forming a heat conduction layer on the chip and between the chip and the heat dissipation wall structure. The method includes bonding a heat dissipation cover to the substrate, the heat dissipation wall structure and the heat conduction layer.

[0160] In some embodiments, the heat dissipation cover includes a top plate and a cover side wall structure, the cover side wall structure is below the top plate and connected to the top plate, the heat dissipation wall structure is between the chip and the cover side wall structure, and a first distance between the chip and the heat dissipation wall structure is less than a second distance between the heat dissipation wall structure and the cover side wall structure. In some embodiments, the chip is bonded to the substrate through a bump, there is a gap between the chip and the substrate, the bump is in the gap, and the thermal conductive layer extends into the gap and surrounds the bump. In some embodiments, the thermal conductive layer directly contacts the heat dissipation cover, the chip, the heat dissipation wall structure, and the substrate.

[0161] According to some embodiments, a chip packaging structure is provided. The chip packaging structure includes a substrate, a chip, a heat dissipation wall structure, a first heat conduction layer, a second heat conduction layer, and a heat dissipation cover. The chip is on the substrate. The heat dissipation wall structure is on the substrate and is separated from the chip. The first heat conduction layer is between the heat dissipation wall structure and the chip. The second heat conduction layer is on the chip. The heat dissipation cover is on the substrate and covers the heat dissipation wall structure, the first heat conduction layer, the second heat conduction layer, and the chip.

[0162] In some embodiments, a portion of the first heat-conducting layer is between the second heat-conducting layer and the heat-dissipating wall structure. In some embodiments, an edge portion of the second heat-conducting layer is buried in the first heat-conducting layer. In some embodiments, the chip packaging structure further includes a bump and a bottom filling layer. A bump is between the chip and the substrate. The bottom filling layer is between the chip and the substrate and surrounds the bump. The first heat-conducting layer is between the bottom filling layer and the heat-dissipating wall structure. In some embodiments, a width of the first heat-conducting layer decreases toward the substrate.

[0163] The features of several embodiments are summarized above so that those skilled in the art can better understand various aspects of the present disclosure. It should be understood by those skilled in the art that the present disclosure can be easily used as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages of the embodiments introduced herein. It should also be understood by those skilled in the art that such equivalent configurations do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions and modifications may be made to the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A method for forming a chip packaging structure, comprising: Disposing a chip on a substrate; A heat dissipation wall structure is formed on the substrate, wherein the heat dissipation wall structure is adjacent to the chip, and a first gap is formed between the chip and the heat dissipation wall structure; forming a first heat-conducting layer in the first gap; After forming the first heat-conducting layer in the first gap, forming a second heat-conducting layer on an exposed portion of a top surface of the chip, wherein the first heat-conducting layer is softer than the second heat-conducting layer; as well as A heat dissipation cover is arranged on the substrate to cover the heat dissipation wall structure, the first heat conduction layer, the second heat conduction layer and the chip, wherein the heat dissipation cover is bonded to the substrate, the heat dissipation wall structure, the first heat conduction layer and the second heat conduction layer. 2 . The method for forming a chip packaging structure according to claim 1 , wherein after the heat dissipation cover is disposed on the substrate, the first heat conductive layer directly contacts the heat dissipation cover, the second heat conductive layer, the heat dissipation wall structure and the substrate. 3 . 3 . The method for forming a chip packaging structure as claimed in claim 1 , wherein the second heat-conducting layer directly contacts the heat dissipation cover, the first heat-conducting layer and the chip. 4 . The method for forming a chip package structure as claimed in claim 1 , wherein a first thermal conductivity of the second thermal conductive layer is greater than a second thermal conductivity of the first thermal conductive layer, and the second thermal conductivity is greater than a third thermal conductivity of air. 5 . The method for forming a chip packaging structure as claimed in claim 1 , wherein the heat dissipation wall structure has a side wall facing the chip, the side wall has a groove, and the first heat conductive layer fills the groove.

6. The method for forming a chip package structure as claimed in claim 1, wherein the chip is bonded to the substrate via a bump, a second gap is provided between the chip and the substrate, the bump is in the second gap, and the method for forming a chip package structure further comprises: Before forming the heat dissipation wall structure on the substrate, a bottom filling layer is formed in the second gap, wherein the bottom filling layer surrounds the bump. 7 . The method for forming a chip package structure as claimed in claim 6 , wherein the first heat conducting layer directly contacts the bottom filling layer. 8 . The method for forming a chip package structure as claimed in claim 1 , wherein forming the heat dissipation wall structure on the substrate comprises bonding the heat dissipation wall structure to the substrate through an adhesive layer.

9. The method for forming a chip packaging structure as described in claim 1, wherein the chip is bonded to the substrate through a bump, there is a second gap between the chip and the substrate, the bump is in the second gap, and the first thermal conductive layer extends into the second gap and surrounds the bump. 10 . The method for forming a chip packaging structure as claimed in claim 1 , wherein the first heat conducting layer surrounds the chip, and the heat dissipation wall structure surrounds the first heat conducting layer.

11. A method for forming a chip packaging structure, comprising: bonding a chip to a substrate; forming a heat dissipation wall structure on the substrate; forming a first heat-conducting layer on the chip and between the chip and the heat-dissipating wall structure; After forming the first heat-conducting layer on the chip and between the chip and the heat-dissipating wall structure, forming a second heat-conducting layer on an exposed portion of a top surface of the chip, wherein the first heat-conducting layer is softer than the second heat-conducting layer; as well as A heat dissipation cover is bonded to the substrate, the heat dissipation wall structure, the first heat conduction layer and the second heat conduction layer.

12. The method for forming a chip packaging structure as described in claim 11, wherein the heat dissipation cover comprises a top plate and a cover side wall structure, the cover side wall structure is below the top plate and connected to the top plate, the heat dissipation wall structure is between the chip and the cover side wall structure, and a first distance between the chip and the heat dissipation wall structure is less than a second distance between the heat dissipation wall structure and the cover side wall structure.

13. The method for forming a chip packaging structure as claimed in claim 11, wherein the chip is bonded to the substrate through a bump, there is a gap between the chip and the substrate, the bump is in the gap, and the first heat conductive layer extends into the gap and surrounds the bump. 14 . The method for forming a chip packaging structure as claimed in claim 11 , wherein the first heat conductive layer directly contacts the heat dissipation cover, the chip, the heat dissipation wall structure and the substrate.

15. A chip packaging structure, comprising: a substrate; a chip on the substrate; a heat dissipation wall structure, on the substrate and separated from the chip; A first heat-conducting layer between the heat-dissipating wall structure and the chip; a second heat-conducting layer on the chip, wherein the second heat-conducting layer is formed on an exposed portion of a top surface of the chip after the first heat-conducting layer is formed between the heat-dissipating wall structure and the chip, wherein the first heat-conducting layer is softer than the second heat-conducting layer; as well as A heat dissipation cover is on the substrate and covers the heat dissipation wall structure, the first heat conduction layer, the second heat conduction layer and the chip. 16 . The chip packaging structure as claimed in claim 15 , wherein a portion of the first heat conducting layer is between the second heat conducting layer and the heat dissipation wall structure. 17 . The chip package structure as claimed in claim 15 , wherein an edge portion of the second heat conducting layer is buried in the first heat conducting layer.

18. The chip packaging structure according to claim 15, further comprising: a bump between the chip and the substrate; as well as A bottom filling layer is between the chip and the substrate and surrounds the bump, wherein the first heat conducting layer is between the bottom filling layer and the heat dissipation wall structure. 19 . The chip package structure as claimed in claim 18 , wherein a width of the first heat conducting layer decreases toward the substrate.

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