GaN Enhancement Mode Devices

Abstract

An enhancement mode compound semiconductor field effect transistor (FET) includes a source, a drain, and a gate therebetween. The transistor also includes a gallium nitride-based first heterointerface below the gate and a buried region below the first heterointerface, the buried p-type region being configured to determine a turn-on threshold voltage of the enhancement mode FET to allow current to flow between the source and the drain.

Description

[0001] Claiming priority

[0002] This application claims the benefit of priority to U.S. patent application serial number 62 / 729,596, filed on September 11, 2018, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This document relates generally, but not exclusively, to semiconductor devices and, more particularly, to techniques for constructing enhancement mode gallium nitride devices. Background Art

[0004] Gallium nitride-based semiconductors have several advantages over other semiconductors as the material of choice for making next-generation transistors or semiconductor devices that can be used in high-voltage and high-frequency applications. For example, gallium nitride (GaN)-based semiconductors have a wide bandgap, which enables devices made from these materials to have a high breakdown electric field and remain robust over a wide temperature range. The two-dimensional electron gas (2DEG) formed by GaN-based heterostructures generally has a high electron mobility, making devices made using these structures useful in power switching and amplification systems. However, GaN-based semiconductors are generally used to make depletion modes, or are generally used in devices that are limited in use in many of these systems due to the complexity of many of the circuits that support these devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 A diagram illustrating an enhancement mode compound semiconductor device incorporating a buried p-type region according to various embodiments is shown.

[0006] Figure 2 Diagrams of enhancement mode compound semiconductor devices incorporating an overlying p-type region and a buried p-type region according to various embodiments are shown.

[0007] Figure 3 Diagrams of enhancement mode compound semiconductor devices incorporating a recessed channel layer and a buried p-type region according to various embodiments are shown.

[0008] Figure 4A , Figure 4B , Figure 4C , Figure 4D and Figure 4E Diagrams collectively illustrating steps for forming a gate region of an enhancement mode compound semiconductor device according to various embodiments.

[0009] Figure 5A and 5B A diagram of an enhancement mode semiconductor device with a controllable buried p-type region according to various embodiments is shown.

[0010] Fig. 6A and Figure 6B Diagrams of enhancement mode semiconductor devices having a buried p-type region patterned with a stepped region according to various embodiments are shown.

[0011] Fig. 7A and 7B A diagram of an enhancement mode semiconductor device having a buried p-type region patterned as a stripe region according to various embodiments is shown.

[0012] Figure 8 Diagrams showing a combined depletion mode compound semiconductor device and enhancement mode compound semiconductor device according to various embodiments are shown.

[0013] Fig. 9 Diagrams showing enhancement mode semiconductor devices with buried resistors according to various embodiments are shown.

[0014] Fig.10 An example of a process for manufacturing an enhancement mode compound semiconductor device according to various embodiments is shown.

[0015] Fig.11A and 11B Diagram showing steps for patterning a p-type region of an enhancement mode compound semiconductor device by ion implantation according to various embodiments.

[0016] Fig. 12A , Fig. 12B and Fig. 12C Diagrams illustrating structures for patterning a p-type region of an enhancement mode compound semiconductor device by annealing according to various embodiments.

[0017] Fig.13A , 13B 13C are diagrams illustrating a p-type region of an enhancement mode compound semiconductor device patterned by annealing according to various embodiments.

[0018] Fig.14A and Fig. 14B Diagrams illustrating structures for patterning a p-type region of an enhancement mode compound semiconductor device by annealing according to various embodiments.

[0019] In the accompanying drawings, which are not necessarily drawn to scale, like numbers may describe similar components in different views. Like numbers with different letter suffixes may represent different instances of similar components. The accompanying drawings generally illustrate various embodiments discussed in this document by way of example and not limitation. DETAILED DESCRIPTION

[0020] The present disclosure describes, among other things, GaN-based enhancement mode semiconductor devices (herein "enhancement mode compound semiconductor devices" or "enhancement mode devices"), such as transistors and switches, fabricated using regional p-type GaN material buried beneath the 2DEG region of a GaN-based high electron mobility transistor. These GaN-based enhancement mode semiconductor devices can be used in high frequency and high power switching applications that require the switching element to be normally in the off state. Such enhancement mode semiconductor devices can be integrated into circuit designs for switching power supply applications with reduced circuit complexity compared to designs using known depletion mode GaN devices, thereby reducing the cost of these designs.

[0021] Exemplary examples include GaN-based enhancement mode semiconductor devices (hereinafter referred to as "enhancement mode GaN devices") such as high electron mobility transistors (HEMTs) that can be used at high power density and high frequency, and methods for manufacturing such devices. The enhancement mode device may include a layer of p-type GaN-based compound semiconductor material (e.g., doped p-type material) disposed on a region of aluminum nitride (AlN) material below a 2DEG region formed by a GaN-based heterostructure. The p-type material layer or AlN material region may be configured to determine an enhancement mode turn-on threshold voltage of the enhancement mode device, such as depleting the 2DEG region when the enhancement mode GaN device is not biased, such as when no voltage is applied to the gate terminal of the device. In one example, such a configuration includes patterning the p-type material layer, such as by selectively activating portions of the p-type material when the p-type material is deactivated, and selectively deactivating points of the p-type material when the p-type material is activated. In another example, such a configuration includes forming an AlN material region within a target distance below the 2DEG so that the AlN material at least partially depletes the 2DEG.

[0022] An illustrative example includes an enhancement mode GaN device formed by recessing a region of a barrier layer of a GaN-based heterostructure so that a 2DEG formed by the GaN-based heterostructure is depleted in a region below the recessed region. The enhancement mode GaN device also includes a gate region formed at least partially within the recessed region.

[0023] Illustrative examples include enhancement mode GaN devices formed according to the recessed techniques and buried region structures described herein.

[0024] As used herein, a GaN-based compound semiconductor material may include a compound of an element including GaN and one or more elements from different groups in the periodic table. Such a compound may include a pairing of an element from Group 13 (i.e., a group including boron (B), aluminum (Al), gallium (Ga), indium (In), and thium (Tl)) with an element from Group 15 (i.e., a group including nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi). Group 13 of the periodic table may also be referred to as Group III, and Group 15 may also be referred to as Group V. In one example, a semiconductor device may be made of GaN and aluminum indium gallium nitride (AlInGaN).

[0025] The heterostructures described herein can be formed as AlN / GaN / AlN heterostructures, InAlN / GaN heterostructures, AlGaN / GaN heterostructures, or heterostructures formed by other combinations of Group 13 and Group 15 elements. These heterostructures can form 2DEGs at the interfaces of compound semiconductors forming heterostructures (e.g., interfaces of GaN and AlGaN). 2DEGs can form a conductive channel for electrons that can be controllably depleted, such as by controlling an electric field formed by a buried layer of p-type material located below the channel. The conductive channel for electrons can also be controllably enhanced, such as by controlling the current flowing through the semiconductor device by an electric field formed by a gate terminal disposed above the channel. Semiconductor devices formed using such conductive channels can include high electron mobility transistors.

[0026] The layers, masks, and device structures described herein are formed using any suitable techniques for forming (eg, depositing, growing, patterning, or etching) such layers, masks, and device structures.

[0027] Figure 1 A diagram of an enhancement mode compound semiconductor device 100 incorporating a buried p-type region is shown according to various embodiments. The enhancement mode device 100 may include an enhancement mode field effect transistor (FET) such as an enhancement mode HEMT. Although the present disclosure primarily discusses the use of GaN-based compound semiconductor materials for fabricating the enhancement mode device 100 and other devices discussed herein, other suitable single crystal compound semiconductor materials may be used, such as materials formed from III-V compounds, such as GaAs-based compounds. The enhancement mode GaN device 100 includes a substrate 105, a device structure 110 disposed above a surface of the substrate 105, a gate electrode 140, a source electrode 145, and a drain electrode 150 coupled to the device structure.

[0028] Substrate 105 includes a wafer, such as a wafer of high quality single crystal semiconductor material, such as sapphire (α-Al2O3), GaN, GaAs, Si, any polymorph of silicon carbide (SiC) (including wurtzite), AlN, InP, or a similar substrate material used to manufacture semiconductor devices.

[0029] The device structure 110 includes one or more layers (e.g., epitaxially formed layers) of a compound semiconductor material. Such layers may include a buffer layer 115, a doped layer 120 (e.g., a p-type layer), and a channel layer 122. The channel layer 122 may include a first layer 125 of a first compound semiconductor material and a second layer 135 (e.g., a barrier layer) of a second compound semiconductor material, such that the first compound semiconductor material has a different band gap than the second compound semiconductor material. In an example, the first compound semiconductor material is GaN and the second compound semiconductor material is AlGaN. The channel layer 122 may also include a 2DEG region 130 formed at an interface of the first layer 125 and the second layer 135 or at a heterojunction formed by the first layer 125 and the second layer 135. When the enhancement mode device 100 is biased to, for example, electrically couple the source electrode 145 (eg, source or source region of the enhancement mode GaN device 100 ) and the drain electrode 150 (eg, drain or drain region of the enhancement mode GaN device 100 ), the 2DEG region 130 forms a conductive channel for free electrons.

[0030] The buffer layer 115 includes a compound semiconductor material, such as an unintentionally doped GaN layer having a 16 / cm 3 The buffer layer may have a dopant concentration of 100 nm and a thickness of 400-500 nm. This material may be formed into a thin film by epitaxial growth or by using other thin film formation techniques, such as chemical vapor deposition. The buffer layer may also include one or more additional layers, such as a nucleation layer for growing additional compound semiconductor layers.

[0031] The doping layer 120 may include a layer of a single crystal compound semiconductor material, such as a layer of p-type GaN (p-GaN). Such a layer may have a thickness of about 100 nm and may be configured to enable enhancement mode operation of the enhancement mode device 100. Such configuration may include selecting a dopant material and a dopant concentration of the dopant material to determine an enhancement mode turn-on threshold voltage (hereinafter referred to as "enhancement mode threshold voltage") to allow current to flow between the source electrode 145 and the drain electrode 150 of the enhancement mode device 100. Such a dopant material may be any p-type dopant that can be combined with a single crystal compound semiconductor material, such as a compound including magnesium (Mg). Such a doping concentration may be selected based on known techniques, based on the desired enhancement mode threshold voltage, the work function of the material used to form the gate electrode 140, the distance 142 from the gate electrode to the 2DEG region 130, and other factors. In some embodiments, the dopant concentration may also be selected based on the distance 157 from the doping layer 120 to the 2DEG region 130. In some embodiments, the doping layer 120 may be approximately 100 nm thick, the distance 142 from the gate electrode to the 2DEG region 130 may be approximately 30 nm, the distance 157 from the doping layer 120 to the 2DEG 130 may be approximately 30 nm, and the dopant concentration may be less than 10 18 / cm 3 .

[0032] In some embodiments, the doped layer 120 may include a region 160 (e.g., a buried p-type region) of activated p-type material (hereinafter referred to as active region 160) disposed below the gate electrode 140. The doped layer 120 may also include regions 170A and 170B (hereinafter referred to as passivation regions 170A and 170B) where the p-type material is inactivated. The active region 160 may be configured to deplete the region 155 of the 2DEG region 130, such as to determine an enhancement mode threshold voltage of the enhancement mode device 100. In some embodiments, the charge on the active region 160 may generate an electric field that displaces or depletes free electrons in the 2DEG region 130 in the region 155. Configuring the active region 160 may include selecting a concentration of activated p-type dopants in the active region, a vertical distance 157 between the active region and the 2DEG region 130, or a geometry (e.g., a length, width, or thickness 162 of the active region) to deplete the 2DEG in the region 155 when the enhancement mode device 100 is unbiased.

[0033] In some embodiments, the enhancement mode device 100 may include a passivation layer 137 , such as a gate oxide layer, disposed between the structure 122 and the gate electrode 140 .

[0034] The gate electrode 140 may be any conductive material selected to bias or control the enhancement mode device 100, such as a metal having a work function, which operates in conjunction with the active region 160 to achieve enhancement mode operation of the enhancement mode device 100. In some embodiments, the gate electrode 140 may be configured, for example by selecting a width 144 of the gate electrode and a metal gate material having a desired work function, to restore the 2DEG in the region 155 when a bias voltage applied to the gate electrode exceeds the enhancement mode threshold voltage of the enhancement mode device 100. Fabrication of the enhancement mode device 100 using the active region 160 may reduce the distance 142 from the gate electrode 140 to the 2DEG region 130 compared to other enhancement mode devices. This reduced distance may increase the efficiency of the electric field generated by the gate electrode when restoring the 2DEG, which in turn may enable the enhancement mode device 100 to be fabricated with a gate electrode having a shorter width 144.

[0035] The source electrode 145 and the drain electrode 150 may be any suitable conductive material capable of forming an ohmic contact or other conductive junction with the 2DEG region 130 .

[0036] In some examples, the AlN region can replace the active region 160. In these examples, the doped layer 120 can be replaced by any suitable doped or undoped material (e.g., the material of the buffer layer 115). The region of AlN is formed within an indicated distance of the interface of the first layer 125 and the second layer 135, such as within a distance 157, so that the AlN region at least partially depletes any 2DEG formed at the interface above the AlN region. In one example, the indicated distance is a distance determined to enable the AlN region to consume an indicated amount of the 2DEG formed at the interface of the first layer and the second layer. In another example, the indicated distance is determined based on a target turn-on voltage of the enhancement mode GaN device 100. In another example, the indicated distance corresponds to the thickness of the first layer, such as a thickness of 5-30 nanometers.

[0037] Figure 2 A diagram of an enhancement mode compound semiconductor device 200 is shown, according to various embodiments, the enhancement mode compound semiconductor device 200 including an overlying p-type region 215 and a buried p-type region 220. The enhancement mode device 200 may be an example of the enhancement mode device 100, modified to include the overlying p-type region 215. In addition to the layers and regions of the enhancement mode device 100, the enhancement mode device 200 may also include a gate electrode 205, an overlying p-type region 215, and a buried p-type region 220. The overlying p-type region 215 may include an activated p-type material, such as activated p-GaN. Figure 1As shown, the gate electrode 205 and the buried p-type region 220 can be substantially similar to the gate electrode 140 and the active region 160. The buried p-type region 220 operates in conjunction with the overlying p-type region 215 to deplete the region 155 of the 2DEG region 130 to enable enhancement mode operation of the enhancement mode device 200 or to determine an enhancement mode threshold voltage of the enhancement mode device, as described herein.

[0038] In some embodiments, the charge of the buried p-type region 220 and the charge of the overlying p-type region 215 can generate a first electric field and a second electric field that displace or deplete free electrons on the region 155 in the 2DEG region 130. The combined operation of the first electric field and the second electric field can result in increased depletion in the region 155 of the enhancement mode device 200 compared to the depletion in the corresponding region of the enhancement mode device 100. In some embodiments, the combined operation of the first electric field and the second electric field can enable the enhancement mode device 200 to have similar electrical characteristics, such as an enhancement mode threshold voltage, to the enhancement mode device 100 while allowing the buried p-type region 220 to have an activation dopant concentration lower than the dopant concentration of the activation region 160.

[0039] Figure 3 A diagram of an enhancement mode compound semiconductor device 300 incorporating a recess 310 and a buried p-type region 315 in the channel layer 110 is shown according to various embodiments. The enhancement mode device 300 may be an example of the enhancement mode device 100, which is modified to include the recess 310. The enhancement mode device 300 may include a gate electrode 305, a recess 310, and a buried p-type region 315 in addition to the indicated layers and regions of the enhancement mode device 100. The recess 310 may be formed over the 2DEG region 130, for example, by an etching process, to reduce the distance from the gate electrode 305 to the 2DEG region 130 while not interfering with or disturbing the 2DEG region. In some embodiments, the recess 310 may be formed in the second layer 135. The gate electrode 305 and the buried p-type region 315 may be substantially similar to the gate electrode 140 and the active region 160, as shown in FIG. Figure 1 However, due to the reduced distance between the gate electrode and the 2DEG region 130, the gate electrode 305 and the buried p-type region 315 can be modified while allowing the enhancement mode device 300 to maintain substantially similar device characteristics as the enhancement mode device 100. Such modifications can include reducing the length or thickness of the gate electrode 305 compared to the length or thickness of the gate electrode 140. Such modifications can also include allowing the buried p-type region 315 to have a lower active dopant concentration than the dopant concentration of the active region 160.

[0040] In some embodiments, the gate electrode 305 or the buried p-type region 315 can have a geometry or chemical composition substantially similar to that of the gate electrode 140 or the active region 160. In these embodiments, the reduced distance between the gate electrode 305 and the 2DEG 130 can enable the enhancement mode device 300 to have a stronger on-state, or allow a greater current to flow between the source electrode 145 and the drain electrode 150 while the enhancement mode device is biased.

[0041] Figure 4A , Figure 4B , Figure 4C , Figure 4D and Figure 4E Together, a method for forming an enhancement mode device 300 ( Figure 3 ) of an enhancement mode compound semiconductor device of the present invention or a process for recessing the gate region. In one example, Figure 4A , Figure 4B , Figure 4C , Figure 4D and Figure 4E The process shown is for recessing the AlGaN barrier using epitaxy. This process can be used to fabricate enhancement mode devices with better stability and reliability than enhancement mode devices fabricated using other techniques (e.g. etching).

[0042] The process involves forming or obtaining Figure 4A In the example, the initial device structure includes a substrate layer 105, a buffer layer 115, and a partially formed channel layer, the channel layer including a GaN-based heterojunction formed by GaN-based compound semiconductor layers 125 and 405. Figure 1-3 As discussed in the discussion of , the compound semiconductor layer 125 includes a first GaN-based compound semiconductor material, and the compound semiconductor layer 405 includes a second GaN-based compound semiconductor material, which is selected to have a different band gap than the first GaN-based compound semiconductor material. In an example, the first compound semiconductor material is GaN and the second compound semiconductor material is AlGaN.

[0043] In the completed enhancement mode device, the compound semiconductor layer 125 is formed to at least a first target height H1, and the compound semiconductor layer 405 is formed to a second target height H2, so that a 2DEG can be formed at the interface between the compound semiconductor layer 125 and the compound semiconductor layer 405. The target height H1 and the target height H2 can be determined or selected based on one or more parameters, such as desired electrical characteristics or dimensional characteristics of the enhancement mode device or characteristics of the first or second compound semiconductor material. In an example, the height H1 is determined based on a target turn-on voltage of the enhancement mode semiconductor device. The height H1 can determine or indicate an unbiased or unpowered electrical characteristic of the enhancement mode device (e.g., the source / drain conductivity of the device required when no voltage is applied to the gate of the device, or the gate voltage required to form a conductive channel between the source and the drain). Figure 4A In the process step shown, the compound semiconductor layer 405 is grown to a height H3 that is less than H2. The height H3 can be selected to determine the electrical or geometric characteristics of the enhancement mode device. In one example, the height H3 corresponds to the amount of the second compound semiconductor material formed, which is insufficient to form a conductive channel of the 2DEG at the interface of the compound semiconductor layer 125 and the compound semiconductor layer 405 without being biased by an electric field, such as an electric field formed between the gate contact of the enhancement mode device in the layer 125 and the first compound semiconductor material. In the example, the height H3 is 5-30nm.

[0044] In one example, Figure 4A The structure shown in FIG. 4 may include a doped layer disposed between the buffer layer 115 and the compound semiconductor layer 405, such as the doped layer 120 ( Figure 1-3 ). The doped layer can be patterned to include regions (e.g., regions 160, 220, or 315) of material configured to deplete or suppress 2DEG formed at the interface of compound semiconductor layers 125 and 405. In an example, as described herein, the patterned region can include an activated p-type material or AlN material.

[0045] Depend on Figure 4B The structure depicted in the illustrated process step includes forming a hard mask 410 on a compound semiconductor layer 405 (e.g., a GaN barrier layer). The hard mask 410 is formed at any location where the compound semiconductor layer 405 for the completed enhancement mode device is thinned, such as to inhibit the formation of a 2DEG conduction channel when the completed enhancement mode device is not powered on (e.g., when a gate voltage is not applied to the completed enhancement mode device). In one example, the hard mask 410 is formed at a specified or specified location of a gate contact of the enhancement device and has a geometry that substantially corresponds to the geometry of the gate terminal. The hard mask is formed using any suitable material (e.g., SiN or SiO).

[0046] Depend on Figure 4C The process steps depicted in the structure shown include further forming or developing the compound semiconductor layer 405 so as to increase the thickness of the layer 405 to H2. Figure 4C As shown, the increased thickness of the compound semiconductor layer 405 may result in the formation of 2DEG in regions 415A and 415B. However, 2DEG is not formed in region 420 where the hard mask 410 prevents the thickness of the compound semiconductor layer 405 from becoming greater than H3.

[0047] Depend on Figure 4D The illustrated structure depicts a process step including removing the hard mask 410 to expose the recess 425 .

[0048] Depend on Figure 4D The structure shown depicts process steps including forming a gate 430 of the enhancement device, such as by depositing a gate dielectric and metal contact material in or around the recess 425. The process may continue with any additional steps suitable to complete the fabrication of the enhancement mode device.

[0049] Figure 5A and Figure 5B A diagram of an enhancement mode semiconductor device 500 with a controllable buried p-type region 510 is shown according to various embodiments. Figure 5A shows a cross section of an enhancement mode device 500, and Figure 5B 5. A top view of an enhancement mode device is shown. Enhancement mode device 500 may be an example of enhancement mode device 100 modified to include control electrode 505 and controllable buried p-type region 510. Control electrode 505 may include any suitable conductive material, such as a metal selected to form an ohmic contact with controllable buried p-type region 510. Controllable buried p-type region 510 may be an activated p-type region, such as region 160 ( Figure 1). The controllable buried p-type region 510 may include a first region 520 disposed below the gate electrode 140, and a second region 525 extending below the source contact 145 to contact the control electrode 505. As described herein, the first region 520 may be configured to determine an enhancement mode threshold voltage of the enhancement mode device 500. The second region 525 may be configured to couple a control signal, such as a charge, from the control electrode 505 to the first region 520. The second region 525 may include a region of deactivated p-type material 515. In some embodiments, the region of deactivated p-type material 515 may be formed by deactivating a portion of the second region 525 between the gate electrode 140 and the control electrode 505, such as by using an ion implantation process. The region of deactivated p-type material 515 may limit the effect of the controllable buried p-type region 510 on the 2DEG region 130 in the region between the gate electrode and the source electrode, thereby limiting the depletion of the 2DEG region 130 to the region 155 below the gate electrode 140.

[0050] In operation of the enhancement mode device 500 , a voltage may be applied to the control electrode 505 , for example to modify the charge in the first region 520 of the controllable buried p-type region 510 , for example to modify the enhancement mode threshold voltage of the enhancement mode device.

[0051] Fig. 6A and Figure 6B A diagram of an enhancement mode semiconductor device 600 having a buried p-type region patterned with stepped regions 620 , 625 , or 630 according to various embodiments is shown. Fig. 6A shows a cross section of an enhancement mode device 600, and Figure 6BA top view of an enhancement mode device is shown. Enhancement mode device 600 may be an example of enhancement mode device 500 modified to include stepped regions 620, 625, or 630. Stepped regions 620, 625, or 630 may be formed by doping layer 120, such as, for example, a layer of activated p-type material, by selectively deactivating p-type dopants in regions 620, 625, or 630, such as by implanting hydrogen at first, second, and third depths, respectively, using an ion implantation process, such that the implantation depth increases from gate electrode 140 to drain electrode 150. Alternatively, stepped regions 620, 625, or 630 may be formed by layer 120 (e.g., a layer of activated p-type material), by selectively deactivating p-type dopants in regions 620, 625, or 630, such as by implanting hydrogen at first, second, and third concentrations, respectively, using an ion implantation process, such that the implantation concentration decreases from gate electrode 140 to drain electrode 150. The stepped regions 620 , 625 , or 630 may function as back surface field plates to reduce the electric field between the gate electrode 140 and the drain electrode 150 , such as to enable the enhancement mode device 600 to be driven by a high voltage compared to other enhancement mode devices.

[0052] In some embodiments, enhancement mode device 600 may be fabricated without control electrode 405 or region 425. In some embodiments, stepped regions 620, 625, or 630 may be formed under gate electrode 140 toward source electrode 145.

[0053] Fig. 7A and Figure 7B A diagram of an enhancement mode semiconductor device 700 having a buried p-type region patterned with stripe regions 720A, 720B, or 720C is shown according to various embodiments. Fig. 7A shows a cross section of an enhancement mode device 700, and Figure 7B A top view of enhancement mode device 700 is shown. Enhancement mode device 700 may be an example of enhancement mode device 500 modified to include banded regions 720A, 720B, or 720C in burred p-type region 510. In some embodiments, enhancement mode device 700 may be fabricated without control contact 405 or region 425.

[0054] As described herein, the stripe regions 720A, 720B, or 720C can be formed under the gate electrode 140 using the doped layer 120 (e.g., a layer of activated p-type material) by selectively deactivating the p-type dopant outside the passivation region, for example, by using an ion implantation process. Alternatively, the stripe regions 720A, 720B, or 720C can be formed under the gate electrode 140 from the doped layer 120, such as a passivated p-type material, by selectively activating the p-type dopant in at least the regions 720A, 720B, or 720C, for example, using an annealing process, as described herein. One or more of the stripe regions 720A, 720B, or 720C can have a different doping level than one or more of the other stripe regions 720A, 720B, or 720C, so as to determine two or more enhancement mode threshold voltages for the enhancement mode device 700. Such different doping levels may include different activated dopant materials, different concentrations of activated dopant materials, or different depths within the buried p-type region 510 at which the dopant is activated or deactivated.

[0055] Figure 8 A diagram of a semiconductor device 800 having a combined depletion mode compound semiconductor device (hereinafter referred to as a "depletion mode device") 800A and an enhancement mode compound semiconductor device 800B according to various embodiments is shown. The depletion mode device 800A may be an example of a depletion mode FET such as a depletion mode HEMT. The enhancement mode device 800B may be an enhancement mode device 100 ( Figure 1 ). The depletion mode device 800A and the enhancement mode device 800B may include a substrate 810 and a device structure including a buffer layer 815, a doped layer 820 of a passivated p-type compound semiconductor material, a first layer 825 of a first compound semiconductor material, a second layer 835 of a second compound semiconductor material, and a 2DEG region 830 formed at an interface of the first layer and the second layer. The depletion mode device 800A may further include a gate electrode 840, a source electrode 845, and a drain electrode 850. The enhancement mode device 800B may further include a gate electrode 860, a source electrode 855, and a drain electrode 870. The enhancement mode device 800B may further include a buried p-type region 875 configured to deplete the region 865 of the 2DEG. As described herein, the buried p-type region 875 may be configured to determine an enhancement mode threshold voltage of the enhancement mode device 800B.

[0056] Fig. 9A diagram of an enhancement mode semiconductor device 900 with a buried resistor 905 according to various embodiments is shown. The enhancement mode device 900 may be substantially similar to the enhancement mode device 100, modified so that the source electrode and the drain electrode contact the buried resistor 905. The buried resistor 905 may include an activation region of the doped layer 120. The activation region may be configured to have a specified concentration of activation dopants, for example to determine the sheet resistance of the activation region. Such sheet resistance may range from 300 ohms per square (Ohms / sq.) to 1000 ohms / sq. Compared to device resistors formed by other techniques, due to the available sheet resistance, the buried resistor 905 may have a high resistance while having a smaller or reduced total area. Therefore, compared to devices manufactured using resistors formed by other techniques, devices manufactured using the buried resistor 905 may have a smaller circuit area.

[0057] Fig.10 An example of a process 1000 that can be used to manufacture an enhancement mode compound semiconductor device according to various embodiments is shown. The process 1000 can be used to manufacture any other enhancement mode device described herein. The process 1000 can begin by receiving a substrate having a basic crystal structure. Such a substrate can be received from a previous manufacturing process, or such a substrate can be produced according to one or more substrate growth and processing techniques. Such a substrate can be a wafer, such as a wafer of sapphire (α-Al2O3), any polymorph of GaN, GaAs, Si, SiC (including wurtzite), AlN, InP, or a similar substrate material used to manufacture semiconductor devices.

[0058] A buffer layer of a first compound semiconductor material may be formed over the surface of the substrate at 1005. The buffer layer may include a heteroepitaxial GaN thin film, such as a thin film formed by epitaxial growth or by using another thin film formation technique such as chemical vapor deposition (CVD) to have a thickness of approximately 400-500 nm.

[0059] At 1010, a doped layer (e.g., a p-type layer) of a second compound semiconductor material may be formed over the buffer layer. The second compound semiconductor material may be epitaxially grown on the buffer layer to a thickness of 100 nm using any suitable process. The second compound semiconductor material may be doped with a p-type dopant such as Mg. In some embodiments, the p-type dopant may be deactivated, for example, by reacting the dopant with a passivating material such as hydrogen.

[0060] At 1015, a channel layer may be formed over the doped layer. Forming the channel layer may include forming a first layer of a third compound semiconductor material over the doped layer, and then forming a second layer of a fourth compound semiconductor material over the first layer. The first layer of the third compound semiconductor material may be formed in substantially the same manner as the buffer layer, such as by epitaxial growth or using another thin film formation technique. In some embodiments, the first layer of the third compound semiconductor material may be a 100 nm thick GaN layer. The second layer of the fourth compound semiconductor material may be, for example, a 30 nm thick AlGaN layer grown over the surface of the first layer using any suitable thin film formation technique. The third compound semiconductor material and the fourth compound semiconductor material may be selected to have different band gaps so as to form a heterojunction at the interface between the first layer and the third layer. Such a selection may enable a 2DEG to be formed at a heterojunction, such as forming a 2DEG region at a heterojunction.

[0061] At 1020, a gate electrode can be formed over the channel layer. As described herein, such a gate electrode can include any suitable gate material selected to enable enhancement mode operation of an enhancement mode device.

[0062] At 1025 , the doped layer can be patterned, for example, to form an isolation region (eg, a buried activated p-type region) below the gate electrode.

[0063] refer to Fig.11A and Fig. 11B , patterning the doped layer may include using ion implantation techniques to selectively deactivate regions of the doped layer. Fig.11A and Fig. 11B Diagram showing steps in an ion implantation process.

[0064] Fig.11A An example enhancement mode device 1100 is depicted having a substrate layer 1110, a buffer layer 1115, a doping layer 1120, a compound semiconductor layer 1125 (e.g., a first layer of a third compound semiconductor), a 2DEG region 1130, a compound semiconductor layer 1135 (e.g., a second layer of a fourth compound semiconductor), a gate electrode 1140, a source electrode 1145, and a drain electrode 1150. The doping layer 1120 may include a layer of an activated p-type material. Fig.11A As depicted in , the doped layer 1120 may be patterned using the gate electrode 1140 as a mask to selectively implant the passivation material 1155 into the regions of the doped layer exposed by the gate electrode so as to self-align the final activated p-type region under the gate electrode. Fig.11A Gate electrode 1140 is depicted as being used for an ion implantation mask, but any other suitable mask may be used.

[0065] Fig. 11B An example enhancement mode device 1105 is depicted after an ion implantation process. Fig. 11B As shown, the ion implantation process deactivates the p-type material in regions 1170A and 1170B exposed by the gate electrode, while maintaining the p-type material activated in masked regions 1165 of d-layer 1120. As a result of the ion implantation process, 2DEG region 1130 is restored except at region 1160 which is depleted by masked regions 1165.

[0066] Return to process 1000, reference Fig. 12A , 12B and 12C, patterning the doped layer may include using an annealing process to selectively activate regions of the doped layer, such as when the doped layer includes a deactivated p-type material layer. Fig. 12A , Fig. 12B and Fig. 12C A diagram showing a device structure for patterning a p-type region of an enhancement mode compound semiconductor device using an annealing process before forming a gate electrode over a channel layer.

[0067] Fig. 12A The structure in may include a passivation layer 1255 and a partially fabricated enhancement mode device having a substrate layer 1210, a buffer layer 1215, a doping layer 1220, a compound semiconductor layer 1225 (e.g., a first layer of a third compound semiconductor), a 2DEG region 1230, a compound semiconductor layer 1235 (e.g., a second layer of a fourth compound semiconductor), a source electrode 1245, and a drain electrode 1250. The doping layer 1220 may include an inactivated p-type material layer, such as an inactivated p-GaN. The passivation layer 1255 may include any suitable passivation material layer, such as silicon nitride. As Fig. 12A As depicted in , the doped layer 1220 may be patterned by forming a cavity 1275 in the passivation layer 1255 to expose a region of the compound semiconductor layer 1235 between the source electrode 1245 and the drain electrode 1250. Annealing is then performed in an N2 or NH3 environment, such as in a chamber filled with ambient N2 / NH3 gas and heated to an annealing temperature between 1100 and 1200 degrees Celsius (°C). Fig. 12B As shown, such an anneal may activate region 1265 of doped layer 1220 beneath cavity 1275 while leaving regions 1270A and 1270B inactive. Passivation layer 1255 may then be removed and gate electrode 1240 may be formed using known techniques, such as Fig. 12C shown.

[0068] Return to process 1000, reference Fig.13A , 13Band 13C, patterning the doped layer may include using an annealing process to selectively activate regions of the doped layer, such as when the doped layer includes a deactivated p-type material layer. Fig.13A , 13B 13C show diagrams for patterning a p-type region of an enhancement mode compound semiconductor device by annealing according to various embodiments. Such a pattern can be used to form an enhancement mode compound semiconductor device having a gate electrode within a threshold distance from a source electrode.

[0069] Fig.13A A partially fabricated enhancement mode device is depicted, which includes a substrate layer 1310, a buffer layer 1315, a doping layer 1320, a compound semiconductor layer 1325 (e.g., a first layer of a third compound semiconductor), a 2DEG region 1330, and a compound semiconductor layer 1335 (e.g., a second layer of a fourth compound semiconductor). The doping layer 1320 may include a passivated p-type material layer. Patterning the doping layer 1320 may include forming a cavity or recess 1350 in the partially completed enhancement mode device, such as Fig. 13B As shown. The partially completed enhancement mode device can then be annealed in a N2 / NH3 environment as previously described to activate region 1340 of doped layer 1320 while leaving region 1345 in a disabled state. Fabrication of the enhancement mode device can then continue, such as by forming gate electrode 1360, source electrode 1365, and drain electrode 1370, as shown. Fig. 13C Such a gate electrode 1360 is formed within a distance (gate-source distance) 1375 from the source electrode so that when the enhancement mode device is turned on (for example, when a sufficient turn-on voltage is applied to the gate electrode), electrons from the source electrode can tunnel through the depletion region 1355 to reach the drain electrode 1370. This patterning can be used to form an enhancement mode compound semiconductor device with a gate-source distance 1375 shorter than 100 nm.

[0070] Returning again to process 1000, the process may include forming a recess in the channel layer, for example in the second layer of the fourth compound semiconductor material, before forming the gate electrode.The gate electrode may then be formed at least partially in the recess.

[0071] In some embodiments, process 1000 may include forming a second doped layer (eg, a second p-type doped layer) between the gate electrode and the channel layer. Process 1000 may further include patterning the first doped layer and the second doped layer formed at 1010 using the gate electrode as a mask, for example, in an ion implantation process.

[0072] Return to process 1000, reference Fig.14A and 14BPatterning the doped layer may include using an annealing process to selectively deactivate regions of the doped layer, such as when the doped layer includes an activated p-type material layer. Fig.14A and Fig. 14B A diagram showing a device structure for patterning a p-type region of an enhancement mode compound semiconductor device using an annealing process after forming a gate electrode over a channel layer.

[0073] Fig.14A The structure 1400A in may include a passivation layer 1455 and an enhancement mode device having a substrate layer 1410, a buffer layer 1415, a doping layer 1420, a compound semiconductor layer 1425 (e.g., a first layer of a third compound semiconductor), a 2DEG region 1430, a compound semiconductor layer 1435 (e.g., a second layer of a fourth compound semiconductor), a source electrode 1445, and a drain electrode 1450. The doping layer 1420 may include a layer of activated p-type material, such as activated p-GaN. The passivation layer 1455 may include a layer of any suitable passivation material, such as silicon nitride. As Fig.14A As shown in , the doping layer 1420 can be patterned by forming a first cavity 1475 and a second cavity 1480 in the passivation layer 1455, thereby exposing a first region of the compound semiconductor layer 1435 between the source electrode 1445 and the gate electrode 1440, and exposing a second region of the compound semiconductor layer 1435 between the gate electrode 1440 and the drain electrode 1450. The structure can then be annealed in an environment including an activating material (e.g., an H2 annealing environment). Fig. 14B As shown, such annealing can deactivate first and second regions 1470A and 1470B of doped layer 1420 beneath cavities 1475 and 1480, respectively, while leaving region 1465 activated. Active region 1465 can deplete region 1460 of the 2DEG.

[0074] Although the above discussion discloses various exemplary embodiments, it will be apparent that various modifications can be made by those skilled in the art which will achieve certain advantages of the invention without departing from the true scope of the invention.

[0075] Each non-limiting aspect or example described herein may stand alone or may be combined with one or more of the other examples in various permutations or combinations.

[0076] The above detailed description includes references to the accompanying drawings, which form a part of the detailed description. The accompanying drawings show specific embodiments in which the present invention can be implemented by way of illustration. These embodiments are also referred to as "examples" in this article. In addition to the elements shown or described, such examples may include elements. However, the inventors also contemplate examples that only provide those elements shown or described. In addition, the inventors also contemplate examples using any combination or arrangement of those elements (or one or more aspects thereof) shown or described, with respect to the specific examples (or one or more aspects thereof) shown or described herein, or other examples (or one or more aspects thereof).

[0077] In the event of an inconsistency in usage between this document and any document incorporated by reference, the usage in this document controls.

[0078] In this document, the terms "a" or "an" are used in patent documents to include one or more, independent of any other instances or uses of "at least one" or "one or more". In this document, unless otherwise stated, the term "or" is used to indicate non-exclusivity or "A or B" includes "A but not B", "B but not A", and "A and B". In this document, the terms "including" and "wherein" are used as ordinary equivalents of the respective terms "comprising" and "wherein". Similarly, in the following claims, the terms "including" and "comprising" are open-ended, that is, systems, devices, articles, compositions, preparations, or methods that include additional elements in addition to the elements listed after the term in the claim are still considered to fall within the scope of the claim. In addition, in the appended claims, the terms "first", "second", and "third", etc. are used merely as labels and are not intended to impose numerical requirements on their objects.

[0079] The above description is intended to be illustrative, not restrictive. For example, the above examples (or one or more aspects thereof) may be used in combination with each other. After reviewing the above description, other embodiments may be used, for example, by a person of ordinary skill in the art. The abstract is provided to comply with 37C.FR§1.72(b) to allow the reader to quickly determine the nature of the technical disclosure. When submitting this document, it should be understood that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the above detailed description, various features may be combined together to simplify the present disclosure. This should not be interpreted as intending to mean that undeclared public features are essential to any claim. Instead, the subject matter of the invention may be less than all the features of a particular disclosed embodiment. Therefore, the following claims are thus incorporated into the detailed description as examples or embodiments, each claim existing independently as an independent embodiment, and it is expected that such embodiments may be combined with each other in various combinations or permutations. The scope of the present invention should be determined with reference to the appended claims and the full scope of equivalents to which these claims are assigned.

Claims

1. An enhancement mode compound semiconductor field effect transistor, comprising: A source electrode, a drain electrode and a gate electrode, wherein the gate electrode is located between the source electrode and the drain electrode; a first gallium nitride-based heterointerface in a channel layer below the gate; and a buried region in a doped layer below the first heterointerface in the channel layer, the buried region comprising an activated p-type material and configured to determine an enhancement mode FET turn-on threshold voltage that allows current to flow between the source and the drain, The buried area comprises: a first strip of p-type material extending laterally below the gate, the first strip of p-type material having a first dopant concentration that determines a first enhancement mode FET turn-on threshold voltage; and A second strip of p-type material extends laterally beneath the gate, the second strip of p-type material having a second dopant concentration to determine a second enhancement mode FET turn-on threshold voltage. 2 . The enhancement mode compound semiconductor field effect transistor according to claim 1 , wherein the buried region further comprises a passivation region. 3 . The enhancement mode compound semiconductor field effect transistor according to claim 1 , wherein when the enhancement mode compound semiconductor field effect transistor is not biased, the p-type buried region is configured to form a depletion region in the first heterointerface.

4. The enhancement mode compound semiconductor field effect transistor according to claim 3, wherein the width of the gate electrode and the metal material of the gate electrode are configured so that the gate electrode can operate to restore the depletion region when a bias voltage is applied to the gate electrode, and the bias voltage is greater than the enhancement mode FET turn-on threshold voltage. 5 . The enhancement mode compound semiconductor field effect transistor according to claim 1 , wherein a first heterointerface based on gallium nitride is formed at an interface between a layer of the first compound semiconductor material and a layer of the second compound semiconductor material.

6. The enhancement mode compound semiconductor field effect transistor according to claim 5, further comprising: A recess is formed in the first compound semiconductor material, the gate being at least partially located in the recess. 7 . The enhancement mode compound semiconductor field effect transistor of claim 1 , further comprising an overlying p-type region between the gate and the first gallium nitride based heterointerface.

8. The enhancement mode compound semiconductor field effect transistor according to claim 1, further comprising: A second gallium nitride based heterointerface is located below the gate.

9. The enhancement mode compound semiconductor field effect transistor of claim 1, further comprising a control electrical contact coupled to the buried region.

10. The enhancement mode compound semiconductor field effect transistor according to claim 1, wherein: The buried region extends laterally from an area beneath the gate to a source contact; and The dopant concentration of the buried region decreases laterally from the area under the gate to the source contact.

11. The enhancement mode compound semiconductor field effect transistor according to claim 1, wherein: The buried region extends laterally from a region below the gate to a region between the gate and the drain; and The dopant concentration of the buried region decreases laterally from a region below the gate to a region between the gate and the drain.

12. The enhancement mode compound semiconductor field effect transistor according to claim 1, wherein: The buried region extends laterally from an area beneath the gate to a source contact; and The buried region includes a region of doped material that is passivated to a depth that increases laterally from a region beneath the gate to the source contact.

13. The enhancement mode compound semiconductor field effect transistor according to claim 1, wherein: The buried region extends laterally from a region below the gate to a region between the gate and the drain; and The buried region includes a region of doped material that is passivated to a depth that increases laterally from a region below the gate to a region between the gate and the drain.

14. The enhancement mode compound semiconductor field effect transistor according to claim 1, combined with a buried resistor formed of the same p-type compound semiconductor material as the p-type buried region. 15 . The enhancement mode compound semiconductor field effect transistor according to claim 14 , wherein the p-type compound semiconductor material is a Group III nitride material. 16 . The enhancement mode compound semiconductor field effect transistor according to claim 1 , wherein the buried region comprises aluminum nitride. 17 . The enhancement mode compound semiconductor field effect transistor of claim 1 , wherein the buried region is located within 30 nanometers of a first gallium nitride based heterointerface.

18. The enhancement mode compound semiconductor field effect transistor according to claim 1, wherein the first gallium nitride-based heterointerface is formed at an interface between a layer of a first compound semiconductor material and a layer of a second compound semiconductor material, and the enhancement mode compound semiconductor field effect transistor further comprises: A recess is formed in the first compound semiconductor material, the gate being at least partially located in the recess.

19. A semiconductor device comprising: a buffer layer comprising a first compound semiconductor material; An enhancement mode compound semiconductor field effect transistor, i.e., an enhancement mode FET, is formed using the buffer layer. The enhancement mode FET comprises: A source and a drain, with a gate therebetween; a first two-dimensional electron gas region in the channel layer below the gate; and a p-type buried region in a doping layer located below the first two-dimensional electron gas region in the channel layer, the buried region comprising an activated p-type material and configured to determine an enhancement mode FET turn-on threshold voltage allowing current to flow between the source and the drain; and A depletion mode compound semiconductor field effect transistor, i.e., a depletion mode FET, is formed using the buffer layer and the first two-dimensional electron gas region; The buried area comprises: a first strip of p-type material extending laterally below the gate, the first strip of p-type material having a first dopant concentration that determines a first enhancement mode FET turn-on threshold voltage; and A second strip of p-type material extends laterally beneath the gate, the second strip of p-type material having a second dopant concentration to determine a second enhancement mode FET turn-on threshold voltage. 20 . The semiconductor device according to claim 19 , wherein the first two-dimensional electron gas region is formed at an interface between a first gallium nitride-based compound semiconductor material and a second gallium nitride-based compound semiconductor material. 21 . The semiconductor device of claim 20 , wherein a recess is formed in the first gallium nitride-based compound semiconductor material, the gate being at least partially located in the recess. 22 . The semiconductor device according to claim 19 , wherein the depletion mode FET comprises a second two-dimensional electron gas region.

23. A method for manufacturing an enhancement mode semiconductor device, the method comprising: forming a buffer layer of a first compound semiconductor material on a substrate; forming a p-type layer of a second compound semiconductor material on the buffer layer; forming a channel layer including a heterostructure formed by forming a layer of a third compound semiconductor material on a layer of a fourth compound semiconductor material, the fourth compound semiconductor material being formed on the p-type layer; forming a gate electrode overlying a region of the channel layer; as well as patterning the p-type layer to form a buried region having activated p-type material beneath the gate electrode, the buried region being configured to determine an enhancement mode FET turn-on threshold voltage; The buried area comprises: a first strip of p-type material extending laterally below the gate electrode, the first strip of p-type material having a first dopant concentration that determines a first enhancement mode FET turn-on threshold voltage; and A second strip of p-type material extends laterally beneath the gate electrode, the second strip of p-type material having a second dopant concentration to determine a second enhancement mode FET turn-on threshold voltage.

24. The method of claim 23, wherein the p-type layer is electrically activated, and patterning the p-type layer comprises: Hydrogen is selectively implanted into the region of the second compound semiconductor material exposed by the gate electrode to electrically passivate the exposed region.

25. The method of claim 24, further comprising using the gate electrode as a mask during selective implantation.

26. The method of claim 23, wherein the p-type layer is electrically passivated, and patterning the p-type layer comprises: forming a cavity in the enhancement mode semiconductor device to expose a region of the p-type layer; and The enhancement mode semiconductor device is annealed in an environment containing an activating material.

27. The method of claim 26, further comprising forming a source electrode in the cavity.

28. The method of claim 26, wherein the activating material is a gas comprising nitrogen.

29. The method of claim 23, wherein the p-type layer is electrically passivated, and patterning the p-type layer comprises: Before forming the gate electrode, forming a passivation layer above the enhancement mode semiconductor device; forming a cavity in the passivation layer between the gate electrode and the source electrode, the cavity exposing a region of the second compound semiconductor material; and The enhancement mode semiconductor device is annealed in an environment containing an activating material.

30. The method of claim 23, further comprising: Before forming the gate electrode, a recess is formed in the third compound semiconductor material, the gate electrode being at least partially formed in the recess.

31. The method of claim 23, further comprising: A second p-type layer is formed between the gate electrode and the channel layer.

32. The method of claim 31 further comprising: The p-type layer and the second p-type layer are patterned using the gate electrode as a mask.

33. The method of claim 23, wherein the p-type layer is electrically activated, and patterning the p-type layer comprises: forming a passivation layer over the enhancement mode semiconductor device; forming a first cavity in the passivation layer between the gate electrode and the source electrode, the first cavity exposing a first region of the second compound semiconductor material; forming a second cavity in the passivation layer between the gate electrode and the drain electrode, the second cavity exposing a second region of the second compound semiconductor material; and The enhancement mode semiconductor device is annealed in an environment containing a passivation material.

34. The method of claim 33, wherein the passivating material is hydrogen.

35. The method of claim 23, wherein: The layer of the third compound semiconductor material has a first thickness, the method comprising: forming a mask on the layer of the third compound semiconductor material, developing the layer of the third compound semiconductor material to increase the thickness of the layer of the third compound semiconductor material to a second thickness; removing the mask to expose the recess in the layer of the third compound semiconductor material; and The gate electrode is formed in the recess. 36 . The method of claim 35 , further comprising determining the first thickness based on a target turn-on threshold voltage that allows current to flow between a source and a drain of the enhancement mode semiconductor device.

37. The method of claim 35, wherein the mask comprises silicon nitride or silicon oxide.

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