Camera components and electronic devices

Abstract

The present invention includes: a first substrate on which a plurality of photoelectric conversion elements are formed; a second substrate on which a pixel transistor is formed for each group having two or more of the photoelectric conversion elements as a unit, and the pixel transistor is shared by the group; and a second wiring, which is connected to a second element common to the plurality of first elements for each photoelectric conversion element among the plurality of elements formed on the first substrate, and is connected to a first wiring formed on the second substrate via a contact portion, and is connected to a plurality of first elements.

Description

Technical Field

[0001] The present disclosure relates to an image pickup element and an electronic device such as a camera provided with the image pickup element. Background Art

[0002] In an imaging device such as a complementary metal-oxide-semiconductor (CMOS), in one example, a configuration is known in which a first semiconductor substrate having a pixel area and a second semiconductor substrate having a logic circuit are stacked on each other (for example, see Patent Document 1 or other related technologies).

[0003] Reference List

[0004] Patent Literature

[0005] Patent Document 1: JP 2010-245506A Summary of the invention

[0006] Technical Problems Solved by the Invention

[0007] The imaging device disclosed in Patent Document 1 has a photoelectric converter and a pixel transistor arranged on the same semiconductor substrate. The pixel transistor reads out an electrical signal corresponding to the amount of light received by the photoelectric converter. However, this configuration cannot satisfactorily reduce the area of ​​the substrate (the space on the substrate surface on which circuit elements such as transistors are formed).

[0008] Therefore, in one example, it is conceivable that a substrate (first substrate) on which a photoelectric converter is formed and a substrate (second substrate) on which a pixel transistor is formed are stacked on each other. In this configuration, in one example, a plurality of photoelectric converters corresponding to a plurality of pixels are set to share a pixel transistor. In this case, in the elements arranged on the first substrate (e.g., circuit elements such as transistors), a plurality of first elements provided for each corresponding photoelectric converter are connected in common to a second element to be a shared element.

[0009] The above configuration requires connecting the plurality of first elements on the first substrate one by one using contacts to wirings leading to the second elements (shared by the first elements and formed on the second substrate), which increases the number of contacts used for wiring, resulting in a large area.

[0010] The present disclosure aims to provide an image pickup element and an electronic device capable of reducing a substrate mounting area.

[0011] Technical Solution

[0012] In order to achieve the above-mentioned purpose, the imaging element according to the present disclosure is such an imaging element, which includes: a first substrate, on which a plurality of photoelectric converters are formed; a second substrate, on which pixel transistors are formed for each group having two or more of the photoelectric converters as constituent units, and the pixel transistors are shared by the groups; and a second wiring, which is connected to a first wiring formed on the second substrate via a contact portion and is connected to a plurality of first elements, the first wiring leading to a second element shared by the plurality of first elements among the plurality of elements formed on the first substrate, and each of the plurality of first elements is formed for each of the photoelectric converters.

[0013] The term "element" used here is a concept that includes all or part of circuit components such as photoelectric converters, transistors, and wiring (including electrodes) formed on a substrate (semiconductor substrate). In addition, the term "pixel transistor" is a transistor that is used to read out an electrical signal corresponding to the amount of light received by the photoelectric converter and can be shared by multiple photoelectric converters (pixels). In one example, the pixel transistor includes at least an amplifier transistor that amplifies and outputs an electrical signal provided from the photoelectric converter.

[0014] (Mode of operation) The imaging element of the present disclosure is provided with a first wiring and a second wiring. The first wiring formed on the second substrate leads to a second element shared by a plurality of first elements on the first substrate. The second wiring is connected to the first wiring via a contact portion and to a plurality of first elements. In other words, the second wiring gathers a plurality of first elements and is connected via a contact portion to a wiring leading to a second element shared (commonly connected) by a plurality of first elements. This makes it sufficient to set the number of contacts formed in the first wiring (for connecting a plurality of first elements as a constituent unit of the gathering) to one. Therefore, the number of contacts and the area of ​​the first wiring can be reduced.

[0015] In addition, the imaging element of the present disclosure has a first substrate on which a photoelectric converter is formed and a second substrate on which a pixel transistor is formed. The first substrate and the second substrate are stacked on each other. Therefore, the area of ​​the substrate can be reduced.

[0016] Effects of the Invention

[0017] According to the present disclosure, the area of ​​the substrate can be reduced. It should be noted that the beneficial effects described here are not restrictive, and any beneficial effects described in the present disclosure can be obtained. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 : is a diagram showing an example of a schematic configuration of an image pickup element applied to each embodiment of the present disclosure.

[0019] Figure 2 It is shown Figure 1 Diagram of an example of a sensor pixel and readout circuitry shown.

[0020] Figure 3 It is shown Figure 1 Diagram of an example of a sensor pixel and readout circuitry shown.

[0021] Figure 4 It is shown Figure 1 Diagram of an example of a sensor pixel and readout circuitry shown.

[0022] Figure 5 It is shown Figure 1 Diagram of an example of a sensor pixel and readout circuitry shown.

[0023] Figure 6 is a diagram showing an example of a connection method between a plurality of readout circuits and a plurality of vertical signal lines.

[0024] Figure 7 It is shown Figure 1 FIG. 1 is a diagram showing an example of a cross-sectional configuration of an imaging element in the vertical direction.

[0025] Figure 8 FIG. 1 is a diagram showing a modified example of the N-type semiconductor region constituting the photodiode of the first embodiment.

[0026] Fig. 9 It is a diagram showing a modified example of the structure of the image pickup element of the first embodiment.

[0027] Fig.10 is a diagram showing the arrangement of connection points between the second substrate and the third substrate.

[0028] Fig.11 1 is a diagram showing a modified example of the arrangement of the connection points between the second substrate and the third substrate.

[0029] Fig.12 It is shown Figure 1 A diagram showing an example of a cross-sectional configuration of an imaging element in the horizontal direction.

[0030] Fig.13 It is shown Figure 1 A diagram showing an example of a cross-sectional configuration of an imaging element in the horizontal direction.

[0031] Fig.14 It is shown Figure 1 A diagram showing an example of a wiring layout of an imaging element in a horizontal plane.

[0032] Fig.15 It is shown Figure 1 A diagram showing an example of a wiring layout of an imaging element in a horizontal plane.

[0033] Fig.16It is shown Figure 1 A diagram showing an example of a wiring layout of an imaging element in a horizontal plane.

[0034] Fig.17 It is shown Figure 1 A diagram showing an example of a wiring layout of an imaging element in a horizontal plane.

[0035] Fig.18 It is a diagram for explaining an example of a method for manufacturing the image pickup element according to the first embodiment.

[0036] Fig.19 It is a diagram for explaining an example of a method for manufacturing the image pickup element according to the first embodiment.

[0037] Fig. 20 It is a diagram for explaining an example of a method for manufacturing the image pickup element according to the first embodiment.

[0038] Fig.21 It is a diagram for explaining an example of a method for manufacturing the image pickup element according to the first embodiment.

[0039] Fig. 22 This is a diagram for explaining an example of a method for manufacturing the image pickup element of the first embodiment.

[0040] Fig.23 It is a diagram for explaining an example of a method for manufacturing the image pickup element according to the first embodiment.

[0041] Fig.24 It is a diagram for explaining an example of a method for manufacturing the image pickup element according to the first embodiment.

[0042] Fig.25 It is a diagram for explaining an example of a method for manufacturing the image pickup element according to the first embodiment.

[0043] Fig.26 1 is a diagram showing a partial cross section of an image pickup element when a configuration in which no wiring is provided is adopted.

[0044] Fig. 27 This is a diagram showing a partial cross section of the image pickup element according to the first embodiment.

[0045] Fig.28 is a schematic plan view of a first substrate of the first embodiment.

[0046] Fig.29 is a schematic plan view of a second substrate of the first embodiment.

[0047] Fig.30 is a schematic plan view of an arrangement in which a second substrate and a first substrate are arranged on top of each other according to the first embodiment.

[0048] Fig.31A diagram showing a modified example of the wiring layout.

[0049] Fig.32 is a schematic plan view of a first substrate according to a modification of the first embodiment.

[0050] Fig.33 is a schematic plan view of a second substrate according to a modification of the first embodiment.

[0051] Fig.34 It is a diagram showing a partial cross section of an image pickup element according to a fourth embodiment.

[0052] Fig.35 It is a diagram showing a partial cross section of an image pickup element according to a fifth embodiment.

[0053] Fig.36 It is a diagram showing a partial cross section of an image pickup element according to a sixth embodiment.

[0054] Fig.37 is a diagram showing a partial cross section of an image pickup element according to a modification of the sixth embodiment.

[0055] Fig.38 is a diagram showing a configuration example of a camera as an example of an electronic device that employs the image pickup element of the present disclosure.

[0056] Fig.39 It is shown Figure 1 Diagram of an example of a sensor pixel and readout circuitry.

[0057] Fig.40 It is shown Figure 1 Diagram of an example of a sensor pixel and readout circuitry.

[0058] Fig.41 It is shown Figure 1 Diagram of an example of a sensor pixel and readout circuitry.

[0059] Fig.42 It is shown Figure 1 Diagram of an example of a sensor pixel and readout circuitry.

[0060] Fig.43 It is shown Figure 1 FIG. 1 is a diagram showing an example of a cross-sectional configuration of an imaging element in the vertical direction.

[0061] Fig.44 It is shown Figure 1 A diagram showing an example of a cross-sectional configuration of an imaging element in the horizontal direction.

[0062] Fig.45 It is shown Figure 1 A diagram showing an example of a cross-sectional configuration of an imaging element in the horizontal direction.

[0063] Fig.46 It is shown Figure 1 A diagram showing an example of a cross-sectional configuration of an imaging element in the horizontal direction.

[0064] Fig.47 It is shown Figure 1 A diagram showing an example of a cross-sectional configuration of an imaging element in the horizontal direction.

[0065] Fig.48 It is shown Figure 1 A diagram showing an example of a cross-sectional configuration of an imaging element in the horizontal direction.

[0066] Fig.49 It is shown Figure 1 A diagram showing an example of a cross-sectional configuration of an imaging element in the horizontal direction.

[0067] Fig.50 It is shown Figure 1 A diagram showing an example of a cross-sectional configuration of an imaging element in the horizontal direction.

[0068] Fig.51 : is a diagram showing an example of a circuit configuration of an image pickup device including an image pickup element according to the above-described embodiment and its modified examples.

[0069] Fig.52 The structure is shown as a structure formed by stacking three substrates on top of each other. Fig.51 FIG. 1 is a diagram of an example of an imaging element.

[0070] Fig.53 1 is a diagram showing an example in which a logic circuit is formed on a substrate provided with sensor pixels and on a substrate provided with a readout circuit, respectively.

[0071] Fig.54 2 is a diagram showing an example in which a logic circuit is formed on a third substrate.

[0072] Fig.55 is a diagram showing an example of a schematic configuration of an imaging system having an imaging element.

[0073] Fig.56 It is shown Fig.55 FIG. 1 is a diagram of an example of an imaging step in an imaging system.

[0074] Fig.57 is a block diagram showing an example of a schematic configuration of a vehicle control system.

[0075] Fig.58 It is a diagram for assisting in explaining an example of the installation positions of the vehicle exterior information detection unit and the camera unit.

[0076] Fig.59 is a diagram showing a schematic configuration of an endoscopic surgery system.

[0077] Fig.60 is a block diagram showing an example of the functional structure of a camera head and a camera control unit (CCU). DETAILED DESCRIPTION

[0078] Now, examples of an image pickup element and an electronic device according to an embodiment of the present disclosure will be described in detail with reference to the drawings. The description will be given in the following order.

[0079] 1. Schematic configuration example of an imaging element

[0080] 2. First Embodiment (Configuration Example of Image Pickup Element)

[0081] 3. Second Embodiment (Configuration Example of Image Pickup Element)

[0082] 4. Third Embodiment (Configuration Example of Image Pickup Element)

[0083] 5. Fourth Embodiment (Configuration Example of Image Pickup Element)

[0084] 6. Fifth Embodiment (Configuration Example of Image Pickup Element)

[0085] 7. Sixth Embodiment (Configuration Example of Image Pickup Element)

[0086] 8. Seventh Embodiment (Configuration Example of Electronic Device)

[0087] 9. Modifications

[0088] 10. Application examples

[0089] 11. Use Case

[0090] <1. Schematic Configuration Example of Image Pickup Element>

[0091] Figure 1 1 is a diagram showing an example of a schematic configuration of an image pickup element 1 applied to each embodiment of the present disclosure. The image pickup element 1 converts received light into an electric signal and outputs it as a pixel signal. In this example, the image pickup element 1 is configured as a CMOS image pickup element.

[0092] Figure 1 An example of a schematic configuration of an image pickup element 1 according to an embodiment of the present disclosure is shown. The image pickup element 1 includes three substrates (a first substrate 10, a second substrate 20, and a third substrate 30). The image pickup element 1 is an image pickup device having a three-dimensional structure in which the three substrates (the first substrate 10, the second substrate 20, and the third substrate 30) are combined together. The first substrate 10, the second substrate 20, and the third substrate 30 are sequentially stacked on each other.

[0093] The first substrate 10 has a plurality of sensor pixels 12 that perform photoelectric conversion. The sensor pixels 12 are arranged on a semiconductor substrate 11. The plurality of sensor pixels 12 are arranged in a matrix form in a pixel region 13 of the first substrate 10. The second substrate 20 has a readout circuit 22 for every four sensor pixels 12. The readout circuit 22 outputs a pixel signal based on the charge output by the sensor pixel 12 to a semiconductor substrate 303. The second substrate 20 has a plurality of pixel drive lines 23 extending in a row direction and a plurality of vertical signal lines 24 extending in a column direction. The third substrate 30 has a logic circuit 32 formed on a semiconductor substrate 31. The logic circuit 32 processes pixel signals. In one example, the logic circuit 32 has a vertical drive circuit 33, a column signal processing circuit 34, a horizontal drive circuit 35, and a system control circuit 36. The logic circuit 32 (specifically, its horizontal drive circuit 35) outputs an output voltage Vout for each sensor pixel 12 to the outside. In one example, the logic circuit 32 may have a low resistance region including silicide made by processing using a self-aligned silicide (salicide) such as CoSi 2 or NiSi on the surface of the impurity diffusion region contacting the source and the drain.

[0094] In one example, the vertical drive circuit 33 sequentially selects a plurality of sensor pixels 12 in units of rows. In one example, the column signal processing circuit 34 performs correlated double sampling (CDS) processing on the pixel signals output by each sensor pixel 12 in the row selected by the vertical drive circuit 33. In one example, the column signal processing circuit 34 extracts the signal level of the pixel signal processed by CDS and holds the pixel data corresponding to the amount of light received by each sensor pixel 12. In one example, the horizontal drive circuit 35 sequentially outputs the pixel data held in the column signal processing circuit 34 to the outside. In one example, the system control circuit 36 ​​controls the driving of each module in the logic circuit 32 (i.e., the vertical drive circuit 33, the column signal processing circuit 34, and the horizontal drive circuit 35).

[0095] Figure 2 1 is a diagram showing an example of a sensor pixel 12 and a readout circuit 22. Figure 2 The description will be made of a case where four sensor pixels 12 share one readout circuit 22. The term “share” used herein means that the outputs of the four sensor pixels 12 are input to the common readout circuit 22.

[0096] The sensor pixels 12 each have constituent elements in common with each other. Figure 2, an identification number (i.e., 1, 2, 3, or 4) is attached to the end of the reference numeral representing the component of each sensor pixel 12 to distinguish the components of each sensor pixel 12 from each other. In the case where it is necessary to distinguish the components of each sensor pixel 12 from each other, the identification number is attached to the end of the reference numeral of the component of each sensor pixel 12. However, in the case where it is not necessary to distinguish the components of each sensor pixel 12 from each other, the identification number at the end of the reference numeral of the component of each sensor pixel 12 may be omitted.

[0097] In one example, the sensor pixels 12 each have a photodiode PD, a transfer transistor TR electrically connected to the photodiode PD, and a floating diffusion FD that temporarily holds the charge output from the photodiode PD via the transfer transistor TR. The photodiode PD corresponds to a specific implementation example of the "photoelectric converter" of the present disclosure. The photodiode PD performs photoelectric conversion to generate a charge corresponding to the amount of received light. The cathode of the photodiode PD is electrically connected to the source of the transfer transistor TR, and the anode of the photodiode PD is electrically connected to a reference potential line (e.g., ground). The drain of the transfer transistor TR is electrically connected to the floating diffusion FD, and the gate of the transfer transistor TR is electrically connected to the pixel drive line 23. In one example, the transfer transistor TR is a complementary metal oxide semiconductor (CMOS) transistor.

[0098] The floating diffusion regions FD of the sensor pixels 12 that share a common readout circuit 22 are electrically connected to each other and are also electrically connected to the input terminal of the common readout circuit 22. In one example, the readout circuit 22 has a reset transistor RST, a selection transistor SEL, and an amplifier transistor AMP. Moreover, if necessary, the selection transistor SEL can be omitted. The source of the reset transistor RST (the input terminal of the readout circuit 22) is electrically connected to the floating diffusion FD, and the drain of the reset transistor RST is electrically connected to the power supply line VDD and the drain of the amplifier transistor AMP. The gate of the reset transistor RST is electrically connected to the pixel drive line 23 (see Figure 1 The source of the amplifier transistor AMP is electrically connected to the drain of the selection transistor SEL, and the gate of the amplifier transistor AMP is electrically connected to the source of the reset transistor RST. The source of the selection transistor SEL (the output end of the readout circuit 22) is electrically connected to the vertical signal line 24, and the gate of the selection transistor SEL is electrically connected to the pixel drive line 23 (see Figure 1 ).

[0099] When the transfer transistor TR is turned on, the charge of the photodiode PD is transferred to the floating diffusion FD. The reset transistor RST resets the potential of the floating diffusion FD to a predetermined potential. When the reset transistor RST is turned on, the potential of the floating diffusion FD is reset to the potential of the power line VDD. The selection transistor SEL controls the output timing of the pixel signal from the readout circuit 22. The amplifier transistor AMP generates a voltage signal corresponding to the level of the charge held in the floating diffusion FD as a pixel signal. The amplifier transistor AMP constitutes a source follower amplifier and outputs a pixel signal having a voltage corresponding to the level of the charge generated by the photodiode PD. When the selection transistor SEL is turned on, the amplifier transistor AMP amplifies the potential of the floating diffusion FD, and outputs a voltage corresponding to the amplified potential to the column signal processing circuit 34 via the vertical signal line 24. In one example, the reset transistor RST, the amplifier transistor AMP, and the selection transistor SEL are CMOS transistors.

[0100] As described above, for each constituent unit of the four sensor pixels 12 in which one readout circuit 22 is shared (hereinafter may be referred to as a "shared constituent unit" or a "shared constituent unit circuit"), four photoelectric converters PD, four transfer transistors TR, one amplifier transistor AMP, one reset transistor RST, and one selection transistor SEL are included. The transfer transistors TR correspond to the photoelectric converters PD one by one. In this example, the four pixels (at least the sensor pixels 12 including the photoelectric converter PD) share a combination of one amplifier transistor AMP, one reset transistor RST, and one selection transistor SEL. In this example, the combination of one amplifier transistor AMP, one reset transistor RST, and one selection transistor SEL corresponds to a "pixel transistor".

[0101] Moreover, as described above, a plurality of photodiodes PD corresponding one-to-one to a plurality of pixels are formed on the first substrate 10 corresponding to the "first substrate" of the present disclosure. More specifically, a transfer transistor TR for transmitting an electrical signal output by the photodiode PD to a pixel transistor is also formed on the first substrate 10 for each of the plurality of photodiodes PD. In this description, two photodiodes PD included in the plurality of photodiodes PD formed on the first substrate 10 correspond to the "first photoelectric converter" and the "second photoelectric converter", respectively. Furthermore, the transfer transistor TR connected to the photodiode PD corresponding to the first photoelectric converter corresponds to the "first transfer transistor", and the transfer transistor TR connected to the photodiode PD corresponding to the second photoelectric converter corresponds to the "second transfer transistor". In other words, the first photoelectric converter and the second photoelectric converter are formed on the first substrate 10. Therefore, it can be considered that the first substrate 10 has a first transfer transistor connected to the first photoelectric converter and a second transfer transistor connected to the second photoelectric converter.

[0102] Moreover, for each group of two or more (four in this example) photodiodes PD as a constituent unit, a group of common pixel transistors is formed on the second substrate 20 corresponding to the "second substrate" of the present disclosure. More specifically, pixel transistors including at least one amplifier transistor AMP (which amplifies and outputs an electrical signal transmitted from each of the two or more transmission transistors TR included in one group) are formed on the second substrate 20 for each group or groups. In this description, it can be considered that the pixel transistors connected to the first photoelectric converter and the second photoelectric converter are formed on the second substrate.

[0103] Moreover, if Figure 3 As shown, the selection transistor SEL can be arranged between the power supply line VDD and the amplifier transistor AMP. In this case, the drain of the reset transistor RST is electrically connected to the power supply line VDD and the drain of the selection transistor SEL. The source of the selection transistor SEL is electrically connected to the drain of the amplifier transistor AMP, and the gate of the selection transistor SEL is electrically connected to the pixel drive line 23 (see Figure 1 ). The source of the amplifier transistor AMP (the output terminal of the readout circuit 22) is electrically connected to the vertical signal line 24, and the gate of the amplifier transistor AMP is electrically connected to the source of the reset transistor RST. Figure 4 and Figure 5 As shown, the FD transfer transistor FDG may be provided between the source of the reset transistor RST and the gate of the amplifier transistor AMP.

[0104] The FD transfer transistor FDG is used to switch the conversion efficiency. The pixel signal is usually small when shooting in a dark place. If the capacitance (FD capacitance C) of the floating diffusion FD is large when the charge-to-voltage conversion is performed based on the formula Q=CV, V is small during the voltage conversion through the amplifier transistor AMP. On the other hand, in a bright place, because the pixel signal is large, the floating diffusion FD cannot receive the charge of the photodiode PD unless the FD capacitance C is large. Moreover, the FD capacitance C needs to be large so that V does not become too large (in other words, remains small) during the voltage conversion through the amplifier transistor AMP. In view of this, when the FD transfer transistor FDG is turned on, the total FD capacitance C increases due to the increase in the gate capacitance of the FD transfer transistor FDG. On the other hand, when the FD transfer transistor FDG is turned off, the total FD capacitance C is small. Therefore, the on / off switching of the FD transfer transistor FDG makes the FD capacitance C variable, so that the conversion efficiency can be switched.

[0105] Figure 62 is a diagram showing an example of a connection method between a plurality of readout circuits 22 and a plurality of vertical signal lines 24. In the case where a plurality of readout circuits 22 are arranged side by side in the extending direction of the vertical signal lines 24 (for example, the column direction), the plurality of vertical signal lines 24 may be respectively allocated to the readout circuits 22. In one example, as Figure 6 As shown, in the case where four readout circuits 22 are arranged side by side in the extending direction (eg, column direction) of the vertical signal lines 24, the four vertical signal lines 24 can be allocated to the respective readout circuits 22. Figure 6 In order to distinguish each vertical signal line 24 , an identification number ( 1 , 2 , 3 , or 4 ) is attached to the end of the reference numeral of each vertical signal line 24 .

[0106] <2. First Embodiment>

[0107] (Arrangement example of imaging element)

[0108] The configuration of the image pickup element 1 according to the first example and a method of manufacturing the same will now be described.

[0109] Figure 7 1 is a diagram showing a partial cross-sectional view corresponding to one common constituent unit circuit of the image pickup element 1 according to the present embodiment. Figure 7 As shown, the imaging element 1 includes a first substrate 10, a second substrate 20, and a third substrate 30 that are stacked on each other and electrically connected. A peripheral circuit is formed on the third substrate 30. In this example, the peripheral circuit includes a logic circuit 32 having a vertical drive circuit 33, a column signal processing circuit 34, a horizontal drive circuit 35, and a system control circuit 36. The peripheral circuit is formed on the third substrate 30. In addition, in one example, all or part of the elements included in the peripheral circuit (such as the vertical drive circuit 33, the column signal processing circuit 34, the horizontal drive circuit 35, and the system control circuit 36) can be formed on the first substrate 10 or the second substrate 20. In this example, the third substrate 30 includes at least the logic circuit 32. The logic circuit 32 corresponds to a "logic circuit formed on the second substrate for processing a signal generated by the first photoelectric converter or the second photoelectric converter". The third substrate 30 corresponds to the "third substrate" of the present disclosure. Moreover, Figure 7 The surface 501 shown represents the surface where the first substrate 10 and the second substrate 20 are bonded together. Figure 7 The illustrated surface 502 represents the surface where the second substrate 20 and the third substrate 30 are bonded together.

[0110] The imaging element 1 according to the present embodiment includes a first wiring and a second wiring. The first wiring is formed on the second substrate 20 and leads to a second element common to a plurality of first elements provided for each photodiode PD among a plurality of elements formed on the first substrate 10. The second wiring is connected to the first wiring via a contact portion. A plurality of first elements are connected to the second wiring. Figure 7 In the example of , the imaging element 1 is provided with a wiring 301 ("second wiring"), which connects the output end side ("first element") of the plurality of transfer transistors TR to a wiring D1 ("first wiring") formed on the second substrate 20 via a contact portion. The wiring D1 leads to the gate ("second element") of the amplifier transistor AMP shared (commonly connected) by the output end side of the plurality of transfer transistors TR. This will be described in detail later.

[0111] Now explain Figure 7 The configuration of the imaging element 1 is shown. Figure 7 As shown, the first substrate 10 is formed by stacking an insulating layer 240 on the semiconductor substrate 11. The first substrate 10 has the insulating layer 240 as a part of the interlayer insulating film 51. The insulating layer 240 is provided in a gap between the semiconductor substrate 11 and a semiconductor substrate 303 described later. The semiconductor substrate 11 is configured as a silicon substrate. In one example, the semiconductor substrate 11 has a P-type semiconductor region 204 (P-well) in a part of the surface or near the surface, and has a conductive (N-type) photodiode PD different from the P-type semiconductor region 204 in another region (region deeper than the P-type semiconductor region 204).

[0112] A plurality of photodiodes PD are formed on the first substrate 10. In addition, a plurality of transfer transistors TR corresponding to the plurality of photodiodes PD are formed on the first substrate 10. Figure 7 In the example of , the photodiode PD is formed in an N-type semiconductor region, and a P-type semiconductor region 202 different from the photodiode PD is formed to cover the side thereof. The photodiodes PD are electrically isolated from each other by a pixel isolation portion 203 for isolating (separating) pixels. In one example, the pixel isolation portion 203 includes a metal, an insulating film (e.g., SiO2), a combination of the two, or the like.

[0113] On the lower surface of the photodiode PD, an insulating film 211 is formed to cover the first substrate 10. In one example, the insulating film 211 includes a film having a fixed charge, etc. Another insulating film as a planarization film 213 may be formed between the insulating film 211 and the color filter 212. The insulating film 211 includes a metal oxide film such as hafnium oxide, tantalum oxide, or aluminum oxide. The planarization film 213 includes an insulating film such as silicon oxide or silicon nitride. Moreover, the insulating film 211 and the planarization film 213 may be arranged in a multilayer form. An on-chip lens 214 is formed below the color filter 212. The on-chip lens 214 gathers the irradiated light, and the gathered light is guided to the photodiode PD through the color filter 212.

[0114] Moreover, the N-type transfer transistor TR is formed on the photodiode PD. More specifically, a P-type semiconductor region 204 (P well) is formed on the photodiode PD in the first substrate 10, and an N-type drain region 221 and an N-type source region 222 are formed near the surface of the semiconductor region 204. And, a gate 223 is formed between the N-type drain region 221 and the N-type source region 222 on the semiconductor region 204. In this example, the gate 223 leads to the photodiode PD. In addition, in this example, the P-type semiconductor region 202 covering the side of the photodiode PD extends to cover a portion of the side of the semiconductor region 204, but its configuration is not limited to the above example. The P-type semiconductor region 202 can have any depth. In one example, the upper surface of the semiconductor region 202 can be flush with the lower surface of the semiconductor region 204.

[0115] Furthermore, the photodiode PD can have any depth, in one example, Figure 8 As shown, a portion of the photodiode PD reaches the same height as the surface of the P-type semiconductor region 204 on which the transfer transistor TR is formed. In this case, the P-type semiconductor region is preferably formed on the N-type photodiode PD, but its arrangement may be Figure 8 Furthermore, in one example, Fig. 9 As shown, the gate 223 of the transfer transistor TR may be formed on the semiconductor region 204 without leading to the photodiode PD. In other words, the transfer transistor TR may have a flat gate (gate 223).

[0116] Refer to Figure 7 Continue to explain. Figure 7 As shown, the source region 222 of each transfer transistor TR is connected to the wiring 301. In this example, since the source region 222 is an N-type semiconductor region, the wiring 301 is formed as P-type polysilicon. Each transfer transistor TR and the wiring 301 are covered by an insulating layer 240, and a semiconductor substrate 303 is formed on the insulating layer 240.

[0117] Furthermore, it can be considered that the combination of the semiconductor substrate 303 and the elements formed on the semiconductor substrate 303 corresponds to the "second substrate" of the present disclosure, or it can be considered that only the semiconductor substrate 303 corresponds to the "second substrate" of the present disclosure. Similarly, for the first substrate 10, it can be considered that the combination of the base silicon substrate and the elements formed on the silicon substrate corresponds to the "first substrate" of the present disclosure, or it can be considered that only the silicon substrate corresponds to the "first substrate" of the present disclosure.

[0118] As described above, pixel transistors are formed on the second substrate 20. The pixel transistors include at least an amplifier transistor AMP. In this example, each transistor included in the pixel transistor is an N-channel MOS transistor, and the semiconductor substrate 303 is a P-type silicon substrate.

[0119] The wiring 301 is connected to the wiring D1 formed on the second substrate 20 via the contact portion Ct penetrating the semiconductor substrate 303. In this example, the second substrate 20 is constituted by laminating the insulating layer 245 above the semiconductor substrate 303. The second substrate 20 has the insulating layer 245 as a part of the interlayer insulating film 51. The insulating layer 245 is provided in the gap between the semiconductor substrate 303 and the semiconductor substrate 31 described later. The second substrate 20 has one readout circuit 22 for every four sensor pixels 12. The second substrate 20 is arranged so that the readout circuit 22 is provided on the surface side (third substrate 30 side) of the semiconductor substrate 303. The second substrate 20 is bonded to the first substrate 10 with the rear surface of the semiconductor substrate 303 facing the front surface side of the semiconductor substrate 11. In other words, the second substrate 20 is bonded to the first substrate 10 in a face-to-back orientation. The second substrate 20 also has the insulating layer 53 penetrating the semiconductor substrate 303 in the same layer as the semiconductor substrate 303. The second substrate 20 has the insulating layer 53 as a part of the interlayer insulating film 51. The insulating layer 53 is provided to cover the side surfaces of the contact portion Ct penetrating the semiconductor substrate 303 .

[0120] The stacked structure having the first substrate 10 and the second substrate 20 has one contact Ct for each sensor pixel 12. The first substrate 10 and the second substrate 20 are electrically connected to each other through the contact Ct. Specifically, the contact Ct is electrically connected to a floating diffusion FD and a wiring D1 described later.

[0121] The stacked structure having the first substrate 10 and the second substrate 20 further has through wirings 47 and 48 (see later described) provided in the interlayer insulating film 51. Fig.12The stacked structure has one through wiring 47 and one through wiring 48 for each sensor pixel 12. The through wirings 47 and 48 extend in the normal direction of the semiconductor substrate 303 and are arranged to penetrate the semiconductor substrate 303. The first substrate 10 and the second substrate 20 are electrically connected to each other through the through wirings 47 and 48. Specifically, the through wiring 47 is electrically connected to the P-type semiconductor region 204 of the semiconductor substrate 11 and the wiring in the second substrate 20. The through wiring 48 is electrically connected to the gate 223 of the transfer transistor TR and the pixel drive line 23.

[0122] The above-mentioned contact portion Ct penetrates the insulating layer 245 and is connected to the wiring D1 included in the wiring layer 246 formed on the insulating layer 245. In one example, the wiring layer 246 includes an insulating layer 247 and a plurality of pixel drive lines 23, a plurality of vertical signal lines 24, etc. provided in the insulating layer 247. In one example, the wiring layer 246 also has a plurality of pad electrodes 58 in the insulating layer 247. In one example, each pad electrode 58 includes a metal such as copper (Cu) or aluminum (Al). Each pad electrode 58 is exposed on the surface of the wiring layer 246. Each pad electrode 58 is used for electrical connection between the second substrate 20 and the third substrate 30 and for combining the second substrate 20 and the third substrate 30 with each other. In one example, a plurality of pad electrodes 58 are provided one by one for each of the pixel drive line 23 and the vertical signal line 24. In this example, the total number of pad electrodes 58 or the total number of contact points between the pad electrodes 58 and pad electrodes 64 (described later) is smaller than the total number of sensor pixels 12 included in the first substrate 10 .

[0123] The above-mentioned wiring D1 is connected to the gate 311 of the amplifier transistor AMP via the contact portion Ct2. Also, a region from the source region 222 via the wiring 301 and the wiring D1 to the gate 311 is a region serving as the above-mentioned floating diffusion portion FD.

[0124] In other words, the wiring 301 gathers the source regions 222 (output terminal side) of each transfer transistor TR of the first substrate 10. And, the wiring 301 connects the gathered source regions 222 to the wiring D1 of the second substrate 20 via a contact portion Ct. The wiring D1 leads to the gate 311 of the amplifier transistor AMP shared by the source regions 222 of each transfer transistor TR. Moreover, in this example, the wiring 301 is formed as a whole, but its configuration is not limited to the above example, and in one example, wirings formed of different materials can be connected to each other. In one example, the wiring extending in the vertical direction from the source region 222 (output terminal side or FD) of each transfer transistor TR and the common wiring extending in the horizontal direction are formed of different materials, and they can be connected to each other to constitute the wiring 301.

[0125] In this example, the source region 222 (output terminal side) of the transfer transistor TR corresponds to the "first element" provided for each photodiode PD among the plurality of elements formed on the first substrate 10. In addition, the gate 311 (gate) of the amplifier transistor AMP corresponds to the "second element" to which the plurality of first elements are commonly connected. In addition, the wiring D1 is a wiring leading to the second element common to the plurality of first elements and corresponds to the "first wiring" formed on the second substrate 20. In addition, the wiring D1 also corresponds to the "second wiring formed on the second substrate 20". Moreover, the wiring 301 corresponds to the "second wiring" which is connected to the first wiring via one contact portion Ct and is connected to the plurality of first elements. In addition, as described above, the wiring 301 is connected (indirectly connected) to each corresponding photodiode PD via the source region 222 of the transfer transistor TR. In other words, it can be considered that the wiring 301 is "a first wiring formed on the first substrate 10 and connected to the first photoelectric converter and the second photoelectric converter". Moreover, the term "connection" used here includes not only a direct connection form but also an indirect connection form as described above. In addition, the wiring 301 is connected to the source region 222 of each transfer transistor TR. In other words, it can be considered that the wiring 301 is connected to the first floating diffusion region connected to the first transfer transistor and the second floating diffusion region connected to the second transfer transistor. In addition, the contact portion Ct corresponds to "a third wiring formed to penetrate the first substrate 10 and the second substrate 20 and connected to the first wiring and the second wiring".

[0126] In one example, the third substrate 30 is formed by stacking an interlayer insulating film 61 on a semiconductor substrate 31. The semiconductor substrate 31 is configured as a silicon substrate. The third substrate 30 has a logic circuit 32 provided on the front surface side of the semiconductor substrate 31. In one example, the third substrate 30 also has a wiring layer 62 on the interlayer insulating film 61. In one example, the wiring layer 62 has an insulating layer 63 and a plurality of pad electrodes 64 provided in the insulating layer 63. The plurality of pad electrodes 64 are electrically connected to the logic circuit 32. Each pad electrode 64 includes, for example, copper (Cu). Each pad electrode 64 is exposed on the front surface of the wiring layer 62. Each pad electrode is used for electrical connection between the second substrate 20 and the third substrate 30 and for combining the second substrate 20 and the third substrate 30. In addition, the number of pad electrodes 64 does not necessarily have to be multiple, and even one pad electrode 64 can be electrically connected to the logic circuit 32. The second substrate 20 and the third substrate 30 are electrically connected to each other by connecting the pad electrodes 58 and 64 to each other. In other words, the gate 223 of the transfer transistor TR is electrically connected to the logic circuit 32 via the above-mentioned contact portion Ct and the pad electrodes 58 and 64. The third substrate 30 is bonded to the second substrate 20, and the surface of the semiconductor substrate 31 faces the front surface side of the semiconductor substrate 303. In other words, the third substrate 30 is bonded to the second substrate 20 in a face-to-face orientation.

[0127] like Fig.10 As shown, the bonding point 503 between the pad electrode 58 of the second substrate 20 and the pad electrode 64 of the third substrate 30 is arranged above the pixel area 13. However, the arrangement is not limited to the above example. In one example, the following example can be used: Fig.11 The form shown. Fig.11 In the form of, the bonding point 503 between the pad electrode 58 of the second substrate 20 and the pad electrode 64 of the third substrate 30 is arranged above the outer area of ​​the pixel area 13. In other words, the pad electrode 58 of the second substrate 20 can be arranged outside the pixel area 13 and can be connected to the pad electrode 64 of the third substrate 30.

[0128] Fig.12 and Fig.13 An example of a cross-sectional configuration in the horizontal direction of the image pickup element 1 is shown. Fig.12 and Fig.13 The figure above shows Figure 7 An example of a cross-sectional configuration of the cross-sectional area Sec1, Fig.12 and Fig.13 The following figure shows Figure 7 Cross-sectional configuration of cross-sectional area Sec2. Fig.12 A configuration is shown in which two groups of two by two four sensor pixels 12 are arranged along the second direction V2. Fig.13 FIG. 4 shows a configuration in which four groups of two by two four sensor pixels 12 are arranged along a first direction V1 and a second direction V2. Fig.12 and Fig.13 In the cross-sectional view above, a diagram showing an example of the front surface configuration of the semiconductor substrate 11 is superimposed on a diagram showing Figure 7 The cross-sectional configuration example of the cross-sectional configuration ... Fig.12 and Fig.13 In the cross-sectional view below, a diagram showing an example of the front surface configuration of the semiconductor substrate 303 is superimposed on a diagram showing Figure 7 An example of the cross-sectional configuration of the cross-sectional view Sec2 is shown in the figure.

[0129] like Fig.12 and Fig.13 As shown, the plurality of through wirings 54, the plurality of through wirings 48, and the plurality of through wirings 47 are arranged in the first direction V1 ( Fig.12 The vertical direction and Fig.13 The horizontal direction in the middle) are arranged side by side in strips in the plane of the first substrate 10. Moreover, Fig.12 and Fig.13A case is shown where a plurality of through wirings 54, a plurality of through wirings 48, and a plurality of through wirings 47 are arranged side by side in two rows in a first direction V1. The first direction V1 is parallel to one of two arrangement directions (e.g., row direction and column direction) of a plurality of sensor pixels 12 arranged in a matrix (e.g., column direction). In one example, in four sensor pixels 12 of a common readout circuit 22, four floating diffusion regions FD are arranged close to each other across a pixel isolation portion 203. In four sensor pixels 12 of a common readout circuit 22, gates 223 of four transfer transistors TR are arranged to surround four floating diffusion regions FD. In one example, the four gates 223 form a ring.

[0130] The insulating layer 53 through which the contact portion Ct penetrates in the portion of the semiconductor substrate 303 described above includes a plurality of blocks extending in the first direction V1. The semiconductor substrate 303 extends in the first direction V1, and includes a plurality of island-shaped blocks 303A arranged side by side in a second direction V2 perpendicular to the first direction V1 via the insulating layer 53 described above. In one example, each block 303A is provided with a plurality of sets of reset transistors RST, amplifier transistors AMP, and selection transistors SEL. In one example, one readout circuit 22 shared by four sensor pixels 12 includes a reset transistor RST, an amplifier transistor AMP, and a selection transistor SEL in a region facing the four sensor pixels 12. In one example, one readout circuit 22 shared by four sensor pixels 12 includes an amplifier transistor AMP in the leftmost block 303A of the insulating layer 53, and includes a reset transistor RST and a selection transistor SEL in the rightmost block 303A of the insulating layer 53.

[0131] Fig.14 , Fig.15 , Fig.16 and Fig.17 An example of a wiring layout of the image pickup element 1 in a horizontal plane is shown. Figures 14 to 17 An example case is shown in which one readout circuit 22 shared by four sensor pixels 12 is provided in a region facing the four sensor pixels 12. In one example, Figures 14 to 17 The illustrated wiring is arranged in a wiring layer 246 of a different layer.

[0132] In one example, if Fig.14 As shown, the four contact portions Ct adjacent to each other are electrically connected to the wiring D1. The four contact portions Ct adjacent to each other are also electrically connected to the gate of the amplifier transistor AMP included in the leftmost block 303A of the insulating layer 53. The contact portion Ct is also electrically connected to the gate of the reset transistor RST included in the rightmost block 303A of the insulating layer 53. In one example, as Fig.14 As shown, this connection is made via the wiring D1 and the contact Ct2.

[0133] In one example, if Fig.15 As shown, the power supply line VDD is arranged at a position facing each readout circuit 22 arranged side by side in the second direction V2. Fig.15 As shown, the power line VDD is electrically connected to the drain of the amplifier transistor AMP and the drain of the reset transistor RST of each readout circuit 22 arranged side by side in the second direction V2 via the contact portion Ct2. Fig.15 As shown, two pixel drive lines 23 are arranged at positions facing the readout circuits 22 arranged side by side in the second direction V2. Fig.15 As shown, one of the pixel drive lines 23 is a wiring RSTG electrically connected to the gates of the reset transistors RST of the readout circuits 22 arranged side by side in the second direction V2. Fig.15 As shown, another pixel driving line 23 is a wiring SELG electrically connected to the gate of the selection transistor SEL of each readout circuit 22 arranged side by side in the second direction V2. Fig.15 As shown, in each readout circuit 22 , the source of the amplifier transistor AMP and the drain of the selection transistor SEL are electrically connected to each other via a wiring 25 .

[0134] In one example, if Fig.16 As shown, two power supply lines VSS are arranged at positions facing the readout circuits 22 arranged side by side in the second direction V2. Fig.16 As shown, each power supply line VS is electrically connected to a plurality of through wirings 47 at positions facing each sensor pixel 12 arranged side by side in the second direction V2. Fig.16 As shown, four pixel drive lines 23 are arranged at positions facing the readout circuits 22 arranged side by side in the second direction V2. Fig.16 As shown, each of the four pixel drive lines 23 is a wiring TRG that is electrically connected to a through wiring 48 corresponding to one of the four sensor pixels 12 of each readout circuit 22 arranged side by side in the second direction V2. In other words, the four pixel drive lines 23 (first control lines) are electrically connected to the gates 223 of the transfer transistors TR of each sensor pixel 12 arranged side by side in the second direction V2. Fig.16 In the example, an identification number (1, 2, 3 or 4) is attached to the end of each wiring TRG to distinguish between the wirings TRG.

[0135] In one example, if Fig.17 As shown, the vertical signal line 24 is arranged at a position facing each readout circuit 22 arranged side by side in the second direction V2. Fig.17 As shown, the vertical signal line 24 (output line) is electrically connected to the output terminals (sources of the amplifier transistors AMP) of the respective readout circuits 22 arranged side by side in the first direction V1.

[0136] A method for manufacturing the image pickup element 1 according to the present embodiment will now be described. First, a semiconductor region and a pixel isolation portion 203 are formed in the first substrate 10 as a silicon substrate, and a photodiode PD and a transfer transistor TR are provided for each pixel. Fig.18 As shown in FIG. 1 , an N-type drain region 221 and an N-type source region 222 are formed near the surface of a P-type semiconductor region (P-well) 204 separated by a pixel isolation portion 203. Then, a gate 223 is formed between them. More specifically, an opening is defined between the N-type drain region 221 and the N-type source region 222 of the P-type semiconductor region 204. The opening leads to the photodiode PD ( Fig.18 (not shown). Then, a gate 223 is formed to fill the opening. In this example, the gate 223 leads to a photodiode PD formed below the semiconductor region 204 (see FIG. Figure 7 ).and, Fig.18 The illustrated area 205 indicates an area for one pixel separated by the pixel isolation portion 203 .

[0137] Furthermore, an electrode 230 is formed on the P-type semiconductor region 204. The electrode 230 is used to guide the photodiode PD to a reference potential line provided with a reference potential (eg, a ground line). The electrode 230 is provided for each pixel and leads to the photodiode PD (not shown).

[0138] In this example, the transfer transistor TR is an N-channel MOS transistor, and its drain region 221 is an N-type semiconductor region. Therefore, the drain region 221 of the transfer transistor TR leads to the P-type semiconductor region 202 covering the side of the photodiode PD. Figure 2 As can be seen from the circuit diagram of FIG. 2 , the terminal (input side terminal) of the two terminals of the photodiode PD that is not connected to the transfer transistor TR leads to the reference potential line. Therefore, in this example, the photodiode PD is connected to the reference potential line via the electrode 230. Therefore, the electrode 230 connected to the photodiode PD formed in the N-type semiconductor region is formed as P-type polysilicon.

[0139] As described above, the N-type drain region 221, the N-type source region 222, the gate 223, and the electrode 230 are provided for each pixel in the P-type semiconductor region 204, and then covered with the insulating layer 240. The insulating layer 240 is configured as an oxide film such as SiO2.

[0140] Then, if Fig.19As shown, the insulating layer 240 is etched to form a wiring groove 241 and a wiring groove 242. The wiring groove 241 is used to form a wiring 301a that gathers the source regions 222 of the plurality of transfer transistors TR. The wiring groove 242 is used to form a wiring 301b that gathers the plurality of electrodes 230. When there is no need to distinguish, the wiring 301a and the wiring 301b are generally referred to as "wiring 301" here.

[0141] As described above, in this example, since the source region 222 of the transfer transistor TR is an N-type semiconductor region, the wiring 301a connected to the source region 222 is formed of P-type polysilicon. In addition, since the electrode 230 is P-type polysilicon, the wiring 301b connected to the electrode 230 is formed of N-type polysilicon.

[0142] In other words, in the case where the transfer transistor TR is an N-type transistor, the wiring 301a on the output end side of the plurality of transfer transistors TR is formed as P-type polysilicon. In addition, as described above, in this case, the electrode 230 connected to the photodiode PD formed in the N-type semiconductor region is formed as P-type polysilicon. Therefore, the wiring 301b on which the plurality of electrodes 230 are gathered is formed as N-type polysilicon.

[0143] Subsequently, P-type polysilicon as a material of the wiring 301a is deposited to fill Fig.19 The wiring groove 241 is formed in the wiring 301a. N-type polysilicon as the material of the wiring 301b is deposited to fill the wiring groove 242. Then, the resulting deposit is polished by chemical mechanical polishing (CMP) to form the wiring 301a and the wiring 301b (see FIG. Fig. 20 ).

[0144] In this example, for each of the four photodiodes PD (for each group of four photodiodes PD), the wiring 301a is connected to the source region 222 of the four transfer transistors TR corresponding to the four photodiodes PD one by one. In other words, the wiring 301a gathers the source regions 222 of the four transfer transistors TR corresponding to the four photodiodes PD one by one for each of the four photodiodes PD. Then, the wiring 301a is connected to the wiring D1 via one contact portion Ct to connect the gathered source regions 222 to the wiring D1 of the second substrate 20 leading to the gate 311 of the amplifier transistor AMP shared by the source regions 222. In this example, one contact portion Ct is provided for every four source regions 222. In addition, in this example, the source region 222 of the transfer transistor TR corresponds to the "first element", and the gate 311 of the amplifier transistor AMP corresponds to the "second element". The wiring D1 corresponds to the "first wiring" or the "second wiring formed on the second substrate", and the wiring 301a corresponds to the "second wiring" or the "first wiring formed on the first substrate and connected to the first photoelectric converter and the second photoelectric converter". Furthermore, the number of pixels as a constituent unit aggregated by the wiring 301a is not limited to four and is optional.

[0145] Moreover, in this example, for each of the four photodiodes PD, the wiring 301b is connected to four electrodes 230 corresponding to the four photodiodes PD one by one. In other words, for each of the four photodiodes PD, the wiring 301b gathers the four electrodes 230 corresponding to the four photodiodes PD one by one. And, the wiring 301b is connected to the wiring D1 via one contact portion Ct to connect the gathered electrodes 230 to the wiring D1 of the second substrate 20 leading to the reference potential line common to the electrodes 230. In this example, one contact portion Ct is provided for every four electrodes 230. Moreover, the wiring D1 leading to the reference potential line is different from the wiring D1 leading to the gate 311 of the amplifier transistor AMP as described above (however, both are wirings formed on the insulating layer 245 of the second substrate 20). In addition, in this example, the electrode 230 corresponds to the "first element", and the reference potential line corresponds to the "second element". The wiring D1 corresponds to the "first wiring", and the wiring 301b corresponds to the "second wiring". Moreover, the number of pixels as a constituent unit gathered by the wiring 301b is not limited to four, and can be arbitrarily selected. In addition, as described above, the wiring 301b is connected (indirectly connected) to each corresponding photodiode PD via each electrode 230. In other words, it can be considered that the wiring 301b also corresponds to "a first wiring formed on the first substrate and connected to the first photoelectric converter and the second photoelectric converter". In addition, it can be considered that the wiring D1 also corresponds to "a second wiring formed on the second substrate".

[0146] Furthermore, in this example, the reference potential line is set to be formed on the second substrate 20, but its configuration is not limited to the above example, and in one example, the reference potential line may be formed on another substrate (e.g., the third substrate 30). In short, the "second element" is not limited to an element formed on the second substrate 20.

[0147] Then, if Fig.21 As shown, an insulating layer 240 is deposited on the wiring 301a and the wiring 301b. Also, a P-type semiconductor substrate 303 is connected to the top of the insulating layer 240 and thinned.

[0148] Then, if Fig. 22 As shown, a portion of the semiconductor substrate 303 facing the wiring 301 is opened to form a pixel transistor on the semiconductor substrate 303. Fig. 22 In the example of FIG. 3 , an amplifier transistor AMP and a selection transistor SEL are shown, and a reset transistor RST (not shown) is also formed on the semiconductor substrate 303. Fig. 22 As shown, an N-type drain region 312 and an N-type source region 313 are formed near the surface of a semiconductor substrate 303. Then, a gate 311 is formed therebetween to form an amplifier transistor AMP.

[0149] Similar to the above description, an N-type drain region 321 and an N-type source region 322 are formed near the surface of the semiconductor substrate 303, and a gate 323 is formed therebetween to form a selection transistor SEL. Moreover, a reset transistor RST (not shown) is also formed in a similar manner. Then, an insulating layer 245 is formed (deposited) so that it covers the opening and pixel transistors (e.g., the amplifier transistor AMP and the selection transistor SEL) formed as described above.

[0150] Then, if Fig.23 As shown, contacts Ct and Ct2 are formed to connect the wiring 301 and each element of the second substrate 20 to the wiring D1. In this example, the contact Ct is provided for each of the drain region 312 of the amplifier transistor AMP, the wiring 301, and the source region 322 of the selection transistor SEL. The contact Ct2 is provided for the gate 311 of the amplifier transistor AMP.

[0151] As a method of forming the contacts Ct and Ct2, in one example, consider the following manner: etching the insulating layer to form an opening defining the contacts Ct and Ct2, forming a barrier layer for electrical isolation on the inner surface of the opening, and then filling it with the material of the contacts Ct and Ct2. In this example, the insulating layer (the insulating layer covering the side of the contact Ct) provided at the opening of the semiconductor substrate 303 is the above-mentioned insulating layer 53. Examples of materials for the contacts Ct and Ct2 include tungsten, etc. In one example, the barrier layer includes Ti, TiN, Ta, TaN, etc. as materials. However, the method of forming the contacts Ct and Ct2 and the materials thereof are not limited to the above-mentioned examples, are optional, and various known techniques can be used.

[0152] Next, if Fig.24 As shown, a wiring D1 connected to the contact portions Ct and Ct2 is formed on the insulating layer 245. In this example, the wiring D1 includes copper (Cu) as its material. Also, the method and material for forming the wiring D1 are optional, and various known techniques may be employed.

[0153] Next, if Fig.25 As shown, the above-mentioned wiring layer 246 is formed on the insulating layer 245. Then, the third substrate 30 on which the peripheral circuit is formed is combined to form a color filter and an on-chip lens for each pixel. Then, it is possible to obtain Figure 7 Configuration shown.

[0154] The operation and effect of the image pickup element 1 according to the present embodiment will now be described. In this description, in one example, it is assumed that the wiring 301 (wiring 301a or wiring 301b) described above is not formed. In this configuration, as shown in FIG. Fig.26 As shown, the source region 222 (output terminal side) of the transfer transistor TR is connected to the wiring D1 leading to the gate 311 of the amplifier transistor AMP through the contact portion Ct. Considering one common constituent unit, it is necessary to connect four contact portions Ct corresponding to the source regions 222 of the four transfer transistors TR to the wiring D1 of the second substrate 20 leading to the gate 311 of the amplifier transistor AMP. This increases the number of contacts of the wiring D1, and the area will also increase. In addition, the opening area of ​​the semiconductor substrate 303 for passing the contact portion Ct will also become larger.

[0155] In addition, in the above configuration ( Fig.26 In the configuration shown in FIG. 1 , the electrodes 230 are also connected to the wiring D1 leading to the reference potential line via the contact portions Ct. Considering one common constituent unit, it is necessary to connect four contact portions Ct corresponding to the four electrodes 230 to the wiring D1 of the second substrate 20 leading to the reference potential line. This increases the number of contact portions of the wiring D1, and the area will also increase. In addition, the opening area of ​​the semiconductor substrate 303 for passing the contact portions Ct will also become larger.

[0156] Therefore, in the above-described configuration, the capacitance (parasitic capacitance) associated with the wiring D1 formed on the second substrate 20 is large, affecting the conversion efficiency of the photoelectric conversion. In one example, the conversion efficiency of the photoelectric conversion may be reduced.

[0157] Therefore, the present embodiment is provided with a wiring 301 leading to a second element (gate 311 of the amplifier transistor AMP or a reference potential line) common to a plurality of first elements such as the output terminal side of the transfer transistor TR and the electrode 230. The wiring 301 is connected to the wiring D1 formed on the second substrate 20 and to the plurality of first elements via one contact portion Ct.

[0158] In other words, the wiring 301 gathers a plurality of first elements and is connected to the wiring D1 leading to the second element shared by the plurality of first elements via one contact portion Ct. Therefore, only one contact portion Ct is formed in the wiring D1 for connecting the plurality of first elements constituting the gathered unit to the wiring D1, so the number and area of ​​the contact portions of the wiring D1 can be reduced. Therefore, the capacitance associated with the wiring D1 can be reduced, and the conversion efficiency of the photoelectric conversion can be improved.

[0159] More specifically, if Fig. 27 As shown in FIG. 1 , the image pickup element 1 according to the present embodiment is provided with a wiring 301a, and the wiring 301a is used to connect the source region 222 (output end side) of each transfer transistor TR to the wiring D1 formed on the second substrate 20 via a contact portion Ct. The wiring D1 leads to the gate 311 of the amplifier transistor AMP shared by the source region 222 of each transfer transistor TR. In addition, the image pickup element 1 according to the present embodiment is further provided with a wiring 301b, and the wiring 301b is used to connect each electrode 230 to the wiring D1 formed on the second substrate 20 via a contact portion Ct. The wiring D1 is a wiring leading to a reference potential line commonly connected to each electrode 230.

[0160] Fig.28 2 is a schematic plan view of the first substrate 10 according to the present embodiment. Each of the plurality of regions 250 separated by the pixel isolation portion 203 corresponds to a pixel. Fig.28 As shown, region 260 represents a group of connection points 261 between the source region 222 and the wiring 301a for each of the four transfer transistors TR corresponding to the four photodiodes PD as a constituent unit of the shared pixel transistor. Fig.28 As shown, the region 270 represents a group of connection points 271 between the electrode 230 and the wiring 301 b for each of the four electrodes 230 corresponding one-to-one to the four photodiodes PD as a constituent unit of the common reference potential line.

[0161] Fig.29 2 is a schematic plan view of the second substrate 20 according to the present embodiment. As described above, for each of the four photodiodes PD, a pixel transistor common to the four photodiodes PD is formed on the second substrate 20. Fig.29 As shown, region 280 indicates a region where a common gate of pixel transistors constituting a unit circuit is formed. More specifically, region 280 indicates a region where gate 311 of amplifier transistor AMP, gate 323 of selection transistor SEL, and gate 333 of reset transistor RST are formed.

[0162] Fig.30 2 is a schematic plan view of the second substrate 20 and the first substrate 10 stacked on each other in this embodiment. Fig.30 In the example of , for each group of four photodiodes PD (the number of groups is optional), the wiring 301a is connected to the source regions 222 of the four transfer transistors TR corresponding to the four photodiodes PD included in one group. And, the wiring 301a is connected to the wiring D1 (not shown) leading to the gate 311 of the amplifier transistor AMP shared by the four source regions 222 via one contact portion Ct. In other words, for each of the four photodiodes PD, the wiring 301a gathers the source regions 222 of the four transfer transistors TR corresponding to the four photodiodes PD. And, the wiring D1 connected to the gate of the amplifier transistor AMP shared by the source region 222 is realized via one contact portion Ct.

[0163] Therefore, even one contact portion formed in the wiring D1 is sufficient to connect the source region 222 to the wiring D1. Specifically, the contact portion is used to connect the source regions 222 of the four transfer transistors TR that are gathered and correspond one to one to the four photodiodes PD as the constituent unit to the wiring D1. This makes it possible to reduce the number of contacts and the area of ​​the wiring D1. Therefore, it is possible to reduce the capacitance associated with the wiring D1 and improve the conversion efficiency of the photoelectric conversion.

[0164] In addition, Fig.30 In the example of FIG. 1 , for each group of four photodiodes PD, the wiring 301 b is connected to four electrodes 230 corresponding to the four photodiodes PD included in one group. Furthermore, the wiring 301 b is connected to a wiring D1 (not shown) leading to a reference potential line common to the four electrodes 230 via one contact portion Ct. In other words, for each of the four photodiodes PD, the wiring 301 b gathers four electrodes 230 corresponding to the four photodiodes PD one by one, and is connected to a wiring D1 leading to a reference potential line common to the electrodes 230 via one contact portion Ct.

[0165] Therefore, even one contact portion formed in the wiring D1 is sufficient to connect the electrode 230 to the wiring D1. Specifically, the contact portion is used to connect the four electrodes 230 that are gathered and correspond to the four photodiodes PD as the constituent units to the wiring D1. This makes it possible to reduce the number of contacts and the area of ​​the wiring D1. Therefore, it is possible to reduce the capacitance associated with the wiring D1 and improve the conversion efficiency of the photoelectric conversion. Moreover, as described above, the wiring 301 (wiring 301a or wiring 301b) gathers a plurality of first elements and is connected to the wiring D1 leading to the second element shared by the plurality of first elements via a contact portion Ct. However, the number of the contact portions Ct is not limited to the above example and can be more than two. In short, the wiring 301 only needs to have a form in which it is connected to the wiring D1 via a contact portion Ct that is less than the number of the gathered constituent units. This form makes it possible to reduce the number of contacts and the area of ​​the wiring D1.

[0166] Moreover, in this example, the four pixels as a constituent unit gathered by the wiring 301a and the four pixels as a constituent unit gathered by the wiring 301b do not completely match. Some of them (two pixels in this example) overlap, but this configuration is not limited to the above example.

[0167] In addition, in the present embodiment, since the first substrate 10 on which the photodiode PD is formed and the second substrate 20 on which the pixel transistor is formed are stacked on each other, the area (plane space) of the substrate can be reduced. More specifically, compared to a configuration in which the photodiode PD and the pixel transistor are provided on the same substrate, the first substrate 10 and the second substrate 20 separated from each other make it possible to increase the area of ​​the photodiode PD and the pixel transistor. This makes it possible to improve the photoelectric conversion efficiency and reduce the transistor noise.

[0168] Furthermore, compared to a configuration in which the photodiode PD and the pixel transistor are provided on the same substrate, the first substrate 10 and the second substrate 20 separated from each other make it possible to increase the number of pixels per unit area and improve the resolution.

[0169] Moreover, as described above, in the present embodiment, for the inter-substrate connection, the first substrate 10 and the second substrate 20 are connected using the through electrodes (contact portion Ct and through wiring 47 or 48) in the pixel area 13. The second substrate 20 and the third substrate 30 are connected using pad electrodes 58 and 64. Compared to the configuration in which the through holes (through silicon vias, TSV) are provided in the peripheral area of ​​the peripheral edge of the pixel area 13 to connect the substrates to each other, this reduces the area required for the inter-substrate connection, thereby reducing the chip size. Alternatively, even with the same chip area, the pixel area 13 can be increased. Moreover, it will be more effective if the inter-substrate connection can be achieved in all pixel areas.

[0170] Furthermore, in the present embodiment, the wiring 301 (wiring 301a or wiring 301b) is provided on the light incident surface side of the second substrate 20 (in this example, the lower layer of the second substrate 20) (for example, see Fig.17 ). This configuration allows the opening facing the wiring 301 formed in the region of the semiconductor substrate 303 of the second substrate 20 to have a size sufficient to allow one contact portion Ct to pass through. Therefore, according to this embodiment, the size of the opening formed in the semiconductor substrate 303 can be reduced.

[0171] Moreover, in the present embodiment described above, the output terminal side or electrode 230 of the transfer transistor TR is given as an example of the "first element", and the gate 311 or reference potential line of the amplifier transistor AMP is given as an example of the "second element". However, the configuration according to the embodiment of the present disclosure is not limited to the above example. In short, it is only necessary that the first element is an element provided for each photodiode PD among the multiple elements formed on the first substrate 10. It is only necessary that the second element is an element common to multiple first elements among the elements formed on the second substrate 20.

[0172] In addition, in this embodiment, the wiring 301a and the wiring 301b are alternately arranged in the vertical direction (see Fig.30 ), but the arrangement of the wiring is not limited to this example, and the layout of the wiring 301 can be changed at will according to design conditions, etc. In one example, Fig.31 As shown, the wiring 301a and the wiring 301b may be alternately arranged in the horizontal direction. Fig.32 1 shows a schematic plan view of the first substrate 10 in the case of the above example, Fig.33 FIG. 2 shows a schematic plan view of the second substrate 20 in the case of the above example. Fig.32 and Fig.33 In the embodiment, the common elements with those in the above-described embodiment are denoted by the same reference numerals.

[0173] <3. Second embodiment>

[0174] (Arrangement example of imaging element)

[0175] An example of the configuration of the imaging element according to the second embodiment is now described. Moreover, since the basic configuration of the imaging element according to this embodiment is the same as the basic configuration of the imaging element 1 according to the first embodiment described above, only the difference from the first embodiment described above is described. The configuration other than the difference is similar to the configuration of the first embodiment described above.

[0176] In the first embodiment described above, the transfer transistor TR is configured as an N-channel MOS transistor, but in the present embodiment, the transfer transistor TR is configured as a P-channel MOS transistor (an example of a P-type transistor). Therefore, the semiconductor region 204 formed on the photodiode PD is an N-type semiconductor region. The drain region 221 and the source region 222 of the transfer transistor TR formed near the front surface of the semiconductor region 204 are P-type semiconductor regions. Therefore, the wiring 301a that gathers the source region 222 of the transfer transistor TR is formed as N-type polysilicon.

[0177] In other words, in the case where the transfer transistor TR is a P-type transistor, the wiring 301 a for connecting the output end sides of the plurality of transfer transistors TR to the wiring D1 via one contact portion is configured as N-type polysilicon.

[0178] In addition, since the N-type drain region 221 of the transfer transistor TR leads to the P-type semiconductor region covering the side of the photodiode PD, the photodiode PD is connected to the electrode 230. Therefore, in this example, the electrode 230 is formed of N-type polysilicon, and the wiring 301b collecting the electrode 230 is formed of P-type polysilicon.

[0179] In other words, in this embodiment, the electrode 230 connected to the photodiode PD is formed of N-type polysilicon. The wiring 301b for connecting the plurality of electrodes 230 to the wiring D1 via one contact portion is formed of P-type polysilicon.

[0180] The configuration of the present embodiment described above also achieves an effect similar to that of the first embodiment described above. In other words, only one contact portion Ct is sufficient to be formed in the wiring D1, and the contact portion Ct is used to connect a plurality of first elements (a plurality of first elements as a constituent unit aggregated) such as the output terminal side of the transfer transistor TR formed on the first substrate 10 and the electrode 230 to the wiring D1. Therefore, the number and area of ​​the contact portions of the wiring D1 can be reduced, so that the capacitance associated with the wiring D1 can be reduced. This makes it possible to improve the photoelectric conversion efficiency.

[0181] <4. Third embodiment>

[0182] (Arrangement example of imaging element)

[0183] An example of the configuration of the imaging element according to the third embodiment is now described. Moreover, since the basic configuration of the imaging element according to this embodiment is the same as the basic configuration of the imaging element 1 according to the first embodiment described above, only the difference from the first embodiment described above is described. The configuration other than the difference is similar to the configuration of the first embodiment described above.

[0184] In the first embodiment described above, the wiring (wiring 301a or wiring 301b) is formed of polysilicon, but its configuration is not limited to the above example, and in one example, the wiring 301 including tungsten (W) may be formed. This makes it possible to reduce the resistance of the wiring 301 compared to the case where the wiring 301 is formed of polysilicon.

[0185] In addition, this configuration also achieves an effect similar to that of the first embodiment described above. In other words, only one contact portion Ct is sufficient to be formed in the wiring D1, and the contact portion Ct is used to connect a plurality of first elements (a plurality of first elements as a constituent unit aggregated) such as the output terminal side of the transfer transistor TR formed on the first substrate 10 and the electrode 230 to the wiring D1. Therefore, the number and area of ​​the contact portions of the wiring D1 can be reduced, so that the capacitance associated with the wiring D1 can be reduced. This makes it possible to improve the photoelectric conversion efficiency.

[0186] <5. Fourth embodiment>

[0187] (Arrangement example of imaging element)

[0188] An example of the configuration of the image pickup element according to the fourth embodiment is now described. Moreover, since the basic configuration of the image pickup element according to this embodiment is the same as the basic configuration of the image pickup element 1 according to the first embodiment described above, only the difference from the first embodiment described above is described. The configuration other than the difference is similar to the configuration of the first embodiment described above.

[0189] In this embodiment, if Fig.34 As shown, the wiring 301a and the wiring 301b are arranged in the respective corresponding openings formed in the second substrate 20 (semiconductor substrate 303). In this description, the "opening formed in the second substrate 20" corresponds to the inside of the region of the insulating film 230 (in the insulating region). The insulating film 230 is formed between the first semiconductor region of the second substrate 20 (for example, the region in which the amplifier transistor AMP is formed) and the second semiconductor region of the second substrate 20 (for example, the region in which the selection transistor SEL is formed). This achieves the beneficial effect of reducing the height in the stacking direction.

[0190] In addition, this configuration also achieves an effect similar to that of the first embodiment described above. In other words, only one contact portion Ct is sufficient to be formed in the wiring D1, and the contact portion Ct is used to connect a plurality of first elements (a plurality of first elements as a constituent unit aggregated) such as the output terminal side of the transfer transistor TR formed on the first substrate 10 and the electrode 230 to the wiring D1. Therefore, the number and area of ​​the contact portions of the wiring D1 can be reduced, so that the capacitance associated with the wiring D1 can be reduced. This makes it possible to improve the photoelectric conversion efficiency.

[0191] Moreover, this embodiment is applicable to the above-mentioned second embodiment. In one example, the wiring 301a can be arranged in the opening formed in the second substrate 20, the transfer transistor TR can be a P-type transistor, and the wiring 301a can be formed as N-type polysilicon. In addition, in one example, the wiring 301b can be arranged in the opening formed in the second substrate 20, the electrode 230 connected to the photodiode PD can be formed as N-type polysilicon, and the wiring 301b can be formed as P-type polysilicon.

[0192] In addition, this embodiment is also applicable to the above-described third embodiment. In one example, the wiring 301 (the wiring 301 a or the wiring 301 b ) may be arranged in an opening formed in the second substrate 20 , and the wiring 301 may include tungsten (W).

[0193] <6. Fifth embodiment>

[0194] (Arrangement example of imaging element)

[0195] An example of the configuration of the imaging element according to the fifth embodiment will now be described. Moreover, since the basic configuration of the imaging element according to this embodiment is the same as the basic configuration of the imaging element 1 according to the first embodiment described above, only the difference from the first embodiment described above will be described. The configuration other than the difference is similar to the configuration of the first embodiment described above.

[0196] In this embodiment, the wiring 301 (wiring 301a or wiring 301b) is arranged between the second element (gate 311 of the amplifier transistor AMP or the reference potential line) and the wiring D1. Fig.35 As shown, the wiring 301 a is arranged between the gate 311 of the amplifier transistor AMP formed on the second substrate 20 and the wiring D1 .

[0197] This configuration also achieves an effect similar to that of the first embodiment described above. In other words, only one contact portion Ct is sufficient to be formed in the wiring D1, and the contact portion Ct is used to connect a plurality of first elements (a plurality of first elements as a constituent unit aggregated) such as the output terminal side of the transfer transistor TR formed on the first substrate 10 and the electrode 230 to the wiring D1. Therefore, the number and area of ​​the contact portions of the wiring D1 can be reduced, so that the capacitance associated with the wiring D1 can be reduced. This makes it possible to improve the photoelectric conversion efficiency.

[0198] Moreover, this embodiment is applicable to the above-mentioned second embodiment. In one example, the wiring 301a can be arranged in the opening formed in the second substrate 20, and can be arranged between the gate 311 of the amplifier transistor AMP and the wiring D1, the transfer transistor TR can be a P-type transistor, and the wiring 301a can be formed as N-type polysilicon. In addition, in one example, the wiring 301 can be arranged between the reference potential line and the wiring D1, the electrode 230 connected to the photodiode PD can be formed as N-type polysilicon, and the wiring 301b can be formed as P-type polysilicon.

[0199] In addition, this embodiment is also applicable to the third embodiment described above. In one example, the wiring 301a can be arranged between the gate 311 of the amplifier transistor AMP and the wiring D1, and the wiring 301a can include tungsten (W). In addition, in one example, the wiring 301b can be arranged between the reference potential line and the wiring D1, and the wiring 301b can include tungsten (W).

[0200] <7. Sixth embodiment>

[0201] (Arrangement example of imaging element)

[0202] An example of the configuration of the imaging element according to the sixth embodiment is now described. Moreover, since the basic configuration of the imaging element according to this embodiment is the same as the basic configuration of the imaging element 1 according to the first embodiment described above, only the difference from the first embodiment described above is described. The configuration other than the difference is similar to the configuration of the first embodiment described above.

[0203] In this embodiment, if Fig.36 In this example, the wiring 301b described above is not provided, and the electrode 230 is connected to the wiring D1 via the respective contact portions.

[0204] This configuration makes it sufficient to set the number of contacts Ct formed in the wiring D1 to one. Specifically, the contact Ct is used to commonly connect the output end sides of the plurality of transfer transistors TR formed on the first substrate 10 to the wiring D1 (the wiring D1 leading to the gate 311 of the amplifier transistor AMP). Therefore, the number and area of ​​the contacts of the wiring D1 leading to the gate 311 of the amplifier transistor AMP can be reduced.

[0205] In addition, in one example, Fig.37 In this example, the above-mentioned wiring 301a is not provided, and the output terminal side of the transfer transistor TR (the source region 222 in this example) is connected to the wiring D1 via respective contacts.

[0206] This configuration also makes it sufficient to set the number of contacts Ct formed in the wiring D1 to one. Specifically, the contact Ct is used to commonly connect the plurality of electrodes 230 formed on the first substrate 10 to the wiring D1 (the wiring D1 leading to the reference potential line). Therefore, the number and area of ​​the contacts of the wiring D1 leading to the reference potential line can be reduced.

[0207] In short, a configuration in which the wiring 301a is provided but the wiring 301b is not provided is feasible. Conversely, a configuration in which the wiring 301b is provided but the wiring 301a is not provided is feasible.

[0208] Moreover, this embodiment is also applicable to the above-mentioned second embodiment. The transfer transistor TR can be a P-type transistor, and the wiring 301a can be formed as N-type polysilicon. In addition, the electrode 230 connected to the photodiode PD can be formed as N-type polysilicon, and the wiring 301b can be formed as P-type polysilicon.

[0209] In addition, this embodiment is also applicable to the above-mentioned third embodiment, and the wiring 301 (the wiring 301a or the wiring 301b) may include tungsten (W).

[0210] In addition, this embodiment is also applicable to the fourth embodiment described above. In one example, in a configuration where the wiring 301a is provided but the wiring 301b is not provided, the wiring 301a can be arranged in an opening in the second substrate 20. In addition, in one example, in a configuration where the wiring 301b is provided but the wiring 301a is not provided, the wiring 301b can be arranged in an opening formed in the second substrate 20.

[0211] Moreover, this embodiment is also applicable to the fifth embodiment described above. In one example, in a configuration in which the wiring 301a is provided but the wiring 301b is not provided, the wiring 301a can be arranged between the gate 311 of the amplifier transistor AMP and the wiring D1. In addition, in one example, in a configuration in which the wiring 301b is provided but the wiring 301a is not provided, the wiring 301b can be arranged between the reference potential line and the wiring D1.

[0212] In short, this embodiment is applicable to each of the second to fifth embodiments described above.

[0213] <8. Seventh embodiment>

[0214] (Configuration example of electronic device)

[0215] In one example, the imaging element described in each of the above embodiments is applicable to electronic devices including various mobile terminal devices such as a digital camera, a digital video camera, and a mobile phone equipped with a camera, or a printer. Fig.381 is a diagram showing a configuration example of a camera 1000, which is an example of an electronic device to which the imaging element of the present disclosure is applied. The camera 1000 is an example of a video camera capable of capturing still images or moving images.

[0216] like Fig.38 As shown, the camera 1000 includes at least a lens group 1011 , an imaging element 1012 , and a DSP circuit 1013 .

[0217] The lens group 1011 takes incident light (image light) from a subject and guides it to the image pickup element 1012. In this example, the lens group 1011 corresponds to an example of an "optical system" for guiding incident light to the image pickup element.

[0218] The imaging element 1012 converts incident light into an electrical signal and supplies it as a pixel signal to the DSP circuit 1013. The conversion is performed in pixel units. As the imaging element 1012, any of the imaging elements of the above-described embodiments can be used.

[0219] The DSP circuit 1013 performs predetermined image processing on the pixel signal provided by the imaging element 1012. The DSP circuit 1013 outputs a group of pixel signals (a group of pixel signals for one frame) processed in pixel units as a video signal. In this example, the DSP circuit 1013 corresponds to an example of a "processing unit" that processes a signal output by the imaging element.

[0220] The video signal output by the DSP circuit 1013 is temporarily stored in a frame memory or the like, and then recorded in a recording medium such as a digital versatile disk (DVD) or a flash memory, or displayed on a display device such as a liquid crystal panel or an organic electroluminescent (EL) panel.

[0221] <9. Modifications>

[0222] Modifications of the image pickup element 1 will now be described.

[0223] [Variation A]

[0224] In the above embodiments, the number of pixels in the shared constituent unit is four, but the number of pixels in the shared constituent unit is not limited to the above examples, and the number of pixels in the shared constituent unit can be selectively changed. Fig.39 and Fig.40 As shown, the number of pixels in the shared constituent unit may be two. In other words, the second substrate 20 may have one readout circuit 22 for each of the two sensor pixels 12 . Fig.39 Shows Figure 2 A variation of the sensor pixel 12 and readout circuit 22 is shown. Fig.40 Shows Figure 3A variation of the sensor pixel 12 and readout circuit 22 is shown.

[0225] In addition, in one example, Fig.41 and Fig.42 As shown, the number of pixels in the shared constituent unit may be one. In other words, the second substrate 20 may have one readout circuit 22 for each of the two sensor pixels 12 . Fig.41 Shows Figure 2 A variation of the sensor pixel 12 and readout circuit 22 is shown. Fig.42 Shows Figure 3 A variation of the sensor pixel 12 and readout circuit 22 is shown.

[0226] [Variation Example B]

[0227] Fig.43 A modification of the cross-sectional configuration of the image pickup element 1 in the vertical direction is shown. In this modification, the electrical connection between the second substrate 20 and the third substrate 30 is performed in the area facing the peripheral area 14 of the first substrate 10. The peripheral area 14 corresponds to the frame area of ​​the first substrate 10 and is provided at the peripheral edge of the pixel area 13. In this modification, the second substrate 20 has a plurality of pad electrodes 58 in the area facing the peripheral area 14, and the third substrate 30 has a plurality of pad electrodes 64 in the area facing the peripheral area 14. The second substrate 20 and the third substrate 30 are electrically connected to each other by connecting the pad electrodes 58 and 64 provided in the area facing the peripheral area 14.

[0228] As described above, in the present modification, the second substrate 20 and the third substrate 30 are electrically connected to each other by connecting the pad electrodes 58 and 64 provided in the region facing the peripheral region 14. This makes it possible to reduce the possibility of hindering the miniaturization of the area per pixel, compared to the case where the pad electrodes 58 and 64 are connected to each other in the region facing the pixel region 13. Therefore, it is possible to provide the image pickup element 1 having a three-layer structure that does not hinder the miniaturization of the area per pixel while having the same chip size as the related art.

[0229] [Variant C]

[0230] Fig.44 and Fig.45 1 is a diagram showing a modified example of the cross-sectional configuration in the horizontal direction of the image sensor 1 . Fig.44 and Fig.45 The figure above shows Figure 7 A modification of the cross-sectional configuration of the cross-sectional area Sec1 is shown in FIG. Fig.23 The following figure shows Figure 7 A modified example of the cross-sectional configuration of the cross-sectional area Sec2. Fig.44 and Fig.45In the upper cross-sectional view, it is shown Figure 7 A diagram showing a modified example of the front surface configuration of the semiconductor substrate 11 is superimposed on Figure 7 The cross-sectional configuration of the cross-sectional view Sec1 is shown in the figure of the modified example, but the insulating layer 240 is omitted. Fig.44 and Fig.45 In the lower cross-sectional view of FIG. 1 , a diagram showing a modified example of the front surface configuration of the semiconductor substrate 303 is superimposed on a diagram showing Figure 7 The figure shows a modified example of the cross-sectional configuration of the cross-sectional area Sec2.

[0231] like Fig.44 and Fig.45 As shown, a plurality of contact portions Ct, a plurality of through wirings 47, and a plurality of through wirings 48 (a plurality of points arranged in a matrix form in the figure) are arranged along a first direction V1 ( Fig.44 and Fig.45 In the horizontal direction of the first substrate 10, the first substrate 10 is arranged side by side in a strip shape. Fig.44 and Fig.45 The case is shown in which a plurality of contacts Ct, a plurality of through wirings 47, and a plurality of through wirings 48 are arranged side by side in two rows along the first direction V1. In one example, in four sensor pixels 12 of the common readout circuit 22, four floating diffusion regions FD are arranged close to each other via the pixel isolation portion 203. In the four sensor pixels 12 of the common readout circuit 22, four transfer gates TG (TG1, TG2, TG3, and TG4) are arranged to surround the four floating diffusion regions FD. In one example, the four transfer gates TG form a ring.

[0232] The insulating layer 53 includes a plurality of blocks extending in the first direction V1. The semiconductor substrate 303 extends in the first direction V1 and includes a plurality of island-shaped blocks 303A arranged side by side in a second direction V2 perpendicular to the first direction V1 via the insulating layer 53. In one example, each block 303A is provided with a reset transistor RST, an amplifier transistor AMP, and a selection transistor SEL. One readout circuit 22 shared by four sensor pixels 12 is not arranged directly opposite to the four sensor pixels 12, but in one example, is arranged offset from the second direction V2.

[0233] exist Fig.44 In the second substrate 20, one readout circuit 22 shared by four sensor pixels 12 includes a reset transistor RST, an amplifier transistor AMP, and a selection transistor SEL in a region deviated from a region facing the four sensor pixels 12 in the second direction V2. In one example, one readout circuit 22 shared by four sensor pixels 12 includes the amplifier transistor AMP, the reset transistor RST, and the selection transistor SEL in one block 303A.

[0234] exist Fig.45 In the second substrate 20, one readout circuit 22 shared by four sensor pixels 12 includes a reset transistor RST, an amplifier transistor AMP, a selection transistor SEL, and an FD transfer transistor FDG in an area deviated from an area facing the four sensor pixels 12 in the second direction V2. In one example, one readout circuit 22 shared by four sensor pixels 12 includes the amplifier transistor AMP, the reset transistor RST, the selection transistor SEL, and the FD transfer transistor FDG in one block 303A.

[0235] In this modification, one readout circuit 22 shared by four sensor pixels 12 is not arranged directly opposite to the four sensor pixels 12, and in one example, is arranged offset from the position directly opposite to the four sensor pixels 12 in the second direction V2. In this case, the wiring 25 can be shortened, or the wiring 25 can be omitted and the source of the amplifier transistor AMP and the drain of the selection transistor SEL can be arranged in a common impurity region. Therefore, the size of the readout circuit 22 can be reduced or the size of other parts of the readout circuit 22 can be increased.

[0236] [Variant D]

[0237] Fig.46 A modified example of the cross-sectional arrangement of the image sensor 1 in the horizontal direction is shown. Fig.46 Shows Fig.12 A variation of the cross-sectional configuration.

[0238] In this modification, the semiconductor substrate 303 includes a plurality of island-shaped blocks 303A arranged side by side in the first direction V1 and the second direction V2 via an insulating layer 53. In one example, each block 303A is provided with a set of a reset transistor RST, an amplifier transistor AMP, and a selection transistor SEL. In this case, the use of the insulating layer 53 makes it possible to reduce or eliminate crosstalk between the readout circuits 22 adjacent to each other. It is also possible to reduce or eliminate the degradation of the resolution of the reproduced image and the degradation of the image quality due to color mixing.

[0239] [Variant E]

[0240] Fig.47 A modified example of the cross-sectional arrangement of the image sensor 1 in the horizontal direction is shown. Fig.47 Shows Fig.46 A variation of the cross-sectional configuration.

[0241] In this modification, one readout circuit 22 shared by four sensor pixels 12 is not arranged directly opposite to the four sensor pixels 12, and in one example, is arranged offset from the first direction V1. Moreover, in this modification, similar to modification D, the semiconductor substrate 303 includes a plurality of island-shaped blocks 303A arranged side by side in the first direction V1 and the second direction V2 via the insulating layer 53. In one example, each block 303A is provided with a set of reset transistors RST, amplifier transistors AMP, and selection transistors SEL. In addition, in this modification, a plurality of through wirings 47 and a plurality of contact portions Ct are arranged along the second direction V2. Specifically, a plurality of through wirings 47 are arranged between four contact portions Ct that share one readout circuit 22 and four through wiring contact portions Ct that share another readout circuit 22 adjacent in the second direction V2 of the readout circuit 22. In this case, the use of the insulating layer 53 and the through wiring 47 makes it possible to reduce or eliminate crosstalk between the readout circuits 22 adjacent to each other. It is also possible to reduce or eliminate the resolution degradation of the reproduced image and the image quality degradation due to color mixing.

[0242] [Variant F]

[0243] Fig.48 An example of a cross-sectional configuration of the image pickup element 1 in the horizontal direction is shown. Fig.48 Shows Fig.12 A variation of the cross-sectional configuration.

[0244] In this modification, the first substrate 10 has a photodiode PD and a transfer transistor TR for each sensor pixel 12, and the floating diffusion FD is common to each of the four sensor pixels 12. Therefore, in this modification, one contact portion Ct is provided for each of the four sensor pixels 12.

[0245] Among the plurality of sensor pixels 12 arranged in a matrix form, four sensor pixels 12 corresponding to an area obtained by shifting a unit area corresponding to four sensor pixels 12 sharing one floating diffusion portion FD in the first direction V1 by one sensor pixel 12 are referred to as four sensor pixels 12A for convenience. In this case, in the present modification, the first substrate 10 shares the through wiring 47 for each of the four sensor pixels 12A. Therefore, in the present modification, one through wiring 47 is provided for each of the four sensor pixels 12A.

[0246] In the present modification, the first substrate 10 has a pixel isolation portion 203 that isolates the photodiode PD and the transfer transistor TR for each sensor pixel 12. The pixel isolation portion 203 does not completely surround the sensor pixel 12 when viewed from the normal direction of the semiconductor substrate 11, and has a gap (unformed region) near the floating diffusion portion FD (through wiring 54) and near the through wiring 47. And, the gap enables four sensor pixels 12 to share one through wiring 54 and four sensor pixels 12A to share one through wiring 47. In the present modification, the second substrate 20 has a readout circuit 22 for each of the four sensor pixels 12 that share the floating diffusion portion FD.

[0247] Fig.49 An example of a cross-sectional configuration in the horizontal direction of the image pickup element 1 according to the present modification is shown. Fig.49 Shows Fig.46 In this modification, the first substrate 10 has a photodiode PD and a transfer transistor TR for each sensor pixel 12, and the floating diffusion portion FD is shared by each of the four sensor pixels 12. In addition, the first substrate 10 has a pixel isolation portion 203 that isolates the photodiode PD and the transfer transistor TR for each sensor pixel 12.

[0248] Fig.50 An example of a cross-sectional configuration in the horizontal direction of the image pickup element 1 according to the present modification is shown. Fig.50 Shows Fig.47 In this modification, the first substrate 10 has a photodiode PD and a transfer transistor TR for each sensor pixel 12, and the floating diffusion portion FD is shared by each of the four sensor pixels 12. In addition, the first substrate 10 has a pixel isolation portion 203 that isolates the photodiode PD and the transfer transistor TR for each sensor pixel 12.

[0249] [Variant G]

[0250] Fig.51 An example of a circuit configuration of an image pickup element 1 according to a modification is shown. The image pickup element 1 according to the present modification is a CMOS image pickup element on which a column-parallel ADC is mounted.

[0251] like Fig.51 As shown, the image pickup element 1 according to the present modification has a pixel area 13, and a plurality of sensor pixels 12 including photoelectric transducers are two-dimensionally arranged in a matrix form in the pixel area 13. The image pickup element 1 also has a vertical drive circuit 33, a column signal processing circuit 34, a reference voltage supply unit 38, a horizontal drive circuit 35, a horizontal output line 37, and a system control circuit 36.

[0252] In this system configuration, the system control circuit 36 ​​generates a clock signal, a control signal, etc. based on the master clock MCK as a reference for the operation of the vertical drive circuit 33, the column signal processing circuit 34, the reference voltage supply unit 38, the horizontal drive circuit 35, etc. The system control circuit 36 ​​supplies the generated signal to the vertical drive circuit 33, the column signal processing circuit 34, the reference voltage supply unit 38, the horizontal drive circuit 35, etc.

[0253] In addition, the vertical drive circuit 33 is formed on the first substrate 10 together with each sensor pixel 12 in the pixel area 13, and the vertical drive circuit 33 is also formed on the second substrate 20 on which the readout circuit 22 is formed. The column signal processing circuit 34, the reference voltage supply unit 38, the horizontal drive circuit 35, the horizontal output line 37, and the system control circuit 36 ​​are formed on the third substrate 30.

[0254] Although not shown in the figure, in one example, the sensor pixel 12 may have a configuration including, in addition to the photodiode PD, a transfer transistor TR that transfers the charge obtained by photoelectric conversion in the photodiode PD to the floating diffusion FD. In addition, although not shown in the figure, the readout circuit 22 may have a three-transistor configuration. In one example, the three-transistor configuration includes a reset transistor RST that controls the potential of the floating diffusion FD, an amplifier transistor AMP that outputs a signal corresponding to the potential of the floating diffusion FD, and a selection transistor SEL that performs pixel selection.

[0255] In the pixel region 13, the sensor pixels 12 are arranged two-dimensionally, the pixel drive lines 23 are wired for each row of the pixel arrangement of m rows and n columns, and the vertical signal lines 24 are wired for each column. Each end of each of the plurality of pixel drive lines 23 is connected to each output end corresponding to each row of the vertical drive circuit 33. The vertical drive circuit 33 is configured as a shift register or the like, and controls row addressing and row scanning of the pixel region 13 via the plurality of pixel drive lines 23.

[0256] In one example, the column signal processing circuit 34 has analog-to-digital conversion circuits (ADC) 34-1 to 34-m provided for each pixel row (i.e., for each vertical signal line 24) in the pixel area 13. The column signal processing circuit 34 converts the analog signal output from each column of each sensor pixel 12 in the pixel area 13 into a digital signal and outputs it.

[0257] In one example, the reference voltage supply unit 38 has a digital-to-analog conversion circuit (DAC) 38A as an element for generating a reference voltage Vref of a so-called ramp waveform whose level changes in a ramp manner over time. Also, the element for generating the reference voltage Vref of the ramp waveform is not limited to the DAC 38A.

[0258] The DAC 38A generates a reference voltage Vref of a ramp waveform based on a clock CK given from the system control circuit 36 ​​under the control of a control signal CS1 given from the system control circuit 36 ​​and supplies to the ADCs 34 - 1 to 34 - m of the column signal processing circuit 34 .

[0259] Moreover, each of the ADCs 34-1 to 34-m is configured to be able to selectively perform AD conversion operations corresponding to each operation mode (including a normal frame rate mode and a high-speed frame rate mode). The normal frame rate mode is a row-by-row scanning mode in which information is read out from all the sensor pixels 12. The high-speed frame rate mode is a mode in which the exposure time of the sensor pixels 12 is set to 1 / N, and the frame rate is increased by N times, for example, twice that of the normal frame rate mode. The execution of this operation mode switching is controlled by control signals CS2 and CS3 given by the system control circuit 36. In addition, instruction information for switching the operation mode between the normal frame rate mode and the high-speed frame rate mode is given to the system control circuit 36 ​​from an external system controller (not shown).

[0260] ADC 34-1 to 34-m have the same configuration, and in this example, ADC 34-m is described as an example. ADC 34-m has a comparator 34A, a counting device such as an up / down counter (indicated as U / DCNT in the figure) 34B, a transmission switch 34C, and a storage device 34D.

[0261] The comparator 34A compares the signal voltage Vx of the vertical signal line 24 corresponding to the signal output by each sensor pixel 12 of the n-th row of the pixel area 13 with the reference voltage Vref of the ramp waveform provided by the reference voltage providing unit 38. In one example, if the reference voltage Vref is greater than the signal voltage Vx, the output Vco of the comparator is at an "H" level, and if the reference voltage Vref is equal to or less than the signal voltage Vx, the output Vco is at an "L" level.

[0262] The up / down counter 34B is an asynchronous counter. The clock CK from the system control circuit 36 ​​is given to the up / down counter 34B and the DAC 38A at the same time under the control of the control signal CS2 given by the system control circuit 36. The up / down counter 34B measures the comparison period from the start of the comparison operation to the end of the comparison operation in the comparator 34A by performing down counting or up counting in synchronization with the clock CK.

[0263] Specifically, in the normal frame rate mode, in the readout operation of the signal from one sensor pixel 12, the comparison time in the first readout operation is measured by performing down-counting in the first readout operation, and the comparison time in the second readout operation is measured by performing up-counting in the second readout operation.

[0264] On the other hand, in the high-speed frame rate mode, the comparison time at the first readout operation is measured by keeping the count result for one row of sensor pixels 12 as it is and performing down-counting at the first readout operation from the previous count result for the next row of sensor pixels 12. The comparison time at the second readout operation is measured by performing up-counting at the second readout operation.

[0265] In the normal frame rate mode, under the control of the control signal CS3 given by the system control circuit 36, the transfer switch 34C is turned on (closed) when the counting operation of the up / down counter 34B for one row of sensor pixels 12 is completed. The transfer switch 34C transfers the counting result of the up / down counter 34B to the storage device 34D.

[0266] On the other hand, in one example, at a high-speed frame rate of N=2, when the counting operation of the up / down counter 34B for one row of sensor pixels 12 is completed, the transfer switch 34C is disconnected (opened), and when the counting operation of the up / down counter 34B for the next row of sensor pixels 12 is completed, the transfer switch 34C is turned on. The counting results of two vertical pixels for the up / down counter 34B are transferred to the storage device 34D.

[0267] Thus, the analog signals supplied to the sensor pixels 12 in the pixel area 13 via the vertical signal lines 24 for the columns are converted into N-bit digital signals by respective operations of the comparators 34A and the up / down counters 34B in the ADCs 34-1 to 34-m, and stored in the memory device 34D.

[0268] The horizontal drive circuit 35 includes a shift register and the like, and controls column addressing and column scanning of the ADCs 34-1 to 34-m in the column signal processing circuit 34. Under the control of the horizontal drive circuit 35, N-bit digital signals AD-converted by each of the ADCs 34-1 to 34-m are sequentially read out to the horizontal output line 37, and are output as image pickup data via the horizontal output line 37.

[0269] Furthermore, although not specifically shown because it is not directly related to the present disclosure, in addition to the above-described constituent elements, a circuit or the like that performs various signal processing on the image pickup data output via the horizontal output line 37 may be provided.

[0270] In the image pickup element 1 equipped with the column-parallel ADC according to the present modification example having the above configuration, the count result of the up / down counter 34B can be selectively transmitted to the storage device 34D via the transmission switch 34C. Therefore, the count operation of the up / down counter 34B and the readout operation of the count result of the up / down counter 34B to the horizontal output line 37 can be controlled separately.

[0271] [Variation H]

[0272] Fig.52 The structure is shown as a structure formed by stacking three substrates (a first substrate 10, a second substrate 20, and a third substrate 30) on each other. Fig.51 An example of an imaging element 1 of the present invention. In this modification, on the first substrate 10, a pixel region 13 including a plurality of sensor pixels 12 is formed in the central portion of the first substrate 10, and a vertical drive circuit 33 is formed around the pixel region 13. In addition, on the second substrate 20, a readout circuit region 15 including a plurality of readout circuits 22 is formed in the central portion of the second substrate 20, and a vertical drive circuit 33 is formed around the readout circuit region 15. On the third substrate 30, a column signal processing circuit 34, a horizontal drive circuit 35, a system control circuit 36, a horizontal output line 37, and a reference voltage supply unit 38 are formed. Therefore, similar to the above-mentioned embodiment and its modification, the structure in which the substrates are electrically connected to each other can prevent the size of the chip from increasing and hindering the miniaturization of the area per pixel. Therefore, it is possible to provide an imaging element 1 having a three-layer structure, which can have the same chip size as the related art without hindering the miniaturization of the area per pixel. Moreover, the vertical drive circuit 33 can be formed only on the first substrate 10 or only on the second substrate 20.

[0273] [Modification Example 1]

[0274] Fig.53 FIG. 1 shows a modified example of the cross-sectional configuration of the image pickup element 1 according to the present modified example. In the first embodiment and its modified example, the image pickup element 1 is configured by stacking three substrates (the first substrate 10, the second substrate 20, and the third substrate 30) on top of each other. However, in the first embodiment and its modified example, the image pickup element 1 may be configured by stacking two substrates (the first substrate 10 and the second substrate 20) on top of each other. In this case, in one example, as Fig.53As shown, the logic circuit 32 is formed in the first substrate 10 and the second substrate 20, respectively. In this example, one circuit 32A of the logic circuit 32 is provided on the first substrate 10 side. The circuit 32A is provided with a transistor having a gate structure in which a high dielectric constant film (e.g., high-k) having a material capable of withstanding high temperature processing and a metal gate are stacked on each other. On the other hand, another circuit 32B is provided on the second substrate 20 side, and a low resistance region 26 is formed thereon. The low resistance region 26 includes a silicide made on the surface of the impurity diffusion region in contact with the source and drain by processing with a self-aligned silicide (salicide) such as CoSi2 or NiSi. The low resistance region including the silicide is formed as a compound of the material of the semiconductor substrate and the metal. Therefore, a high temperature process such as thermal oxidation can be used when forming the sensor pixel 12. In addition, in the case where the circuit 32B provided on the second substrate 20 side of the logic circuit 32 is provided with a low resistance region 26 (including a silicide on the surface of the impurity diffusion region in contact with the source and drain), the contact resistance can be reduced. Therefore, the calculation speed of the logic circuit 32 can be increased.

[0275] Fig.54 A variation of the cross-sectional configuration of the image pickup element 1 according to the first embodiment and its variation is shown. A low resistance region 37 may be formed on the logic circuit 32 of the third substrate 30 according to the first embodiment and its variation. The low resistance region 37 includes a silicide made on the surface of the impurity diffusion region in contact with the source and drain by processing with a self-aligned silicide (salicide) such as CoSi2 or NiSi. Therefore, a high temperature process such as thermal oxidation may be used when forming the sensor pixel 12. In addition, in the case where the logic circuit 32 is provided with a low resistance region 37 (including a silicide on the surface of the impurity diffusion region in contact with the source and drain), the contact resistance can be reduced. Therefore, the calculation speed of the logic circuit 32 can be increased.

[0276] <10. Application Examples>

[0277] Fig.55 An example of a schematic configuration of an imaging system 2 having an imaging element 1 is shown.

[0278] In one example, the imaging system 2 is an electronic device including an imaging device such as a digital camera or a video camera and a mobile terminal device such as a smartphone or a tablet terminal. The imaging system 2 includes, for example, an imaging element 1, a DSP circuit 141, a frame memory 142, a display unit 143, a storage unit 144, an operation unit 145, and a power supply unit 146. In the imaging system 2, the imaging element 1, the DSP circuit 141, the frame memory 142, the display unit 143, the storage unit 144, the operation unit 145, and the power supply unit 146 are connected to each other via a bus 147.

[0279] The imaging element 1 outputs image data corresponding to incident light. The DSP circuit 141 is a signal processing circuit that processes a signal (image) output from the imaging element 1. The frame memory 142 temporarily holds the image data processed by the DSP circuit 141 in units of frames. The display unit 143 is a flat-panel display device such as a liquid crystal display panel or an organic electroluminescent (EL) panel and displays a moving image or a still image captured by the imaging element 1. The storage unit 144 records the image data of the moving image or the still image captured by the imaging element 1 on a recording medium such as a semiconductor memory or a hard disk. The operation unit 145 issues operation instructions for various functions of the imaging system 2 in response to user operations. The power supply unit 146 appropriately supplies various power sources used as operation power sources to the target to be powered for the imaging element 1, the DSP circuit 141, the frame memory 142, the display unit 143, the storage unit 144, and the operation unit 145.

[0280] The imaging procedure of the imaging system 2 will now be described.

[0281] Fig.56 An example of a flowchart of an imaging operation in the imaging system 2 is shown. The user instructs to start imaging by operating the operating unit 145 (step S101). Then, the operating unit 145 sends an imaging command to the imaging element 1 (step S102). Upon receiving the imaging command, the imaging element 1 (specifically, the system control circuit 36) performs imaging according to a predetermined imaging mode (step S103).

[0282] The imaging element 1 outputs the image data obtained by imaging to the DSP circuit 141. In this description, the image data is data for all pixels of the pixel signal generated based on the charge temporarily held in the floating diffusion FD. The DSP circuit 141 performs predetermined signal processing (for example, noise reduction processing) based on the image data input from the imaging element 1 (step S104). The DSP circuit 141 causes the frame memory 142 to hold the image data subjected to the predetermined signal processing, and the frame memory 142 stores the image data in the storage unit 144 (step S105). In this way, imaging is performed in the imaging system 2.

[0283] In this application example, the image pickup element 1 is applied to an image pickup system 2. Therefore, it is possible to reduce the size of the image pickup element 1 or realize an image pickup element with high resolution, thereby providing a small-sized or high-resolution image pickup system 2.

[0284] <11. Example of use>

[0285] [Use Example 1]

[0286] The technology according to the embodiments of the present disclosure (the present technology) can be applied to various products. For example, the technology according to the embodiments of the present disclosure can be implemented as a device installed in any of the following mobile bodies, for example, a car, an electric car, a hybrid electric car, a motorcycle, a bicycle, a personal mobile device, an airplane, a drone, a ship, or a robot, etc.

[0287] Fig.57 : is a block diagram showing an example of a schematic structure of a vehicle control system as an example of a moving body control system to which the technology according to the present disclosure is applied.

[0288] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Fig.57 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a main body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an overall control unit 12050. In addition, a microcomputer 12051, a sound / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown as the functional configuration of the overall control unit 12050.

[0289] The drive system control unit 12010 controls the operation of the devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 is used as a control device for the following devices: a drive force generating device (such as an internal combustion engine, a drive motor, etc.) for generating the drive force of the vehicle, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating the braking force of the vehicle, etc.

[0290] The main body system control unit 12020 controls the operation of various devices provided on the vehicle body according to various programs. For example, the main body system control unit 12020 is used as a control device for a keyless entry system, a smart key system, a power window device, or various lights such as a headlight, a backup light, a brake light, a turn signal light, a fog light, etc. In this case, a radio wave sent from a mobile device instead of a key or a signal of various switches may be input to the main body system control unit 12020. The main body system control unit 12020 receives these input radio waves or signals, and controls the door lock device, the power window device, the lights, etc. of the vehicle.

[0291] The vehicle exterior information detection unit 12030 detects information about the exterior of the vehicle having the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to the camera unit 12031. The vehicle exterior information detection unit 12030 causes the camera unit 12031 to capture an image of the exterior of the vehicle and receives the captured image. Based on the received image, the vehicle exterior information detection unit 12030 may perform a process of detecting a target such as a person, a vehicle, an obstacle, a mark, a symbol, etc. on the road surface, or perform a process of detecting the distance thereto.

[0292] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or output the electrical signal as information about the measured distance. In addition, the light received by the imaging unit 12031 may be visible light, or may be invisible light such as infrared rays.

[0293] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. For example, the in-vehicle information detection unit 12040 is connected to a driver state detection unit 12041 that detects the driver's state. The driver state detection unit 12041 includes, for example, a camera that photographs the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue level or the driver's concentration level, or can determine whether the driver is dozing off.

[0294] Based on the information about the inside or outside of the vehicle obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, the microcomputer 12051 can calculate the control target value of the driving force generation device, the steering mechanism or the braking device, and output the control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control to realize the functions of the advanced driver assistance system (ADAS), which includes vehicle collision prevention or shock absorption, follow-up driving based on vehicle spacing, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc.

[0295] In addition, based on information about the outside or inside of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040, the microcomputer 12051 can perform collaborative control by controlling the driving force generation device, steering mechanism, braking device, etc. to perform automatic driving, etc., so that the vehicle can drive autonomously without relying on the driver's operation.

[0296] In addition, based on the information about the outside of the vehicle obtained by the vehicle outside information detection unit 12030, the microcomputer 12051 can output a control command to the main system control unit 12020. For example, the microcomputer 12051 can control the headlights to switch the high beam to the low beam according to the position of the preceding vehicle or the oncoming vehicle detected by the vehicle outside information detection unit 12030, thereby performing cooperative control to achieve anti-glare.

[0297] The sound / image output unit 12052 sends an output signal of at least one of sound or image to an output device capable of visually or auditorily indicating information to a passenger of the vehicle or outside the vehicle. Fig.57 In the example of FIG. 1 , an audio speaker 12061, a display unit 12062, and a dashboard 12063 are shown as output devices. For example, the display unit 12062 may include at least one of an in-vehicle display and / or a head-up display.

[0298] Fig.58 12031 is a diagram showing an example of the installation position of the imaging unit 12031.

[0299] exist Fig.58 In the figure, vehicle 12100 includes camera units 12101, 12102, 12103, 12104 and 12105 as camera unit 12031.

[0300] For example, the camera units 12101, 12102, 12103, 12104, and 12105 are located at the front nose, side mirrors, rear bumper, rear door, upper portion of the windshield inside the vehicle 12100, etc. The camera unit 12101 located at the front nose and the camera unit 12105 located at the upper portion of the windshield inside the vehicle mainly acquire images in front of the vehicle 12100. The camera units 12102 and 12103 located at the side mirrors mainly acquire images of the side areas of the vehicle 12100. The camera unit 12104 located at the rear bumper or rear door mainly acquires images of the rear of the vehicle 12100. The images in front of the vehicle acquired by the camera units 12101 and 12105 are mainly used to detect vehicles, pedestrians, obstacles, traffic signals, traffic signs, lanes, etc. traveling in front.

[0301] in addition, Fig.58An example of the imaging ranges of the imaging units 12101 to 12104 is shown. The imaging range 12111 indicates the imaging range of the imaging unit 12101 provided at the front nose. The imaging ranges 12112 and 12113 respectively indicate the imaging ranges of the imaging units 12102 and 12103 provided at the side mirrors. The imaging range 12114 indicates the imaging range of the imaging unit 12104 provided at the rear bumper or the rear door. For example, a bird's-eye view of the vehicle 12100 viewed from above can be obtained by superimposing the image data captured by the imaging units 12101 to 12104.

[0302] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0303] For example, based on the distance information obtained from the camera units 12101 to 12104, the microcomputer 12051 can determine the distance to each three-dimensional target within the camera range 12111 to 12114 and the time change of the distance (relative speed relative to the vehicle 12100), thereby extracting the nearest three-dimensional target (particularly on the driving path of the vehicle 12100 and traveling in the same direction as the vehicle 12100 at a predetermined speed (for example, 0 km / h or more)) as the vehicle traveling ahead. In addition, the microcomputer 12051 can pre-set the distance between the vehicles and the vehicle in front of the vehicle 12100 to be maintained, and can perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed to perform automatic driving that allows the vehicle to travel autonomously without relying on the driver's operation.

[0304] For example, based on the distance information obtained from the camera units 12101 to 12104, the microcomputer 12051 can classify the three-dimensional target data of the three-dimensional target into three-dimensional target data of two-wheeled vehicles, standard vehicles, large vehicles, pedestrians, and other three-dimensional targets such as public utility poles, extract the classified three-dimensional target data, and automatically avoid obstacles using the extracted three-dimensional target data. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that can be visually recognized by the driver of the vehicle 12100 and obstacles that are difficult for the driver of the vehicle 12100 to visually recognize. Then, the microcomputer 12051 determines the collision risk indicating the risk of collision with each obstacle. When the collision risk is equal to or higher than the set value and there is a possibility of collision, the microcomputer 12051 outputs a warning to the driver through the audio speaker 12061 or the display unit 12062, and performs forced deceleration or steering avoidance through the drive system control unit 12010. The microcomputer 12051 can thus assist driving and avoid collisions.

[0305] At least one of the camera units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 is capable of identifying pedestrians by determining whether there are pedestrians in the captured images of the camera units 12101 to 12104. For example, such identification of pedestrians is achieved by extracting feature points from the captured images of the camera units 12101 to 12104 as infrared cameras, and determining whether there are pedestrians by pattern matching a series of feature points representing the contour of the target. When the microcomputer 12051 determines that there are pedestrians in the captured images of the camera units 12101 to 12104 and thus identifies the pedestrians, the sound / image output unit 12052 controls the display unit 12062 so that a rectangular contour line for emphasis is displayed as superimposed on the identified pedestrian. In addition, the sound / image output unit 12052 may also control the display unit 12062 so that an icon representing a pedestrian is displayed at a desired position.

[0306] The above describes an example mobile control system that can adopt the technology according to the present disclosure. The technology according to the present disclosure can be applied to the camera unit 12031 in the above-mentioned structure. Specifically, the camera element 1 according to the above-mentioned embodiment and its modified example can be applied to the camera unit 12031. The technology according to the present disclosure applied to the camera unit 12031 makes it possible to obtain a high-resolution image captured with little noise. Therefore, it is possible to perform high-precision control using the image captured in the mobile control system.

[0307] [Use Example 2]

[0308] Fig.59is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) can be applied.

[0309] exist Fig.59 , a state is shown in which a surgeon (doctor) 11131 uses an endoscopic surgery system 11000 to perform surgery on a patient 11132 on a bed 11133. As shown in the figure, the endoscopic surgery system 11000 includes an endoscope 11100, other surgical tools 11110 such as a pneumoperitoneum tube 11111 and an energy device 11112, a support arm device 11120 for supporting the endoscope 11100, and a cart 11200 on which various devices for endoscopic surgery are installed.

[0310] The endoscope 11100 includes a lens barrel 11101, a region of a predetermined length from the end of the lens barrel 11101 is inserted into the body cavity of the patient 11132, and a camera 11102 is connected to the proximal end of the lens barrel 11101. In the example shown, the endoscope 11100 is shown as a rigid endoscope having a rigid lens barrel 11101. However, the endoscope 11100 can also be used as a flexible endoscope having a flexible lens barrel.

[0311] An opening is provided at the end of the lens barrel 11101, and an objective lens is embedded in the opening. A light source device 11203 is connected to the endoscope 11100, so that the light generated by the light source device 11203 is guided to the end of the lens barrel through a light guide extending in the lens barrel 11101, and the light is irradiated to the observation object in the body cavity of the patient 11132 through the objective lens. It should be noted that the endoscope 11100 can be a forward-viewing endoscope or can be an oblique-viewing endoscope or a side-viewing endoscope.

[0312] An optical system and an imaging device are provided inside the camera head 11102, so that the reflected light (observation light) from the observation object is gathered on the imaging element by the optical system. The observation light is photoelectrically converted by the imaging element to generate an electrical signal corresponding to the observation light, that is, an image signal corresponding to the observation image. The image signal is sent to the camera control unit (CCU) 11201 as RAW data.

[0313] The CCU 11201 includes a central processing unit (CPU), a graphics processing unit (GPU), etc., and integrally controls the operations of the endoscope 11100 and the display device 11202. In addition, the CCU 11201 receives an image signal from the camera 11102, and performs various image processing such as development processing (demosaic processing) on ​​the image signal to display an image based on the image signal.

[0314] Under the control of the CCU 11201, the display device 11202 displays an image based on the image signal (which has been image-processed by the CCU 11201).

[0315] For example, the light source device 11203 includes a light source such as a light emitting diode (LED), and provides irradiation light to the endoscope 11100 when photographing a surgical site or the like.

[0316] The input device 11204 is an input interface of the endoscopic surgery system 11000. The user can input various information or instructions to the endoscopic surgery system 11000 through the input device 11204. For example, the user can input instructions to change the imaging conditions of the endoscope 11100 (type of irradiation light, magnification, focal length, etc.).

[0317] The treatment tool control device 11205 controls the driving of the energy device 11112 for tissue cauterization or cutting, blood vessel sealing, etc. The pneumoperitoneum device 11206 supplies gas to the body cavity of the patient 11132 through the pneumoperitoneum tube 11111 to expand the body cavity so as to ensure the field of view of the endoscope 11100 and the operating space of the operating staff. The recorder 11207 is a device capable of recording various information related to the operation. The printer 11208 is a device capable of printing various information related to the operation in various formats such as text, images, or charts.

[0318] It should be noted that the light source device 11203 that provides irradiation light to the endoscope 11100 when photographing the surgical site may include a white light source, such as an LED, a laser light source, or a combination of an LED and a laser light source. In the case where the white light source includes a combination of red, green, and blue (RGB) laser light sources, since the output intensity and output timing of each color (each wavelength) can be controlled with high precision, the white balance of the image photographed by the light source device 11203 can be adjusted. In addition, in this case, if the laser light from each RGB laser light source is irradiated onto the observed object in a time-division manner, and the driving of the imaging element of the camera 11102 can be controlled synchronously with the light emission timing, it is also possible to acquire images corresponding to the respective colors of R, G, and B in a time-division manner. According to the above method, a color image can be obtained even if a color filter is not provided in the imaging element.

[0319] In addition, the light source device 11203 can be controlled so that the light intensity to be output changes at each predetermined time. The driving of the imaging element of the camera 11102 is controlled synchronously with the timing of the light intensity change, and images are acquired in a time-division manner, and the images are synthesized, so that images with a high dynamic range can be generated without underexposed shadows and overexposed highlights.

[0320] In addition, the light source device 11203 can also be configured to provide light of a predetermined wavelength band suitable for special light observation. In special light observation, for example, by emitting a narrow band of light compared to the illumination light (i.e., white light) during ordinary observation, narrow-band light observation (narrow-band photography) is performed with high contrast to photograph predetermined tissues such as blood vessels on the surface of the mucosa by utilizing the wavelength dependence of light absorption in human tissue. Alternatively, in special light observation, fluorescence observation in which an image is obtained by emitting fluorescence generated by excitation light can also be performed. In fluorescence observation, by emitting excitation light to human tissue, fluorescence from human tissue can be observed (autofluorescence observation), or, for example, by locally injecting reagents such as indocyanine green (ICG) into human tissue, and emitting excitation light corresponding to the fluorescence wavelength of the reagent to the human tissue, a fluorescent image can be obtained. The light source device 11203 can be configured to provide narrow-band light and / or excitation light suitable for special light observation as described above.

[0321] Fig.60 It is shown Fig.59 A block diagram of an example of the functional configuration of the camera 11102 and the CCU 11201 shown.

[0322] The camera 11102 includes a lens unit 11401, an imaging unit 11402, a driving unit 11403, a communication unit 11404, and a camera control section 11405. The CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control section 11413. The camera 11102 and the CCU 11201 are communicably connected to each other via a transmission cable 11400.

[0323] The lens unit 11401 is an optical system provided at a position connected to the lens barrel 11101. Observation light acquired from the end of the lens barrel 11101 is guided to the camera 11102 and enters the lens unit 11401. The lens unit 11401 includes a combination of a plurality of lenses (including a zoom lens and a focus lens).

[0324] The imaging unit 11402 includes an imaging element. The number of imaging elements included in the imaging unit 11402 may be one (so-called single-board type) or multiple (so-called multi-board type). For example, in the case where the imaging unit 11402 is configured as a multi-board type, the imaging element generates image signals corresponding to the colors R, G, and B, and the image signals can be synthesized to obtain a color image. The imaging unit 11402 may also be configured to have a pair of imaging elements for acquiring image signals for the right eye and the left eye suitable for three-dimensional (3D) display. If a 3D display is performed, the surgeon 11131 can more accurately grasp the depth of the body tissue of the surgical site. It should be noted that in the case where the imaging unit 11402 is configured as a multi-board type, a plurality of systems of lens units 11401 are provided corresponding to each imaging element.

[0325] In addition, the camera unit 11402 does not have to be arranged on the camera head 11102. For example, the camera unit 11402 can be arranged in the lens barrel 11101 immediately behind the objective lens.

[0326] The driving unit 11403 includes an actuator, and moves the zoom lens and the focus lens of the lens unit 11401 along the optical axis by a predetermined distance under the control of the camera control section 11405. Therefore, the magnification and focus of the image captured by the imaging unit 11402 can be appropriately adjusted.

[0327] The communication unit 11404 includes a communication device for transmitting and receiving various information to and from the CCU 11201. The communication unit 11404 transmits an image signal obtained as RAW data from the imaging unit 11402 to the CCU 11201 through the transmission cable 11400.

[0328] In addition, the communication unit 11404 receives a control signal for controlling the driving of the camera 11102 from the CCU 11201, and provides the control signal to the camera control unit 11405. For example, the control signal includes information related to the imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value during imaging, and / or information specifying the magnification and focus of the captured image.

[0329] It should be noted that imaging conditions such as a frame rate, an exposure value, a magnification, or a focus may be appropriately specified by a user, or may be automatically set based on an acquired image signal by the control unit 11413 of the CCU 11201. In the latter case, an auto exposure (AE) function, an auto focus (AF) function, and an auto white balance (AWB) function are incorporated in the endoscope 11100.

[0330] The camera control unit 11405 controls the driving of the camera 11102 based on the control signal from the CCU 11201 received through the communication unit 11404 .

[0331] The communication unit 11411 includes a communication device for transmitting and receiving various information to and from the camera 11102. The communication unit 11411 receives an image signal transmitted from the camera 11102 through the transmission cable 11400.

[0332] In addition, the communication unit 11411 transmits a control signal for controlling the driving of the camera 11102 to the camera 11102. The image signal and the control signal can be transmitted through electrical communication, optical communication, or the like.

[0333] The image processing unit 11412 performs various image processing on the image signal in the form of RAW data sent from the camera 11102 .

[0334] The control unit 11413 performs various controls related to the endoscope 11100 capturing images of the surgical site, etc., and various controls related to the display of captured images obtained by capturing images of the surgical site, etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102 .

[0335] In addition, based on the image signal processed by the image processing unit 11412, the control unit 11413 controls the display device 11202 to display the captured image in which the surgical site and the like are captured. In this way, the control unit 11413 can use various image recognition technologies to recognize various objects in the captured image. For example, the control unit 11413 can recognize surgical tools such as forceps, specific body parts, bleeding, mist when the energy device 11112 is used, etc. by detecting the shape, color, etc. of the edge of the object included in the captured image. When the control unit 11413 controls the display device 11202 to display the captured image, the control unit 11413 can use the recognition result to display various surgical auxiliary information in a manner superimposed on the image of the surgical site. When the surgical auxiliary information is superimposed and displayed and presented to the surgical staff 11131, the burden on the surgical staff 11131 can be reduced, and the surgical staff 11131 can perform the operation with certainty.

[0336] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 to each other is an electric signal cable suitable for electric signal communication, an optical fiber suitable for optical communication, or a composite cable suitable for both electric communication and optical communication.

[0337] Here, in the example shown, although communication is performed in a wired manner using the transmission cable 11400, communication between the camera 11102 and the CCU 11201 may be performed in a wireless manner.

[0338] An example of an endoscopic surgical system that can adopt the technology according to the present disclosure has been described above. The technology according to the present disclosure is applicable to the imaging unit 11402 of the camera head 11102 of the endoscope 11100 in the above-mentioned structure. Applying the technology according to the present disclosure to the imaging unit 11402 makes it possible to reduce the size of the imaging unit 11402 or to realize a high-resolution imaging unit. Therefore, a small-sized or high-resolution endoscope 11100 can be provided.

[0339] Although the present disclosure is described above through embodiments and their variations, application examples and use examples, the technical scope of the present disclosure is not limited to the original above-mentioned embodiments, etc., and various changes and modifications can be made to it without departing from the essence and scope of the present disclosure. In addition, the constituent elements described in different embodiments and variations can be arbitrarily combined.

[0340] Furthermore, the effects of the embodiments described in this specification are merely exemplary and not restrictive, and other effects may be obtained.

[0341] Additionally, the present technology may also be configured as described below. (1)

[0343] A camera element, comprising:

[0344] a first substrate on which a plurality of photoelectric converters are formed;

[0345] a second substrate having a pixel transistor formed for each group having two or more of the photoelectric converters as a constituent unit, the pixel transistor being shared by the group; and

[0346] A second wiring is connected to a first wiring formed on the second substrate via a contact portion and is connected to a plurality of first elements, wherein the first wiring leads to a second element shared by the plurality of first elements among the plurality of elements formed on the first substrate, each of the plurality of first elements being formed for each of the photoelectric transducers. (2)

[0348] The imaging device according to (1), wherein:

[0349] The second wiring is connected to a plurality of the first elements corresponding one-to-one to the two or more photoelectric transducers included in each group for the two or more photoelectric transducers, and is connected to the first wiring leading to the second element common to the plurality of the first elements via a contact portion. (3)

[0351] According to the imaging element of (1) or (2),

[0352] The second wiring is arranged closer to the light incident surface side than the second substrate. (4)

[0354] The imaging device according to any one of (1) to (3), wherein:

[0355] The first substrate has a transfer transistor, which is formed on the first substrate and is used to transfer an electrical signal output from the photoelectric converter to the pixel transistor for each photoelectric converter,

[0356] The second substrate has the pixel transistors formed on the second substrate, the pixel transistors including at least one amplifying transistor configured to amplify and output, for each or more of the groups, an electrical signal transmitted by each of the two or more transmission transistors included in the group,

[0357] The first element includes an output terminal side of the pass transistor, and

[0358] The second element includes a gate of the amplifying transistor. (5)

[0360] According to the imaging element of (4),

[0361] The output terminal side of the transfer transistor is a floating diffusion portion that temporarily holds the electrical signal output from the photoelectric converter. (6)

[0363] The imaging element according to (4) or (5), wherein:

[0364] The transfer transistor is an N-type transistor, and

[0365] The second wiring is formed of P-type polysilicon. (7)

[0367] The imaging device according to (6), wherein:

[0368] The first element includes an electrode connected to the photoelectric transducer,

[0369] the second element comprises a reference potential line supplied with a reference potential,

[0370] The electrode is formed of P-type polysilicon, and

[0371] The second wiring for connecting the plurality of electrodes to the first wiring leading to the reference potential line via one contact portion is formed of N-type polysilicon. (8)

[0373] According to the imaging element of (4),

[0374] The transfer transistor is a P-type transistor, and

[0375] The second wiring is formed of N-type polysilicon. (9)

[0377] The imaging device according to (8), wherein:

[0378] The first element includes an electrode connected to the photoelectric transducer,

[0379] the second element comprises a reference potential line supplied with a reference potential,

[0380] The electrode is formed of N-type polysilicon, and

[0381] The second wiring for connecting the plurality of electrodes to the first wiring leading to the reference potential line via one contact portion is formed of P-type polysilicon. (10)

[0383] The imaging device according to any one of (1) to (4), wherein:

[0384] The first element includes an electrode connected to the photoelectric transducer, and

[0385] The second element includes a reference potential line supplied with a reference potential. (11)

[0387] The imaging device according to any one of (1) to (4) or (10),

[0388] Wherein, the second wiring is formed to include tungsten. (12)

[0390] The imaging device according to any one of (1), (2) or (4) to (11),

[0391] The second wiring is arranged in an insulating region formed between a first semiconductor region of the second substrate and a second semiconductor region of the second substrate. (13)

[0393] The imaging device according to any one of (1), (2) or (4) to (11),

[0394] The second wiring is arranged between the second element and the first wiring. (14)

[0396] An electronic device, comprising:

[0397] Camera element;

[0398] an optical system configured to guide incident light to the imaging element; and

[0399] a processing unit configured to process a signal output from the imaging element,

[0400] Wherein, the imaging element comprises:

[0401] a first substrate on which a plurality of photoelectric converters are formed,

[0402] a second substrate having a pixel transistor formed for each group having two or more of the photoelectric converters as a constituent unit, the pixel transistor being shared by the group; and

[0403] A second wiring is connected to a first wiring formed on the second substrate via a contact portion, the first wiring leading to a second element shared by a plurality of first elements among a plurality of elements formed on the first substrate, each of the plurality of first elements being formed for each of the photoelectric transducers. (15)

[0405] A camera element, comprising:

[0406] a first substrate having a first photoelectric converter and a second photoelectric converter formed on the first substrate;

[0407] a first wiring formed on the first substrate and connected to the first photoelectric transducer and the second photoelectric transducer;

[0408] a second substrate having a pixel transistor formed on the second substrate, the pixel transistor being connected to the first photoelectric converter and the second photoelectric converter;

[0409] a second wiring formed on the second substrate; and

[0410] A third wiring is formed to penetrate the first substrate and the second substrate and is connected to the first wiring and the second wiring. (16)

[0412] According to the imaging element of (15),

[0413] The pixel transistor includes at least one of an amplification transistor, a reset transistor and a selection transistor. (17)

[0415] According to the imaging element of (15) or (16),

[0416] The first substrate has a first transfer transistor connected to the first photoelectric converter and a second transfer transistor connected to the second photoelectric converter. (18)

[0418] According to the imaging element of (17),

[0419] The first wiring is connected to a first floating diffusion region connected to the first transfer transistor and a second floating diffusion region connected to the second transfer transistor. (19)

[0421] The imaging device according to (18), further comprising:

[0422] A third substrate is stacked on the second substrate and has a logic circuit configured to process a signal generated by the first photoelectric transducer or the second photoelectric transducer. (20)

[0424] An electronic device, comprising:

[0425] Camera element;

[0426] an optical system configured to guide incident light to the imaging element; and

[0427] a processing unit configured to process a signal output from the imaging element,

[0428] Wherein, the imaging element comprises:

[0429] a first substrate having a first photoelectric converter and a second photoelectric converter formed on the first substrate;

[0430] a first wiring formed on the first substrate and connected to the first photoelectric transducer and the second photoelectric transducer;

[0431] a second substrate having a pixel transistor formed on the second substrate, the pixel transistor being connected to the first photoelectric converter and the second photoelectric converter;

[0432] a second wiring formed on the second substrate; and

[0433] A third wiring is formed to penetrate the first substrate and the second substrate and is connected to the first wiring and the second wiring.

[0434] Reference numerals list

[0435] 1. Camera element

[0436] 10. First substrate

[0437] 20 Second substrate

[0438] 30 Third substrate

[0439] 202 Semiconductor Area

[0440] 203 Pixel isolation unit

[0441] 204 Semiconductor Area

[0442] 221 Drain region

[0443] 222 Source region

[0444] 223 Gate

[0445] 301a, 301b wiring

[0446] 311 Gate

[0447] 312 Drain region

[0448] 313 Source Region

[0449] 321 Drain region

[0450] 322 Source region

[0451] 323 Gate

[0452] AMP Amplifier Transistor

[0453] Ct, Ct2 contact

[0454] D1 wiring

[0455] PD Photodiode

[0456] RST Reset transistor

[0457] SEL select transistor

[0458] TR Pass Transistor

Claims

1. An imaging element, comprising: a first substrate on which a plurality of photoelectric converters are formed; a second substrate having a pixel transistor formed thereon for each group having two or more of the photoelectric converters as a constituent unit, the pixel transistor being shared by the group; as well as a second wiring connected to a first wiring formed on the second substrate via a contact portion and connected to a plurality of first elements, the first wiring leading to a second element shared by the plurality of first elements among a plurality of elements formed on the first substrate, each of the plurality of first elements being formed for each of the photoelectric transducers, wherein The first element includes an electrode connected to the photoelectric transducer, and The second element includes a reference potential line supplied with a reference potential.

2. The imaging element according to claim 1, wherein: The second wiring is connected to a plurality of the first elements corresponding one-to-one to the two or more photoelectric transducers included in each group for two or more photoelectric transducers, and is connected to the first wiring leading to the second element shared by the plurality of the first elements via a contact portion.

3. The imaging element according to claim 1 or 2, wherein: The second wiring is arranged closer to the light incident surface side than the second substrate.

4. The imaging element according to claim 1 or 2, wherein: A transfer transistor is formed on the first substrate, and the transfer transistor is used to transfer an electrical signal output from the photoelectric converter to the pixel transistor for each photoelectric converter. The pixel transistors are formed on the second substrate, and the pixel transistors include at least one amplifying transistor, and the amplifying transistor is configured to amplify and output an electrical signal transmitted from each of the two or more transmission transistors included in the group for one or more of the groups, The first element includes an output terminal side of the pass transistor, and The second element includes a gate of the amplifying transistor.

5. The imaging element according to claim 4, wherein: The output terminal side of the transfer transistor is a floating diffusion that temporarily holds the electric signal output from the photoelectric converter.

6. The imaging element according to claim 4, wherein: The transfer transistor is an N-type transistor, and The second wiring is formed of P-type polysilicon.

7. The imaging element according to claim 6, wherein: The electrode is formed of P-type polysilicon, and The second wiring for connecting the plurality of electrodes to the first wiring leading to the reference potential line via one contact portion is formed of N-type polysilicon.

8. The imaging element according to claim 4, wherein: The transfer transistor is a P-type transistor, and The second wiring is formed of N-type polysilicon.

9. The imaging element according to claim 8, wherein: The electrode is formed of N-type polysilicon, and The second wiring for connecting the plurality of electrodes to the first wiring leading to the reference potential line via one contact portion is formed of P-type polysilicon.

10. The imaging element according to claim 1 or 2, wherein: The second wiring is formed to include tungsten.

11. The imaging element according to claim 1 or 2, wherein: The second wiring is arranged in an insulating region formed between a first semiconductor region of the second substrate and a second semiconductor region of the second substrate.

12. The imaging element according to claim 1 or 2, wherein: The second wiring is arranged between the second element and the first wiring.

13. An electronic device comprising: The imaging element according to any one of claims 1 to 12; an optical system that guides incident light to the imaging element; as well as A processing unit processes the signal output from the imaging element.

Images