Electronic packaging and method of manufacturing the same

Abstract

An electronic package and a method for manufacturing the same include: a first supporting structure having a first circuit layer, a packaging module disposed on the first supporting structure and electrically connected to the first circuit layer, a first electronic component disposed on the first supporting structure and electrically connected to the first circuit layer, and a second electronic component stacked on the first electronic component and electrically connected to the first electronic component. By stacking the first electronic component and the second electronic component, the surface area of ​​the first supporting structure occupied by the electronic components is reduced, so that there is enough space to place the packaging module.

Description

Technical Field

[0001] The invention relates to a semiconductor packaging process, and in particular to an electronic packaging component and a manufacturing method thereof. Background Art

[0002] With the development of the electronics industry, today's electronic products have tended to be designed to be thin, light, short and with diversified functions. Semiconductor packaging technology has also developed different packaging types. In order to meet the needs of high integration, miniaturization and high circuit performance of semiconductor devices, flip chip bonding packaging technology has been developed.

[0003] Flip chip packaging technology is a method of forming multiple metal bumps on the active surface of a chip (or other semiconductor structure) so that the active surface of the chip can be electrically connected to an external electronic device or a packaging substrate through the metal bumps. This design can significantly reduce the volume of the overall package.

[0004] like Figure 1A and Figure 1B As shown, in the manufacturing process of a conventional flip-chip semiconductor package 1, a semiconductor chip 11 is first bonded to a package substrate 10 via a plurality of solder bumps 13, and then an underfill 12 is formed between the semiconductor chip 11 and the package substrate 10 to cover the solder bumps 13. Afterwards, a plurality of solder balls 14 are implanted on the lower side of the package substrate 10 to be connected to a computing mainboard (major board) 8 of an electronic product.

[0005] However, it is known that in the semiconductor package 1, if many semiconductor chips 11 need to be arranged horizontally on the surface of the package substrate 10 at the same time, too much surface area of ​​the package substrate 10 will be occupied, so there will not be enough space to place other package modules. On the other hand, if the surface area of ​​the package substrate 10 is enlarged, the volume of the semiconductor package 1 will be forced to increase, resulting in the semiconductor package 1 not meeting the trend of development of light, thin and short.

[0006] In addition, the package substrate 10 is a general organic substrate or core substrate, which is limited by the manufacturing process and can only produce circuits with a single line width / line spacing specification, so it is difficult to simultaneously meet the different circuit specifications required by different electronic components. For example, a miniaturized functional chip needs to be configured on a circuit with a smaller line width / line spacing specification, and a power socket and a ground socket need to be formed on a circuit with a wider line width / line spacing specification.

[0007] Therefore, how to overcome the various problems of the above-mentioned known technologies has become a topic that needs to be solved urgently. Summary of the invention

[0008] In view of the above-mentioned defects of the prior art, the present invention provides an electronic package and a manufacturing method thereof, which are beneficial to reducing the volume of electronic products using the electronic package.

[0009] The electronic package of the present invention includes: a first supporting structure, which is defined by a first surface and a second surface relative to each other and has a first circuit layer; a packaging module, which is configured on the first surface of the first supporting structure and electrically connected to the first circuit layer; a first electronic component, which is configured on the first surface of the first supporting structure and electrically connected to the first circuit layer; and a second electronic component, which is stacked on the first electronic component and electrically connected to the first electronic component.

[0010] The present invention also provides a method for manufacturing an electronic package, which includes: providing a first supporting structure, which has a first circuit layer and defines a first surface and a second surface relative to each other; and configuring a packaging module, a first electronic component and a second electronic component on the first surface of the first supporting structure, wherein the packaging module and the first electronic component are electrically connected to the first circuit layer, and the second electronic component is stacked on the first electronic component and electrically connected to the first electronic component.

[0011] In the aforementioned electronic package and its manufacturing method, the packaging module includes: a second supporting structure having a second circuit layer, which is arranged on the first surface of the first supporting structure via a plurality of conductors, and the plurality of conductors electrically connect the first circuit layer and the second circuit layer; at least one functional electronic component, which is arranged on the second supporting structure and electrically connected to the second circuit layer; and a packaging layer, which covers the functional electronic component. For example, the circuit specifications of the first circuit layer are different from the circuit specifications of the second circuit layer. Alternatively, the line width / line spacing of the first circuit layer is greater than the line width / line spacing of the second circuit layer.

[0012] In the aforementioned electronic package and its manufacturing method, the first electronic element is electrically connected to the first circuit layer via a welding wire.

[0013] In the aforementioned electronic package and its manufacturing method, the second electronic component is electrically connected to the first electronic component via a conductive bump.

[0014] The aforementioned electronic package and its manufacturing method further include forming a coating layer on the first surface of the first supporting structure so that the coating layer covers the first electronic component and the second electronic component. For example, a portion of the surface of the second electronic component is exposed to the coating layer. Alternatively, the coating layer also covers the packaging module.

[0015] The aforementioned electronic package and its manufacturing method further include forming a plurality of conductive elements on the second surface of the first supporting structure, and the plurality of conductive elements are electrically connected to the first circuit layer.

[0016] From the above, it can be seen that in the electronic package and the manufacturing method of the present invention, the first electronic component and the second electronic component are mainly stacked to reduce the area of ​​the first surface of the first supporting structure occupied by the electronic component. Therefore, compared with the known technology, the electronic package of the present invention not only has enough space to place the packaging module, but also helps to reduce the volume of the electronic product using the electronic package, so that the electronic product meets the development trend of being light, thin and short.

[0017] In addition, by forming the first circuit layer and the second circuit layer with two circuit specifications, the functional electronic components of the miniaturized chip specifications can be electrically connected to the first circuit layer through the second circuit layer.

[0018] In addition, the manufacturing method of the present invention can make the first circuit layer into the line width / line spacing required for the power contact and the ground contact, so that the first electronic component can be electrically connected to the first circuit layer without making all the circuits into the line width / line spacing like the second circuit layer. Therefore, compared with the single circuit specification of the known technology, the manufacturing method of the present invention is more cost-effective.

[0019] In addition, the first electronic component and the second electronic component are electrically connected to each other in a "working surface contact" manner to shorten the electrical transmission path, so the electronic package of the present invention can increase the signal transmission speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1A to Figure 1B The invention is a cross-sectional view showing a method for manufacturing a flip-chip semiconductor package.

[0021] FIG. 2A to FIG. 2E It is a cross-sectional schematic diagram of the method for manufacturing the electronic package of the present invention.

[0022] Figure 2C 'for Figure 2C A cross-sectional schematic diagram of another process of FIG.

[0023] Figure 2E 'and Figure 2E "for Figure 2E Schematic cross-sectional view of other embodiments.

[0024] Description of Reference Numerals

[0025] 1 semiconductor package 10 package substrate

[0026] 11 semiconductor chip 12 primer

[0027] 13 Solder bump 14 Solder ball

[0028] 2,2',2” Electronic Package 2a Package Module

[0029] 20 first supporting structure 20a first surface

[0030] 20b Second surface 200 Insulation layer

[0031] 201 first circuit layer 21 second bearing structure

[0032] 210 insulator 211 second circuit layer

[0033] 22 Functional electronic components 220 Conductive bumps

[0034] 23 Packaging layer 24 Conductor

[0035] 240 Binding material 25 First electronic component

[0036] 25a, 26a Active surface 25b, 26b Non-active surface

[0037] 250,250',260 Electrode pad 251 Adhesive material

[0038] 26 Second electronic component 27a Bonding wire

[0039] 27b Conductive bump 28 Covering layer

[0040] 28a surface 29 conductive element

[0041] 8. Operation motherboard 9. Support member. DETAILED DESCRIPTION

[0042] The following describes the implementation of the present invention through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0043] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions under which the present invention can be implemented, so they have no substantial technical significance. Any structural modification, change in proportional relationship, or adjustment in size should still fall within the scope of the technical contents disclosed by the present invention without affecting the effects and purposes that can be achieved by the present invention. At the same time, the terms such as "first", "second", and "one" cited in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. Changes or adjustments in their relative relationships should also be regarded as the scope of the implementation of the present invention without substantially changing the technical contents.

[0044] FIG. 2A to FIG. 2E It is a cross-sectional schematic diagram of a method for manufacturing an electronic package 2 of the present invention.

[0045] like Figure 2AAs shown, a first bearing structure 20 is provided. For example, the first bearing structure 20 is disposed on a support member 9 .

[0046] In the present embodiment, the first supporting structure 20 is in the form of a full-page substrate, that is, the full-page substrate includes a plurality of substrate units. The first supporting structure 20 is, for example, a package substrate having a core layer and a circuit structure or a coreless circuit structure, which has a first surface 20a and a second surface 20b opposite to each other, and the circuit structure includes at least one insulating layer 200 and at least one first circuit layer 201 combined with the insulating layer 200, such as at least one fan-out type redistribution layer (RDL). It should be understood that the first supporting structure 20 can also be other chip-carrying plates, such as a lead frame, a wafer, or other carriers with metal routing, etc., and is not limited to the above.

[0047] In the present embodiment, the first supporting structure 20 may be manufactured in a variety of process methods. For example, a circuit layer may be manufactured by a wafer process, and silicon nitride or silicon oxide may be formed by chemical vapor deposition (CVD) as an insulating layer. Alternatively, a circuit layer may be formed by a general non-wafer process method, that is, a low-cost polymer dielectric material may be used as an insulating layer, such as polyimide (PI), polybenzoxazole (PBO), prepreg (PP), molding compound, photosensitive dielectric layer or other materials, etc., which are formed by coating.

[0048] In addition, the circuit specifications of the first circuit layer 201 are that the line width and line spacing (L / S) are greater than 2 micrometers (um).

[0049] In addition, the support member 9 is a glass plate, a wafer plate or other appropriate plates.

[0050] like Figure 2B As shown, a packaging module 2 a is disposed on the first surface 20 a of the first supporting structure 20 , and the packaging module 2 a is electrically connected to the first circuit layer 201 .

[0051] In this embodiment, the packaging module 2a includes a second supporting structure 21, at least one functional electronic component 22 arranged on the second supporting structure 21, and a packaging layer 23 covering the functional electronic component 22, and the second supporting structure 21 is arranged on the first surface 20a of the first supporting structure 20 via a plurality of conductors 24 and is electrically connected to the first circuit layer 201 via the conductors 24.

[0052] The second supporting structure 21 is, for example, a package substrate with a core layer and a circuit structure or a coreless circuit structure, which includes an insulator 210 and a second circuit layer 211 (such as at least one fan-out type redistribution circuit layer (RDL)) combined with the insulator 210. It should be understood that the second supporting structure 21 can also be other chip-carrying plates, such as a lead frame, a wafer, or other carriers with metal routing, etc., and is not limited to the above. Specifically, the second supporting structure 21 has many process methods. For example, the circuit layer can be made by a wafer process, and silicon nitride or silicon oxide can be formed by chemical vapor deposition (CVD) as an insulating layer; or, the circuit layer can be formed by a general non-wafer process, that is, a low-cost polymer dielectric material is used as an insulator, such as polyimide (PI), poly(p-oxadiazole) (PBO), prepreg (PP), packaging colloid, photosensitive dielectric layer or others, etc., which are formed by coating.

[0053] In addition, the circuit specifications of the first circuit layer 201 are different from those of the second circuit layer 211. For example, the second circuit layer 211 is manufactured using a redistribution layer (RDL) process, and its line width / line spacing is less than or equal to 2 um, so the line width / line spacing of the first circuit layer 201 is greater than the line width / line spacing of the second circuit layer 211.

[0054] The functional electronic component 22 is an active component, a passive component or a combination thereof, wherein the active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor and an inductor. For example, the functional electronic component 22 is a semiconductor chip, which can be disposed on the upper side of the second supporting structure 21 in a flip chip manner via a plurality of conductive bumps 220 such as solder materials, metal pillars or other materials and electrically connected to the second circuit layer 211; or, the functional electronic component 22 can be electrically connected to the second circuit layer 211 in a wire bonding manner via a plurality of welding wires; or, the functional electronic component 22 can directly contact the second circuit layer 211.

[0055] The packaging layer 23 also covers the conductive bumps 220, and the packaging layer 23 is an insulating material, such as polyimide (PI), dry film, packaging colloid or molding compound such as epoxy, which can be formed on the second supporting structure 21 by lamination, coating or molding. For example, the packaging layer 23 can be exposed (such as Figure 2B) or covers (not shown) the functional electronic component 22.

[0056] The conductor 24 is a metal bump such as a copper column, solder material, metal needle or other conductive structure, which is formed on the lower side of the second supporting structure 21, and a bonding material 240 such as a primer is formed between the first supporting structure 20 and the second supporting structure 21 to cover the conductor 24 and fix the packaging module 2a.

[0057] like Figure 2C As shown, a first electronic component 25 and a second electronic component 26 are disposed on the first surface 20 a of the first supporting structure 20 .

[0058] In this embodiment, the second electronic component 26 is stacked on the first electronic component 25 .

[0059] The first electronic component 25 is an active component, a passive component or a combination thereof, wherein the active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor and an inductor. For example, the first electronic component 25 is a semiconductor chip having an active surface 25a and an inactive surface 25b opposite to each other, wherein the inactive surface 25b is disposed on the first surface 20a of the first supporting structure 20 via an adhesive 251, and is electrically connected to the first circuit layer 201 via a plurality of welding wires 27a on a portion of the electrode pads 250 of the active surface 25a.

[0060] The second electronic component 26 is an active component, a passive component or a combination thereof, wherein the active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor and an inductor. For example, the second electronic component 26 is a semiconductor chip having an active surface 26a and an inactive surface 26b opposite to each other, wherein the active surface 26a is disposed on the active surface 25a of the first electronic component 25, and the electrode pad 260 thereof is electrically connected to the other electrode pads 250' of the first electronic component 25 in a flip chip manner via a plurality of conductive bumps 27b. In other embodiments, the electrode pad 260 of the second electronic component 26 and the electrode pad 250' of the first electronic component 25 can be directly bonded without conductive bumps.

[0061] Therefore, the first electronic component 25 and the second electronic component 26 are stacked on each other in a manner that the active surfaces 25 a and 26 a are in contact with each other.

[0062] In addition, the first electronic component 25 and the second electronic component 26 can be arranged in various ways. Figure 2CAs shown in FIG. 1 , the first electronic component 25 and the second electronic component 26 can be firstly connected to each other and then placed on the first supporting structure 20, and then the wire bonding operation can be performed. Alternatively, the first electronic component 25 and the second electronic component 26 can be arranged in sequence, and the wire bonding operation can be performed before or after the second electronic component 26 is arranged.

[0063] In addition, in other embodiments, the first electronic component 25 may also be electrically connected to the first circuit layer 201 by flip chip, and the second electronic component 26 may also be electrically connected to the first electronic component 25 by wire bonding.

[0064] It should be understood that any form, type or number of electronic components can be connected to the first surface 20a and the second surface 20b of the first supporting structure 20 to enhance its electrical function, and there are many ways to electrically connect the electronic components, which are not limited to the above.

[0065] Similarly, the arrangement sequence of the packaging module 2 a , the first electronic component 25 , and the second electronic component 26 can also be designed according to the requirements, and the sequence of the manufacturing process is not limited to the above.

[0066] like Figure 2D As shown, a coating layer 28 is formed on the first surface 20 a of the first supporting structure 20 , so that the coating layer 28 covers the first electronic component 25 , the second electronic component 26 , the bonding wires 27 a and the conductive bumps 27 b .

[0067] In this embodiment, the coating layer 28 contacts the first surface 20a of the first supporting structure 20, and the material forming the coating layer 28 is an insulating material, such as polyimide (PI), epoxy resin packaging colloid or packaging material, which can be formed by molding.

[0068] In addition, the material forming the coating layer 28 can be the same as or different from the material forming the packaging layer 23 .

[0069] In addition, the second electronic component 26 is not exposed on the surface 28a of the coating layer 28, but part of the coating layer 28 can be removed as needed to expose the inactive surface 26b of the second electronic component 26. For example, a part of the coating layer 28 is removed through a flattening process such as grinding to make the inactive surface 26b of the second electronic component 26 flush with the surface 28a of the coating layer 28. Figure 2E'The electronic package 2' shown. Alternatively, a plurality of openings exposing the second electronic component 26 are formed on the surface 28a of the coating layer 28 by drilling with a laser, for example. Alternatively, after removing part of the material of the coating layer 28, the inactive surface 26b of the second electronic component 26 protrudes from the surface 28a of the coating layer 28. It should be understood that there are many ways to expose the coating layer 28 for the electronic component, and they are not limited to the above.

[0070] In addition, since the packaging module 2a is already provided with the packaging layer 23, the encapsulation layer 28 does not encapsulate the packaging module 2a. Figure 2E ” As shown, the encapsulation layer 28 can also be made to encapsulate the packaging module 2a as required.

[0071] like Figure 2E As shown, the support member 9 is removed to expose the second surface 20b of the first supporting structure 20, and a singulation process can be performed as required to obtain an electronic package 2, and a plurality of conductive elements 29 are formed on the second surface 20b of the first supporting structure 20 for the electronic package 2 to be connected to an electronic device such as a circuit board (not shown).

[0072] In this embodiment, the conductive element 29 is electrically connected to the first circuit layer 201 of the first supporting structure 20, and can be a metal column such as a copper column, a metal bump coated with an insulating block, a solder ball, a solder ball with a core copper ball, or other suitable conductive structures, and there is no special limitation on its shape, such as a cylinder, an elliptical cylinder, or a polygonal cylinder.

[0073] In the manufacturing method of the electronic package 2, 2', 2" of the present invention, the first electronic component 25 and the second electronic component 26 are mainly stacked to reduce the area of ​​the first surface 20a of the first supporting structure 20 occupied by the electronic components. Therefore, compared with the known technology, the electronic package 2, 2', 2" of the present invention not only has enough space to place the packaging module 2a or other discrete components (discrete components) (not shown), but also helps to reduce the volume of the electronic product using the electronic package 2, 2', so that the electronic product meets the development trend of being light, thin and short.

[0074] In addition, through two fan-out type circuit redistribution layer processes (i.e., the first circuit layer 201 and the second circuit layer 211), the miniaturized chip (i.e., the functional electronic component 22 that meets the miniaturized specification requirements) can be electrically connected to the first circuit layer 201 via the second circuit layer 211.

[0075] In addition, the manufacturing method of the present invention manufactures the first circuit layer 201 into the line width / line spacing required for the power contact and the ground contact, so that the first electronic component 25 can be electrically connected to the first circuit layer 201 (line width / line spacing is 2 to 10um) without having to manufacture all circuits into the line width / line spacing of the second circuit layer 211 (which is within 2um). Therefore, compared with the known technology that the line width / line spacing of all circuit layers is within 2um, the manufacturing method of the present invention is more cost-effective.

[0076] In addition, the first electronic component 25 and the second electronic component 26 are electrically connected to each other in a manner of “active surfaces 25a, 26a in contact” to shorten the electrical transmission path. Therefore, compared with the known technology, the electronic package 2, 2', 2" of the present invention can increase the signal transmission speed.

[0077] The present invention further provides an electronic package 2, 2', 2", which includes: a first supporting structure 20 having a first circuit layer 201, a packaging module 2a, a first electronic component 25 and a second electronic component 26.

[0078] The first supporting structure 20 is defined with a first surface 20 a and a second surface 20 b opposite to each other.

[0079] The packaging module 2a is configured on the first surface 20a of the first supporting structure 20 and electrically connected to the first circuit layer 201, wherein the packaging module 2a includes: a second supporting structure 21 having a second circuit layer 211, which is arranged on the first surface 20a of the first supporting structure 20 via a plurality of conductors 24, and the plurality of conductors 24 electrically connect the first circuit layer 201 and the second circuit layer 211; at least one functional electronic component 22, which is configured on the second supporting structure 21 and electrically connected to the second circuit layer 211; and a packaging layer 23, which covers the functional electronic component 22.

[0080] The first electronic component 25 is disposed on the first surface 20 a of the first supporting structure 20 and is electrically connected to the first circuit layer 201 .

[0081] The second electronic component 26 is stacked on the first electronic component 25 and electrically connected to the first electronic component 25 .

[0082] In one embodiment, the circuit specification of the first circuit layer 201 is different from the circuit specification of the second circuit layer 211 .

[0083] In one embodiment, the line width / line spacing of the first circuit layer 201 is greater than the line width / line spacing of the second circuit layer 211 .

[0084] In one embodiment, the first electronic component 25 is electrically connected to the first circuit layer 201 via a plurality of bonding wires 27 a.

[0085] In one embodiment, the second electronic component 26 is electrically connected to the first electronic component 25 via a plurality of conductive bumps 27 b.

[0086] In one embodiment, the electronic package 2, 2', 2" further includes a coating layer 28, which is formed on the first surface 20a of the first supporting structure 20 to cover the first electronic component 25 and the second electronic component 26. For example, the non-active surface 26b of the second electronic component 26 of the electronic package 2' is exposed from the coating layer 28. Alternatively, in the electronic package 2", the coating layer 28 also covers the packaging module 2a.

[0087] In one embodiment, the electronic package 2 , 2 ′, 2 ″ further includes a plurality of conductive elements 29 formed on the second surface 20 b of the first supporting structure 20 and electrically connected to the first circuit layer 201 .

[0088] In summary, the electronic package of the present invention and the method for manufacturing the same mainly stack the first electronic component and the second electronic component to reduce the area of ​​the first surface of the first supporting structure occupied by the electronic component. Therefore, the electronic package of the present invention not only has enough space to place the packaging module, but also helps to reduce the volume of the electronic product using the electronic package, so that the electronic product meets the development trend of being light, thin and short.

[0089] In addition, by forming the first circuit layer and the second circuit layer with two circuit specifications, the functional electronic components of the miniaturized chip specifications can be electrically connected to the first circuit layer through the second circuit layer.

[0090] In addition, the manufacturing method of the present invention is more cost-effective because the first circuit layer is made into the line width / line spacing required for the power contact and the ground contact, so that the first electronic component can be electrically connected to the first circuit layer without having to make all the circuits into the line width / line spacing like the second circuit layer.

[0091] In addition, the first electronic component and the second electronic component are electrically connected to each other in a "working surface contact" manner to shorten the electrical transmission path, so the electronic package of the present invention can increase the signal transmission speed.

[0092] The above embodiments are only used to illustrate the principles and effects of the present invention, and are not used to limit the present invention. Any person skilled in the art may modify the above embodiments without violating the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as listed in the claims.

Claims

1. An electronic package, characterized in that: include: A first supporting structure is defined with a first surface and a second surface opposite to each other and has a first circuit layer; A packaging module, which is disposed on the first surface of the first supporting structure and is electrically connected to the first circuit layer; A first electronic component is disposed on the first surface of the first supporting structure and is electrically connected to the first circuit layer; as well as A second electronic component is stacked on the first electronic component and electrically connected to the first electronic component, In which, the packaging module simultaneously includes a second supporting structure, a packaging layer, a first conductive bump and a functional electronic component, and the first electronic component and the second electronic component are stacked adjacent to each other. The second supporting structure, the first conductive bump and the functional electronic component of the packaging module are stacked in sequence above the first supporting structure. The packaging layer of the packaging module is formed between the second supporting structure and the functional electronic component to cover the first conductive bump. The first conductive bump covered by the packaging layer of the packaging module is formed between the second supporting structure and the functional electronic component to electrically connect the second supporting structure and the functional electronic component. The packaging layer and the first conductive bump formed between the second supporting structure and the functional electronic component of the packaging module ensure that the second supporting structure does not directly contact the functional electronic component.

2. The electronic package according to claim 1, characterized in that: The second supporting structure has a second circuit layer and is disposed on the first surface of the first supporting structure via a plurality of conductors, and the plurality of conductors electrically connect the first circuit layer and the second circuit layer; The functional electronic element is disposed on the second supporting structure and electrically connected to the second circuit layer; as well as The packaging layer also covers the functional electronic component.

3. The electronic package according to claim 2, characterized in that: The circuit specification of the first circuit layer is different from the circuit specification of the second circuit layer.

4. The electronic package according to claim 2, characterized in that: The line width / line spacing of the first circuit layer is greater than the line width / line spacing of the second circuit layer.

5. The electronic package according to claim 1, characterized in that: The first electronic element is electrically connected to the first circuit layer via a bonding wire.

6. The electronic package according to claim 1, characterized in that: The second electronic component is electrically connected to the first electronic component via a second conductive bump.

7. The electronic package according to claim 1, characterized in that: The electronic package also includes a coating layer formed on the first surface of the first supporting structure to cover the first electronic element and the second electronic element.

8. The electronic package according to claim 7, characterized in that: A portion of the surface of the second electronic component is exposed from the covering layer.

9. The electronic package according to claim 7, characterized in that: The covering layer also covers the packaging module.

10. The electronic package according to claim 1, characterized in that The electronic package also includes a plurality of conductive elements formed on the second surface of the first supporting structure and electrically connected to the first circuit layer.

11. A method for manufacturing an electronic package, characterized in that: include: Providing a first supporting structure having a first circuit layer and defining a first surface and a second surface opposite to each other; as well as The packaging module, the first electronic component and the second electronic component are arranged on the first surface of the first supporting structure, wherein the packaging module and the first electronic component are electrically connected to the first circuit layer, and the second electronic component is stacked on the first electronic component and electrically connected to the first electronic component. In which, the packaging module simultaneously includes a second supporting structure, a packaging layer, a first conductive bump and a functional electronic component, and the first electronic component and the second electronic component are stacked adjacent to each other. The second supporting structure, the first conductive bump and the functional electronic component of the packaging module are stacked in sequence above the first supporting structure. The packaging layer of the packaging module is formed between the second supporting structure and the functional electronic component to cover the first conductive bump. The first conductive bump covered by the packaging layer of the packaging module is formed between the second supporting structure and the functional electronic component to electrically connect the second supporting structure and the functional electronic component. The packaging layer and the first conductive bump formed between the second supporting structure and the functional electronic component of the packaging module ensure that the second supporting structure does not directly contact the functional electronic component.

12. The method for manufacturing an electronic package according to claim 11, wherein: The second supporting structure has a second circuit layer and is disposed on the first surface of the first supporting structure via a plurality of conductors, and the plurality of conductors electrically connect the first circuit layer and the second circuit layer; The functional electronic element is disposed on the second supporting structure and electrically connected to the second circuit layer; as well as The packaging layer also covers the functional electronic component.

13. The method for manufacturing an electronic package according to claim 12, characterized in that: The circuit specification of the first circuit layer is different from the circuit specification of the second circuit layer.

14. The method for manufacturing an electronic package according to claim 12, characterized in that: The line width / line spacing of the first circuit layer is greater than the line width / line spacing of the second circuit layer.

15. The method for manufacturing an electronic package according to claim 11, characterized in that: The first electronic element is electrically connected to the first circuit layer via a bonding wire.

16. The method for manufacturing an electronic package according to claim 11, characterized in that: The second electronic component is electrically connected to the first electronic component via a second conductive bump.

17. The method for manufacturing an electronic package according to claim 11, characterized in that: The manufacturing method further comprises forming a coating layer on the first surface of the first supporting structure so that the coating layer covers the first electronic component and the second electronic component.

18. The method for manufacturing an electronic package according to claim 17, characterized in that: A portion of the surface of the second electronic component is exposed from the covering layer.

19. The method for manufacturing an electronic package according to claim 17, characterized in that: The covering layer also covers the packaging module.

20. The method for manufacturing an electronic package according to claim 11, characterized in that: The manufacturing method further includes forming a plurality of conductive elements on the second surface of the first supporting structure, and the plurality of conductive elements are electrically connected to the first circuit layer.

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