A filtering circuit and a filtering method

Abstract

The present invention discloses a filtering circuit and a filtering method, which can filter different types of glitches in a signal without affecting the inherent characteristics of the signal. The filtering circuit includes: an edge detection module, a reset and set module, and an edge delay module. The edge detection module is configured to receive an input signal from the outside and output a first signal and a second signal according to the phase difference between the input signal and the output signal, where the output signal is obtained by passing the input signal through the filtering circuit; the reset and set module is configured to generate a third signal according to the first signal and the second signal; the edge delay module is configured to generate a fourth signal according to the third signal and the input signal, where the fourth signal is obtained by delaying the input signal by a preset time duration and is used to filter the input signal.

Description

Technical Field

[0001] The present invention relates to the field of analog integrated circuits, and in particular, to a filtering circuit and a filtering method. Background Art

[0002] An integrated circuit is a circuit with a specific function obtained by integrating electronic components such as resistors, capacitors, and transistors through semiconductor processes.

[0003] Since electronic components are easily affected by the external environment during operation, such as lightning and power grid fluctuations, the signals generated by the electronic components are prone to glitches. Here, the glitches can be considered as perturbations that affect the frequency and / or amplitude of the signals. Glitches not only affect the normal operation of the integrated circuit, but may also cause damage to the integrated circuit in severe cases. Therefore, it is necessary to filter out the glitches.

[0004] Currently, a method for filtering out glitches is to set a filtering circuit on the signal interaction path, such as a first-order passive RC filtering circuit, a delay circuit, etc., to filter out the glitches. However, the first-order passive RC filtering circuit can only eliminate the positive or negative glitches of the signal, that is, it can only eliminate the unilateral glitches and cannot eliminate the high-frequency glitches; the delay circuit can only eliminate the nanosecond-level delay, which will affect the inherent characteristics of the signal, such as the duty cycle. It can be seen that the current filtering circuits are either only effective for a certain type of glitches or may change the inherent characteristics of the signal during the filtering process. Summary of the Invention

[0005] Embodiments of the present invention provide a filtering circuit and a filtering method, which can filter out different types of glitches in the signal and do not affect the inherent characteristics of the signal.

[0006] In a first aspect, an embodiment of the present invention provides a filtering circuit, which includes an edge detection module, a reset-set module, and an edge delay module. The output end of the edge detection module is connected to the input end of the reset-set module, and the output end of the reset-set module is connected to the input end of the edge delay module; wherein,

[0007] The edge detection module is configured to receive an input signal from the outside and output a first signal and a second signal according to the phase difference between the input signal and the output signal, where the output signal is the input signal obtained after passing through the filtering circuit;

[0008] The reset-set module is configured to generate a third signal according to the first signal and the second signal;

[0009] The edge delay module is configured to generate a fourth signal according to the third signal and the input signal. The fourth signal is obtained by delaying the input signal by a preset duration and is used to filter the input signal.

[0010] Optionally, the edge delay module includes a positive edge delay module and a negative edge delay module, where:

[0011] When the third signal is at a low level and the input signal is at a high level, the edge delay module generates the fourth signal through the positive edge delay module;

[0012] When the third signal is at a low level and the input signal is at a low level, the edge delay module generates the fourth signal through the negative edge delay module.

[0013] Optionally, the positive edge delay module and the negative edge delay module include capacitors, and the value of the capacitors is determined according to the preset duration, and the preset duration is greater than the pulse width of the signal glitch.

[0014] Optionally, the level of the first signal changes from low to high, the level of the second signal is at a low level, and the level of the third signal is at a low level; or,

[0015] The level of the second signal changes from high to low, the level of the first signal is at a high level, and the level of the third signal is at a low level.

[0016] Optionally, the circuit further includes a channel selection module, the input end of the channel selection module is connected to the output end of the reset-set module, and the output end of the channel selection module is connected to the input end of the edge detection module;

[0017] The channel selection module is configured to select the output signal of the reset-set module or the edge delay module from the reset-set module and the edge delay module according to the third signal.

[0018] Optionally, the channel selection module includes a first NOT gate and a transmission gate. The input end of the first NOT gate is configured to receive the third signal, the output end of the first NOT gate is connected to the first input end of the transmission gate, the second input end of the transmission gate is configured to receive the third signal, the third input end of the transmission gate is connected to the output end of the delay unit, and the output end of the transmission gate is connected to the reset-set module. Wherein, when the third signal is at a high level, the transmission gate is in a closed state, and when the third signal is at a low level, the transmission gate is in an open state.

[0019] Optionally, the edge detection module includes a NAND gate and a first NOR gate. The first input terminal of the NAND gate is connected to the first input terminal of the first NOR gate and receives the output signal. The second input terminal of the NAND gate and the second input terminal of the first NOR gate are used to receive the input signal. The output terminal of the NAND gate is used to output the first signal, and the output terminal of the first NOR gate is used to output the second signal.

[0020] Optionally, the reset - set module includes a first sub - module and a second sub - module. The first sub - module is used to generate the third signal according to the first signal and the second signal, and the second sub - module is used to charge or discharge the capacitor according to the first signal and the second signal.

[0021] Optionally, the first sub - module includes a second NOT gate, a second NOR gate, and a third NOT gate. The input terminal of the second NOT gate is connected to the output terminal of the NAND gate. The output terminal of the second NOT gate is connected to the first input terminal of the second NOR gate. The second input terminal of the second NOR gate is connected to the output terminal of the first NOR gate. The output terminal of the second NOR gate is connected to the input terminal of the third NOT gate. The output terminal of the third NOT gate is used to output the third signal.

[0022] Optionally, the second sub - module includes a PMOS and an NMOS. The output terminal of the PMOS is connected to the power supply. The second input terminal of the PMOS is connected to the output terminal of the NAND gate. The first input terminal of the PMOS is connected to the first input terminal of the NMOS. The second input terminal of the NMOS is connected to the output terminal of the first NOR gate. The output terminal of the NMOS is grounded.

[0023] In a second aspect, an embodiment of the present invention provides a filtering method. The method is applied to the filtering circuit as described in the first aspect. The method includes:

[0024] The edge detection module generates and outputs a first signal and a second signal according to the phase difference between the received input signal and the output signal. The output signal is obtained by passing the input signal through the filtering circuit;

[0025] The reset - set module generates a third signal according to the first signal and the second signal;

[0026] The edge delay module generates a fourth signal according to the third signal and the input signal. The fourth signal is obtained by delaying the input signal by a preset time duration and is used to filter the input signal.

[0027] Optionally, the edge delay module includes a positive edge delay module and a negative edge delay module. The edge delay module generates a fourth signal according to the third signal and the input signal, including:

[0028] When the edge delay module determines that the third signal is at a low level and the input signal is at a high level, it starts the positive edge delay module to generate the fourth signal;

[0029] When the edge delay module determines that the third signal is at a low level and the input signal is at a low level, it starts the negative edge delay module to generate the fourth signal.

[0030] Optionally, the circuit further includes a channel selection module. The input end of the channel selection module is connected to the output end of the reset - set module, and the output end of the channel selection module is connected to the input end of the edge detection module. The method further includes:

[0031] The channel selection module selects the output signal of the reset - set module or the edge delay module from the reset - set module and the edge delay module according to the third signal.

[0032] The filtering circuit provided by the present invention can filter the input signal. The edge detection module therein can determine whether the glitch of the input signal is positive or negative according to the phase difference between the input signal and the output signal, and generate a first signal and a second signal. The first signal and the second signal can be used by the reset - set module to generate a third signal to determine the turn - on and turn - off of the edge delay module. The edge delay module can generate a fourth signal for filtering the glitch of the input signal, and the fourth signal can be a delayed signal of the input signal. In this way, no matter whether the glitch of the input signal is a positive glitch or a negative glitch, as long as the pulse width of the glitch is less than the pulse width of the fourth signal, it can be filtered by the fourth signal. That is, the filtering circuit provided by the embodiments of the present invention can filter different types of glitches in the input signal. And the fourth signal will produce a delay effect whether at the positive edge or the negative edge of the input signal, even if the input signal is delayed at both the positive edge and the negative edge, so it will not affect the inherent characteristics of the input signal. Description of the Drawings

[0033] Figure 1 It is a schematic diagram of the glitch type in an integrated circuit provided by the embodiment of the present invention;

[0034] Figure 2 It is a schematic framework diagram of a filtering circuit provided by the embodiment of the present invention;

[0035] Figure 3 It is a schematic diagram of the specific logic circuit of a filtering circuit provided by the embodiment of the present invention;

[0036] Figure 4 Equivalent circuit diagram of a filtering circuit provided by an embodiment of the present invention;

[0037] Figure 5 Equivalent circuit diagram of a filtering circuit provided by an embodiment of the present invention;

[0038] Figure 6 Equivalent circuit diagram of a capacitor provided by an embodiment of the present invention;

[0039] Figure 7 Filtering schematic diagram of a filtering circuit provided by an embodiment of the present invention;

[0040] Figure 8 Flow schematic diagram of a filtering method provided by an embodiment of the present invention. Detailed implementation manners

[0041] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings.

[0042] Glitches can be roughly divided into four categories: low-frequency positive glitches, low-frequency negative glitches, high-frequency positive glitches, and high-frequency negative glitches. Please refer to Figure 1 , Figure 1 Taking the input signal (SIG_IN) being divided into five stages in time as an example, these five stages are the first stage, the second stage, the third stage, the fourth stage, and the fifth stage. Among them, the input signal in the first stage has no glitches, the input signal in the second stage has low-frequency positive glitches, the input signal in the third stage has low-frequency negative glitches, the input signal in the fourth stage has high-frequency positive glitches, and the input signal in the fifth stage has high-frequency negative glitches. Figure 1 Only for the purpose of illustrating the above four types of glitches, the input signal may have one or more of the above types of glitches. To ensure the normal operation of the integrated circuit, currently the following four methods are usually adopted to filter glitches.

[0043] The first method is to set an analog low-pass filter, such as a first-order passive RC filter, on the signal interaction path, and the integration effect of the capacitor on the charge can be used to eliminate glitches;

[0044] The second method is to set a D flip-flop on the signal interaction path, sample the input signal using the edge of the clock signal, and capture the input signal only when the edge arrives. Since the probability of disturbance of the input signal at the edge moment is relatively low, the filtering effect is achieved;

[0045] The third method is to change the signal encoding method. For example, convert a set of data from binary encoding to Gray code encoding, so that only one bit changes between any two adjacent code groups, to reduce the spike pulse current generated during digital state switching, thereby reducing logical errors during state switching to achieve a filtering effect;

[0046] The fourth method is to set a delay unit on the signal interaction path. This delay unit is used to delay the input signal, and then perform logical operations such as "AND" and "OR" to achieve glitch elimination.

[0047] The above-mentioned first method can only eliminate unilateral glitches, that is, it can only eliminate positive glitches or negative glitches at a time, and cannot eliminate high-frequency glitches; the second method requires the participation of a high-frequency clock signal to complete filtering; the third method is only applicable to data composed of multiple signals and cannot filter glitches of a single signal; the fourth method can only eliminate glitches at the nanosecond level and will change the original inherent characteristics of the signal, such as period, duty cycle, etc. It can be seen that the current four methods for filtering glitches are either only effective for a certain type of glitch or may change the inherent characteristics of the signal during the filtering process.

[0048] In view of this, the embodiments of the present invention provide a filtering circuit and a filtering method. This filtering circuit can be used to filter different types of glitches in the input signal and does not change the inherent characteristics of the input signal. The filtering circuit and filtering method provided by the embodiments of the present invention will be introduced in detail below with reference to the accompanying drawings of the specification.

[0049] Please refer to Figure 2 , which is a schematic framework diagram of a filtering circuit provided by an embodiment of the present invention. The filtering circuit provided by the embodiment of the present invention includes an edge detection module 201, an edge delay module 202, and a reset and set module 203. The output end of the edge detection module 201 is connected to the input end of the reset and set module 203, and the output end of the reset and set module 203 is connected to the input end of the edge delay module 202.

[0050] The filtering circuit provided by the embodiment of the present invention can be used to filter glitches of a signal. For the sake of convenience of description, the signal for which glitches need to be filtered is called an input signal, such as Figure 2 the signal SIG_IN in. This input signal is input to the input end of the filtering circuit, and after the filtering circuit filters out the glitches, the filtered signal is output. For the sake of convenience of description, the signal with glitches filtered out output at the output end of the filtering circuit is called an output signal hereinafter, such as Figure 2The signal SIG_OUT therein. In an embodiment of the present invention, the input signal is input to the input terminal of the input signal edge detection module 201. The edge detection module 201 can be used to detect the edge polarity of the input signal, that is, whether the glitch of the input signal is a positive glitch or a negative glitch. The output signal output by the input signal through the filter circuit before can be used by the edge detection module 201 to determine the edge polarity of the current input signal. That is, the output signal output by the input signal through the filter circuit before is also input to the input terminal of the edge detection module 201. That is, the input terminal of the edge detection module 201 receives the input signal and the output signal. The edge detection module 201 can determine the edge polarity of the input signal according to the phase difference between the input signal and the output signal, that is, determine whether the edge of the incoming input signal is a positive edge or a negative edge. When the edge detection module 201 detects that the phase difference between the input signal and the output signal is negative, it can be determined that there is a negative edge in the input signal, then the negative edge detection PDT_N (Negative Pulse Detect) signal output by the edge detection module 201 will generate a jump; when the edge detection module 201 detects that the phase difference between the input signal and the output signal is positive, it can be determined that there is a positive edge in the input signal, then the PDT_P (Positive Pulse Detect) signal output by the edge detection module 201 will generate a jump. For the convenience of description, hereinafter, the negative edge detection PDT_N (Negative Pulse Detect) signal is referred to as the first signal, and the positive edge detection PDT_P (Positive Pulse Detect) signal is referred to as the second signal.

[0051] The input terminal of the reset and set module 203 is connected to the output terminal of the edge detection module 201, and the output terminal of the reset and set module 203 is connected to the input terminal of the edge delay module 202. The edge detection module 201 outputs the first signal and the second signal to the reset and set module 203. The reset and set module 203 can determine whether to perform reset or set according to the first signal and the second signal. If both the first signal and the second signal are at a high level, the reset and set module 203 is in a reset state; if both the first signal and the second signal are at a low level, the reset and set module 203 is in a set state.

[0052] When the first signal is at a high level and the second signal is at a low level, the reset - set module 203 neither resets nor sets, but instead enables the edge - delay module 202. It can also be understood that the reset - set module 203 can also determine whether to enable or disable the edge - delay module 202 based on the first signal and the second signal. Exemplarily, the reset - set module 203 can generate a PDT (Pulse Detect) signal according to the first signal and the second signal. This PDT signal is hereinafter referred to as the third signal, and this third signal can determine whether to enable the edge - delay module 202. For example, when the third signal is at a high level, the edge - delay module 202 is in a closed state; when the third signal is at a low level, the edge - delay module 202 is in an open state. In this way, when it is determined that the glitches of the input signal need to be filtered, the edge - delay module 202 is enabled; if it is determined that the glitches of the input signal do not need to be filtered, the edge - delay module 202 is disabled, so that the edge - delay module 202 does not need to be continuously enabled, wasting electrical energy.

[0053] The edge - delay module 202 can include a positive - edge - delay module and a negative - edge - delay module. The positive - edge - delay module is used to filter the positive glitches of the input signal, and the negative - edge - delay module is used to filter the negative glitches of the input signal. The edge - delay module 202 can determine whether to enable the edge - delay module 202 according to the third signal and the input signal. Among them, the input end of the edge - delay module 202 is also connected to a signal source that provides an input signal externally.

[0054] When the third signal is at a low level and the input signal is at a high level, the positive - edge - delay module in the edge - delay module 202 is determined to be enabled and the negative - edge - delay module is determined to be disabled; when the third signal is at a low level and the input signal is at a high level, the edge - delay module 202 determines that the negative - edge - delay module is enabled and the positive - edge - delay module is disabled. Exemplarily, the edge - delay module 202 can be used to generate a signal for filtering the glitches of the input signal, and the input signal is filtered through this signal. For example, the edge - delay module 202 can generate a fourth signal. The fourth signal can be a delayed signal of the input signal, that is, the fourth signal is a signal obtained by delaying the input signal by a preset time duration. Assuming that the preset time duration is Td, then the fourth signal can filter the glitches of the input signal with a pulse width less than Td, while retaining the signal with a pulse width greater than Td, and output it after Td. The output signal is as Figure 2 the signal DLY_OUT in, hereinafter referred to as the output signal. In this way, both the glitches of the input signal can be filtered and the inherent characteristics of the input signal will not be changed.

[0055] Considering that sometimes there are no glitches in the input signal, in this case, the edge - delay module 202 can be not enabled, that is, the input signal is directly output. For this reason, please continue to refer to Figure 2, the filter circuit provided by the embodiment of the present invention may further include a channel selection module 204. The input end of the channel selection module 204 is connected to the output end of the reset and set module 203, and the output end of the channel selection module 204 is connected to the input end of the edge detection module 201. The channel selection module 204 can select the reset and set module 203 or the edge delay module 202 from the reset and set module 203 and the edge delay module 202 according to the third signal to output an output signal. That is, according to the third signal, it can be determined whether the input signal needs to filter out glitches. If the glitches do not need to be filtered out, the output from the reset and set module 203 is selected. At this time, the output signal SIG_OUT of the filter circuit can be considered as the output signal SH_OUT of the reset and set module 203. If the glitches need to be filtered out, the input signal is selected to be output after filtering out glitches via the edge delay module 202. At this time, the output signal SIG_OUT of the filter circuit can be considered as the output signal DLY_OUT of the edge delay module 202. In this way, when the reset and set module 203 determines that the edge delay module 202 does not need to be turned on, and at the same time the channel selection module 204 determines to select the output from the reset and set module 203, the two work together to output the signal in a timely manner.

[0056] For ease of understanding, the following will introduce each of the above-provided module circuits in detail with reference to the accompanying drawings.

[0057] Please refer to Figure 3 , which is a schematic diagram of the specific logic circuit of a filter circuit provided by an embodiment of the present invention. The edge detection module 201 includes a NAND gate nand1 and a NOR gate nor1. For ease of description, in the following text, the NAND gate nand1 is referred to as the first NAND gate, and the NOR gate nor1 is referred to as the first NOR gate. The first input end of the first NAND gate is connected to the first input end of the first NOR gate and receives the output signal. The second input end of the first NAND gate and the second input end of the first NOR gate are used to receive the input signal. The output end of the first NAND gate is used to output the first signal, and the output end of the first NOR gate is used to output the second signal. When the level of the first signal changes from low to high and the level of the second signal remains low, it can be considered that there is a negative edge in the input signal. When the level of the first signal remains high and the level of the second signal changes from high to low, it can be considered that there is a positive edge in the input signal.

[0058] The reset - set module 203 includes an inverter inv1, a nor - gate nor2, and an inverter inv2. For the convenience of distinction, hereinafter, the inverter inv1 is referred to as the first inverter, the nor - gate nor2 is referred to as the second nor - gate, and the inverter inv2 is referred to as the second inverter. The first inverter, the second nor - gate, and the second inverter are connected in sequence. Among them, the input terminal of the first inverter is connected to the output terminal of the first nand - gate, the output terminal of the first inverter is connected to the first input terminal of the second nor - gate, the second input terminal of the second nor - gate is connected to the output terminal of the first or - gate, the output terminal of the second nor - gate is connected to the second inverter, and the output terminal of the second inverter outputs a third signal to actuate or turn off the edge - delay module 202.

[0059] In some embodiments, the reset - set module 203 may further include a positive - channel metal - oxide - semiconductor (PMOS) transistor and a negative - channel - metal - oxide - semiconductor (NMOS) transistor, which are used to control whether the reset - set module 203 performs reset or set. In Figure 3 PM6 is used to denote the PMOS, and NM4 is used to denote the NMOS. The output terminal of PM6 is connected to the power supply, the first input terminal of PM6 is connected to the first input terminal of the fourth NM4, the second input terminal of PM6 is connected to the output terminal of the first nand - gate, the second input terminal of NM4 is connected to the output terminal of the first or - gate, and the output terminal of NM4 is grounded. As Figure 3 shown, when both the first signal and the second signal are at low level and PM6 is in the conducting state and NM4 is in the off state, the output SH_OUT of the reset - set module 203 is in the set state. When both the PDT_N signal and the PDT_P signal are at high level, PM6 is in the off state and NM4 is in the conducting state, and the output SH_OUT of the reset - set module 203 is in the reset state.

[0060] The edge delay module 202 includes five PMOS transistors, three NMOS transistors, and a capacitor C1. The five PMOS transistors are PM1, PM2, PM3, PM4, and PM5 respectively, and the three NMOS transistors are NM1, NM2, and NM3 respectively. The source of the PMOS transistor is defined as the first input terminal, the gate is defined as the second input terminal, and the drain is defined as the output terminal. The drain of the NMOS is defined as the first input terminal, the gate is defined as the second input terminal, and the source is defined as the output terminal. The current provided by the edge delay module 202 is called the bias current IBIAS. The bias current IBIAS is input to the first input terminal of PM1. The second input terminal of PM1 is connected to the output terminal of the reset and set module 203, and determines whether PM1 is turned on according to the third signal. For example, when the third signal is at a low level, PM1 is in the on state; when the third signal is at a high level, PM1 is in the off state. The output terminal of PM1 is connected to the first input terminal and the second input terminal of PM2, and the output terminal of PM1 is also connected to the second input terminal of PM3 and the second input terminal of PM4. The output terminals of PM2, PM3, and PM4 are connected to the power supply VDD. The first input terminal of PM4 is connected to the output terminal of PM5. The second input terminal of PM5 is connected to the second input terminal of NM3. The first input terminal of PM5 is connected to the first input terminal of NM3. The output terminal of NM3 is connected to the first input terminal of NM2. The first input terminal of PM3 is connected to the first input terminal of NM1, the second input terminal of NM1, and the second input terminal of NM2. The output terminals of NM1 and NM2 are grounded together.

[0061] The edge delay module 202 can filter out the positive glitches of the input signal and can also filter out the negative glitches of the input signal. The module circuit used to filter out the positive glitches of the input signal is called the positive edge delay module, and the module circuit used to filter out the negative glitches of the input signal is called the negative edge delay module. In Figure 3Among them, the circuit composed of PM1, PM2, PM4, PM5, and capacitor C1 is a positive edge delay module; the circuit composed of PM1, PM2, PM3, NM1, NM2, NM3, and capacitor C1 is a negative edge delay module. In addition, the second input terminals of PM5 and NM3 are both connected to the NOT gate inv4, that is, the fourth NOT gate. The input signal can be input to the input terminal of the fourth NOT gate and output to PM5 and NM3 through the fourth NOT gate, so that the edge delay module 202 can determine whether to turn on the edge delay module 202 according to the input signal and the third signal, that is, turn on the positive edge delay module or the negative edge delay module. Exemplarily, when the third signal is at a low level and the input signal is at a high level, the edge delay module 202 can generate the above-mentioned fourth signal through the positive edge delay module. The pulse width of the fourth signal is a preset duration. When the pulse width of the positive glitch is less than the preset duration, the positive glitch can be filtered out. When the third signal is at a low level and the input signal is at a low level, the edge delay module 202 can generate the fourth signal through the negative edge delay module. The pulse width of the fourth signal is a preset duration. When the pulse width of the negative glitch is less than the preset duration, the negative glitch can be filtered out.

[0062] In addition, PM1, PM2, PM3, NM1, and NM2 can also play a current mirroring role, mirroring current from the bias circuit IBIAS in a certain proportion. When it is necessary to filter out glitches with different pulse widths, for example, from the nanosecond (ns) level to the microsecond (us) level, the purpose can be achieved by modifying the mirror current ratio of the current sources PM1, PM2, PM3, NM1, and NM2 or changing the parameters of capacitor C1.

[0063] As an alternative solution, please refer to Figure 4 , Figure 3 The mirror current source composed of PM2, PM3, PM4, NM1, and NM2 described in can be replaced by resistors R1 and R2 respectively. Since the current mirror branch is removed, PM1 originally in this branch also needs to be equivalently designed, and the equivalent function can be realized by a combination of AND gates, NAND gates, and NOR gates. When the third signal is at a high level, both PM5 and NM3 are turned off, and the charging and discharging path of capacitor C1 is turned off. When the third signal is at a low level, the charging and discharging of capacitor C1 by the current source is controlled by the input signal SIG_IN. Therefore, it is equivalent to the original circuit in terms of logical function. However, resistors are greatly affected by temperature in CMOS process manufacturing, so there are restrictions on the materials of the resistors, and resistors with less temperature effect should be selected for replacement.

[0064] As another alternative solution, please refer to Figure 5 , different from Figure 4 in that the resistors used for charging and discharging, such as Figure 5R1 therein is connected to the second input terminals of PM5 and NM3.

[0065] As another alternative solution, please refer to Figure 6 , the source, drain, and substrate of the MOS transistor can be shorted together. Utilizing the dielectric characteristics of the gate oxide layer, when the voltage between the gate and source exceeds the turn-on threshold of the MOS transistor, a capacitor is formed between the gate and substrate of the MOS transistor. This MOS capacitor can be implemented using a PMOS transistor or an NMOS transistor.

[0066] The channel selection module 204 includes an inverter inv3 and a transmission gate tg1. For ease of distinction, the inverter inv3 will be referred to as the third inverter and the transmission gate tg1 will be referred to as the first transmission gate in the following text. The input terminal of the third inverter is used to receive the PDT signal. The output terminal of the third inverter is connected to the first input terminal of the first transmission gate. The second input terminal of the first transmission gate is used to receive the PDT signal. The third input terminal of the first transmission gate is connected to the output terminal of the edge delay module 202 for receiving the filtered input signal. The output terminal of the first transmission gate is connected to the reset and set module 203. The first transmission gate determines whether to turn on the first transmission gate according to the PDT signals received by the first input terminal and the second input terminal. When the PDT signal is at a high level, the first transmission gate is in the off state, or when the PDT signal is at a low level, the first transmission gate is in the on state. If the first transmission gate is in the on state, the output terminal of the first transmission gate is used to output the filtered input signal DLY_OUT, then the output of the filter circuit is the filtered input signal; if the first transmission gate is in the off state, the output of the filter circuit is the output SH_OUT of the reset and set module 203.

[0067] In addition, the output terminal of the reset and set module 203 is connected to the input terminal of the inverter inv5. The output terminal of the inverter inv5 is connected to the input terminal of the inverter inv6. The output terminal of the inverter inv6 is connected to the output terminal SIG_OUT of the filter circuit. For ease of distinction, the inverter inv5 will be referred to as the fifth inverter and the inverter inv6 will be referred to as the sixth inverter in the following text. The fifth inverter and the sixth inverter are mainly used for waveform shaping and enhancing the drive of the output signal SH_OUT of the reset and set module 203 or the output signal DLY_OUT of the edge delay module.

[0068] As Figure 1As shown, considering that the glitches generated in the integrated circuit can be classified into low-frequency positive glitches, low-frequency negative glitches, high-frequency positive glitches, and high-frequency negative glitches. Glitch signals may occur at any time during signal transmission, so the combination types of glitches and signals are diverse. However, when performing glitch filtering analysis, a fixed high level or a fixed low level can be regarded as a special case of a high-low alternating level signal (the high / low level duration is extremely long), and low-frequency positive / negative glitches can be regarded as special cases of high-frequency positive / negative glitches (the situation where high-frequency positive / negative glitches occur only once). Therefore, in the embodiments of the present invention, it is only necessary to determine the high-low alternating level signal and the high-low alternating level signal superimposed with high-frequency glitches. The following will be combined with Figure 3 and Figure 7 to introduce the filtering process in detail.

[0069] Please refer to Figure 7 , and the combination of glitches and signals is divided into three stages.

[0070] The first stage: the stage without glitches.

[0071] When the input signal is at a low level in the edge detection module 201, that is, SIG_IN = 0. Since the state of the output signal is uncertain, that is, the state of SIG_OUT is uncertain, then it can be assumed in advance that SIG_OUT = 0. On the one hand, since SIG_IN = 0 and SIG_OUT = 0, the output of the first NAND gate is 1, that is, PDT_N = 1, and the output of the first NOR gate is 1, that is, PDT_P = 1. Then PM6 in the reset-set module 203 is in the off state, and NM4 is in the on state. Also, since the output terminal of NM4 is grounded, the output SH_OUT of the reset-set module 203 is 0. At this time, the capacitor C1 discharges quickly, and it can be considered that the reset-set module 203 performs a reset operation on the capacitor C1. On the other hand, the PDT_N signal and the PDT_P signal pass through the first NOT gate, the second NOR gate, and the second NOT gate to obtain the PDT signal. At this time, PDT = 1, so PM1 is in the off state, and there is no current in the entire edge delay module 202, that is, the edge delay module 202 is in the off state at this time. Then the output of the entire filter circuit is equal to the output of the reset-set module 202, that is, SIG_OUT = SH_OUT = 0, which is consistent with the pre-assumption. Therefore, when the input signal is at a low level, the state of the output signal will follow the state of the input signal and still maintain a low level.

[0072] When the input signal is at a high level in the edge detection module 201, i.e., SIG_IN = 1. Since the state of the output signal is uncertain, i.e., the state of SIG_OUT is uncertain, then it can be pre-assumed that SIG_OUT = 1. On the one hand, since SIG_IN = 1 and SIG_OUT = 1, the output of the first NAND gate is 0, i.e., PDT_N = 0, and the output of the first NOR gate nor1 is 0, i.e., PDT_P = 0. Then PM6 in the reset-set module 203 is in the on state and NM4 is in the off state. Also, since the output terminal of PM6 is connected to the power supply, the output SH_OUT of the reset-set module 203 is 1. At this time, the capacitor C1 is quickly charged, and it can be considered that the reset-set module 203 performs a setting operation on the capacitor C1. On the other hand, the PDT_N signal and the PDT_P signal pass through the first NOT gate, the second NOR gate, and the second NOT gate to obtain the PDT signal. At this time, PDT = 1, then PM1 is in the off state, and there is no current in the entire edge delay module 202, i.e., the edge delay module 202 is in the off state at this time. Then the output of the entire filter circuit is equal to the output of the reset-set module 202, i.e., SIG_OUT = SH_OUT = 1, which is consistent with the pre-assumption. Therefore, when the input signal is at a high level, the state of the output signal will follow the state of the input signal and still maintain a high level.

[0073] When in the edge detection module 201, the input signal jumps from a low level to a high level, that is, there is a positive edge in SIG_IN. As can be seen from the above analysis, when SIG_IN is at a low level, SIG_OUT will follow SIG_IN, that is, SIG_OUT is also at a low level. On the one hand, when the positive edge of SIG_IN arrives, at this time the input signal SIG_IN = 1 and the output signal SIG_OUT = 0, then the output of the first NAND gate is 1, that is, PDT_N = 1, and the output of the first NOR gate is 0, that is, PDT_P = 0. Then both PM6 and NM4 in the reset-set module 203 are in the off state. Therefore, the output SH_OUT of the reset-set module 203 is not controlled by PM6 and NM4. On the other hand, the PDT_N signal and PDT_P pass through the first NOT gate, the second NOR gate, and the second NOT gate to obtain the PDT signal. At this time, PDT = 0, then PM1 is in the on state, and there is current in all of PM1, PM2, PM3, and PM4. Since SIG_IN = 1 at this time, PM5 is in the on state and NM3 is in the off state, that is, the positive edge delay module is in the on state. And under the control of the PDT signal, the first transmission gate is also in the on state. Then the capacitor C1 starts charging from 0. When the voltage on the capacitor C1 is higher than the critical voltage, it can cause the subsequent logic gate to flip. The time taken to charge the capacitor C1 from a voltage of 0 to the critical voltage is defined as Td. That is, after Td time, the output DLY_OUT of the edge delay module 202 flips, jumping from a low level to a high level. At this time, the output SIG_OUT of the filter circuit is the output DLY_OUT of the edge delay module 202, that is, SIG_OUT = 1. Therefore, when the positive edge of the input signal arrives, after a delay of Td, the positive edge of the output signal will also arrive.

[0074] When in the edge detection module 201, the input signal changes from high level to low level, that is, there is a negative edge in SIG_IN. As can be seen from the above analysis, when SIG_IN is at high level, SIG_OUT will follow SIG_IN, that is, SIG_OUT is also at high level. On the one hand, when the negative edge of SIG_IN arrives, at this time the input signal SIG_IN = 0 and the output signal SIG_OUT = 1, then the output of the first NAND gate is 1, that is, PDT_N = 1, and the output of the first NOR gate is 0, that is, PDT_P = 0. Then both PM6 and NM4 in the reset and set module 203 are in the off state. Therefore, the output SH_OUT of the reset and set module 203 is not controlled by PM6 and NM4. On the other hand, the PDT_N signal and PDT_P pass through the first NOT gate, the second NOR gate and the second NOT gate to obtain the PDT signal. At this time, PDT = 0, then PM1 is in the on state, and there is current in PM1, PM2, PM3 and PM4. Since SIG_IN = 0 at this time, PM5 is in the off state and NM3 is in the on state, that is, the negative edge delay module is in the on state. And under the control of the PDT signal, the first transmission gate is also in the on state. Then the capacitor C1 starts to discharge from 1. When the voltage on the capacitor C1 is lower than the critical voltage, it can cause the subsequent logic gate to flip. The time taken for the capacitor C1 to discharge from the voltage of 1 to the critical voltage is defined as Td. That is, after Td time, the output DLY_OUT of the edge delay module 202 flips, changing from high level to low level. At this time, the output SIG_OUT of the filter circuit is the output DLY_OUT of the edge delay module 202, that is, SIG_OUT = 0. Therefore, when the negative edge of the input signal arrives, after a delay of Td, the negative edge of the output signal will also arrive.

[0075] As can be seen from the above, when the input signal is at a fixed level, the output signal is also at the same type of fixed level. When there is a jump in the input signal, after a delay time Td, there is also the same type of jump in the output signal. Since the positive edge and negative edge of the output signal both pass through the same delay time Td, it will not change the inherent characteristics of the signal, such as period, frequency and pulse width, etc. It's just that the output signal has an overall delay time Td relative to the input signal.

[0076] The second stage: there are high-frequency positive-going spikes.

[0077] When the positive edge of the high-frequency positive glitch arrives, in the edge detection module 201, the input signal jumps from low level to high level. At this time, the input signal SIG_IN = 1 and the output signal SIG_OUT = 0. Then the output of the first NAND gate is 1, that is, PDT_N = 1, and the output of the first NOR gate is 0, that is, PDT_P = 0. Then both PM6 and NM4 in the reset-set module 203 are in the off state. Therefore, the output SH_OUT of the reset-set module 203 is not controlled by PM6 and NM4. On the other hand, the PDT_N signal and PDT_P pass through the first NOT gate, the second NOR gate, and the second NOT gate to obtain the PDT signal. At this time, PDT = 0, then PM1 is in the on state, and there is current in PM1, PM2, PM3, and PM4. Since SIG_IN = 1 at this time, PM5 is in the on state and NM3 is in the off state, that is, the positive edge delay module is in the on state. And under the control of the PDT signal, the first transmission gate is also in the on state. Then the capacitor C1 starts charging from 0. Since the pulse width of the glitch is less than Td, the voltage on the capacitor C1 cannot exceed the critical voltage, that is, it cannot cause the subsequent logic gate to flip. The output DLY_OUT of the edge delay module 202 will remain low. At this time, the output SIG_OUT of the filter circuit is the output DLY_OUT of the edge delay module 202. Then SIG_OUT = 0.

[0078] When the negative edge of the high-frequency positive glitch arrives, in the edge detection module 201, when the input signal jumps from high level to low level, at this time the input signal SIG_IN = 0 and the output signal SIG_OUT = 0. Then the output of the first NAND gate is 1, that is, PDT_N = 1, and the output of the first NOR gate is 1, that is, PDT_P = 1. Then PM6 in the reset-set module 203 is in the off state and NM4 is in the on state. Since the output terminal of NM4 is grounded, the output SH_OUT of the reset-set module 203 is 0. At this time, the voltage accumulated on the capacitor C1 is quickly discharged, and it can be considered that the reset-set module 203 performs a reset operation on the capacitor C1. On the other hand, the PDT_N signal and PDT_P pass through the first NOT gate, the second NOR gate, and the second NOT gate to obtain the PDT signal. At this time, PDT = 1, then PM1 is in the off state, and there is no current in the entire edge delay module 202, that is, the edge delay module 202 is in the off state at this time. Then the output of the entire filter circuit is equal to the output of the reset-set module 202, that is, SIG_OUT = SH_OUT = 0.

[0079] When the positive edge of the second positive glitch arrives, since the negative edge of the previous positive glitch discharges the voltage accumulated by capacitor C1 to ground, the voltage across capacitor C1 needs to be re - accumulated during this cycle. Also, because the pulse width of the glitch is less than Td, the voltage across capacitor C1 cannot cause the subsequent logic gate to flip, and the output SIG_OUT of the filter circuit continues to maintain a low level.

[0080] When the negative edge of the second positive glitch arrives, the voltage accumulated on capacitor C1 will be discharged to ground by NM4 again. Therefore, the output SIG_OUT of the filter circuit still maintains a low level.

[0081] As can be seen from the above, when the pulse width of the positive glitch is lower than Td, the output signal maintains its original state (low level) unchanged. Since there is a reset at the falling edge of each glitch (i.e., the voltage across capacitor C1 is quickly discharged to ground), high - frequency glitches can be considered independent of each other without an accumulative memory effect. For a normal signal with a pulse width greater than Td, after a delay of Td, a completely identical characteristic signal is sent out.

[0082] Stage 3: There are high - frequency negative glitches.

[0083] When the negative edge of the high - frequency negative glitch arrives, in the edge - detection module 201, when the input signal jumps from high level to low level, at this time the input signal SIG_IN = 0 and the output signal SIG_OUT = 1. Then the output of the first NAND gate is 1, that is, PDT_N = 1, and the output of the first NOR gate is 0, that is, PDT_P = 0. Then both PM6 and NM4 in the reset - set module 203 are in the off state. Therefore, the output SH_OUT of the reset - set module 203 is not controlled by PM6 and NM4. On the other hand, the PDT_N signal and PDT_P pass through the first NOT gate, the second OR gate, and the second NOT gate to obtain the PDT signal. At this time, PDT = 0, then PM1 is in the on state, and there is current in PM1, PM2, PM3, and PM4. Since SIG_IN = 0 at this time, PM5 is in the off state and NM3 is in the on state, that is, the negative - edge delay module is in the on state. And under the control of the PDT signal, the first transmission gate is also in the on state, then capacitor C1 starts to discharge from 1. Since the pulse width of the glitch is less than Td, the voltage across capacitor C1 cannot be lower than the critical voltage, that is, it cannot cause the subsequent logic gate to flip. The output DLY_OUT of the edge - delay module 202 will remain at a high level unchanged. At this time, the output SIG_OUT of the filter circuit is the output DLY_OUT of the edge - delay module 202, so SIG_OUT = 1.

[0084] When the positive edge of the high-frequency negative glitch arrives, in the edge detection module 201, when the input signal jumps from low level to high level, at this time the input signal SIG_IN = 1 and the output signal SIG_OUT = 1. Then the output of the first NAND gate is 0, that is, PDT_N = 0, and the output of the first NOR gate is 0, that is, PDT_P = 0. Then PM6 in the reset-set module 203 is in the on state and NM4 is in the off state. Also, since the output terminal of PM6 is connected to the power supply, the output SH_OUT of the reset-set module 203 is 1. At this time, the capacitor C1 is quickly charged, and it can be considered that the reset-set module 203 performs a setting operation on the capacitor C1. On the other hand, the PDT_N signal and PDT_P pass through the first NOT gate, the second NOR gate, and the second NOT gate to obtain the PDT signal. At this time, PDT = 1, then PM1 is in the off state, and there is no current in the entire edge delay module 202, that is, the edge delay module 202 is in the off state at this time. Then the output of the entire filter circuit is equal to the output of the reset-set module 202, that is, SIG_OUT = SH_OUT = 1.

[0085] When the negative edge of the second negative glitch arrives, since the positive edge of the previous negative glitch quickly charges the capacitor C1, therefore, within this cycle, the voltage on the capacitor C1 needs to be discharged again. Also, since the pulse width of the glitch is less than Td, the voltage on the capacitor C1 cannot cause the subsequent logic gates to flip, and the output SIG_OUT of the filter circuit continues to maintain a high level.

[0086] When the positive edge of the second negative glitch arrives, the capacitor C1 will be quickly charged by PM6 again. Therefore, the output SIG_OUT of the filter circuit still maintains a high level.

[0087] As can be seen from the above, when the pulse width of the negative glitch is lower than Td, the output signal maintains the original state (high level) unchanged. Since there is a reset at the positive edge of each glitch (that is, the voltage on the capacitor C1 is quickly pulled to the power supply voltage), therefore, the high-frequency glitches can be considered to be independent of each other and there is no cumulative memory effect. While the pulse width of the normal signal is greater than Td, after a delay of Td, a completely identical characteristic signal will be sent out.

[0088] Please refer to Figure 8 , based on the same inventive concept, an embodiment of the present invention provides a filtering method applied to a filter circuit. The flow of this method is described as follows.

[0089] Step 801: The edge detection module 201 generates and outputs a first signal and a second signal according to the phase difference between the received input signal and the output signal. The output signal is obtained by the input signal passing through the filter circuit.

[0090] Step 802: The reset-set module 203 generates a third signal according to the first signal and the second signal.

[0091] Step 803: The edge delay module 202 generates a fourth signal according to the third signal and the input signal. The fourth signal is obtained by delaying the input signal by a preset duration and is used to filter the input signal.

[0092] The filtering circuit further includes a channel selection module 204. The channel selection module 204 selects the output signal of the reset module 203 or the edge delay module 202 from the reset module 203 and the edge delay module 202 according to the third signal.

[0093] The filtering circuit provided by the embodiment of the present invention can filter different types of glitches in the input signal. Moreover, the above fourth signal will produce a delay effect whether at the positive edge or the negative edge of the input signal. Even if the input signal is delayed at both the positive edge and the negative edge, it will not affect the inherent characteristics of the input signal.

[0094] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these changes and modifications.

Claims

1. A filtering circuit, characterized in that, Comprising: An edge detection module, a reset - set module, and an edge delay module. The output end of the edge detection module is connected to the input end of the reset - set module, and the output end of the reset - set module is connected to the input end of the edge delay module; Wherein, the edge detection module is used to receive an input signal from the outside, and output a first signal and a second signal according to the phase difference between the input signal and the output signal. The output signal is obtained by the input signal passing through the filter circuit; the first signal characterizes whether there is a negative edge in the input signal, and the second signal characterizes whether there is a positive edge in the input signal; The reset - set module is used to generate a third signal according to the first signal and the second signal; The edge delay module is used to be turned on or off according to the third signal, and when it is turned on, generate a fourth signal based on the input signal. The fourth signal is obtained by delaying the input signal by a preset duration and is used to filter the input signal.

2. The circuit according to claim 1, wherein The edge delay module includes a positive - edge delay module and a negative - edge delay module, wherein: When the third signal is at a low level and the input signal is at a high level, the edge delay module generates the fourth signal through the positive - edge delay module; When the third signal is at a low level and the input signal is at a low level, the edge delay module generates the fourth signal through the negative - edge delay module.

3. The circuit according to claim 2, wherein, The positive - edge delay module and the negative - edge delay module include a capacitor, and the value of the capacitor is determined according to the preset duration, and the preset duration is greater than the pulse width of the signal glitch.

4. The circuit according to claim 3, wherein The level of the first signal jumps from low to high, the level of the second signal is at a low level, and the level of the third signal is at a low level; Or The level of the second signal jumps from high to low, the level of the first signal is at a high level, and the level of the third signal is at a low level.

5. The circuit according to any one of claims 1-4, characterized in that, The circuit further includes a channel selection module. The input end of the channel selection module is connected to the output end of the reset - set module, and the output end of the channel selection module is connected to the input end of the edge detection module; The channel selection module is used to select the reset - set module or the edge delay module from the reset - set module and the edge delay module to output an output signal according to the third signal.

6. The circuit according to claim 5, characterized in that, The channel selection module includes a first NOT gate and a transmission gate. The input end of the first NOT gate is used to receive the third signal, the output end of the first NOT gate is connected to the first input end of the transmission gate, the second input end of the transmission gate is used to receive the third signal, the third input end of the transmission gate is connected to the output end of the edge delay module, and the output end of the transmission gate is connected to the reset - set module. Wherein, when the third signal is at a high level, the transmission gate is in a closed state, and when the third signal is at a low level, the transmission gate is in an open state.

7. The circuit according to claim 3, wherein The edge detection module includes a NAND gate and a first NOR gate. The first input terminal of the NAND gate is connected to the first input terminal of the first NOR gate and receives the output signal. The second input terminal of the NAND gate and the second input terminal of the first NOR gate are used to receive the input signal. The output terminal of the NAND gate is used to output the first signal, and the output terminal of the first NOR gate is used to output the second signal.

8. A filtering method, characterized in that, The method is applied to the filter circuit according to any one of claims 1-7, and the method includes: The edge detection module generates and outputs a first signal and a second signal according to the phase difference between the received input signal and the output signal. The output signal is obtained by passing the input signal through the filter circuit. The first signal represents whether there is a negative edge in the input signal, and the second signal represents whether there is a positive edge in the input signal. The reset-set module generates a third signal according to the first signal and the second signal. The edge delay module is turned on or off according to the third signal, and when it is turned on, it generates a fourth signal based on the input signal. The fourth signal is obtained by delaying the input signal by a preset duration and is used to filter the input signal.

9. The method according to claim 8, characterized in that: The edge delay module includes a positive edge delay module and a negative edge delay module. The edge delay module generates a fourth signal according to the third signal and the input signal, including: When the edge delay module determines that the third signal is at a low level and the input signal is at a high level, it starts the positive edge delay module to generate the fourth signal. When the edge delay module determines that the third signal is at a low level and the input signal is at a low level, it starts the negative edge delay module to generate the fourth signal.

10. The method according to claim 9, wherein The circuit further includes a channel selection module. The input terminal of the channel selection module is connected to the output terminal of the reset-set module, and the output terminal of the channel selection module is connected to the input terminal of the edge detection module. The method further includes: The channel selection module selects the output signal of the reset-set module or the edge delay module from the reset-set module and the edge delay module according to the third signal.

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