Quenching of SPAD

Abstract

Embodiments of the present disclosure relate to quenching of SPADs. The present disclosure relates to an apparatus including a photodiode having a first terminal and a second terminal, the first terminal being coupled to a first rail through a resistor, the first rail being configured to receive a high supply potential, the second terminal being coupled to a second rail through a switch, the second rail being configured to receive a reference potential. A readout circuit is configured to provide a pulse when the photodiode enters avalanche, and a control circuit is configured to: in response to the start of the pulse, control the opening of the switch, and in response to the end of the pulse, control the closing of the switch.

Description

Technical Field

[0001] The present disclosure generally relates to electronic circuits, and more particularly, to SPADs or single-photon avalanche diodes. Background Art

[0002] To detect a single photon, an SPAD diode or a photodiode is reverse-biased to a voltage (in absolute value) greater than the avalanche voltage. In other words, the diode is in the Geiger state or Geiger mode. In this mode, when a single photon arrives at the diode, the free carriers generated by the single photon are sufficiently accelerated by the electric field present at the diode junction to create additional free carriers. The diode thus enters an avalanche, and a current flows in the diode. To detect a new single photon, the diode should be quenched by reducing the voltage at the diode terminals below the avalanche voltage (as an absolute value) of the diode to empty the free carriers of the diode, and then the diode is put back into the Geiger state. For this purpose, a quenching circuit is provided. Summary of the Invention

[0003] There is a need for a device that includes an SPAD and a quenching circuit associated with the SPAD, which device solves all or some of the drawbacks of known devices that include an SPAD and a quenching circuit associated with the SPAD.

[0004] In particular, there is a need for a compact device that includes an SPAD and its quenching circuit, for example, for implementing a compact image sensor that includes a plurality of such devices, which devices are arranged in a matrix, for example.

[0005] There is also a need for a device that includes an SPAD and a quenching circuit associated with the SPAD, which device allows for a reduction in the dead time between two consecutive detections of a single photon compared to known devices that include an SPAD and a quenching circuit associated with the SPAD.

[0006] One or more embodiments solve all or some of the drawbacks of known devices that include an SPAD and a quenching circuit associated with the SPAD.

[0007] One embodiment provides a device that includes:

[0008] A photodiode, a first terminal of the photodiode is coupled to a first rail through a resistor, the first rail is configured to receive a high supply potential, a second terminal of the photodiode is coupled to a second rail through a switch (in some embodiments, a MOS transistor), the second rail is configured to receive a reference potential;

[0009] A readout circuit, configured to provide a pulse when the diode enters an avalanche; and

[0010] A control circuit, configured to: in response to the start of the pulse, control the disconnection of the switch, and in response to the end of the pulse, control the closing of the switch.

[0011] According to one embodiment, the control circuit includes a logic gate, which includes an input configured to receive the pulse and an output configured to provide a control signal for the switch.

[0012] According to one embodiment, the control circuit is further configured to: during the switching of the control signal that causes the switch to close, control the slope of the control signal according to the value of the slope adjustment potential.

[0013] According to one embodiment, the control circuit includes a MOS transistor, which is connected between the power supply terminal of the control circuit and the first power supply terminal of the gate of the control circuit, and the gate of the MOS transistor is configured to receive the slope adjustment potential.

[0014] According to one embodiment, the device is configured to: as long as the deactivation signal for deactivating the device is in the first state, interrupt the conduction path that couples the second terminal of the diode to the second rail via the switch.

[0015] According to one embodiment:

[0016] An additional switch controlled by the deactivation signal for deactivating the device is connected in series with the switch between the second terminal of the diode and the second rail; or

[0017] The gate of the control circuit includes an input configured to receive the deactivation signal for deactivating the device.

[0018] According to one embodiment, the control circuit is further configured to: as long as the deactivation signal for deactivating the control circuit is in the first state, keep the switch closed. In some embodiments, the gate of the control circuit includes an input configured to receive the deactivation signal for deactivating the control circuit.

[0019] According to one embodiment, the control circuit includes a MOS transistor, which is connected between the second power supply terminal of the gate of the control circuit and the second rail, and the gate of the transistor is configured to receive the deactivation signal for deactivating the control circuit.

[0020] According to one embodiment, the device further includes a capacitive bridge voltage divider, which is connected between the first terminal of the diode and the second rail, and the input terminal of the reading circuit is connected to the middle node of the capacitive divider bridge.

[0021] According to one embodiment, the reading circuit is further configured to modify the duration of the pulse by adjusting the value of a potential according to the pulse duration.

[0022] According to one embodiment, the reading circuit includes a MOS transistor connected between a power supply terminal of the reading circuit and an intermediate node, and the gate of the MOS transistor is configured to receive a pulse duration adjustment potential.

[0023] According to one embodiment, the reading circuit includes a logic gate (in some embodiments, an inverter), the logic gate includes an input terminal and an output terminal, the input terminal is coupled to (in some embodiments, connected to) the intermediate node, and the output terminal is configured to provide the pulse.

[0024] According to one embodiment, the reading circuit and the control circuit are respectively connected between a second rail and a third rail, and the third rail is configured to receive a low power supply potential.

[0025] According to one embodiment, the device further includes a potential limiting circuit configured to limit the maximum level of the potential on the second terminal of the diode. The potential limiting circuit may include an additional diode connected between the second terminal of the diode and a node configured to receive an intermediate power supply potential.

[0026] According to one embodiment, the device further includes a capacitor connected between the second terminal of the diode and the second rail.

[0027] Another embodiment provides an image sensor including a plurality of the devices as described above, which are arranged in a matrix in some embodiments, and each device may form a pixel of the sensor. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In the following description of specific embodiments given by way of illustration and not limitation, the above features and advantages and other features and advantages will be described in detail with reference to the accompanying drawings, in which:

[0029] Figure 1 One embodiment of the device is illustrated in circuit form, the device including a diode adapted to be used as a SPAD and a quenching circuit of the diode;

[0030] Figure 2 Illustrated is Figure 1 Timing diagrams A and B depicting the operation of one embodiment of the illustrated device;

[0031] Figure 3 Illustrated is Figure 1 A timing diagram depicting the operation of another embodiment of the illustrated device;

[0032] Figure 4 illustrates the depiction of Figure 1 a timing diagram depicting the operation of yet another embodiment of the device shown;

[0033] Figure 5 illustrates Figure 1 a variant embodiment of the device shown;

[0034] Figure 6 illustrates Figure 1 another variant embodiment of the device shown;

[0035] Figure 7 illustrates Figure 1 yet another variant embodiment of the device shown; and

[0036] Figure 8 illustrates Figure 1 yet another variant embodiment of the device shown. DETAILED DESCRIPTION

[0037] In the various figures, the same features have been denoted by the same reference numerals. In particular, structural and / or functional features common to the various embodiments may have the same reference numerals and may have the same structural characteristics, dimensional characteristics, and material characteristics.

[0038] For clarity, only the operations and elements useful for understanding the embodiments described herein have been illustrated and described in detail. In particular, the circuit for counting the pulses generated by the readout circuit of the SPADs, at each detection of a single photon (i.e., each time a SPAD in Geiger mode enters avalanche after being struck by a photon), has not been described in detail. The embodiments described are compatible with conventional circuits for counting pulses. In addition, the implementation of an image sensor including a plurality of devices or pixels (each having a SPAD) has not been described in detail. The embodiments described are compatible with such conventional image sensors. More generally, the various applications providing one or more SPADs for detecting single photons have not been described in detail. The embodiments described are compatible with these conventional applications. In addition, the actual implementation of the diodes adapted to be used as SPADs has not been described in detail. The embodiments described are compatible with the conventional implementations of diodes adapted to be used as SPADs.

[0039] Unless otherwise indicated, when referring to two elements connected together, this means a direct connection without any intermediate element other than a conductor, while when referring to two elements linked or coupled together, this means that the two elements can be connected or linked or coupled through one or more other elements.

[0040] In the following disclosure, unless otherwise specified, when referring to absolute position determiners (such as the terms "front", "rear", "top", "bottom", "left", "right", etc.) or relative position determiners (such as the terms "above", "below", "higher", "lower", etc.) or orientation determiners (such as "horizontal", "vertical", etc.), the orientation shown in the figures is referred to.

[0041] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "nearly" mean within 10%, and in some embodiments, within 5%.

[0042] A "digital signal" means a signal that alternates between at least two constant states. For example, for a "binary signal", it alternates between a low state (labeled "0") and a high state (labeled "1"). In fact, a digital signal can correspond to a potential referenced with respect to a reference potential (usually ground GND), or to a current that may not be perfectly constant for a given state of the signal. In the following disclosure, the first state of a first signal can correspond to the low state of the signal, while the first state of a second signal can correspond to the high state of the signal. Thus, the first state of the first signal and the first state of the second signal can correspond to different potential levels.

[0043] There are two types of quenching circuits, namely, a passive quenching circuit and an active quenching circuit. The passive quenching circuit includes a resistor in series with the SPAD, such that once an avalanche in the SPAD has been triggered, the voltage drop (as an absolute value) at the SPAD terminals directly results from the voltage drop across the resistor. The active quenching circuit includes means for reducing the voltage at the SPAD terminals below the avalanche voltage (as an absolute value) after detecting an avalanche in the SPAD. In particular, the active quenching circuit includes components such as transistors, which are provided with or receive a potential having a value approximately equal to the voltage value at the terminals of a SPAD in Geiger mode.

[0044] In the following disclosure, an embodiment is described in which the start of the SPAD quenching process is passive (i.e., the SPAD quenching process starts directly after the voltage drop across a resistor connected in series with the SPAD). Then, the quenching process continues under voltage and time conditions determined by a control circuit, which also controls the phase for returning the system to its initial state.

[0045] Figure 1 An embodiment of device 1 is illustrated in circuit form. The device 1 includes a diode 100 adapted to be used as a SPAD and a quenching circuit for the diode 100.

[0046] Apparatus 1 includes a resistor R and a switch 102 (“SW”). The resistor R couples a first terminal of the diode 100 (in some embodiments, the cathode of the diode 100) to a first rail 104, which is intended to receive a high supply potential VH. In some embodiments, the terminals of the resistor R are connected to the rail 104, and the second terminal of the resistor R is connected to the cathode of the diode 100. The switch 102 couples a second terminal of the diode 100 (in some embodiments, the anode of the diode 100) to a second rail 106, which is intended to receive a reference potential GND, typically ground. The potential VH is referenced to ground GND. In some embodiments, the potential VH is positive, for example, approximately equal to 25V.

[0047] According to one embodiment, the switch 102 is implemented by a MOS transistor 102, and in some embodiments, by an N-channel MOS transistor. The conductive terminals of the switch 102 thus correspond to the respective conductive terminals of the transistor 102, that is, to the drain terminal and the source terminal of the transistor 102. Additionally, the control terminal of the switch 102 thus corresponds to the control terminal or gate of the transistor 102.

[0048] According to Figure 1 the depicted embodiment, the conductive terminals of the switch 102 are correspondingly connected to the second terminal (anode) of the diode 100 and the second rail 106. For example, the drain of the transistor 102 is connected to the anode of the diode 100, and the source of the transistor 102 is connected to the rail 106.

[0049] Apparatus 1 includes a capacitive voltage divider bridge, which is connected between the cathode of the diode 100 and the rail 106. The capacitive voltage divider bridge includes an intermediate node 108. The capacitive voltage divider bridge is configured such that a change in the cathode potential of the diode 100 causes a change in the potential of the node 108.

[0050] In this example, the capacitive voltage divider bridge includes two capacitors C1 and C2 connected in series between the cathode of the diode 100 and the rail 106. The capacitor C1 is coupled (in some embodiments, connected) to the diode 100, the capacitor C2 is coupled (in some embodiments, connected) to the rail 106, and the capacitors C1 and C2 are connected to each other at the node 108.

[0051] Apparatus 1 includes a read circuit 110 (“LECT”). The circuit 110 (by Figure 1The dashed box (defined therein) is configured to provide the output signal OUT of the device 1. More particularly, the circuit 110 is configured to provide a pulse under each avalanche in the diode 100. In other words, under each avalanche in the diode 100, the circuit 110 is configured to cause the signal OUT to switch from a first state (e.g., a low state) to a second state (e.g., a high state), and then, after a given duration, to cause the signal OUT to switch from the second state to the first state. The input terminal 112 of the reading circuit 110 is connected to the node 108.

[0052] According to one embodiment, the circuit 110 receives a low supply potential VL, similar to the potential VH, the potential VL being referenced to the ground GND. The concepts of the low potential VL and the high potential VH are relative concepts of these two potentials with respect to each other, and the potential VL is lower than the potential VH. The circuit 110 is connected between a third rail 114 for applying the potential VL and the rail 106. In other words, the supply terminal 116 (e.g., the high supply terminal) of the circuit 110 is connected to the rail 114, and the other supply terminal 118 (e.g., the low supply terminal) of the circuit 110 is connected to the rail 106. The potential VL is positive, for example, approximately 1.1V.

[0053] According to one embodiment, the circuit 110 includes a logic gate 120 (in some embodiments, an inverter), the logic gate 120 including an input and an output 122, the input being coupled (in some embodiments, connected) to the terminal 112, and thus being coupled (in some embodiments, connected) to the node 108, the output 122 being configured to provide the signal OUT and corresponding to the output terminal of the circuit 110. The gate 120 includes a first supply terminal and a second supply terminal (e.g., the high supply terminal and the low supply terminal, respectively), the first supply terminal and the second supply terminal being coupled to (in some embodiments, connected to) the corresponding supply terminals 116 and 118 of the reading circuit 110.

[0054] According to one embodiment, the circuit 110 is configured to: modify the duration or width of the pulse of the signal OUT by adjusting the value of the potential VB according to the pulse duration. Here, the potential VB is referenced to the ground GND and is, for example, included between the potential VL and 0V. In some embodiments, the circuit 110 thus includes a MOS transistor 124 (in some embodiments, a P-channel MOS transistor), the MOS transistor 124 being connected between the terminal 116 and the node 108, and the gate of the transistor 124 being configured to receive the potential VB. The value of the potential VB and the transistor 124 fix the duration of the pulse of the signal OUT. In this example, the lower the value of the potential VB, the shorter the pulse.

[0055] Apparatus 1 includes a control circuit 126 (“CTRL”) for controlling switch 102. Circuit 126 is configured to: in response to the start of a pulse of signal OUT (the switching of signal OUT from its first state to its second state), control the opening of switch 102, and in response to the end of the pulse (the switching of signal OUT from its second state to its first state), control the closing of switch 102. The input terminal 128 of the circuit is coupled (in some embodiments, connected) to the output terminal 122 of circuit 110. The output terminal 130 of circuit 126 is configured to provide a control signal cmd for controlling switch 102, and terminal 130 is coupled (in some embodiments, connected) to the control terminal of switch 102. More particularly, circuit 126 is configured to: in response to the start of a pulse of signal OUT, switch the signal cmd from a first state in which switch 102 is closed (e.g., a high state) to a second state in which switch 102 is open (e.g., a low state), and conversely, in response to the end of the pulse of signal OUT, switch the control signal for controlling switch 102 from the second state to the first state.

[0056] According to one embodiment, circuit 126 receives a supply potential VL. In other words, circuit 126 is connected between rails 114 and 106. In yet other words, the supply terminal 132 (e.g., high supply terminal) of circuit 126 is connected to rail 114, and the other supply terminal 134 (e.g., low supply terminal) of circuit 126 is connected to rail 106.

[0057] According to one embodiment, circuit 126 includes a logic gate 136 (in the example shown, an inverter), which logic gate 136 includes an input and an output, the input being coupled to (in some embodiments, connected to) terminal 128, and the output being coupled to (in some embodiments, connected to) terminal 130, and the output of gate 136 is configured to provide signal cmd. Gate 136 includes a first supply terminal and a second supply terminal (e.g., high supply terminal and low supply terminal respectively), which first supply terminal and second supply terminal are coupled to the corresponding supply terminals 132 and 134.

[0058] According to one embodiment, circuit 126 is configured to control or modify the slope of signal cmd by adjusting the value of potential VC according to a slope during the transition of signal cmd that causes switch 102 to switch to the closed state. In some embodiments, circuit 126 thus includes MOS transistor 140 (a P-channel MOS transistor in some embodiments), which is connected between the power supply terminal 132 of circuit 126 and the corresponding power supply terminal of gate 136 of circuit 126, i.e., the power supply terminal of gate 136 is configured to receive a potential level corresponding to the second state of signal cmd. Thus, the lower the value of potential VC relative to the value of potential VL (e.g., the closer the value of potential VC is to 0V), the steeper the slope of signal cmd during the transition to the first state of signal cmd, and the faster switch 102 switches to the closed state of switch 102.

[0059] During the transition of signal cmd, a relatively weak slope is preset in advance (e.g., about 0.1V / ns -1 ) allows switch 102 to close gradually, which avoids triggering an undesired or untimely avalanche in diode 100 when diode 100 is being returned to the Geiger state. This also allows limiting the interference at node 108, thus avoiding false detection in circuit 110. In addition, by reducing the slope of this transition of signal cmd, the delay between the end of the pulse of signal OUT on terminal 128 and the corresponding closing of switch 102 increases.

[0060] According to one embodiment, device 1 includes circuit 142, which is configured to limit the maximum level of the potential on the anode of diode 100. In this example, circuit 142 is diode 142 connected between the anode of diode 100 and node 144, and this node 144 is used to apply an intermediate supply potential VI, which is referenced to ground GND and is positive in some embodiments. The concepts of high potential VH, low potential VL, and intermediate potential VI are relative concepts of these potentials with respect to each other, and potential VI is included between potential VH and VL. The anode of diode 142 is connected to the anode of diode 100 in some embodiments, and the cathode of diode 142 is connected to node 144 in some embodiments. Potential VI is positive, for example, about 7V.

[0061] The provision of circuit 142 allows preventing the voltage at the terminals of switch 102 in the open state from reaching a value that can cause damage to switch 102 (in this example, damage to transistor 102).

[0062] According to one embodiment, device 1 includes capacitor CA connected between the anode of diode 100 and rail 106.

[0063] Now reference will be made toFigures 2 to 5 to describe the operation of the device 1 Figures 2 to 5 Each of the accompanying drawings depicts the operation of a different embodiment of the device 1.

[0064] Figure 2 Illustrates Figure 1 Timing diagrams A and B depicting the operation of an embodiment of the device shown. Timing diagram A depicts the variation of the signal OUT according to time t, and timing diagram B depicts the variation of the voltage VSPAD corresponding to the difference between the cathode potential and the anode potential of the diode 100 according to time t. Timing diagrams A and B are not drawn to scale.

[0065] In Figure 2 an embodiment of the device 1 is considered, where the value of the capacitor CA is negligible, or where the capacitor CA is omitted, i.e., an embodiment is considered where the anode of the diode 100 is considered floating when the switch 102 is open.

[0066] At time t0, the diode 100 is in the Geiger state. In other words, the value V0 of the voltage VSPAD is greater than the value of the avalanche voltage VBD of the diode 100 (as an absolute value), and no current flows in the diode 100. The value V0 is, for example, substantially equal to the value of the potential VH.

[0067] Furthermore, the potential on the input 112 of the circuit 110 is a high value sufficient to cause the signal OUT to be in a low value (the first state of the signal OUT). For example, the high value of the potential on the input 112 is at least partially determined by the ratio of the capacitors C1 and C2. In an embodiment where the circuit 110 is configured to modify the pulse width of the signal VOUT according to the value of the potential VB, the high value of the potential on the input 112 is at least partially determined by the value of the potential VB.

[0068] As a result of the first state of the signal OUT on the input 128 of the circuit 126, the signal cmd is in its first state (e.g., the high state of the signal cmd), and the switch 102 is closed.

[0069] At a time t1 later than t0, a photon is received by diode 100 and causes an avalanche in diode 100. A current flows between rails 104 and 106, through resistor R, diode 100, and closed switch 102. The voltage drop at the terminals of resistor R causes a corresponding decrease in the cathode potential of diode 100, and thus voltage VSPAD decreases to a value V1 (as an absolute value) lower than the avalanche voltage VBD. The decrease of voltage VSPAD to value V1 quenches the avalanche in diode 100. At the same time, the decrease in the cathode potential of diode 100 causes the potential at input 112 of circuit 110 to decrease to a certain value, causing signal OUT to switch to a high value (the second state of signal OUT). This switching of signal OUT corresponds to the start of a pulse of signal OUT, and circuit 126 thus controls the opening of switch 102 by switching signal cmd to its second state (e.g., the low state of signal cmd).

[0070] Starting from time t1, the cathode potential of diode 100 gradually increases via the charging of circuit RC, which includes resistor R and capacitive divider bridge C1, C2.

[0071] At a time t2 later than time t1, the cathode potential of diode 100 reaches a value such that the potential value at input 112 of circuit 110 is sufficient to cause signal OUT to switch from its second state to its first state (the end of the pulse of signal OUT). Circuit 126 thus controls the closing of switch 102 by switching signal cmd to its first state. Starting from a time t2' after time t2, switch 102 closes, and in some embodiments, closes gradually.

[0072] Between time t1 and t2', since switch 102 is open, the anode of diode 100 is floating, and the anode potential of diode 100 follows the cathode potential of diode 100. As a result, between time t1 and t2', voltage VSPAD remains equal to voltage V1. The duration tquench between time t1 and t2' is determined such that the avalanche phenomenon in diode 100 is quenched or stopped, and all free carriers generated during the avalanche are emptied from diode 100. Additionally, with the anode of diode 100 floating, each new avalanche in diode 100 is immediately terminated. This duration tquench is commonly referred to as the quench time.

[0073] Starting from time t2’, the anode potential of diode 100 approaches the potential of rail 106. In some embodiments, as switch 102 closes, the anode potential of diode 100 gradually approaches the potential of rail 106. At the same time, the cathode potential of diode 100 continues to increase, and thus voltage VSPAD gradually increases until voltage VSPAD reaches value V0 at time t3 after time t2’. From time t3 onwards, diode 100 is in Geiger mode, ready to detect a new single photon. After the avalanche in diode 100 starts, the duration tdead_time between times t1 and t3 for putting diode 100 back into Geiger mode is generally referred to as the dead time.

[0074] In device 1, the quenching circuit of SPAD diode 100 thus includes resistor R, capacitive bridge C1, C2, readout circuit 110, circuit 126, and switch 102.

[0075] For comparison, a virtual device similar to device 1 is considered, but in this virtual device, circuit 126 and switch 102 are omitted, and the anode of diode 100 is connected to rail 106. In such a virtual device, the quenching time tquench of diode 100 would only depend on the time constant of circuit RC, which includes resistor R and capacitive divider bridge C1, C2. Thus, a value can be provided for resistor R that is sufficient to obtain the same quenching time tquench as that of device 1. However, this would increase the dead time tdead_time of the virtual device relative to the dead time of device 1, which is undesirable.

[0076] Therefore, compared to this virtual device, device 1 allows the value of resistor R to be reduced without changing the quenching time tquench, thereby reducing the dead time tdead_time. More generally, compared to conventional passive quenching devices, with device 1, the value of resistor R can be reduced, thereby reducing the value of the dead time tdead_time while still maintaining the same quenching time tquench. This advantage of device 1 over conventional passive quenching devices is obtained by simply adding switch 102 and circuit 126, and thus device 1 remains compact, especially compared to active quenching devices. In fact, MOS transistor 102 of device 1 is more compact and consumes less than the transistors of active quenching circuits.

[0077] Due to the compactness and low consumption of device 1, device 1 is adapted to implement an image sensor including a plurality of devices or pixels 1, and in some embodiments, the plurality of devices or pixels 1 are arranged in a matrix. Additionally, in such a sensor, all SPADs 100 of the sensor have the same quenching time tquench and the same dead time tdead_time, except for manufacturing dispersion. In particular, this is caused by the fact that for each pixel 1, these times tquench and tdead_time depend only on the signal generated directly in pixel 1. Additionally, in such a sensor, compared to, for example, an image sensor with a longer dead time (e.g., this is the case for a sensor including a plurality of virtual devices as described above), the reduction of the dead time tdead_time between two consecutive single-photon detections allows for a greater dynamic range.

[0078] Figure 3 The timing diagram illustrates the operation of another embodiment of the described Figure 1 device. In the case of an embodiment where the capacitor CA of device 1 has a non-negligible value, Figure 3 the timing diagram shown corresponds to Figure 2 the timing diagram B shown. In other words, Figure 3 the timing diagram shown corresponds to an embodiment of device 1 in which, when switch 102 is open, the change in the anode potential of diode 100 depends on the value of capacitor CA. Here, only the operational differences between these embodiments of device 1 are emphasized.

[0079] Compared to that described with respect to Figure 2 the timing diagram B shown in Figure 3 in, the anode potential of diode 100 increases between time t1 and t2'. More particularly, the increase in the anode potential of diode 100 is not as fast as the increase in the cathode potential of diode 100, and those skilled in the art can select the sizes of the various capacitors CA, C1, and C2 of device 1 to obtain this operation. As an example, the value of capacitor CA is between 0.1 times and 10 times the value of the internal capacitance of diode 100.

[0080] Therefore, between time t1 and t2', the voltage VSPAD increases from a value V1 that is lower (as an absolute value) than the value of the avalanche voltage VBD until a value V2.

[0081] In some embodiments, the value V2 is greater than the voltage VBD (as an absolute value) and less than the value V0, and is, for example, equal to (V0 + VBD) / 2 plus or minus (V0 - VBD) / 4.

[0082] Providing a value V2 greater than the value of the voltage VBD allows faster draining of the free carriers generated in the diode 100 during the avalanche. Providing a value V2 greater than the value of the voltage VBD also allows ensuring that all free carriers generated in the diode 100 are drained even in the case where the diode 100 tends to store carriers due to its internal structure. Figure 2 In the case shown in , the quenching time tquench can therefore be reduced, and thus the dead time tdead_time can be reduced, which can be achieved, for example, by modifying the value of the potential VC and / or the value of the potential VB. A person skilled in the art can determine the duration tquench to quench the avalanche in the diode 100 and clear the free carriers generated by the diode 100 during the avalanche.

[0083] Furthermore, between instants t1 and t2′, the anode of the diode 100 is connected to the rail 106 via the low capacitor CA and any new avalanche in the diode 100 will involve only a weak current and therefore a small change in the potential of the node 112. Therefore, between instants t1 and t2′, a new avalanche will not be detected by the reading circuit 110, but it will contribute to draining the free carriers present in the diode 100.

[0084] Figure 4 The diagram depicts Figure 1 A timing diagram of the operation of another embodiment of the device shown. In the case of the following embodiment of the device 1, Figure 4 The timing diagram shown corresponds to Figure 3 In the timing diagram shown, in this embodiment, the capacitor CA has a non-negligible value and the resistance of the switch or transistor 102 in the on state has a value different from zero, for example, between 0.1 and 10 times the value of the resistor R. Here, only the connection between the device 1 and the corresponding Figure 3 and Figure 4 The corresponding differences.

[0085] exist Figure 4 , at time t1 , the voltage VSPAD decreases from the value V0 to the value V1 resulting in not only a voltage drop across the resistor R, but also a voltage drop across the closed switch 102 .

[0086] Then, once the switch 102 is opened, the cathode potential of the diode 100 increases, and the anode potential of the diode 100 also increases, but not as fast as the cathode potential. Therefore, the voltage VSPAD increases until it reaches the value V2 at time t1', which is after time t1 but before time t2 corresponding to the end of the pulse of the signal OUT. From time t1' to time t2', the voltage VSPAD is constant and equal to the value V2. This is due to the fact that when the switch 102 is opened, the increase amplitude of the voltage VSPAD is limited by the value of the voltage drop across the resistor R during avalanche, and this value is Figure 4 lower in the case shown than in the case Figure 3 shown.

[0087] Compared with the case Figure 3 shown, the embodiment of the device 1 described with respect to Figure 4 allows better control of the value V2 and the duration during which the diode 100 is biased to the value V2. This allows avoiding the potential difference between the terminals of the diode 100 from becoming too close to the value V0 between times t1' and t2'. In other words, compared with the case Figure 3 shown, the probability of the diode 100 entering avalanche inappropriately can be reduced using the embodiment of the device 1 described with respect to Figure 4 described.

[0088] A person skilled in the art can select the value of the resistor R and select the on-resistance value of the switch or transistor 102 by choosing the size of the switch or transistor 102 to obtain the target value V2.

[0089] In the variant embodiments described below, it is desirable, especially when the device 1 is used as a pixel of an image sensor, to be able to deactivate the device 1 described with respect to Figures 1 to 4 described. In fact, in this way, during the operating phases when the device 1 is not used, the consumption of the system including the device 1 (e.g., an image sensor) can be reduced. Moreover, in the specific case where the image sensor includes, for example, a plurality of pixels 1 arranged in a matrix, one or more defective pixels 1 can be deactivated in this way.

[0090] In these variant embodiments, to deactivate the device 1, an interruption of the conductive path coupling the diode 100 to the rail 106 is provided by means of the switch 102. This interruption of the conductive path is regulated by the state of the deactivation signal EN for deactivating the device 1. More particularly, as long as the signal EN is in the first state, this conductive path is interrupted.

[0091] Now this variant of the device 1 will be described with respect to Figure 5 and Figure 6 here only emphasizing Figure 5 andFigure 6 the difference between the device 1 shown and Figure 1 the device 1 shown.

[0092] Figure 5 A variant embodiment is depicted in which, in order to interrupt the conductive path of the diode 100 coupled to the rail 106 via the switch 102, the device 1 includes an additional switch 500.

[0093] The switch 500 is a MOS transistor 500 in some embodiments and an N-channel MOS transistor 500 in some embodiments. The switch 500 is connected in series with the switch 102 between the diode 100 and the rail 106. In addition, the switch 500 is controlled by the signal EN, and the control terminal of the switch 500 (e.g., the gate of the MOS transistor 500) is configured to receive the signal EN. The switch 500 is configured to: open when the signal EN is in the first state and close when the signal EN is in the second state.

[0094] In Figure 5 the example shown, the switch 500 is connected between the diode 100 and the switch 102. In other words, the conductive terminal of the switch 500 (e.g., the drain of the transistor 500) is coupled (connected in some embodiments) to the diode 100, and more particularly, to the anode of the diode 100, and the other conductive terminal of the switch 500 (e.g., the source of the transistor 500) is coupled (connected in some embodiments) to the conductive terminal of the switch 102 (e.g., the drain of the transistor 102).

[0095] In another example not shown, the switch 500 is connected between the switch 102 and the rail 106. In other words, the conductive terminal of the switch 500 (e.g., the drain of the transistor 500) is coupled (connected in some embodiments) to the conductive terminal of the switch 102 (e.g., the source of the transistor 102), and the other conductive terminal of the switch 500 (e.g., the source of the transistor 500) is coupled (connected in some embodiments) to the rail 106.

[0096] The selection of the position of switch 500 relative to switch 102 is determined, for example, by the potential level available for the first state of signal EN. For example, in a situation where it is desired to place the system (such as an image sensor including, for example, a plurality of pixels 1 arranged in a matrix) in a standby state to minimize system consumption, this potential level can have a value very close to the threshold voltage of transistor 500, for example, approximately 0.7V, and thus in some embodiments, switch 500 is set on one side of rail 106 rather than on the side of transistor 100. Conversely, when the value of potential VL is relatively close to the threshold voltage of transistor 102, it is desired that switch 500 be set on the side of diode 100, and the potential level corresponding to the first state of signal EN is adapted accordingly.

[0097] Figure 6 A variant embodiment is depicted in which read circuit 126 is configured to interrupt the conductive path coupling diode 100 to rail 106 via switch 102 as long as signal EN is in its first state. In other words, circuit 126 is configured to keep switch 102 open as long as signal EN is in its first state.

[0098] More particularly, in Figure 6 in addition to the input coupled (connected in some embodiments) to input 128 of circuit 126, gate 136 (e.g., a NOR gate) of circuit 126 also includes an additional input configured to receive signal EN. Gate 136 is configured to keep signal cmd in its first state (opening switch 102) as long as signal EN is in the first state of signal EN.

[0099] It should be noted that compared to the variant embodiment of Figure 5 in which, in some embodiments, the first state and the second state of signal EN correspond to the low state and the high state of signal EN respectively, in the specific variant embodiment shown in Figure 6 where gate 136 is a NOR gate, the first state and the second state of signal EN correspond to the high state and the low state of signal EN respectively. For example, the high state of signal EN corresponds to a potential substantially equal to potential VL, and the low state signal EN corresponds to potential GND, for example.

[0100] In another variant embodiment not shown, when signal EN is in its first state, the conductive path coupling diode 100 to rail 106 via switch 102 is interrupted by forcing potential VC to a value that turns off MOS transistor 140. In other words, signal VC can be used as an analog signal or a digital signal, the value of the analog signal regulating the slope of signal cmd during the transition to the first state of signal cmd, and the digital signal controlling the transition to the off state of transistor 140.

[0101] In this case, after the transition to the second state of signal cmd (switch 102 open), as long as MOS transistor 140 is held off by signal VC, it is not possible to transition to the first state of the signal. In other words, signal VC is at a value such that the slope of signal cmd is zero during the transition from its second state to its first state.

[0102] In yet another variant (not shown), circuit 126 is not configured to control the slope of signal cmd during the transition that closes switch 102, and transistor 140 is controlled only by signal EN in a manner similar to that described above.

[0103] In other variant embodiments described below, it may also be desirable to deactivate only circuit 126 of device 1 as described. Figures 1 to 6 In these variants, circuit 126 is thus configured to keep switch 102 closed as long as deactivation signal ACT, which is used to deactivate circuit 126, is in a first state.

[0104] Now such variants of device 1 will be described with respect to Figure 7 and Figure 8 here emphasizing only the differences between Figure 7 and Figure 8 the device 1 shown and Figure 1 the device 1 shown.

[0105] Figure 7 depicts a variant embodiment in which, in addition to an input coupled (connected in some embodiments) to input 128 of circuit 126, gate 136 (e.g., a NAND gate) of circuit 126 includes an additional input configured to receive signal ACT. Gate 136 is configured to keep signal cmd in its first state (switch 102 closed) as long as signal ACT is in a first state of signal ACT. In Figure 7 the example shown, the first state of signal ACT corresponds to the low state of signal ACT, e.g., corresponds to potential GND.

[0106] Figure 8 depicts a variant embodiment in which circuit 126 includes MOS transistor 800, e.g., an N-channel MOS transistor. Transistor 800 is connected between terminal 134 of circuit 126 and the corresponding supply terminal of gate 136, i.e., the supply terminal of gate 136 is configured to receive a potential level corresponding to the second state of signal cmd (switch open). For example, the drain of transistor 800 is connected to this supply terminal of gate 136, and the source of transistor 800 is connected to terminal 134 of circuit 126.

[0107] The transistor 800 is controlled by the signal ACT, and the gate of the transistor 800 is configured to receive the signal ACT. The transistor 800 is further configured to be turned off as long as a first state of the signal ACT (e.g., a low state of the signal ACT) is applied to the gate of the transistor 800. Thus, as long as the MOS transistor 800 is kept off by the first state of the signal ACT, it is impossible to switch to a second state of the signal cmd, and the switch 102 remains closed.

[0108] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these embodiments can be combined, and other variations will readily occur to those skilled in the art. In particular, embodiments in which the read circuit 126 can be deactivated can be combined with embodiments in which the device 1 can be deactivated. In particular, by modifying the gate 136 of the device 1 (e.g., by providing a logic gate 136 including three inputs configured to receive respective signals OUT, ACT, and EN), those skilled in the art are able to implement these combinations.

[0109] More generally, those skilled in the art can implement the functions of the above-described circuit 126 by using a logic gate 136 different from the Figure 1 and Figures 5 to 8 logic gates described, particularly a logic gate corresponding to a combination of multiple basic OR, AND, NOR, NAND, XOR, inverter, etc. logic gates.

[0110] In addition, it will be understood that each of the capacitors CA, C1, and C2 can correspond to one or more capacitive components, to one or more intrinsic capacitances of the circuit, or to a combination of one or more capacitive components and one or more intrinsic capacitances of the circuit. Similarly, the resistor R can correspond to one or more resistive components, to the equivalent resistance of the electrical conductor between the rail 104 and the node 108, or to a combination of one or more resistive components and the equivalent resistance of the electrical conductor between the rail 104 and the node 108.

[0111] In addition, although it has been previously indicated that the signal OUT is the output signal of the device 1, other signals of the device can be used as the output signal. For example, the output signal of the device 1 can correspond to the output of an inverter whose input is coupled (e.g., connected) to the anode of the photodiode 100.

[0112] Finally, based on the functional descriptions provided above, the actual implementation of the embodiments and variations described herein is within the capabilities of those skilled in the art.

[0113] The various embodiments described above can be combined to provide other embodiments. These and other changes to the embodiments can be made in accordance with the above detailed description. Generally, in the appended claims, the terms used should not be construed as limiting the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include the full scope of all possible embodiments claimed by such claims and equivalents. Thus, the claims are not limited by the disclosure.

Claims

1. An electronic device, comprising: A photodiode having a first terminal and a second terminal; A resistor coupled between the first terminal of the photodiode and a first rail, the first rail being configured to receive a high supply potential; A switch coupled between the second terminal of the photodiode and a second rail, the second rail being configured to receive a reference potential; A read circuit configured to provide a pulse when the photodiode enters avalanche; And A control circuit configured to, in response to the start of the pulse, control the opening of the switch and, in response to the end of the pulse, control the closing of the switch; Wherein the control circuit includes a logic gate having an input and an output, the input being configured to receive the pulse and the output being configured to provide a control signal to the switch; Wherein the control circuit is further configured to, during a transition of the control signal that causes the switch to close, control the slope of the control signal according to a value of a slope adjustment potential; Wherein the control circuit includes a MOS transistor connected between a supply terminal of the control circuit and a first supply terminal of the logic gate of the control circuit, and a gate of the MOS transistor is configured to receive the slope adjustment potential.

2. The device according to claim 1, wherein the switch is a MOS transistor.

3. The device according to claim 1, configured to interrupt a conduction path that couples the second terminal of the photodiode to the second rail via the switch as long as a deactivation signal for deactivating the device is in a first state.

4. The device according to claim 3, further comprising: An additional switch connected in series with the switch between the second terminal of the photodiode and the second rail, the additional switch being configured to deactivate the device in response to the deactivation signal.

5. The device according to claim 3, wherein the logic gate of the control circuit includes an input configured to receive the deactivation signal for deactivating the device.

6. The device according to claim 1, wherein the control circuit is further configured to keep the switch closed as long as a deactivation signal for deactivating the control circuit is in a first state, and the logic gate of the control circuit includes an input configured to receive the deactivation signal for deactivating the control circuit.

7. The device according to claim 1, wherein the gate of the MOS transistor is configured to receive a deactivation signal for deactivating the control circuit.

8. The device according to claim 1, further comprising a capacitive bridge voltage divider connected between the first terminal of the photodiode and the second rail, and an input terminal of the read circuit is connected to an intermediate node of the capacitive bridge voltage divider.

9. The device according to claim 8, wherein the read circuit is further configured to modify a duration of the pulse according to a value of a pulse duration adjustment potential.

10. The device according to claim 9, wherein the reading circuit includes MOS transistors, the MOS transistors being connected between a power supply terminal of the reading circuit and the intermediate node, and a gate of the MOS transistors being configured to receive the pulse duration adjustment potential.

11. The device according to claim 8, wherein the reading circuit includes a logic gate having an input terminal coupled to the intermediate node and an output terminal configured to provide the pulse.

12. The device according to claim 1, wherein the reading circuit and the control circuit are respectively connected between the second rail and the third rail, the third rail being configured to receive a low supply potential.

13. The device according to claim 1, further comprising a potential limiting circuit configured to limit a maximum level of a potential on the second terminal of the photodiode, the potential limiting circuit including an additional photodiode connected between the second terminal of the photodiode and a node configured to receive an intermediate supply potential.

14. The device according to claim 1, further comprising a capacitor connected between the second terminal of the photodiode and the second rail.

15. An image sensor, comprising: a plurality of devices arranged in a pixel matrix of the image sensor, each of the plurality of devices including: a photodiode having a first terminal and a second terminal; a resistor coupled between the first terminal of the photodiode and a first rail configured to receive a high supply potential; a switch coupled between the second terminal of the photodiode and a second rail configured to receive a reference potential; a reading circuit configured to: provide a pulse when the photodiode enters avalanche; and a control circuit configured to: in response to a start of the pulse, control the switch to open, and in response to an end of the pulse, control the switch to close; wherein the control circuit includes a logic gate and a MOS transistor, the logic gate having an input and an output, the input being configured to receive the pulse, the output being configured to provide a control signal to the switch; the MOS transistor being connected between a power supply terminal of the logic gate of the control circuit and the second rail, a gate of the MOS transistor being configured to receive a deactivation signal for deactivating the control circuit.

16. The image sensor according to claim 15, wherein the reading circuit and the control circuit are respectively connected between the second rail and the third rail, the third rail being configured to receive a low supply potential.

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