Display device and power management integrated circuit

Abstract

The present invention provides a display device and a power management integrated circuit. The present invention relates to a power management integrated circuit for dynamically controlling the ripple of a driving voltage, which enables the power consumption of the power management integrated circuit to be reduced in an interval where there is no operation of a display.

Description

Technical Field

[0001] The present invention relates to a technique for dynamically controlling the ripple of a driving voltage of a power management integrated circuit. Background Art

[0002] The most important issue related to electronic devices including mobile devices is how to minimize power consumption. As electronic devices become miniaturized, power consumption needs to be reduced. For this reason, research on minimizing power consumption is ongoing. Display devices used in almost all electronic devices can be components that can significantly reduce power consumption. For a typical example, the quiescent current of the source driver can be reduced.

[0003] There are various ideas for reducing the current consumption of display devices. Most research focuses on minimizing the quiescent current present in integrated circuits to drive or control display devices. For a typical example, the quiescent current of the source driver can be reduced by reducing the frame rate of the display to maximize the length of the blanking section.

[0004] However, there is little research on minimizing the power consumption of the power management integrated circuit itself. The power consumption of the power management integrated circuit can also be reduced during the blanking interval when the display operation is not required. Like other driving circuits, the power management integrated circuit can be improved in terms of power consumption.

[0005] In this regard, the present invention is directed to providing techniques for reducing power consumption of a power management integrated circuit by improving management of ripple in the power supplied by the power management integrated circuit. Summary of the invention

[0006] In this context, an aspect of the present invention is to provide a technique for roughly managing the ripple of a driving signal supplied by a power management integrated circuit in an interval in which there is no operation of a display.

[0007] Another aspect of the present invention is to provide a technology for controlling a ripple period of a driving voltage to be longer in an interval in which there is no operation of a display.

[0008] Still another aspect of the present invention is to provide a technique for reducing the number of times a driving voltage is output in an interval in which there is no operation of a display.

[0009] To this end, on the one hand, a display device is provided, comprising: a panel including pixels to which image data is output; a data driving circuit for applying a data voltage corresponding to the image data to the pixels in a first time interval, and not applying the data voltage to the pixels in a second time interval; and a power management integrated circuit for converting power supplied from the outside to generate a driving voltage, and outputting the driving voltage to the data driving circuit, wherein the power management integrated circuit controls the fluctuation range of the driving voltage in the second time interval to be wider than the fluctuation range of the driving voltage in the first time interval.

[0010] In the display device, the power management integrated circuit may receive a timing control signal including timings of the first time interval and the second time interval, and output the driving voltage in the first time interval or in the second time interval according to the timing.

[0011] In the display device, the timing control signal may be generated in the data driving circuit or a data processing circuit for controlling the data driving circuit, and transmitted to the power management integrated circuit.

[0012] In the display device, the fluctuation range includes a peak value as a maximum level value of the driving voltage and a threshold value as a minimum level value of the driving voltage, and when the driving voltage is being output, the level of the driving voltage can rise or fall between the threshold value and the peak value.

[0013] In the display device, the power management integrated circuit may control the threshold value in the second time interval to be lower than the threshold value in the first time interval.

[0014] In the display device, the power management integrated circuit can stop generating the driving voltage during a skip period in which the level of the driving voltage drops from the peak value to the threshold value, and generate the driving voltage during a driving period in which the level of the driving voltage rises from the threshold value to the peak value.

[0015] In the display device, when the level of the driving voltage reaches the threshold value, the power management integrated circuit may start converting the power.

[0016] In the display device, when the level of the driving voltage reaches the peak value, the power management integrated circuit may stop converting the power.

[0017] In the display device, the skip period may be longer than the driving period.

[0018] In the display device, as the threshold value of the second time interval becomes lower, the power management integrated circuit may control the skip cycle of the second time interval to be longer.

[0019] In the display device, as the threshold value of the second time interval becomes lower, the power management integrated circuit may control the number of alternations of the driving cycle and the skipping cycle in the second time interval to be smaller.

[0020] In the display device, the driving voltage may form a ripple by the level of the driving voltage rising or falling between the threshold and the peak value, the ripple may have a ripple amplitude which is the distance between the threshold and the peak value, and the ripple amplitude of the second time interval may be greater than the ripple amplitude of the first time interval.

[0021] On the other hand, a power management integrated circuit includes: a power stage for converting power supplied from the outside to generate a driving voltage and outputting the driving voltage; and a power control circuit for receiving a timing control signal including a timing of a first time interval and a second time interval, and controlling the output of the driving voltage, wherein a data voltage corresponding to image data is applied to a pixel in the first time interval, and the data voltage is not applied to the pixel in the second time interval, wherein the power control circuit determines the first time interval and the second time interval according to the timing, and controls the driving voltage so that the fluctuation range of the driving voltage in the second time interval is greater than the fluctuation range of the driving voltage in the first time interval.

[0022] In the power management integrated circuit, the fluctuation range includes a peak value as the maximum level value of the driving voltage and a threshold value as the minimum level value of the driving voltage, and the power control circuit can control the threshold value in the second time interval to be lower than the threshold value in the first time interval.

[0023] In the power management integrated circuit, when the level of the driving voltage reaches the threshold, the power stage may convert the power.

[0024] In the power management integrated circuit, when the level of the driving voltage reaches the peak value, the power stage may stop converting the electric power.

[0025] As described above, the present invention enables the power consumption of the power management integrated circuit to be reduced in the interval where the display does not operate. In addition, the present invention enables the power consumption to be reduced as much as the number of outputs of the drive voltage supplied by the power management integrated circuit in the interval where the display does not operate. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a structural diagram of a display device according to an embodiment;

[0027] Figure 2 is a structural diagram of a display device including a timing control signal according to an embodiment;

[0028] Figure 3 is a diagram showing a timing control signal and corresponding changes in power consumption and load according to an embodiment;

[0029] Figure 4 is a diagram showing supplied power, driving voltage, and driving voltage control signals in a display driving interval and a display non-driving interval according to a conventional technique;

[0030] Figure 5 is a diagram showing a comparison of supply power, drive voltage, and drive voltage control signal in a display drive interval and a display non-drive interval according to a conventional technique;

[0031] Figure 6 is a diagram showing the supply power, the driving voltage, and the driving voltage control signal in the display driving interval and the display non-driving interval according to the embodiment;

[0032] Figure 7 is a diagram showing a comparison of supply power, drive voltage, and drive voltage control signal in a display drive interval and a display non-drive interval according to the embodiment; and

[0033] Figure 8 is a structural diagram of a power management integrated circuit according to an embodiment. DETAILED DESCRIPTION

[0034] Figure 1 is a structural diagram of a display device according to an embodiment.

[0035] refer to Figure 1 , the display device 100 may include a panel 110 , a data driving circuit 120 , a gate driving circuit 130 , a data processing circuit 140 , and a power management integrated circuit (PMIC) 150 .

[0036] On the panel 110 , a plurality of data lines DL and a plurality of gate lines GL may be arranged, and a plurality of pixels P may also be arranged.

[0037] The gate driving circuit 130 may supply a scanning signal of an on voltage or an off voltage through the gate line GL. When the scanning signal of an on voltage is supplied to the pixel P, the pixel P is connected to the data line DL, and when the scanning signal of an off voltage is supplied to the pixel P, the pixel P is disconnected from the data line DL.

[0038] The data driving circuit 120 supplies a data voltage through the data line DL. The data voltage supplied through the data line DL is transmitted to the pixel P connected to the data line DL according to the scan signal.

[0039] The data processing circuit 140 may supply various control signals to the gate driving circuit 130 and the data driving circuit 120. The data processing circuit 140 may generate a gate control signal GCS for initiating scanning according to the timing for each frame, and send the gate control signal GCS to the gate driving circuit 130. The data processing circuit 140 may convert image data RGB input from the outside into image data RGB in a data format used in the data driving circuit 120, and output the converted image data RGB to the data driving circuit 120. In addition, the data processing circuit 140 may send a data control signal DCS to control the data driving circuit 120 to supply a data voltage to each pixel P at an appropriate timing.

[0040] On the other hand, the data driving circuit 120 may be referred to as a source driver, the gate driving circuit 130 may be referred to as a gate driver, and the data processing circuit 140 may be referred to as a timing controller. The data driving circuit 120 may be included in one integrated circuit together with the pixel sensing circuit and is referred to as a source driver integrated circuit (IC). In addition, the data driving circuit 120, the pixel sensing circuit, and the data processing circuit may be included in one integrated circuit and is referred to as a combined IC. Although the present invention is not limited thereto, in the following description of the embodiments, descriptions related to some well-known components of the source driver, the gate driver, or the timing controller will be omitted. Therefore, the description of the embodiments should be understood in view of the fact that descriptions related to some such components are omitted.

[0041] The power management integrated circuit 150 may supply power to the panel 110, the data driving circuit 120, the gate driving circuit 130, and the data processing circuit 140. The power management integrated circuit 150 may supply power to the panel 110, the data driving circuit 120, the gate driving circuit 130, and the data processing circuit 140 by sending a driving voltage DRV to the panel 110, the data driving circuit 120, the gate driving circuit 130, and the data processing circuit 140 via a power line. The driving voltages DRV having different voltage values ​​may be supplied to the corresponding circuits, respectively. The power management integrated circuit 150 may be used as a power source for the panel 110, the data driving circuit 120, the gate driving circuit 130, and the data processing circuit 140.

[0042] The panel 110 may be an organic light emitting display panel. In this case, each pixel P arranged on the panel 110 may include an organic light emitting diode (OLED) and at least one transistor. The characteristics of the organic light emitting diode OLED and at least one transistor included in each pixel P may vary according to time or surrounding environment.

[0043] Figure 2 is a structural diagram of a display device including a timing control signal according to an embodiment.

[0044] refer to Figure 2 , the timing control signal DIS_T may be input from the data driving circuit 120 or the data processing circuit 140 to the power management integrated circuit 150 .

[0045] The timing control signal DIS_T may be generated in the data driving circuit 120 or the data processing circuit 140 and transmitted to the power management integrated circuit 150 .

[0046] The timing control signal DIS_T may include information related to an operating condition of the panel 110. The timing control signal DIS_T will be described in detail below.

[0047] The power management integrated circuit 150 may receive the timing control signal DIS_T and control the driving voltage DRV according to the operating conditions of the panel 110. Preferably, the power management integrated circuit 150 may adjust the fluctuation range of the driving voltage DRV in different ways according to the operating conditions of the panel 110.

[0048] Figure 3 is a diagram showing a timing control signal and corresponding changes in power consumption and load according to an embodiment.

[0049] Figure 3 The relationship among the timing control signal DIS_T, the power PWR supplied by the power management integrated circuit or the power PWR consumed in the display device, and the load LD on the power management integrated circuit is shown.

[0050] The timing control signal DIS_T can instruct the panel ( Figure 1 For example, the timing control signal DIS_T may indicate a display driving interval DISPLAY_ON and a non-driving interval DISPLAY_OFF. The display driving interval DISPLAY-ON may be an interval in which the data driving circuit ( Figure 1 120) driver panel ( Figure 1110), for example, the data driving circuit supplies a data voltage corresponding to the image data to the pixel. The display non-driving interval DISPLAY_OFF may be an interval in which the data driving circuit ( Figure 1 120) neither drives the panel ( Figure 1 In the display non-driving interval DISPLAY_OFF, operations other than panel driving can be performed. For example, pixels or touch can be sensed in the display non-driving interval DISPLAY_OFF.

[0051] The timing control signal DIS_T may be a horizontal synchronization signal HSYNC or a vertical synchronization signal VSYNC. The display driving interval DISPLAY_ON and the display non-driving interval DISPLAY_OFF may correspond to an interval where a data voltage is applied and an interval where a data voltage is not applied, respectively, as indicated by the horizontal synchronization signal HSYNC or the vertical synchronization signal VSYNC.

[0052] The power consumed by the display device in the display drive interval DISPLAY_ON may be different from the power consumed by the display device in the display non-drive interval DISPLAY_OFF. In the display drive interval DISPLAY_ON, a relatively larger amount of power may be consumed than in the display non-drive interval DISPLAY_OFF. The reason is that in the display drive interval DISPLAY_ON, various circuits work to drive the panel, while in the display non-drive interval DISPLAY_OFF, relatively fewer circuits work. In the figure, the power PWR consumed in the display device corresponding to the display drive interval DISPLAY_ON is indicated by high (HIGH), and the power PWR corresponding to the display non-drive interval DISPLAY_OFF is indicated by low (LOW) (shaded interval).

[0053] In each interval, the power consumption PWR can correspond to the power management integrated circuit ( Figure 1 The power PWR consumed by the circuit in the display driving interval DISPLAY_ON may be the same as the power PWR supplied to the circuit in the display driving interval DISPLAY_ON.

[0054] For example, in the display driving interval DISPLAY_ON, the gate driving circuit ( Figure 1 130), a data processing circuit for generating image data ( Figure 1 140 in the figure), a data driving circuit ( Figure 1120 in), and a touch sensing circuit (not shown) for sensing touch may require power. Figure 1 150) in can supply power to such a circuit.

[0055] On the contrary, in the display non-driving interval DISPLAY_OFF, since there is no panel driving, only the touch sensing circuit (not shown) (which is used to sense touch) may require power. Figure 1 150) in can supply power only to the touch sensing circuit.

[0056] As mentioned above, the power management integrated circuit ( Figure 1 The power supplied in the display driving interval DISPLAY_ON or the display non-driving interval DISPLAY_OFF may mean the power consumed in each interval. Therefore, although the power PWR is described as the power management integrated circuit ( Figure 1 150) in the figure, but this is not limited to this and can be understood as the power consumed in the display device.

[0057] The load LD on the power management integrated circuit may be different in the display driving interval DISPLAY_ON and the display non-driving interval DISPLAY_OFF.

[0058] The load LD in the display driving interval DISPLAY_ON may be greater than the load LD in the display non-driving interval DISPLAY_OFF. Since various circuits operate to drive the panel in the display driving interval DISPLAY_ON and these circuits are loads, the load may increase as the number of circuits in operation increases. Conversely, since relatively few circuits as loads operate in the display non-driving interval DISPLAY_OFF, the load may decrease as the number of circuits in operation decreases. Figure 1 In the figure, the load LD in the display driving interval DISPLAY_ON can be large, and can be small in the display non-driving interval DISPLAY_OFF. In this figure, the load LD in the display driving interval DISPLAY_ON is indicated by heavy (HEAVY), and the load LD in the display non-driving interval DISPLAY_OFF is indicated by light (LIGHT) (shaded interval).

[0059] Depending on the panel operation, the power management integrated circuit ( Figure 1 The power PWR supplied by 150) and applied to the power management integrated circuit ( Figure 1For example, as the display driving interval DISPLAY_ON and the display non-driving interval DISPLAY_OFF alternate, the supply power PWR may alternate between a high state and a low state, and the load LD may also alternate between a heavy state and a light state according to the alternation of the supply power PWR.

[0060] Figure 4 : is a diagram showing the supply power, the driving voltage, and the driving voltage control signal in the display driving section and the display non-driving section according to the conventional technology.

[0061] A conventional power management integrated circuit can output a driving voltage with a ripple of uniform amplitude in both the display driving interval DISPLAY_ON and the display non-driving interval DISPLAY_OFF. However, the period of the ripple may be longer in the display non-driving interval DISPLAY_OFF than in the display driving interval DISPLAY_ON.

[0062] The power PWR to be supplied can be transmitted from the power management integrated circuit to the external circuit in the form of a drive voltage DRV. The power management integrated circuit outputs some drive voltages immediately when it generates them. The power management integrated circuit can also store some other voltages generated during a predetermined time period in the capacitor and output these other voltages from the capacitor. For example, the generated voltage can be output in the first period, and the stored voltage can be output in the second period.

[0063] When the stored voltage is output so that the capacitor is discharged, the level of the driving voltage DRV may decrease. Since the operation of the external circuit is unstable when the level of the driving voltage is too low, the power management integrated circuit may generate a voltage again when the level of the driving voltage DRV decreases to a threshold value. The generated voltage may be stored in the capacitor. The level of the driving voltage DRV may be increased to a peak value again. The power management integrated circuit ( Figure 1 The power management integrated circuit (105 in FIG. 1 ) can stably supply power to the external circuit by increasing the level of the driving voltage DRV. When the level of the driving voltage increases to a peak value, the power management integrated circuit (105 in FIG. 1 ) can stop generating voltage. At this time, the stored voltage can be taken out from the capacitor and output as the driving voltage DRV.

[0064] As described above, the driving voltage may be generated at fixed intervals during a predetermined period of time, and may not be generated during the above intervals. However, regardless of whether the driving voltage is generated, the driving voltage is continuously output.

[0065] The peak value and the threshold value may define the fluctuation range of the level of the driving voltage DRV to be output. The peak value and the threshold value may be the upper limit and the lower limit of the level of the driving voltage. The peak value and the threshold value may be the maximum level and the minimum level of the driving voltage.

[0066] When the generated voltage and the stored voltage are alternately output, the driving voltage DRV may have ripples. Since the charging time of charging the capacitor with the generated voltage is delayed, the level of the driving voltage DRV may not immediately reach the desired value, but may slowly increase to the value. In addition, since the discharge time of discharging the capacitor is delayed, when the driving voltage is output, the level of the driving voltage may not immediately drop to the desired value, but may slowly decrease to the value. Repeating this increase and decrease in the level of the driving voltage may form ripples.

[0067] In power management integrated circuits ( Figure 1 In the case where the power PWR supplied by 150) is small, the discharge time delay may be longer than when the power PWR is large. In addition, when the load LOAD to which the power PWR needs to be supplied is light, the discharge time delay may be longer than when the load LOAD is heavy.

[0068] The driving voltage DRV is generated whenever the level of the driving voltage drops to the threshold value. Here, since the generation of the driving voltage increases the level of the driving voltage DRV, the generation may be referred to as "boosting of the driving voltage".

[0069] The generation (boosting) of the drive voltage may result in the power management integrated circuit ( Figure 1 Here, the power management integrated circuit ( Figure 1 The power consumption and power supply PWR in 150 of FIG. 1 may have different meanings. The power supply PWR may mean the power supplied by the power management integrated circuit ( Figure 1 The power consumed may refer to the power supplied to the external circuit or consumed by the external circuit by the power management integrated circuit ( 150 in ), and the power consumed may refer to the power consumed by the power management integrated circuit ( Figure 1 The additional power consumed internally by the 150).

[0070] Here, frequent generation (boosting) of the driving voltage DRV may increase power consumption of the power management integrated circuit ( 150 in FIG. 1 ).

[0071] refer to Figure 4According to the operation of the panel indicated by the timing control signal DIS_T, the supplied (or consumed) power PWR may be high in the display driving interval DISPLAY_ON and relatively low in the display non-driving interval DISPLAY_OFF.

[0072] However, the fluctuation range of the driving voltage DRV may be the same in the display driving interval DISPLAY_ON and the display non-driving interval DISPLY_OFF. That is, when the driving voltage DRV is output, the driving voltage DRV may fluctuate between the same peak value and the same threshold value in the two intervals.

[0073] The driving voltage DRV may be intermittently generated in the display non-driving interval DISPLAY_OFF and may be frequently generated in the display driving interval DISPLAY_ON. In other words, the number of times of generation in the display non-driving interval DISPLAY_OFF may be smaller than the number of times of generation in the display driving interval DISPLAY_ON.

[0074] For example, when the display driving interval DISPLAY_ON and the display non-driving interval DISPLAY_OFF have the same duration, the driving voltage DRV may be generated eleven times b1 to b11 in the display driving interval DISPLAY_ON, and may be generated four times B12 to B15 in the display non-driving interval DISPLAY_OFF.

[0075] Since the load is heavy in the display drive interval DISPLAY_ON and the power PWR consumed due to the load is high, the time period for the level of the driving voltage to drop from the peak value to the threshold value may be short. On the contrary, since the load is light in the display non-driving interval DISPLAY_OFF and the power PWR consumed due to the load is low, the time period for the level of the driving voltage to drop from the peak value to the threshold value may be long. Since the level of the driving voltage drops more slowly in the display non-driving interval DISPLAY_OFF than in the display driving interval DISPLAY_ON, the driving voltage DRV can be generated less frequently in the display non-driving interval DISPLAY_OFF than in the display driving interval DISPLAY_ON. Therefore, the period of the ripple can be longer in the display non-driving interval DISPLAY_OFF than in the display driving interval DISPLAY_ON.

[0076] The driving voltage control signal CTR_DRV may include information for adjusting the fluctuation range of the driving voltage DRV. The driving voltage control signal CTR_DRV may determine the fluctuation range in the display driving interval DISPLAY_ON and the display non-driving interval DISPLAY_OFF by changing its level.

[0077] According to conventional technology, the fluctuation ranges in both the display driving interval DISPLAY_ON and the display non-driving interval DISPLAY_OFF may be the same, which means that the driving voltage control signal CTR_DRV may have the same level for both the display driving interval DISPLAY_ON and the display non-driving interval DISPLAY_OFF.

[0078] Figure 5 : is a diagram showing a comparison of supply power, drive voltage, and drive voltage control signal between a display driving section and a display non-driving section according to a conventional technique.

[0079] refer to Figure 5 According to conventional technology, the driving voltage may have the same fluctuation range in the display driving interval DISPLAY_ON and the display non-driving interval DISPLAY_OFF. The fluctuation range may affect the period and amplitude of the ripple.

[0080] The driving voltage may have a ripple amplitude h in the display driving voltage DISPLAY_ON and the display non-driving voltage DISPLAY_OFF. When the driving voltage is generated, the level of the driving voltage may increase from the first threshold Vth to the peak value Vpeak, and when the generation stops, the level of the driving voltage may decrease from the peak value Vpeak to the first threshold Vth. The ripple amplitude h may correspond to the difference between the first threshold Vth and the peak value Vpeak. The voltage of the driving voltage may maintain the ripple amplitude h in both the display driving interval DISPLAY_ON and the display non-driving interval DISPLAY_OFF while the voltage of the driving voltage alternately rises and falls.

[0081] However, the level of the driving voltage DRV may have different ripple periods in the display driving interval DISPLAY_ON and the display non-driving interval DISPLAY_OFF. The ripple period in the display non-driving interval DISPLAY_OFF may be longer than the ripple period in the display driving interval DISPLAY_ON.

[0082] The ripple period of the level of the driving voltage may include a driving period and a skip period. The driving period is a period for generating the driving voltage DRV, and the skip period is a period for stopping the generation of the driving voltage. The skip period in the display non-driving interval DISPLAY_OFF is much longer than the skip period in the display driving interval DISPLAY_ON. Therefore, the ripple period in the display non-driving interval DISPLAY_OFF may be longer than the ripple period in the display driving interval DISPLAY_ON.

[0083] For example, the ripple period T1 in the display driving interval DISPLAY_ON may include a driving period T1d and a skip period T1s. The ripple period T2 in the display non-driving interval DISPLAY_OFF may also include a driving period T2d and a skip period T2s. Since the load is light and the power consumption is low in the display non-driving interval DISPLAY_OFF, the level of the driving voltage may drop more slowly than in the display driving interval DISPLAY_ON. Therefore, the skip period T2s in the display non-driving interval DISPLAY_OFF may be longer than the skip period T1s in the display driving interval DISPLAY_ON.

[0084] When the ripple periods in the display driving interval DISPLAY_ON and the display non-driving interval DISPLAY_OFF are different, the ripple frequencies of the driving voltage levels in the display driving interval DISPLAY_ON and the display non-driving interval DISPLAY_OFF may be different. The ripple frequency in the display non-driving interval DISPLAY_OFF may be smaller than the ripple frequency in the display driving interval DISPLAY_ON.

[0085] Figure 6 : is a diagram showing the supply power, the driving voltage, and the driving voltage control signal in the display driving interval and the display non-driving interval according to the embodiment.

[0086] According to an embodiment of the invention, a power management integrated circuit ( Figure 1 150) can control the fluctuation range of the driving voltage DRV in the display non-driving interval DISPLAY_OFF to be wider than the fluctuation range of the driving voltage according to the conventional technology. Preferably, the fluctuation range in the display non-driving interval DISPLAY_OFF can be set to be wider than the fluctuation range in the display driving interval DISPLAY_ON.

[0087] When the fluctuation range in the display non-driving interval DISPLAY_OFF is wider than that in the display driving interval DISPLAY_ON, the ripple period in the display non-driving interval DISPLAY_OFF may be longer than the ripple period according to the conventional technology in which the fluctuation ranges in the display driving interval and the display non-driving interval are the same.

[0088] In addition, the ripple amplitude in the display non-driving interval DISPLAY_OFF may be larger than the ripple amplitude according to the conventional technology, and preferably may be larger than the ripple amplitude in the display driving interval DISPLAY_ON.

[0089] As the fluctuation range in the display non-driving interval DISPLAY_OFF becomes wider, the number of times the driving voltage DRV is generated can be reduced, and as the number of times the generation is reduced, the power management integrated circuit ( Figure 1 The power consumption in 150) can be reduced. That is, when the number of times the driving voltage DRV is generated is reduced, the power consumption caused by generating the driving voltage DRV can be reduced. In addition, the ripple of the driving voltage DRV can be flexibly managed.

[0090] refer to Figure 6 , the level of the driving voltage DRV in the display non-driving interval DISPLAY_OFF can rise or fall between the peak value and a threshold value lower than the threshold value according to the conventional technology. When the reference value (i.e., the threshold value) indicating the start of generating the driving voltage DRV becomes lower, the range between the peak value and the threshold value can be wider than the range between the two according to the conventional technology.

[0091] The ripple period in the display non-driving interval DISPLAY_OFF may be longer as the fluctuation range of the ripple becomes wider. Preferably, the ripple period may be longer as the threshold becomes lower. The reason is that it takes more time for the level of the driving voltage to drop to the threshold.

[0092] The number of times the driving voltage is generated (boosted) in the display non-driving interval DISPLAY_OFF can be reduced as the fluctuation range becomes wider. For example, according to conventional technology, four times ( Figure 4 b12-b15) driving voltage DRV, while according to the embodiment of the present invention, the driving voltage DRV is only generated twice (b12' and b13').

[0093] On the other hand, the driving voltage control signal CTR_DRV may include information for widening the fluctuation range of the driving voltage in the display non-driving interval DISPLAY_OFF.

[0094] For example, in order to include information for adjusting the fluctuation range in the display non-driving interval DISPLAY_OFF to be wider than the fluctuation range in the display driving interval DISPLAY_ON, the driving voltage control signal CTR_DRV may have different levels in the display non-driving interval DISPLAY_OFF. Figure 1 The power stage (powerstage) of 150) in FIG. 1 can reduce the threshold value for determining the fluctuation range in the display non-driving interval DISPLAY_OFF according to the level of the driving voltage control signal CTR_DRV.

[0095] Figure 7 : is a diagram showing a comparison of the supply power, the driving voltage, and the driving voltage control signal between the display driving section and the display non-driving section according to the embodiment.

[0096] refer to Figure 7 , Power Management Integrated Circuit ( Figure 1 150 in the figure) can control the driving voltage DRV so that its fluctuation range in the display non-driving interval DISPLAY_OFF is wider than its fluctuation range in the display driving interval DISPLAY_ON. Preferably, the power management integrated circuit ( Figure 1 150) can control the lower limit of the fluctuation range in the display non-driving interval DISPLAY_OFF to be lower than the lower limit of the fluctuation range in the display driving interval DISPLAY_ON. The power management integrated circuit ( Figure 1 150) in the method may set the second threshold value Vth' indicating the start of generating the driving voltage to be lower than the first threshold value Vth.

[0097] When the lower limit of the fluctuation range of the driving voltage DRV in the display non-driving interval DISPLAY_OFF decreases by the second threshold Vth', the ripple amplitude of the driving voltage may be widened. The ripple amplitude h' in the display non-driving interval DISPLAY_OFF may be wider than the ripple amplitude h in the display driving interval DISPLAY_ON.

[0098] In addition, the ripple period T2′ in the display non-driving interval DISPLAY_OFF according to the present invention can be longer than the ripple period (T2′) in the display non-driving interval according to the conventional technology. Figure 5 When the level of the driving voltage DRV decreases to a second threshold value Vth' lower than the first threshold value Vth, the skip period T2s' in the display non-driving interval DISPLAY_OFF according to the present invention may be longer than the skip period ( Figure 5 in T2s).

[0099] On the contrary, the ripple frequency in the display non-driving interval DISPLAY_OFF according to the present invention can be lower than the ripple frequency in the display non-driving interval according to the conventional technology. Since the ripple period T2' in the non-driving section DISPLAY_OFF is longer than the ripple period when the fluctuation range is not wide, the ripple frequency can be lower because the period is inversely proportional to the frequency.

[0100] Figure 8 is a structural diagram of a power management integrated circuit according to an embodiment.

[0101] refer to Figure 8 , the power management integrated circuit 150 may include a power control circuit 151 and a power stage 152 .

[0102] The power control circuit 151 may receive a control signal including a timing control signal DIS_T. The control signal may be received by the data drive circuit ( Figure 1 120) or data processing circuit ( Figure 1 140) and is sent to the power control circuit 151. The timing control signal DIS_T may indicate whether the panel is operating in a first time interval in which a data voltage for image data is applied or in a second time interval in which the data voltage is not applied. Here, the first time interval may be referred to as a display drive interval, and the second time interval may be referred to as a display non-drive interval (blanking interval). The power control circuit 151 may generate a drive voltage control signal CTR_DRV according to the timing indicated by the timing control signal DIS_T to determine the fluctuation range of the drive voltage in each interval.

[0103] The power stage 152 can receive the power signal PW and convert the power signal PW into a driving voltage DRV suitable for the driving circuit. For example, for the data driving circuit ( Figure 1 120 in), gate drive circuit ( Figure 1 130) and data processing circuit ( Figure 1 140), different driving voltages can be generated. That is, the driving voltages have different voltage values ​​or different voltage ranges according to the circuits.

[0104] The power stage 152 may output a driving voltage DRV. The power stage 152 may convert the power signal PW into the driving voltage DRV. In other words, the power stage 152 may generate the driving voltage. Since the driving voltage is generated when it is continuously supplied to the external circuit, the level of the driving voltage may increase from low to high.

[0105] The power stage 152 may not convert the power signal PW into a driving voltage. In other words, the power stage 152 may not generate a driving voltage. Since the driving voltage is not generated while being continuously supplied to an external circuit, the level of the driving voltage may decrease from high to low.

[0106] The level of the driving voltage may rise or fall between low and high. Such rise and fall of the level of the driving voltage may form ripples.

[0107] The power control circuit 151 may generate a driving voltage control signal CTR_DRV for controlling the power stage 152, and send the driving voltage control signal CTR_DRV to the power stage 152. The driving voltage control signal CTR_DRV may include information for determining the fluctuation range of the driving voltage DRV. The power control circuit 151 may use the driving voltage control signal CTR_DRV to adjust a peak value as an upper limit of the fluctuation range and a threshold value as a lower limit of the fluctuation range.

[0108] For example, the power control circuit 151 may send a drive voltage control signal CTR_DRV to the power stage 152 to reduce the threshold of the fluctuation range. The power stage 152 may output the drive voltage DRV based on the reduced threshold instead of the original threshold. At the beginning of the display non-driving interval, the power stage 152 may convert the power, and the level of the drive voltage DRV may increase to a peak value. When the level of the drive voltage reaches a peak value, the power stage 152 may stop converting the power, and the level of the drive voltage DRV may be reduced to a reduced threshold lower than the original threshold.

[0109] The timing control signal may be a synchronization signal or a signal caused by a synchronization signal. For example, the timing control signal may be a horizontal synchronization signal HSYNC, a vertical synchronization signal VSYNC, or a signal caused by a horizontal synchronization signal HSYNC or a vertical synchronization signal VSYNC. The power management integrated circuit may receive the horizontal synchronization signal and generate the timing control signal using an internal clock signal. Alternatively, the power management integrated circuit may receive the vertical synchronization signal VSYNC and generate the timing control signal using an internal clock signal.

[0110] CROSS-REFERENCE TO RELATED APPLICATIONS

[0111] This application claims the benefit of Korean Patent Application No. 10-2019-0126924, filed on October 14, 2019, which is hereby incorporated by reference in its entirety.

Claims

1. A display device, comprising: a panel including pixels to which image data is output; a data driving circuit, configured to apply a data voltage corresponding to the image data to the pixel in a first time interval, and not apply the data voltage to the pixel in a second time interval; as well as a power management integrated circuit for converting power supplied from the outside to generate a driving voltage, and outputting the driving voltage to the data driving circuit, The power management integrated circuit controls the fluctuation range of the driving voltage in the second time interval to be wider than the fluctuation range of the driving voltage in the first time interval. wherein the fluctuation range in at least one of the first time interval or the second time interval includes a peak value as a maximum level value of the driving voltage and a threshold value as a minimum level value of the driving voltage, and while the driving voltage is being output, the level of the driving voltage rises or falls between the threshold value and the peak value, The power management integrated circuit controls the threshold in the second time interval to be lower than the threshold in the first time interval.

2. The display device according to claim 1, wherein: The power management integrated circuit receives a timing control signal including timings of the first time interval and the second time interval, and outputs the driving voltage in the first time interval or in the second time interval according to the timing.

3. The display device according to claim 2, wherein: The timing control signal is generated in the data driving circuit or a data processing circuit for controlling the data driving circuit, and is sent to the power management integrated circuit.

4. The display device according to claim 1, wherein: The power management integrated circuit stops generating the driving voltage during a skip period in which a level of the driving voltage drops from the peak value to the threshold value, and generates the driving voltage during a driving period in which a level of the driving voltage rises from the threshold value to the peak value.

5. The display device according to claim 4, wherein: When the level of the driving voltage reaches the threshold, the power management integrated circuit starts converting the power.

6. The display device according to claim 5, wherein: When the level of the driving voltage reaches the peak value, the power management integrated circuit stops converting the power.

7. The display device according to claim 4, wherein: The skip period is longer than the driving period.

8. The display device according to claim 4, wherein: As the threshold value of the second time interval becomes lower, the power management integrated circuit controls the skip cycle of the second time interval to be longer.

9. The display device according to claim 4, wherein: As the threshold value of the second time interval becomes lower, the power management integrated circuit controls the number of alternations of the driving cycle and the skipping cycle in the second time interval to be smaller.

10. The display device according to claim 1, wherein: By the level of the driving voltage rising or falling between the threshold and the peak, the driving voltage forms a ripple having a ripple amplitude as the distance between the threshold and the peak, and the ripple amplitude in the second time interval is greater than the ripple amplitude in the first time interval.

11. A power management integrated circuit, comprising: A power stage for converting power supplied from the outside to generate a driving voltage, and outputting the driving voltage; as well as a power control circuit, configured to receive a timing control signal including a timing of a first time interval and a second time interval, and control the output of the driving voltage, wherein a data voltage corresponding to image data is applied to a pixel in the first time interval, and the data voltage is not applied to the pixel in the second time interval, The power control circuit determines the first time interval and the second time interval according to the timing, and controls the driving voltage so that the fluctuation range of the driving voltage in the second time interval is greater than the fluctuation range of the driving voltage in the first time interval. Wherein, the fluctuation range in at least one of the first time interval or the second time interval includes a peak value as the maximum level value of the driving voltage and a threshold value as the minimum level value of the driving voltage, and the power control circuit controls the threshold value in the second time interval to be lower than the threshold value in the first time interval.

12. The power management integrated circuit according to claim 11, wherein: When the level of the driving voltage reaches the threshold, the power stage converts the electric power.

13. The power management integrated circuit according to claim 11, wherein: When the level of the driving voltage reaches the peak value, the power stage stops converting the electric power.

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