Gate drive circuit for power transistors and motor controller

Abstract

This invention discloses a gate drive circuit for a power transistor and a motor controller. The gate drive circuit for the power transistor includes a driver chip and a control module. A first terminal of the control module is connected to the output terminal of the driver chip, and a second terminal is connected to the gate of the power transistor. This solves the technical problem of excessive switching losses during the power transistor's turn-on or turn-off process.

Description

Technical Field

[0001] This invention relates to the technical field of gate driving of power devices, and particularly to a gate driving circuit for a power transistor and a motor controller. Background Technology

[0002] Motor control equipment is widely used in electric vehicles, rail transportation, and industrial manufacturing. IGBTs (Insulated Gate Bipolar Transistors) / MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) are core components of these devices, and their drive technology is crucial, especially regarding the losses during the switching process. During the loss-generating phase, a larger gate current results in lower losses. In exemplary technologies, a combination of resistors and capacitors is used to form the drive circuit. While this ensures switching reliability, the gate current is relatively small during the loss-generating phase—specifically, the current and voltage change phases—leading to significant losses and reduced efficiency of the motor control equipment. Summary of the Invention

[0003] The main objective of this invention is to provide a gate drive circuit for a power transistor. This aims to solve the technical problem of excessive switching losses during the power transistor's turn-on or turn-off process.

[0004] To achieve the above objectives, this invention proposes a gate drive circuit for a power transistor, applied to a power transistor for driving the power transistor. The gate drive circuit for the power transistor comprises:

[0005] A driver chip, which is used to output a drive signal;

[0006] A control module, wherein the first end of the control module is connected to the output end of the driver chip, and the second end is connected to the gate of the power transistor;

[0007] During the turn-on or turn-off phase of the power transistor, the control module controls the gate current to rise with a delay, and during the drain current or drain voltage change phase, it extends the duration for which the gate current remains at the current peak value as much as possible.

[0008] Optionally, the control module adjusts the waveform of the gate current.

[0009] Optionally, the control module includes at least a damping unit for adjusting gate current oscillation and a current stabilizing unit for adjusting gate current waveform; the first end of the damping unit is connected to the driver chip, the second end is connected to the first end of the current stabilizing unit, and the second end of the current stabilizing unit is connected to the gate of the power transistor.

[0010] Optionally, the damping unit for adjusting the gate current oscillation consists of one or more resistors connected in series.

[0011] Optionally, the current stabilizing unit for adjusting the gate current waveform includes an inductor.

[0012] Optionally, the control module further includes a current amplification unit for adjusting the maximum current value, wherein the first end of the current amplification unit is connected to the driver chip, and the second end is connected to the first end of the current stabilization unit.

[0013] Optionally, the current amplification unit for adjusting the maximum current value includes a capacitor.

[0014] Optionally, it also includes a power supply module and a push-pull module. The first end of the push-pull module is connected to the driver chip, the second end is connected to the first end of the control module, and the third end is connected to the power supply module. The push-pull module amplifies the drive signal emitted by the driver chip.

[0015] Optionally, the motor control device is the push-pull module, which includes a first switch and a second switch. The first end of the first switch is connected to the first end of the power module, the first end of the second switch is connected to the second end of the power module, the second ends of the first switch and the second switch are respectively connected to the driver chip, and the third ends of the first switch and the second switch are respectively connected to the first end of the control module.

[0016] A motor controller comprising a gate drive circuit for a power transistor as described in any of the preceding claims.

[0017] This invention constructs a gate drive circuit for a power transistor by incorporating a driver chip and a control module. The driver chip outputs a drive signal to turn the power transistor on or off, while the control module maintains the gate current at its peak value. This slows down the rate at which the gate current rises to and falls from its maximum value, increases the gate current, accelerates the power transistor's on / off process, and reduces switching losses, thus solving the technical problem of excessive switching losses during power transistor on / off. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the gate drive circuit of the power transistor of the present invention.

[0020] Figure 2 This is a circuit diagram of an embodiment of the gate drive circuit for the power transistor of the present invention;

[0021] Figure 3 A circuit diagram of an embodiment of a gate drive circuit, which is an exemplary technology for IGBT / MOSFET gate drive circuits;

[0022] Figure 4 This is a schematic diagram comparing the parameters of the gate drive circuit of the power transistor of the present invention during the conduction phase with those of the gate drive circuit of an exemplary technology during the conduction phase.

[0023] Explanation of icon numbers:

[0024]

[0025] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0026] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0027] It should be noted that if the embodiments of the present invention involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

[0028] Furthermore, if the embodiments of this invention include descriptions such as "first," "second," etc., these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one such feature. Additionally, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is no longer within the scope of protection claimed by this invention.

[0029] To address the problem of excessive switching losses caused by low gate current during the di / dt stage (current change stage) and dv / dt voltage stage (voltage change stage) of a switching transistor during its turn-on or turn-off process, this invention provides a gate drive circuit for a power transistor, thereby solving the technical problem of excessive losses caused by low gate current during the loss generation stage of the switching transistor's turn-on or turn-off process.

[0030] The switching process of a transistor consists of four stages: a delay stage, a di / dt change stage (current change stage), a dv / dt change stage (voltage change stage), and a steady-state stage. Switching losses occur during the current change stage and the voltage change stage. A larger gate current results in a faster gate voltage change rate. A faster gate voltage change rate means a faster switching speed, which in turn shortens the current and voltage change stages during the switching process, resulting in lower losses.

[0031] refer to Figure 1 This invention proposes a gate drive circuit for a power transistor, which is applied to a power transistor. The gate drive circuit for the power transistor includes: a driver chip 00 and a control module 10. The first end of the control module 10 is connected to the output end of the driver chip 00, and the second end of the control module 10 is connected to the gate of the power transistor.

[0032] In this system, the driver chip 00 outputs a drive signal, and the control module 10 controls the gate current to maintain it at its peak value. During the switching process of the power transistor, the driver chip 00 outputs a drive signal to turn the power transistor on or off. The control module 10 delays the rate at which the gate current rises to its maximum value and decreases from its maximum value, thereby extending the duration of the gate current at its peak value during the on / off phase and maintaining the gate current at its peak value. A larger gate current results in a faster gate voltage change rate. A faster gate voltage change rate means a faster power transistor on / off speed, resulting in shorter current and voltage change phases during the on / off process and lower losses.

[0033] This invention constructs a gate drive circuit for a power transistor by setting up a driver chip 00 and a control module 10. The driver chip 00 outputs a drive signal to turn the power transistor on or off, and the control module 10 controls the gate current to maintain its peak value. This slows down the rate at which the gate current rises to and falls from its maximum value, increases the gate current, accelerates the turn-on or turn-off process of the power transistor, and reduces the switching losses of the power transistor, thereby solving the technical problem of excessive switching losses during the turn-on or turn-off process of the power transistor.

[0034] refer to Figure 2In one embodiment of the present invention, IGBT / MOSFET will be used as an example for explanation, and the driving process of the two switching devices is the same.

[0035] refer to Figure 3 The exemplary IGBT / MOSFET gate drive scheme controls the switching speed by adjusting the gate resistor or capacitor.

[0036] As voltage-controlled semiconductor devices, IGBTs and MOSFETs exhibit similar switching transient processes, and their driving methods are essentially the same. The switching process of an IGBT / MOSFET can be divided into several stages. The turn-on process consists of a turn-on delay stage, a di / dt rise stage (current rise stage), a dv / dt fall stage (voltage fall stage), and a stable turn-on stage. The turn-off process consists of a turn-off delay stage, a dv / dt rise stage (voltage rise stage), a di / dt fall stage (current fall stage), and a stable turn-off stage. During the switching process, switching losses occur during the di / dt (current change) stage and the dv / dt (voltage change) stage. The larger the gate current, the faster the gate voltage changes. A faster gate voltage change means a faster turn-on or turn-off speed, resulting in shorter current and voltage change stages during the turn-on or turn-off process and lower losses. To reduce switching losses, the gate current needs to be maintained at a relatively large value during these two stages. In the exemplary technology, at the beginning of the switching delay phase of the IGBT / MOSFET, the voltage difference between the drive voltage and the gate voltage is the largest, and the gate current is the largest. During the di / dt (current change) phase and dv / dt (voltage change) phase, the gate current drops to a smaller value, which increases the switching loss.

[0037] refer to Figure 2 In one embodiment of the present invention, the control module 10 adjusts the waveform of the gate current. The control module 10 includes a damping unit 11 and a current stabilizing unit 13. The first end of the damping unit 11 is connected to the driver chip 00, the second end of the damping unit 11 is connected to the first end of the current stabilizing unit 13, and the second end of the current stabilizing unit 13 is connected to the gate of the power transistor.

[0038] The damping unit 11 is used to adjust the gate current oscillation, and the current stabilizing unit 13 is used to stabilize the gate current waveform. Since the gate and emitter or gate and source of the power transistor are capacitive, and the parasitic inductance of the gate circuit is unavoidable, the gate circuit will form an LC oscillation circuit, generating strong oscillations during the power transistor's turn-on or turn-off process. Therefore, by setting the damping unit 11, this application can suppress gate voltage oscillations during the power transistor's turn-on or turn-off process, improving the reliability of the switch. Secondly, the current stabilizing unit 13 can suppress the rate of change of current during the power transistor's turn-on or turn-off process, maintaining the gate current at a relatively high value and reducing the power transistor's losses during turn-on or turn-off. Through the damping unit 11 and the current stabilizing unit 13, the gate voltage oscillation of the power transistor can be reduced. After passing through the current stabilizing unit 13, the rate of change of the gate current is reduced, keeping it at a relatively large value during the power transistor's turn-on and turn-off process, thereby reducing the switching losses of the power transistor.

[0039] refer to Figure 2 In one embodiment of the present invention, the damping unit includes one or more resistors connected in series.

[0040] In this invention, a damping unit is formed by setting a first resistor R1. The first end of the first resistor R1 is connected to the output terminal of the driver chip 00. By setting the first resistor R1, the LC oscillation formed between the parasitic inductance and gate capacitance of the gate drive circuit can be eliminated. In addition, R1 can also protect the power transistor and transfer power loss. Due to the presence of resistor R1, most of the drive voltage will drop across resistor R1, thereby effectively avoiding the possibility of excessive power loss and damage to the MOSFET caused by the drive voltage dropping across it.

[0041] refer to Figure 2 In one embodiment of the present invention, the current stabilizing unit for adjusting the gate current waveform includes an inductor.

[0042] In this invention, a current-stabilizing unit is formed by setting a first inductor L1. The first end of the first inductor L1 is connected to the second end of the first resistor R1, and the second end of the first inductor L1 is connected to the gate of the power transistor. When a direct current flows through the inductor, the inductor generates an induced magnetic field. Changes in the direct current cause changes in the magnetic flux of the induced magnetic field. The change in magnetic flux induces a voltage inside the inductor, and the voltage direction is opposite to the current direction. The induced voltage generates an induced current, and the induced current is opposite to the direct current direction. This can suppress changes in the direct current until the current no longer changes. The faster the direct current changes, the stronger the suppression effect of the inductor. In this application, through the first inductor L1, when the gate current starts to increase, according to the properties of the inductor, a current in the opposite direction to the gate current will be generated to suppress the change of the gate current. When the gate current increases, the rate of increase of the gate current is suppressed, and when the gate current decreases, the rate of decrease of the gate current is slowed down. In this way, the changes of the gate current in the di / dt (current change) stage and the dv / dt (voltage change) stage during the switching process of IGBT / MOSFET can be suppressed, the gate current decrease rate and decrease process can be slowed down, the gate current is kept at a large value, and the switching loss is reduced.

[0043] refer to Figure 2 In one embodiment of the present invention, the control module 10 further includes a current amplification unit 12. The first end of the current amplification unit 12 is connected to the output end of the driver chip, and the second end is connected to the first end of the current stabilization unit 13. The current amplification unit 12 includes a first capacitor C1. The first end of the first capacitor C1 is connected to the first end of the first resistor R1, and the second end of the first capacitor C1 is connected to the second end of the first resistor R1.

[0044] The current amplification unit 12 is used to adjust the maximum gate current value. The first capacitor C1 is connected in parallel with the first resistor R1. As an energy storage element, capacitor C1 effectively increases the amplitude of the gate current and its maximum value. The maximum gate current is directly proportional to the capacitance of capacitor C1; the larger the capacitance of C1, the larger the maximum gate current. Simultaneously, a smaller value of the first resistor R1 results in a larger gate current, faster switching speed, and lower losses. However, a small resistance of the first resistor R1 can cause gate voltage oscillation, reducing switching reliability. In this embodiment, the maximum gate current can be increased by increasing the value of the first capacitor C1. This, in turn, allows for a relative increase in the resistance of the first resistor R1, improving switching reliability and ensuring both a larger gate current and reliable switching.

[0045] refer to Figure 2In one embodiment of the present invention, the gate drive circuit of the power transistor further includes a power supply module and a push-pull module 20. The first end of the push-pull module 20 is connected to the output end of the driver chip 00, the second end of the push-pull module 20 is connected to the first end of the control module 10, and the third end of the push-pull module 20 is connected to the power supply module.

[0046] The push-pull module 20 amplifies the drive signal emitted by the driver chip. By amplifying the voltage value of the drive signal, the voltage of the power transistor can be increased, thereby accelerating the turn-on or turn-off speed and reducing switching losses.

[0047] refer to Figure 2 In one embodiment of the present invention, the push-pull module 20 includes a first switch Q1 and a second switch Q2. The first end of the first switch Q1 is connected to the first end of the power supply module, and the first end of the second switch Q2 is connected to the second end of the power supply module. The second ends of the first switch Q1 and the second switch Q2 are respectively connected to the output end of the driver chip 00. The third ends of the first switch Q1 and the third ends of the second switch Q2 are respectively connected to the first end of the control module 10. The first end of the power supply module is the driving voltage VCC, and the second end of the power supply module is the turn-off voltage VEE.

[0048] The drive signal output by driver chip 00 is PWM. When the PWM signal is high, Q1's second terminal receives a high level, and Q1 is an NPN transistor. According to the conduction property of NPN transistors, when U(B) is greater than U(E), the NPN transistor conducts. Therefore, Q1 meets the conduction condition, and its first and third terminals are connected. Simultaneously, Q2 is a PNP transistor, and its second terminal receives a high level. According to the PNP conduction property, when U(B) is less than U(E), the PNP transistor conducts. Since Q2's first terminal is connected to the turn-off voltage VEE, and its second terminal receives a high level, the conduction regulation is not met, and Q2 is turned off. In summary, when the PWM signal is high, the path between the drive voltage VCC and the first resistor R1 is completed.

[0049] Similarly, when the PWM is low, Q1 is turned off and Q2 is turned on, thus opening the path between the turn-off voltage VEE and the first resistor R1.

[0050] Optionally, Q1 is an NPN transistor and Q2 is a PNP transistor. In addition, Q1 and Q2 can be other electronic switches, MOSFETs, IGBTs, etc. In practical applications, appropriate switching transistors can be selected according to actual needs, and there are no restrictions here.

[0051] The following combines the content of the above modules and Figure 3 and Figure 4The working principle of this invention will be explained as follows:

[0052] refer to Figure 3 In one embodiment of the exemplary technology, the turn-on process of a MOSFET is used as an example for explanation. Q3 is an NPN transistor and Q4 is a PNP transistor. The first terminal of Q3 is connected to the drive voltage VCC. The third terminals of Q3 and Q4 are respectively connected to the first terminal of the second resistor R2. The second terminals of Q3 and Q4 are respectively connected to the PWM output terminal. The second terminal of the second resistor R2 and the first terminal of the second capacitor C2 are respectively connected to the gate of the IGBT / MOSFET. The second terminal of the second capacitor C2 is connected to the source of the IGBT / MOSFET.

[0053] refer to Figure 4 In one embodiment of the present invention, the turn-on process of a MOS transistor is used as an example for explanation. Figure 4 The diagram shows a comparison of waveforms of various parameters during the turn-on process of a MOSFET using the driving circuit of the exemplary technology and the driving circuit proposed in this invention. In the diagram, Vg represents the driving voltage, Ig represents the gate current, Vgs represents the gate voltage, Id represents the drain current, Vds represents the drain-source voltage, Loss represents the power loss during turn-on, Vth represents the turn-on threshold voltage, VCC represents the driving voltage, VEE represents the turn-off voltage, t0~t1 represents the turn-on delay stage of the driving circuit of the exemplary technology during the turn-on process of the MOSFET, t1~t2 represents the current rise stage of the driving circuit of the exemplary technology during the turn-on process of the MOSFET, t2~t3 represents the voltage drop stage of the driving circuit of the exemplary technology during the turn-on process of the MOSFET, t2~t3' represents the voltage drop stage of the driving circuit of this invention during the turn-on process of the MOSFET, and t3~t4 represents the stable conduction stage of the driving circuit of the exemplary technology during the turn-on process of the MOSFET. In this embodiment of the invention, by adjusting R1, C1, and L1, the maximum gate current value in the invention is made consistent with the maximum gate current value in the exemplary technology, so as to unify the variables for easy comparison.

[0054] Activation delay phase of exemplary technology:

[0055] During the turn-on delay phase, the PWM output is high, and the first terminal of R2 receives the drive voltage VCC. After receiving the drive voltage VCC, the gate voltage Vgs of the MOSFET gradually increases to the threshold voltage state, the MOSFET starts to conduct, and the drain current Id begins to increase. In the exemplary technology, Ig reaches its maximum value during the turn-on delay phase and then gradually decreases.

[0056] The activation delay stage in this invention:

[0057] During the turn-on delay phase, the PWM output is high, and the first terminal of R1 receives the drive voltage VCC. After receiving the drive voltage VCC, the gate voltage Vgs of the MOSFET gradually increases to the threshold voltage state, the MOSFET begins to conduct, and the drain current Id begins to increase. In this invention, due to the current-suppressing property of L1, and because the first inductor L1 and the first capacitor C1 form a resonant circuit, the gate current Ig does not reach its maximum value and begins to rise slowly. Compared with the exemplary technology, this invention controls the gate current waveform through the first resistor R1, the first capacitor C1, and the first inductor L1, so that the maximum value of the gate current Ig does not occur at t0, and because the first inductor L1 and the first capacitor C1 form a resonant circuit, the gate current begins to increase slowly.

[0058] The current rise phase of the exemplary technology:

[0059] During the current rise phase, the gate current Ig gradually decreases, while the drain current Id rises from zero to its maximum value. When the drain current Id reaches its maximum value, according to the conduction characteristics of the MOS, when the drain current reaches its maximum, the freewheeling diode is reverse biased, the drain-source voltage Vds begins to accelerate its decline, the gate voltage Vgs remains unchanged and forms a Miller plateau, and losses begin to occur.

[0060] The current rise phase in this invention:

[0061] During the current rise phase, the gate current Ig gradually decreases, while the drain current Id rises from zero to its maximum value. When the drain current Id reaches its maximum value, according to the conduction characteristics of the MOSFET, the freewheeling diode reverse-biases, the drain-source voltage Vds begins to accelerate its decline, the gate voltage Vgs remains unchanged and forms a Miller plateau, and losses begin to occur. Compared with exemplary techniques, by adjusting resistor R1, first capacitor C1, and first inductor L1, the MOSFET accelerates conduction, the drain current rises faster, and it can reach its maximum value more quickly than in exemplary techniques. Conversely, the gate voltage Vgs rises faster and forms a Miller plateau at the maximum drain current. Because the gate current Ig is affected by the resonant circuit formed by first capacitor C1 and first inductor L1, it remains at a relatively large value during the current rise phase. During the loss generation, the gate current Id in this invention remains at a relatively large value, and the current rise phase is shorter, thus reducing losses compared to conventional techniques.

[0062] Voltage drop phase of exemplary technology:

[0063] During the voltage drop phase, the gate current Ig continues to decrease, the gate voltage Vgs remains at the Miller plateau and does not change, the drain current drops to a stable value and remains unchanged, the drain-source voltage Vds begins to decrease rapidly, and the loss Loss is generated during the process from t2 to t3 and gradually decreases.

[0064] Voltage drop phase of exemplary technology:

[0065] During the voltage drop phase, the gate current Ig rises to its maximum value and remains stable for a period before slowly decreasing. The gate voltage Vgs maintains a Miller plateau and remains unchanged. The drain current drops to a stable value and remains constant. The drain-source voltage Vds begins to decrease rapidly, the MOSFET turns on faster, and the loss Loss occurs during t2 to t3' and gradually decreases. Compared to exemplary technologies, because the first capacitor C1 and the first inductor L1 form a resonant circuit, the gate current Ig gradually reaches its maximum value and begins to decrease slowly. The drain-source voltage decreases faster, and t2 to t3' is the voltage drop phase in this invention, which is shorter than the t2 to t3 phase in conventional technologies. In terms of loss, because the gate current Ig remains at a large value and the voltage drop phase is shorter in this invention, the loss is smaller than in conventional technologies, and the time for loss to occur is shorter.

[0066] Stable conduction phase of exemplary technology:

[0067] The gate voltage Vgs rises to VCC and remains constant, the drain-source voltage Vds remains constant, the drain current Id remains constant, and the MOSFET is stably turned on.

[0068] Stable conduction phase of exemplary technology:

[0069] The gate voltage Vgs rises to VCC and remains constant, the drain-source voltage Vds remains constant, the drain current Id remains constant, and the MOSFET is stably turned on.

[0070] Similarly, the turn-off process follows the same driving principle as the turn-on process, maintaining the gate current at a relatively large value during the current and voltage changes in the turn-off phase to reduce power consumption. The implementation process and technical principles have been presented above and will not be repeated here.

[0071] In summary, compared with the driving circuits of exemplary technologies, the driving circuit of this invention adjusts the gate current waveform through the first resistor R1, the first capacitor C1, and the first inductor L1, maintaining the gate current at a relatively large value and accelerating the current rise and voltage fall phases, thus shortening the time for losses to occur. This achieves the maintenance of a large gate current during the loss generation phase, thereby solving the technical problem of excessive switching losses during IGBT / MOSFET switching and improving switching efficiency.

[0072] The present invention also proposes a motor controller, which includes a gate drive circuit for a power transistor, the specific circuit of which is described in the above embodiments.

[0073] It is worth noting that, since the motor controller of the present invention includes all embodiments of the gate drive circuit of the power transistor described above, the motor controller of the present invention has all the beneficial effects of the gate drive circuit of the power transistor described above, which will not be repeated here.

[0074] The above description is merely a preferred embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural transformations made using the contents of the present invention's specification and drawings under the inventive concept of the present invention, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present invention.

Claims

1. A gate drive circuit for a power transistor, used in a power transistor, characterized in that, The gate drive circuit of the power transistor includes: A driver chip, which is used to output a drive signal; The control module has its first terminal connected to the output terminal of the driver chip and its second terminal connected to the gate of the power transistor. During the turn-on or turn-off phase of the power transistor, the control module controls the gate current to rise with a delay, and extends the duration for which the gate current remains at its peak value during the drain current or drain voltage change phase. The control module is used to slow down the rate at which the gate current rises to the current peak and falls from the current peak during the current change and voltage change phases of the turn-on or turn-off process. The control module includes a current amplification unit and a current stabilization unit. The current amplification unit is used to adjust the maximum current value of the gate current. The current stabilization unit is used to suppress the rate of increase of the gate current when the gate current increases and to slow down the rate of decrease of the gate current when the gate current decreases.

2. The gate drive circuit for the power transistor as described in claim 1, characterized in that, The control module adjusts the waveform of the gate current.

3. The gate drive circuit for the power transistor as described in claim 2, characterized in that, The control module includes at least a damping unit for adjusting the gate current oscillation; the first end of the damping unit is connected to the driving chip, the second end is connected to the first end of the current stabilizing unit, and the second end of the current stabilizing unit is connected to the gate of the power transistor.

4. The gate drive circuit for the power transistor as described in claim 3, characterized in that, The damping unit for adjusting gate current oscillation consists of one or more resistors connected in series.

5. The gate drive circuit for the power transistor as described in claim 3, characterized in that, The current stabilizing unit for adjusting the gate current waveform includes an inductor.

6. The gate drive circuit for the power transistor as described in claim 3, characterized in that, The first end of the current amplification unit is connected to the driver chip, and the second end is connected to the first end of the current stabilization unit.

7. The gate drive circuit for the power transistor as described in claim 6, characterized in that, The current amplification unit that adjusts the maximum current value includes a capacitor.

8. The gate drive circuit for the power transistor as described in claim 1, characterized in that, It also includes a power supply module and a push-pull module. The first end of the push-pull module is connected to the driver chip, the second end is connected to the first end of the control module, and the third end is connected to the power supply module. The push-pull module amplifies the drive signal emitted by the driver chip.

9. The gate drive circuit for the power transistor as described in claim 8, characterized in that, The push-pull module includes a first switch transistor and a second switch transistor. The first end of the first switch transistor is connected to the first end of the power module, the first end of the second switch transistor is connected to the second end of the power module, the second ends of the first switch transistor and the second end of the second switch transistor are respectively connected to the driver chip, and the third ends of the first switch transistor and the third ends of the second switch transistor are respectively connected to the first end of the control module.

10. A motor controller, characterized in that, The motor controller includes the gate drive circuit of the power transistor as described in any one of claims 1-9.

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