Display device driving method and display device operated by the same

Abstract

Provided is a method for driving a display device and a display device operated by the method. The method for driving the display device starts in sequence according to each frame period: an initialization voltage supply step of supplying an initialization voltage to a gate electrode of a driving transistor; and a data signal supply and threshold voltage compensation step of supplying a data signal to a source electrode or a drain electrode of the driving transistor, wherein the method for driving the display device includes: a first frame period, in the initialization voltage supply step, an initialization voltage of a first voltage level is supplied, and before the initialization voltage of the first voltage level is supplied, the initialization voltage is shifted to a second voltage level; and a second frame period, in the initialization voltage supply step, an initialization voltage of the first voltage level is supplied, and before the initialization voltage of the first voltage level is supplied, the initialization voltage is shifted to a third voltage level.

Description

Technical Field

[0001] The present disclosure relates to a driving method of a display device and a display device operated by the driving method. Background Art

[0002] With the development of information technology, the importance of display devices as a connection medium between users and information is becoming more prominent. In response to this, the use of flat panel display devices (FPD) such as liquid crystal display devices (LCD), organic light emitting display devices (OLED) and plasma display panels (PDP) has increased.

[0003] Among flat panel display devices, organic light emitting display devices display images using organic light emitting diodes that generate light through recombination of electrons and holes, and have the advantages of having a fast response speed and being driven with low power consumption.

[0004] An organic light-emitting display device has a plurality of pixels arranged in a matrix at the intersection of a plurality of data lines, scan lines, and power lines. A pixel generally includes an organic light-emitting diode and a driving transistor for controlling the amount of current flowing to the organic light-emitting diode. Such a pixel generates light of a predetermined brightness while supplying current from the driving transistor to the organic light-emitting diode in response to a data voltage.

[0005] However, in the existing pixels, when a white grayscale is displayed after a black grayscale is realized, light with a brightness lower than the desired brightness is generated during a predetermined frame period. In this case, an image with a desired brightness corresponding to the grayscale cannot be displayed in each pixel, which acts as a major factor in reducing brightness uniformity and deteriorating video quality.

[0006] In an organic light-emitting display device, the problem of reduced response characteristics may be caused by a characteristic problem of a driving transistor included in a pixel. In other words, the threshold voltage of the driving transistor shifts in response to a voltage applied to the driving transistor in a previous frame period, and due to the shifted threshold voltage, light of a desired brightness cannot be generated in the current frame.

[0007] In addition, due to the hysteresis phenomenon of the driving transistor, light of desired brightness cannot be generated in the current frame. Summary of the invention

[0008] The problem to be solved by the present disclosure is to provide a display device driving method and a display device based thereon, wherein the display device driving method can display an image of desired brightness corresponding to grayscale in each pixel even when there is a characteristic problem of a driving transistor, thereby minimizing the reduction in brightness uniformity.

[0009] The subjects of the present disclosure are not limited to the subjects mentioned above, and other subjects not mentioned will be clearly understood by a person skilled in the art from the following description.

[0010] A driving method for a display device according to an embodiment of the present disclosure for solving the above-mentioned problem starts in sequence according to each frame period: an initialization voltage providing step of providing an initialization voltage to a gate electrode of a driving transistor; and a data signal providing and threshold voltage compensation step of providing a data signal to a source electrode or a drain electrode of the driving transistor, wherein the driving method for the display device includes: a first frame period, in the initialization voltage providing step, providing an initialization voltage of a first voltage level, and before providing the initialization voltage of the first voltage level, shifting to a second voltage level; and a second frame period, in the initialization voltage providing step, providing an initialization voltage of the first voltage level, and before providing the initialization voltage of the first voltage level, shifting to a third voltage level.

[0011] It may be that in the initialization voltage providing step, a first scanning signal of a conduction level is supplied to the pixel through the first scanning line, and in the data signal providing and threshold voltage compensation step, a second scanning signal of a conduction level is supplied to the pixel through the second scanning line.

[0012] It may be that, in the first frame period, before the supply of the first scanning signal maintaining the on-level ends, the initialization voltage shifts to the second voltage level and then maintains the first voltage level again.

[0013] It may be that, in the first frame period, before supply of the first scan signal of the on-level starts, the initialization voltage starts shifting to the second voltage level.

[0014] It may be that, in the first frame period, during supply of the first scan signal maintaining the on-level, the initialization voltage is shifted to the second voltage level.

[0015] It may be that the first voltage level, the second voltage level, and the third voltage level are different from each other.

[0016] The second voltage level may be a voltage level shifted from the first voltage level in a negative direction, and the third voltage level may be a voltage level shifted from the first voltage level in a positive direction.

[0017] It may be that the first frame period and the second frame period alternate.

[0018] The second voltage level and the third voltage level may be shifted from the first voltage level to the same extent (absolute value) as each other.

[0019] It may be that the first voltage level is -5V to -3V, the second voltage level is -11V to -9V, and the third voltage level is 0V to 2V.

[0020] It may be that the first frame period is continuous for at least two times, and the second frame period is continuous for at least two times.

[0021] It may be that, in the first frame period, before the initialization voltage of the first voltage level is provided, the initialization voltage of the first voltage level is shifted to the third voltage level and then shifted to the second voltage level; in the second frame period, before the initialization voltage of the first voltage level is provided, the initialization voltage of the first voltage level is shifted to the second voltage level and then shifted to the third voltage level.

[0022] Alternatively, the method for driving the display device further includes a step of compensating an anode, wherein the step of compensating an anode is started after the step of providing the data signal and compensating the threshold voltage is started, and the initialization voltage is provided to the anode of the light emitting diode.

[0023] It may be that, in the step of compensating the anode, a third scanning signal of a conduction level is supplied to the pixel through a third scanning line.

[0024] It may be that, in the step of compensating the anode, the initialization voltage is maintained at the first voltage level.

[0025] It may be that a period during which the third scan signal of the on level is supplied through the third scan line does not overlap with a period during which the initialization voltage is shifted to the second voltage level or a period during which the initialization voltage is shifted to the third voltage level.

[0026] A display device according to another embodiment of the present disclosure for solving the above-mentioned problem includes: a display unit including a plurality of pixels; a scanning driving unit connected to each of the pixels through a plurality of scanning lines; a data driving unit connected to each of the pixels through a data line; and a power supply unit connected to each of the pixels through an initialization line and including an initialization voltage generating unit, wherein the initialization voltage generating unit provides an initialization voltage to each of the pixels for initializing a gate electrode of a driving transistor in each of the pixels, the initialization voltage generating unit provides an initialization voltage of a first voltage level to the driving transistor during a first frame period, and before providing the initialization voltage of the first voltage level, shifts the initialization voltage of the first voltage level to a second voltage level, the initialization voltage generating unit provides the initialization voltage of the first voltage level to the driving transistor during a second frame period, and before providing the initialization voltage of the first voltage level, shifts the initialization voltage of the first voltage level to a third voltage level.

[0027] The second voltage level may be a voltage level shifted from the first voltage level in a negative direction, and the third voltage level may be a voltage level shifted from the first voltage level in a positive direction.

[0028] The initialization voltage generator may provide the initialization voltage for initializing the anode of the light emitting diode in each pixel to the first voltage level to each pixel during the first frame period and the second frame period.

[0029] It may be that, in the first frame period and the second frame period, the gate electrode of the driving transistor is initialized to the first voltage level before the anode electrode of the light emitting diode.

[0030] Details of other embodiments are included in the detailed description and drawings.

[0031] (Effect of Publicity)

[0032] According to the embodiments of the present disclosure, the display device can display an image of desired brightness corresponding to grayscale in each pixel, minimize the reduction in brightness uniformity, and minimize the visual recognition of visual persistence by the user.

[0033] The effects based on the embodiment are not limited to the above-exemplified contents, and more various effects are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 FIG. 1 is a top view schematically showing a display device according to an embodiment of the present disclosure.

[0035] Figure 2is a block diagram briefly showing a display device according to an embodiment of the present disclosure.

[0036] Figure 3 yes Figure 2 Equivalent circuit diagram of a pixel in a display device.

[0037] Figure 4 is a graph showing a drain-source current of a driving transistor according to a gate-source voltage difference of the driving transistor in a gate-on bias state and a gate-off bias state in a display device according to an embodiment of the present disclosure.

[0038] Figures 5 to 7 FIG. 1 is a top view of a display device showing an example of a hysteresis phenomenon as a comparative example.

[0039] Figure 8 is a sequence diagram illustrating a method for driving a display device according to an embodiment of the present disclosure.

[0040] Fig. 9 is a timing diagram illustrating a method for driving a display device according to an embodiment of the present disclosure.

[0041] Fig.10 is a timing diagram illustrating a driving method of a display device according to another embodiment of the present disclosure.

[0042] Fig.11 is a timing diagram illustrating a method for driving a display device according to yet another embodiment of the present disclosure.

[0043] Fig.12 is a timing diagram illustrating a method for driving a display device according to yet another embodiment of the present disclosure.

[0044] Fig.13 is an equivalent circuit diagram of a pixel in a display device according to yet another embodiment of the present disclosure.

[0045] Fig.14 is an equivalent circuit diagram of a pixel in a display device according to yet another embodiment of the present disclosure. DETAILED DESCRIPTION

[0046] The advantages and features of the present disclosure and methods for achieving them are described in detail in the accompanying drawings. Figure 1 The detailed embodiments described later will become clear. However, the present disclosure is not limited to the embodiments disclosed below, and may be implemented in a variety of different forms. The embodiments are only provided to make the disclosure of the present disclosure complete and to fully inform the scope of the disclosure to those who have common knowledge in the technical field to which the present disclosure belongs. The present disclosure is only defined by the scope of the claims.

[0047] When an element or layer is referred to as being "on" another element or layer, it includes the case where the element is directly on the other element or has other layers or elements interposed therebetween. Throughout the specification, the same reference numerals refer to the same components.

[0048] Although the terms first, second, etc. are used to describe a variety of constituent elements, these constituent elements are of course not limited by these terms. These terms are used only to distinguish one constituent element from other constituent elements. Therefore, of course, the first constituent element mentioned below can also be the second constituent element within the technical concept of the present disclosure. Unless the context clearly indicates otherwise, the singular expression includes the plural expression.

[0049] Hereinafter, the embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same or similar reference numerals are used for the same components in the drawings.

[0050] Figure 1 FIG. 1 is a top view schematically showing a display device according to an embodiment of the present disclosure.

[0051] Reference Figure 1 , the display device 1 according to an embodiment of the present disclosure may include a display area DA and a non-display area NDA.

[0052] The display area DA is defined as an area for displaying an image. In addition, the display area DA may also be used as a detection component for detecting an external environment. That is, the display area DA may be used as an area for displaying an image or recognizing a user's fingerprint or touch. As an embodiment, the display area DA may have a flat shape. However, it is not limited thereto, and at least a portion of the display area DA may also be curved.

[0053] The non-display area NDA is arranged outside the display area DA and is defined as an area where no image is displayed. As an embodiment, a speaker assembly, a camera assembly, and a sensor assembly may be arranged in the non-display area NDA. Here, the sensor assembly may include at least one of an illumination sensor, a proximity sensor, an infrared sensor, and an ultrasonic sensor.

[0054] Figure 2 is a block diagram briefly showing a display device according to an embodiment of the present disclosure. Figure 3 yes Figure 2 Equivalent circuit diagram of a pixel in a display device.

[0055] Reference Figure 2 The display device 1 includes a timing control unit 10 , a data driving unit 20 , a scanning driving unit 30 , a light emitting driving unit 40 , a display unit 50 and a power supply unit 60 .

[0056] The timing control section 10 may receive an external input signal about an image frame from an external processor and generate a signal required by the display device 1. For example, the timing control section 10 may provide a grayscale value and a control signal to the data driving section 20. In addition, the timing control section 10 may provide a clock signal, a scanning start signal, etc. to the scanning driving section 30. In addition, the timing control section 10 may provide a clock signal, a light emission stop signal, etc. to the light emission driving section 40.

[0057] The data driving unit 20 may generate data voltages to be provided to the data lines DL1, DL2, and DLm using the grayscale values ​​and control signals received from the timing control unit 10. For example, the data driving unit 20 may sample the grayscale values ​​using the clock signal, and apply the data voltages corresponding to the grayscale values ​​to the data lines DL1, DL2, and DLm in units of pixel rows (e.g., pixels connected to the same scan line). Here, m may be a natural number.

[0058] The scan driving unit 30 may receive a clock signal, a scan start signal, etc. from the timing control unit 10 to generate a scan signal to be provided to the scan lines GIL1, GWL1, GBL1, GILn, GWLn, and GBLn. Here, n may be a natural number.

[0059] Although not shown in the figure, the scanning drive unit 30 may include a plurality of sub-scanning drive units. For example, the first sub-scanning drive unit may provide a scanning signal for the first scanning lines GIL1 and GILn, the second sub-scanning drive unit may provide a scanning signal for the second scanning lines GWL1 and GWLn, and the third sub-scanning drive unit may provide a scanning signal for the third scanning lines GBL1 and GBLn. Each sub-scanning drive unit may include a plurality of scanning stages connected in the form of a shift register. For example, a scanning signal may be generated by sequentially transmitting a pulse of a conduction level of a scanning start signal supplied to a scanning start line to a next scanning stage.

[0060] The light-emitting driving section 40 may receive a clock signal, a light-emitting stop signal, etc. from the timing control section 10 to generate a light-emitting signal to be provided to the light-emitting lines EL1, EL2, and ELn. For example, the light-emitting driving section 40 may sequentially provide a light-emitting signal having a pulse of an off level to the light-emitting lines EL1, EL2, and ELn. For example, the light-emitting driving section 40 may be configured in the form of a shift register, and generate a light-emitting signal by sequentially transmitting the pulse of the off level of the light-emitting stop signal to the next light-emitting stage according to the control of the clock signal.

[0061] The display unit 50 includes pixels PXnm. For example, the pixels PXnm can be connected to a corresponding data line DLm, a plurality of scan lines GILn, GWLn, GBLn, and a light emitting line ELn. However, the number of data lines DLm, scan lines GILn, GWLn, GBLn, and light emitting lines ELn corresponding to the pixels PXnm is not limited to those shown in the figure.

[0062] A plurality of pixels PXnm may define a light emitting region that emits a plurality of colors of light. For example, a plurality of pixels PXnm may define a light emitting region that emits red light, green light, and blue light. As one embodiment, the pixel PXnm includes a plurality of transistors and at least one capacitor. In some other embodiments, at least a portion of the plurality of transistors of the pixel PXnm may also be a dual-gate transistor having two gate electrodes.

[0063] The display unit 50 may define a display area DA including a light emitting area defined by the pixels PXnm that emits light of a plurality of colors (see Figure 1 ).

[0064] The power supply unit 60 can receive an external input voltage and provide the power supply voltage to the output terminal by converting the external input voltage. For example, the power supply unit 60 generates a high power supply voltage ELVDD and a low power supply voltage ELVSS based on the external input voltage. In this specification, the high power supply and the low power supply can be power supplies with relative voltage levels to each other. The power supply unit 60 can provide an initialization voltage VINT to each pixel PXnm, and the initialization voltage VINT is applied to the gate electrode of the driving transistor and / or the light emitting diode LD (refer to Figure 3 )’s anode is initialized.

[0065] The power supply unit 60 may receive an external input voltage from a battery or the like, and may boost the external input voltage to generate a power supply voltage higher than the external input voltage. For example, the power supply unit 60 may be composed of a PMIC (power management integrated chip). For example, the power supply unit 60 may be composed of an external DC / DC IC.

[0066] The power supply unit 60 may include an initialization voltage generating unit 61. The initialization voltage generating unit 61 may control the voltage level of the initialization voltage VINT provided to each pixel PXnm. That is, the initialization voltage generating unit 61 may control the voltage level of the initialization voltage VINT provided to each pixel PXnm so that the voltage level has multiple voltage levels instead of a constant voltage level. In the following description, it can be understood that the initialization voltage VINT described later is controlled by the initialization voltage generating unit 61.

[0067] Reference Figure 3 According to an embodiment of the present disclosure, a pixel PXnm includes a plurality of transistors T1, T2, T3, T4, T5, T6, T7, a storage capacitor Cst, and a light emitting diode LD.

[0068] The first transistor T1 may have a first electrode connected to a first electrode of the second transistor T2, a second electrode connected to a first electrode of the third transistor T3, and a gate electrode connected to a second electrode of the third transistor T3. The first transistor T1 may also be referred to as a driving transistor. In this specification, any one of the first electrode and the second electrode of each transistor is a source electrode, and the other is equivalent to a drain electrode.

[0069] The second transistor T2 may have a first electrode connected to the first electrode of the first transistor T1, a second electrode connected to the data line DLm, and a gate electrode connected to the second scan line GWLn. The second transistor T2 may also be called a scan transistor.

[0070] The third transistor T3 may have a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the gate electrode of the first transistor T1, and a gate electrode connected to the second scan line GWLn. The third transistor T3 may also be called a diode-connected transistor.

[0071] The fourth transistor T4 may have a first electrode connected to the second electrode of the storage capacitor Cst, a second electrode connected to the initialization line VINTL, and a gate electrode connected to the first scan line GILn. The fourth transistor T4 may be referred to as a gate initialization transistor.

[0072] The fifth transistor T5 may have a first electrode connected to the high power line ELVDDL, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the light emitting line ELn. The fifth transistor T5 may be referred to as a first light emitting transistor.

[0073] The sixth transistor T6 may have a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the anode of the light emitting diode LD, and a gate electrode connected to the light emitting line ELn. The sixth transistor T6 may be referred to as a second light emitting transistor.

[0074] The seventh transistor T7 may have a first electrode connected to the anode of the light emitting diode LD, a second electrode connected to the initialization line VINTL, and a gate electrode connected to the third scan line GBLn. The seventh transistor T7 may be referred to as an anode initialization transistor.

[0075] The storage capacitor Cst may have a first electrode connected to the high power line ELVDDL and a second electrode connected to the gate electrode of the first transistor T1 .

[0076] The light emitting diode LD may be an anode connected to the second electrode of the sixth transistor T6, and a cathode connected to the low power line ELVSSL. The voltage applied to the low power line ELVSSL may be set to be lower than the voltage applied to the high power line ELVDDL. The light emitting diode LD may be an organic light emitting diode, an inorganic light emitting diode, a quantum dot light emitting diode, etc.

[0077] The light emitting diode LD can determine the amount of light emitted by the current level of the driving current Ids supplied from the high power line ELVDDL. The driving current Ids can be the drain-source current Ids of the first transistor T1. The current level of the driving current Ids can be directly affected by the transistor connected between the high power line ELVDDL and the low power line ELVSSL. For example, in the present embodiment, the transistor connected between the high power line ELVDDL and the low power line ELVSSL is equivalent to the first transistor T1, the fifth transistor T5, and the sixth transistor T6. In this specification, since the driving current Ids and the drain-source current Ids of the first transistor T1 are substantially the same current, the same reference numerals are used.

[0078] As an embodiment, each transistor T1 to T7 may be a PMOS transistor. The channels of the transistors T1 to T7 may also be formed of polysilicon. The polysilicon transistor may also be an LTPS (low temperature polysilicon) transistor. The polysilicon transistor has high electron mobility and has a fast driving characteristic based on this.

[0079] In other embodiments, transistors T1 to T7 may be NMOS transistors. At this time, the channels of transistors T1 to T7 may also be composed of oxide semiconductors. Oxide semiconductor transistors can be processed at low temperatures and have low charge mobility compared to polysilicon. Therefore, the amount of leakage current generated by the oxide semiconductor transistor in the off state is less than the amount of leakage current of the polysilicon transistor.

[0080] In yet another embodiment, a portion of the transistors (for example, T1, T2, T5, T6, and T7) may be P-type transistors, and the remaining transistors (for example, T3 and T4) may be N-type transistors.

[0081] On the other hand, during the period when the second transistor T2 is turned on and the data signal is supplied, the third transistor T3 is also turned on and the gate electrode and the second electrode of the first transistor T1 are electrically connected, so the gate electrode and the second electrode have substantially the same potential. When the voltage difference (gate-source voltage difference) Vgs between the gate electrode and the first electrode of the first transistor T1 is greater than the threshold voltage, the first transistor T1 forms a current path until the voltage difference between the gate electrode and the first electrode reaches the threshold voltage of the first transistor T1, thereby charging the voltage of the gate electrode and the second electrode. That is, when the data signal is provided to the first electrode of the first transistor T1, the voltage of the gate electrode and the second electrode of the first transistor T1 rises to the difference voltage between the data signal and the threshold voltage. Therefore, the first transistor T1 can be diode-connected and the threshold voltage can be compensated. It can be performed in the "step of providing a data signal and compensating for the threshold voltage" described later.

[0082] Figure 4 is a graph showing a drain-source current of a driving transistor according to a gate-source voltage difference of the driving transistor in a gate-on bias state and a gate-off bias state in a display device according to an embodiment of the present disclosure. Figures 5 to 7 FIG. 1 is a top view of a display device showing an example of a hysteresis phenomenon as a comparative example.

[0083] The on bias state means a state in which a peak white grayscale voltage dW is applied to the gate electrode of the first transistor T1 and a drain-source current Ids of the first transistor T1 flows in large quantities. The off bias state means a state in which a peak black grayscale voltage dB is applied to the gate electrode of the first transistor T1 and a drain-source current Ids of the first transistor T1 hardly flows. The peak white grayscale voltage dW means a voltage applied to the gate electrode of the first transistor T1 in order for the light emitting diode to emit light at a peak white grayscale, and the peak black grayscale voltage dB means a voltage applied to the gate electrode of the first transistor T1 in order for the light emitting diode to emit light at a peak black grayscale. For example, in the case where the grayscale value is represented as an 8-bit digital value, the peak black grayscale may mean a minimum value "0" and the peak white grayscale may mean a maximum value "255".

[0084] However, refer to Figure 4 Since there is a difference in the sweep curves of the on bias state and the off bias state in the P-type first transistor T1, a difference in the drain-source current Ids value of the first transistor T1 may occur under the same gray scale.

[0085] That is, in gray representation, the difference between the sweep curves of the drain-source current characteristics of the driving transistor in the on-bias state and the off-bias state according to the gate-source voltage difference of the driving transistor is called hysteresis, which may cause visual persistence.

[0086] In addition, when a P-type transistor is used as a driving thin film transistor of an organic light-emitting display device, such a difference in the drain-source current Ids value may not stabilize the driving characteristics of the light-emitting diode driven based on the driving current Ids, resulting in brightness differences.

[0087] Figures 5 to 7 The display devices 2a, 2b, and 2c are used as comparative examples, and the case where the initialization voltage VINT provided to the display devices 2a, 2b, and 2c is in a DC form with a constant voltage level is illustrated.

[0088] like Figure 5 As shown, the display area DA of the display device 2a may include, during a specific time (e.g., 2 hours), a plurality of first sub-display areas DA1, which are composed of pixels to which a peak white grayscale voltage dW is applied; and a plurality of second sub-display areas DA2, which are composed of pixels to which a peak black grayscale voltage dB is applied. The first sub-display areas DA1 and the second sub-display areas DA2 may be alternately arranged in a matrix form.

[0089] After the specified time has passed, if Figure 6 As shown, if the peak white grayscale voltage dW is applied to the pixels in the entire display area DA, the brightness of the first sub-display area DA1 of the display device 2b can be lower than the brightness of the second sub-display area DA2. That is, a chess pattern can be formed in the display area DA.

[0090] If time passes, then Figure 7 As shown, the brightness of the first sub-display area DA1 of the display device 2c can gradually become similar to the brightness of the second sub-display area DA2.

[0091] Such a phenomenon may be recognized by the user as a momentary persistence of vision, which may be caused by the hysteresis phenomenon of the driving transistor.

[0092] The following describes a driving method of a display device according to an embodiment of the present disclosure. Figure 2 and Figure 3 .

[0093] Figure 8 is a sequence diagram illustrating a method for driving a display device according to an embodiment of the present disclosure. Fig. 9is a timing diagram illustrating a method for driving a display device according to an embodiment of the present disclosure.

[0094] As an example, the following describes that each transistor T1 to T7 in the pixel is a P-type transistor that is turned on in response to a predetermined low logic level signal (on signal) at the gate electrode, and is turned off in response to a predetermined high logic level signal (off signal).

[0095] Reference Figure 8 and Fig. 9 The pixel can receive the light-emitting control signal EM of a high logic level and maintain the non-light-emitting (cut-off) state of the light-emitting diode LD, and can receive the light-emitting control signal EM of a low logic level and maintain the light-emitting (on) state of the light-emitting diode LD.

[0096] During each frame period, the light emitting control signal EM of a high logic level and the light emitting control signal EM of a low logic level may be alternately provided to each pixel. Alternatively, the period during which the light emitting control signal EM of a high logic level is provided to the pixel is referred to as a data writing period, and the period during which the light emitting control signal EM of a low logic level is provided to the pixel is referred to as a light emitting period.

[0097] It can be that in one frame period, while the light emitting diode LD is kept in the non-light emitting (off) state, a compensation mechanism for compensating the threshold voltage of the driving transistor is provided to each pixel so that the light emitting diode LD has the target brightness when it becomes the light emitting (on) state in the next frame period. That is, Fig. 9 A timing diagram for the compensation mechanism is shown in an i-th frame period, an i+1-th frame period, an i+2-th frame period, and an i+3-th frame period as arbitrary consecutive frame periods.

[0098] First, a method of driving the display device 1 in a period of maintaining a non-light emitting state, which is a period in which a pixel receives supply of a light emitting control signal EM of a high logic level within one frame period, is described.

[0099] While maintaining the non-luminous (cut-off) state of the light-emitting diode LD, the following can be started in sequence: "step S100 of providing initialization voltage" of supplying the first scanning signal GI of a low logic level to each pixel through the first scanning lines GIL1 and GILn; "step S200 of providing data signal and compensating for threshold voltage" of supplying the second scanning signal GW of a low logic level to each pixel through the second scanning lines GWL1 and GWLn; and "step S300 of compensating for anode" of supplying the third scanning signal GB of a low logic level to each pixel through the third scanning lines GBL1 and GBLn.

[0100] Despite Figure 8It is described in the sequence diagram that each step is performed in sequence, but as long as the concept of the present disclosure is not changed, it is obvious that a part of the steps shown as being performed continuously can be performed simultaneously, or the order of each step can be changed, or a part of the steps can be omitted, or other steps can be included between each step. In addition, although the "step S100 of providing an initialization voltage", "step S200 of providing a data signal and compensating for a threshold voltage" and "step S300 of compensating for an anode" are illustrated in the accompanying drawings as not overlapping in time, it is not limited thereto, and in some other embodiments, each step can also partially overlap in time.

[0101] In the step S100 of providing the initialization voltage, the fourth transistor T4 is turned on, and the gate electrode of the first transistor T1 is connected to the initialization line VINTL. Thus, the voltage of the gate electrode of the first transistor T1 is initialized to the initialization voltage VINT of the initialization line VINTL, and is maintained by the storage capacitor Cst. For example, the initialization voltage VINT of the initialization line VINTL may be a voltage sufficiently lower than the voltage of the high power line ELVDDL. For example, the initialization voltage VINT may be a voltage of a similar level to the voltage of the low power line ELVSSL.

[0102] On the other hand, the initialization voltage VINT may have a plurality of voltage levels. As an embodiment, as a driving method of the display device 1, the "step S100 of providing the initialization voltage" may include a frame period for supplying the initialization voltage VINT having other voltage levels. As an embodiment, the initialization voltage VINT may be about -10V to 2V.

[0103] As an embodiment, the initialization voltage VINT may have: a first voltage level a1 having a reference voltage level; a second voltage level a2 lower than the first voltage level a1; and a third voltage level a3 higher than the first voltage level a1. For example, the first voltage level a1 may be -5V to -3V, the second voltage level a2 may be -11V to -9V, and the third voltage level a3 may be 0V to 2V. Hereinafter, as an example, the first voltage level a1 is -4V, the second voltage level a2 is -10V, and the third voltage level a3 is 1V.

[0104] The initialization voltage VINT may be set to initialize the voltage of the gate electrode of the first transistor T1 to a first voltage level a1. In the "step S100 of providing the initialization voltage", the initialization voltage VINT may be shifted to a specific voltage such as a second voltage level a2 or a third voltage level a3 before the first scan signal GI of the low logic level is supplied. In the "step S100 of providing the initialization voltage" of each frame period, the period of supplying the first scan signal GI of the low logic level may include: a period of supplying the initialization voltage VINT of the first voltage level a1; and a period of supplying the initialization voltage VINT shifted from the first voltage level a1. In this case, the initialization voltage VINT may have the first voltage level a1 before the first scan signal GI of the low logic level is supplied.

[0105] The offset direction of the initialization voltage VINT may be different for each frame period. That is, the driving method of the display device may include a frame period in which the offset direction of the initialization voltage VINT is from the first voltage level a1 to the positive voltage level direction and a frame period in which the offset direction is from the first voltage level a1 to the negative voltage level direction. In other words, the driving method of the display device may include a frame period in which the initialization voltage VINT is offset from the first voltage level a1 to the second voltage level a2 in the negative direction and a frame period in which the initialization voltage VINT is offset from the first voltage level a1 to the third voltage level a3 in the positive direction.

[0106] As an embodiment, the degree of shift (absolute value) may be the same in each frame period. For example, in the "step S100 of providing initialization voltage" in the i-th frame period, the first voltage level a1 (e.g., -4V) is shifted to the second voltage level a2 (e.g., -9V) by 5V, and in the "step S100 of providing initialization voltage" in the i+1-th frame period, the first voltage level a1 (e.g., -4V) is shifted to the third voltage level a3 (e.g., 1V) by 5V.

[0107] As an embodiment, in the "step S100 of providing an initialization voltage" of the i-th frame period, the initialization voltage VINT can be shifted to the second voltage level a2 and then maintained at the first voltage level a1, and in the "step S100 of providing an initialization voltage" of the i+1-th frame period, the initialization voltage VINT can be shifted to the third voltage level a3 and then maintained at the first voltage level a1.

[0108] As an embodiment, the shift direction may be alternated for each frame period. For example, the shift direction may be alternated for each frame period, such as shifting to the second voltage level a2 in the "step S100 of providing the initialization voltage" in the i-th frame period, shifting to the third voltage level a3 in the "step S100 of providing the initialization voltage" in the i+1-th frame period, shifting to the second voltage level a2 in the "step S100 of providing the initialization voltage" in the i+2-th frame period, and shifting to the third voltage level a3 in the "step S100 of providing the initialization voltage" in the i+3-th frame period.

[0109] As an embodiment, the time period during which the initialization voltage VINT remains offset may include the time point when the first scanning signal GI of the low logic level is started to be supplied. For example, in the i-th frame period, in the "step S100 of providing the initialization voltage", before the first scanning signal GI of the low logic level is started to be supplied, the initialization voltage VINT may be offset from the first voltage level a1 to the second voltage level a2, and after the first scanning signal GI of the low logic level is started to be supplied, the initialization voltage VINT may return to the first voltage level a1.

[0110] Before the supply of the first scan signal GI of the low logic level is terminated, the initialization voltage VINT is shifted, thereby minimizing the persistence of vision caused by the hysteresis phenomenon. In addition, the shift direction is alternated every frame period, thereby reducing the stress of the driving transistor.

[0111] Next, in the step S200 of "providing a data signal and compensating for a threshold voltage", a second scan signal GW of a low logic level (on level) is supplied to the second scan line GWLn, and the second transistor T2 and the third transistor T3 are turned on. Thus, the data voltage applied to the data line DLm is written to the storage capacitor Cst through the second transistor T2, the first transistor T1, and the third transistor T3. However, the data voltage at this time is the data voltage of the previous pixel, and is not used for the light emission of the pixel PXnm, but is used to apply the on-bias voltage to the first transistor T1. If the on-bias voltage is applied to the first transistor T1 before the actual data voltage is written, the hysteresis phenomenon can be improved. In addition, the data voltage written to the storage capacitor Cst at this time can be a voltage reflecting the reduction amount of the threshold voltage of the first transistor T1.

[0112] Next, in the "anode compensation step S300", the third scan line GBLn is supplied with the third scan signal GB of a low logic level (on level), and the seventh transistor T7 is turned on. Therefore, the voltage of the anode of the light emitting diode LD is initialized.

[0113] On the other hand, in the "step S300 of compensating the anode", the initialization voltage VINT may maintain a constant voltage level. That is, during the period in which the third scan signal GB of a low logic level is supplied through the third scan lines GBL1 and GBLn, the initialization voltage VINT may not shift but maintain the first voltage level a1. In other words, the period in which the initialization voltage VINT shifts from the first voltage level a1 may not overlap with the period in which the third scan signal GB of a low logic level is supplied through the third scan lines GBL1 and GBLn. Thus, the anode voltage of the light emitting diode LD may be initialized to the first voltage level a1.

[0114] Next, a driving method of the display device 1 in a light emission period which is a period in which a pixel receives supply of a light emission control signal EM of a low logic level within one frame period is described.

[0115] Although not explicitly shown, if the light emitting signal EM becomes a low logic level (on level), the fifth transistor T5 and the sixth transistor T6 become turned on. Thus, a driving current Ids path connected to the high power line ELVDDL, the fifth transistor T5, the first transistor T1, the sixth transistor T6, the light emitting diode LD and the low power line ELVSSL is formed, and the driving current Ids flows. The amount of the driving current Ids corresponds to the data voltage stored in the storage capacitor Cst. At this time, since the driving current Ids flows through the first transistor T1, the reduction in the threshold voltage of the first transistor T1 is reflected. Thus, the reduction in the threshold voltage reflected in the data voltage stored in the storage capacitor Cst and the reduction in the threshold voltage reflected in the driving current Ids offset each other, so the driving current Ids corresponding to the data voltage can flow regardless of the threshold voltage value of the first transistor T1.

[0116] The light emitting diode LD emits light at a target brightness according to the amount of the driving current Ids, so that the visual recognition of the user's visual persistence caused by the hysteresis phenomenon can be minimized.

[0117] Next, a display device and a method for driving the display device according to other embodiments are described. Figures 1 to 9 The same components in the drawings will be denoted by the same or similar reference numerals and their descriptions will be omitted.

[0118] Fig.10 is a timing diagram illustrating a driving method of a display device according to another embodiment of the present disclosure.

[0119] Reference Fig.10 According to the driving method of the display device of this embodiment, Fig. 9Compared with the embodiment, the difference lies in that during the supply of the first scanning signal GI maintaining a low logic level (on level) in each frame period, the initialization voltage VINT of the first voltage level a1 is shifted to the second voltage level a2 or the third voltage level a3.

[0120] It can be that, in the "step of providing initialization voltage" in the i-th frame period, after supplying the first scan signal GI of the low logic level, the initialization voltage VINT of the first voltage level a1 is shifted to the second voltage level a2, and before ending the supply of the first scan signal GI of the low logic level, the initialization voltage VINT maintains the first voltage level a1.

[0121] Similarly, in the "step of providing initialization voltage" in the i+1th frame period, after supplying the first scan signal GI of a low logic level, the initialization voltage VINT of the first voltage level a1 is shifted to the third voltage level a3, and before ending the supply of the first scan signal GI of the low logic level, the initialization voltage VINT maintains the first voltage level a1.

[0122] Fig.11 is a timing diagram illustrating a method for driving a display device according to yet another embodiment of the present disclosure.

[0123] Reference Fig.11 According to the driving method of the display device of this embodiment, Fig. 9 Compared with the embodiment of the present invention, the difference lies in that, in the "step of providing the initialization voltage", the frame period shifted to the second voltage level a2 can be continuous, and the frame period shifted to the third voltage level a3 can be continuous.

[0124] As an embodiment, in the “step of providing the initialization voltage”, the frame period shifted to the second voltage level a2 and the frame period shifted to the third voltage level a3 may be continuous at least twice.

[0125] For example, the initialization voltage VINT may be shifted to the second voltage level a2 in the "step of providing the initialization voltage" of the i-th frame period, shifted to the second voltage level a2 in the "step of providing the initialization voltage" of the i+1-th frame period, shifted to the third voltage level a3 in the "step of providing the initialization voltage" of the i+2-th frame period, shifted to the third voltage level a3 in the "step of providing the initialization voltage" of the i+3-th frame period, shifted to the second voltage level a2 in the "step of providing the initialization voltage" of the i+4-th frame period, shifted to the second voltage level a2 in the "step of providing the initialization voltage" of the i+5-th frame period, shifted to the third voltage level a3 in the "step of providing the initialization voltage" of the i+6-th frame period, and shifted to the third voltage level a3 in the "step of providing the initialization voltage" of the i+7-th frame period.

[0126] Fig.12 is a timing diagram illustrating a method for driving a display device according to yet another embodiment of the present disclosure.

[0127] Reference Fig.12 According to the driving method of the display device of this embodiment, Fig. 9 Compared with the embodiment of the present invention, the difference lies in that, in the "step of providing the initialization voltage" according to each frame period, the initialization voltage VINT is shifted twice in different directions from each other.

[0128] For example, in the "step S100 of providing the initialization voltage" in the i-th frame period, before providing the initialization voltage VINT of the first voltage level a1, the initialization voltage VINT of the first voltage level a1 is shifted to the third voltage level a3 and then shifted to the second voltage level a2.

[0129] Correspondingly, in the "step S100 of providing initialization voltage" in the (i+1)th frame period, before providing the initialization voltage VINT of the first voltage level a1, the initialization voltage VINT of the first voltage level a1 is shifted to the second voltage level a2, and then shifted to the third voltage level a3.

[0130] According to each frame period, in the “step of supplying the initialization voltage”, as the initialization voltage VINT is shifted twice in directions different from each other, it is possible to reduce the offset stress applied to the driving transistor while minimizing the hysteresis phenomenon.

[0131] Fig.13 is an equivalent circuit diagram of a pixel in a display device according to yet another embodiment of the present disclosure. Fig.13 Equivalent to Figure 3 A variation of .

[0132] Reference Fig.13 , the pixel PXnm_1 may include a first transistor M1, a second transistor M2, a third transistor M3, a storage capacitor Cst and a light emitting diode LD. In this embodiment, the first transistor M1 may also be a driving transistor. In this embodiment, all contents except the third scanning signal GB in the timing diagram described above may be applied.

[0133] The second transistor M2 functions to supply the data voltage supplied through the data line DL to the first node N1 in response to the second scan signal GW supplied through the second scan line GWL.

[0134] The third transistor M3 functions to provide an initialization voltage VINT for initializing a second node N2 between the driving transistor and the light emitting diode LD in response to a first scan signal GI supplied through the first scan line GIL.

[0135] Fig.14 is an equivalent circuit diagram of a pixel in a display device according to yet another embodiment of the present disclosure. Fig.14 Equivalent to Figure 3 Other variations of .

[0136] Reference Fig.14 , the pixel PXnm_1 may include a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, a fifth transistor Q5, a first capacitor C1, a second capacitor C2 and a light emitting diode LD. In this embodiment, the first transistor Q1 may also be a driving transistor.

[0137] The first transistor Q1 may be located between the high power line ELVDDL and the second node N2, and provide a driving current corresponding to the data voltage to the light emitting diode LD. For example, the first transistor Q1 may include: a gate electrode connected to the first node N1; a first electrode connected to the second electrode of the fifth transistor Q5; and a second electrode connected to the second node N2.

[0138] The second transistor Q2 may apply the data voltage received from the data line DL to the first node N1 in response to the second scan signal GW received from the second scan line GWL. For example, the second transistor Q2 may include: a gate electrode receiving the second scan signal GW; a first electrode receiving the data voltage; and a second electrode connected to the first node N1.

[0139] The third transistor Q3 may apply a reference voltage to the first node N1 in response to a third scan signal GB received from the third scan line GBL. For example, the third transistor Q3 may include: a gate electrode receiving the third scan signal GB; a first electrode connected to the reference voltage line VREFL; and a second electrode connected to the first node N1. The reference voltage may be obtained from the power supply unit 60 (refer to Figure 2 Here, the reference voltage may be set to a voltage higher than the data voltage of the peak white gray scale, and may be set to a voltage lower than the data voltage of the peak black gray scale.

[0140] In one embodiment, the second transistor Q2 receives the data voltage from the data line DL, and the third transistor Q3 receives the reference voltage from the reference voltage line VREFL. That is, by receiving the reference voltage from the reference voltage line VREFL different from the data line DL, the pixel can freely adjust the length of the period for compensating the threshold voltage without being limited to one horizontal period.

[0141] The fourth transistor Q4 may apply the initialization voltage VINT to the second node N2 in response to the first scan signal GI received from the first scan line GIL. For example, the fourth transistor Q4 may include: a gate electrode receiving the first scan signal GI; a first electrode receiving the initialization voltage VINT; and a second electrode connected to the second node N2.

[0142] The fifth transistor Q5 may include a gate electrode connected to the second scan line GWL, a first electrode connected to the high power line ELVDDL, and a second electrode connected to the first electrode of the first transistor Q1.

[0143] The first capacitor C1 may be connected between the first node N1 and the second node N2. For example, the first capacitor C1 may include: a first electrode connected to the first node N1; and a second electrode connected to the second node N2.

[0144] The second capacitor C2 may be connected between the second node N2 and the high power line ELVDDL. For example, the second capacitor C2 may include: a first electrode connected to the second node N2; and a second electrode connected to the high power line ELVDDL.

[0145] The light emitting diode LD may include an anode connected to the second node N2 and a cathode connected to the low power line ELVSSL.

[0146] Although the embodiments of the present disclosure are described above with reference to the attached drawings, it is understood by those skilled in the art that the present disclosure belongs to that the present disclosure can be implemented in other specific forms without changing the technical concept or essential features of the present disclosure. Therefore, it should be understood that the embodiments described above are illustrative in all aspects and not restrictive.

Claims

1. A method for driving a display device, starting in sequence according to each frame period: Initialization voltage supplying step of supplying an initialization voltage to a gate electrode of a driving transistor ； as well as A data signal providing and threshold voltage compensation step of providing a data signal to a source electrode or a drain electrode of the driving transistor, wherein: The driving method of the display device comprises: During a first frame period, in the initialization voltage providing step, an initialization voltage of a first voltage level is provided, and before the initialization voltage of the first voltage level is provided, the voltage level is shifted to a second voltage level; as well as In the second frame period, in the initialization voltage providing step, an initialization voltage of the first voltage level is provided, and before the initialization voltage of the first voltage level is provided, the voltage level is shifted to a third voltage level, In the initialization voltage supplying step, a first scanning signal of a conduction level is supplied to the pixel through the first scanning line. In the first frame period, the initialization voltage starts shifting to the second voltage level before supply of the first scan signal of the on level starts.

2. The method for driving a display device according to claim 1, in, In the data signal supplying and threshold voltage compensating step, a second scanning signal of a turn-on level is supplied to the pixel through a second scanning line.

3. The method for driving a display device according to claim 2, in, In the first frame period, before the supply of the first scanning signal maintaining the on-level ends, the initialization voltage is shifted to the second voltage level and then the first voltage level is maintained again.

4. The method for driving a display device according to claim 3, in, In the first frame period, during supply of the first scan signal maintaining the on-level, the initialization voltage is shifted to the second voltage level.

5. The method for driving a display device according to claim 1, in, The first voltage level, the second voltage level, and the third voltage level are different from each other.

6. A display device, in, include: A display unit including a plurality of pixels; A scanning driving unit connected to each of the pixels through a plurality of scanning lines; A data driving unit connected to each of the pixels via a data line; as well as a power supply unit connected to each of the pixels through an initialization line and comprising an initialization voltage generating unit, wherein the initialization voltage generating unit provides each of the pixels with an initialization voltage for initializing a gate electrode of a driving transistor in each of the pixels, The initialization voltage generating section supplies an initialization voltage of a first voltage level to the driving transistor during a first frame period, and shifts the initialization voltage of the first voltage level to a second voltage level before supplying the initialization voltage of the first voltage level, the initialization voltage generating section supplies the initialization voltage of the first voltage level to the driving transistor during a second frame period, and shifts the initialization voltage of the first voltage level to a third voltage level before supplying the initialization voltage of the first voltage level, The scanning driving unit supplies a first scanning signal of a conduction level to the pixel through the first scanning line. In the first frame period, the initialization voltage starts shifting to the second voltage level before supply of the first scan signal of the on level starts.

7. The display device according to claim 6, in, The second voltage level is a voltage level shifted in a negative direction from the first voltage level, The third voltage level is a voltage level shifted in a positive direction from the first voltage level.

8. The display device according to claim 6, in, The initialization voltage generator provides the initialization voltage for initializing an anode of a light emitting diode in each pixel to the first voltage level to each pixel during the first frame period and the second frame period, respectively.

9. The display device according to claim 8, in, The gate electrode of the driving transistor is initialized to the first voltage level before the anode electrode of the light emitting diode in the first frame period and the second frame period, respectively.

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