Semiconductor device structure and method for forming the same

Abstract

An embodiment of the present invention provides a semiconductor device structure and a method for forming the same. The semiconductor device structure includes a plurality of semiconductor nanostructures and two epitaxial structures located above a substrate. Each of the semiconductor nanostructures is located between the two epitaxial structures. The semiconductor device structure also includes a gate stack structure surrounding the semiconductor nanostructure. The semiconductor device structure also includes a stress structure located between the gate stack structure and the substrate. The epitaxial structure extends beyond the top surface of the stress structure.

Description

Technical Field

[0001] The embodiments of the present invention relate to a semiconductor structure, and more particularly to a semiconductor device structure with a stress structure and a manufacturing method thereof. Background Art

[0002] The semiconductor integrated circuit industry has experienced rapid growth. Technological advances in the materials and design of integrated circuits have produced generations of integrated circuits. Each generation has smaller and more complex circuits than the previous generation.

[0003] In the development of integrated circuits, as the geometry size (that is, the minimum device size or line width that can be manufactured using a process) decreases, the functional density (that is, the number of devices connected per chip area) has generally increased. The process of shrinking the size usually has the advantages of improving production efficiency and reducing related costs.

[0004] However, these advances have also increased the complexity of processing and manufacturing integrated circuits. As feature sizes continue to shrink, the manufacturing process continues to become more difficult to perform. Therefore, it has become a challenge to form semiconductor devices that are smaller and smaller and reliable. Summary of the invention

[0005] The present disclosure aims to provide a semiconductor device structure and a method for forming the same to solve at least one of the above problems.

[0006] An embodiment of the present disclosure discloses a semiconductor device structure, including a plurality of semiconductor nanostructures, two epitaxial structures, a gate stack structure, and a stress structure. The plurality of semiconductor nanostructures are located above a substrate; the two epitaxial structures are located above the substrate, wherein each of the plurality of semiconductor nanostructures is located between the two epitaxial structures; the gate stack structure surrounds the plurality of semiconductor nanostructures; and the stress structure is located between the gate stack structure and the substrate, wherein the two epitaxial structures extend beyond the top surface of the stress structure.

[0007] An embodiment of the present disclosure discloses a semiconductor device structure, including: a semiconductor fin located above a substrate; a plurality of channel structures stacked above the semiconductor fin; a gate stack structure surrounding each of the plurality of channel structures; an epitaxial structure adjacent to the plurality of channel structures; and a stress structure located between the substrate and the plurality of channel structures, wherein the stress structure contains oxygen and a semiconductor material other than silicon.

[0008] One embodiment of the present disclosure discloses a method for forming a semiconductor device structure, comprising: forming a base layer on a semiconductor substrate; forming a semiconductor stacking structure on the base layer, wherein the semiconductor stacking structure has a plurality of sacrificial layers and a plurality of semiconductor layers arranged alternately; patterning the semiconductor stacking structure and the base layer to form a fin structure; forming an isolation structure surrounding a lower portion of the fin structure, wherein a top surface of the isolation structure is higher than a top surface of the base layer; removing the plurality of sacrificial layers to release a plurality of semiconductor nanostructures, wherein the plurality of semiconductor nanostructures are composed of remaining portions of the plurality of semiconductor layers; converting at least an upper portion of the base layer into a stress structure; and forming a metal gate stacking structure to surround each of the plurality of semiconductor nanostructures.

[0009] An embodiment of the present invention provides a semiconductor device structure and a method for forming the same, wherein the semiconductor device structure has a stress structure located below a channel structure. A gate stack structure surrounds the channel structure. For example, the semiconductor device structure includes a stack structure of multiple channel structures, wherein the multiple channel structures are surrounded by a metal gate stack structure. Before the gate stack structure is formed, the semiconductor element located below the channel structure is converted into a stress structure. The stress structure can induce an epitaxial structure located next to the channel structure to apply stress (e.g., tensile stress) to the channel structure. In this way, the carrier mobility in the channel structure can be improved, greatly improving the performance and reliability of the semiconductor device structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The following detailed description is provided in conjunction with the accompanying drawings for complete disclosure. It should be noted that, in accordance with common practices in the industry, the illustrations are not necessarily drawn to scale. In fact, the dimensions of the components may be arbitrarily enlarged or reduced for clarity of illustration.

[0011] Figure 1A-1B are top views of various stages of a process for forming a semiconductor device structure according to some embodiments.

[0012] Figure 2A-2J are cross-sectional diagrams illustrating various stages of a process for forming a semiconductor device structure according to some embodiments.

[0013] Figure 3A-Figure 3N are cross-sectional diagrams illustrating various stages of a process for forming a semiconductor device structure according to some embodiments.

[0014] Figure 4A-4B are cross-sectional diagrams illustrating various stages of a process for forming a semiconductor device structure according to some embodiments.

[0015] Figure 5 is a schematic cross-sectional view of a semiconductor device structure according to some embodiments.

[0016] Figure 6is a schematic cross-sectional view of a semiconductor device structure according to some embodiments.

[0017] Figure 7A-7C are cross-sectional diagrams illustrating various stages of a process for forming a semiconductor device structure according to some embodiments.

[0018] Figures 8A-8C are cross-sectional diagrams illustrating various stages of a process for forming a semiconductor device structure according to some embodiments.

[0019] Fig. 9 is a schematic cross-sectional view of a semiconductor device structure according to some embodiments.

[0020] Fig.10 is a schematic cross-sectional view of a semiconductor device structure according to some embodiments.

[0021] Fig.11 is a schematic cross-sectional view of a semiconductor device structure according to some embodiments.

[0022] Fig.12 is a schematic cross-sectional view of a semiconductor device structure according to some embodiments.

[0023] Fig.13 is a schematic cross-sectional view of a semiconductor device structure according to some embodiments.

[0024] Figure 14A-Figure 14C are cross-sectional diagrams illustrating various stages of a process for forming a semiconductor device structure according to some embodiments.

[0025] Fig.15 is a schematic cross-sectional view of a semiconductor device structure according to some embodiments.

[0026] Fig.16 is a schematic cross-sectional view of a semiconductor device structure according to some embodiments.

[0027] Figure 17A-17C are cross-sectional diagrams illustrating various stages of a process for forming a semiconductor device structure according to some embodiments.

[0028] The reference numerals are as follows:

[0029] 100:Semiconductor substrate

[0030] 101A: Semiconductor fins

[0031] 101B: Semiconductor fins

[0032] 102a: semiconductor layer

[0033] 102a': semiconductor element

[0034] 102a”: Semiconductor components

[0035] 102a”': Semiconductor components

[0036] 102b: semiconductor layer

[0037] 102c: Semiconductor layer

[0038] 102d: Semiconductor layer

[0039] 104a: semiconductor layer

[0040] 104b: semiconductor layer

[0041] 104c: Semiconductor layer

[0042] 104d: Semiconductor layer

[0043] 104a': Semiconductor Nanostructures

[0044] 104b': Semiconductor Nanostructures

[0045] 104c': Semiconductor Nanostructures

[0046] 104d': Semiconductor Nanostructures

[0047] 105a: Edge element

[0048] 105b: Edge element

[0049] 105c: Edge element

[0050] 105d: Edge component

[0051] 106A: Fin structure

[0052] 106B: Fin structure

[0053] 108: first mask layer

[0054] 110: second mask layer

[0055] 112: Groove

[0056] 114: Isolation Structure

[0057] 116: dummy gate dielectric layer

[0058] 118: dummy gate electrode

[0059] 120A: Dummy gate stack structure

[0060] 120B: dummy gate stack structure

[0061] 122: mask layer

[0062] 124: mask layer

[0063] 126: spacer layer

[0064] 126': Spacer element

[0065] 128: spacer layer

[0066] 128': Spacer element

[0067] 130: Notch

[0068] 132: Notch

[0069] 134: Spacer layer

[0070] 134': Spacer layer

[0071] 136: Internal spacer

[0072] 136': Bottom internal spacer

[0073] 138: Epitaxial structure

[0074] 139: Contact Etch Stop Layer

[0075] 140: Dielectric layer

[0076] 142: Groove

[0077] 144: Notch

[0078] 146: Stress Structure

[0079] 148: Oxide element

[0080] 150: Gate dielectric layer

[0081] 152: Work function layer

[0082] 154: Conductive filler

[0083] 156A: Metal gate stack structure

[0084] 156B: Metal gate stack structure

[0085] T1: Thickness

[0086] T2: Thickness DETAILED DESCRIPTION

[0087] The following disclosure provides many different embodiments or examples to implement different features of the present invention. The following disclosure describes specific examples of each component and its arrangement to simplify the description. Of course, these specific examples are not intended to be limiting. For example, if this specification describes a first component formed on or above a second component, it means that it may include an embodiment in which the first component and the second component are in direct contact, and may also include an embodiment in which an additional component is formed between the first component and the second component, so that the first component and the second component may not be in direct contact. In addition, the different examples disclosed below may reuse the same reference symbols and / or marks. These repetitions are for the purpose of simplicity and clarity, and are not used to limit the specific relationship between the different embodiments and / or structures discussed.

[0088] Additionally, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like are used to facilitate describing the relationship of one element or component to another element or components in the drawings. These spatially relative terms are intended to encompass different orientations of the device of the components in addition to the orientation depicted in the drawings. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative terms used herein should likewise be interpreted accordingly.

[0089] A person of ordinary skill in the art to which the present invention belongs will understand the term "substantially" in the specification, such as "substantially flat" or "substantially coplanar", etc. In some embodiments, the adjective "substantially" may be omitted. Where applicable, the term "substantially" may also include embodiments with "entirely", "completely", "all", etc. Where applicable, the term "substantially" may also mean 90% or higher, for example, 95% or higher, in particular 99% or higher, including 100%. Furthermore, terms such as "substantially parallel" or "substantially perpendicular" are interpreted as not excluding minor deviations from a specific configuration, and may include, for example, deviations of up to 10°. The term "substantially" does not exclude "completely", for example, a composition "substantially free of" Y may be completely free of Y.

[0090] For example, the term "about" in combination with a specific distance or size is to be interpreted as not excluding minor deviations from the specific distance or size and may include deviations of, for example, up to 10%. The term "about" is used for a numerical value x and may mean x±5% or 10%.

[0091] Embodiments of the present invention may be related to a fin field effect transistor (FinFET) structure having fins. The fins may be patterned using any suitable method. For example, the fins may be patterned using one or more photolithography processes, including a double patterning process or a multiple patterning process. Generally speaking, a double patterning or multiple patterning process combines a photolithography process with a self-aligned process to create a pattern with a smaller pitch, for example, a pattern having a pitch smaller than that obtainable using a single direct photolithography process. For example, in some embodiments, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. Thereafter, the sacrificial layer is removed, and the fins may then be patterned using the remaining spacers. However, one or more other applicable processes may be used to form the fins.

[0092] Embodiments of the present invention may relate to a gate all around (GAA) transistor structure. The gate all around structure may be patterned using any suitable method. For example, the structures may be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Generally speaking, the double patterning or multiple patterning process combines a photolithography process with a self-alignment process to create a pattern with a smaller pitch, for example, a pattern having a pitch smaller than that obtainable using a single direct photolithography process. For example, in some embodiments, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. Thereafter, the sacrificial layer is removed, and the remaining spacers may then be used to pattern the gate all around structure.

[0093] The specification describes some embodiments of the present disclosure. Additional operation steps may be provided before, between, and / or after the stages described in these embodiments. For different embodiments, some of the step stages described may be replaced or omitted. Additional components may be added to the semiconductor device structure. For different embodiments, some of the components described below may be replaced or omitted. Although some embodiments are described as operating in a specific order, these operations may also be performed in other logical orders.

[0094] Figure 2A-2J is a cross-sectional schematic diagram of various stages of a process for forming a semiconductor device structure according to some embodiments. Figure 2AAs shown, a semiconductor substrate 100 is received or provided. In some embodiments, the semiconductor substrate 100 is a bulk semiconductor substrate, such as a semiconductor wafer. The semiconductor substrate 100 includes silicon or other elemental semiconductor materials, such as germanium. The semiconductor substrate 100 can be undoped or doped (e.g., p-type, n-type, or a combination thereof). In some embodiments, the semiconductor substrate 100 includes an epitaxially grown semiconductor layer on a dielectric layer. The epitaxially grown semiconductor layer can be formed of silicon germanium, silicon, germanium, one or more other suitable materials, or a combination thereof.

[0095] In some other embodiments, the semiconductor substrate 100 includes a compound semiconductor. For example, the compound semiconductor includes one or more III-V group compound semiconductors having a chemical formula of Al X1 Ga X2 In X3 As Y1 P Y2 N Y3 Sb Y4 The composition defined herein, wherein X1, X2, X3, Y1, Y2, Y3 and Y4 represent relative ratios. Each of X1, X2, X3, Y1, Y2, Y3 and Y4 is greater than or equal to 0, and the sum thereof is equal to 1. The compound semiconductor may include silicon carbide, gallium arsenide, indium arsenide, indium phosphide, one or more other suitable compound semiconductors, or a combination thereof. Other suitable substrates including Group II-VI compound semiconductors may also be used.

[0096] In some embodiments, the semiconductor substrate 100 is an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor-on-insulator substrate can be manufactured using a separation by implantation of oxygen (SIMOX) process, a wafer bonding process, other applicable methods, or a combination thereof. In some other embodiments, the semiconductor substrate 100 includes a multilayer structure. For example, the semiconductor substrate 100 includes a silicon germanium layer formed on a bulk silicon layer.

[0097] According to some embodiments, Figure 2A As shown, a semiconductor stack structure having a plurality of semiconductor layers is formed on a semiconductor substrate 100. In some embodiments, the semiconductor stack structure includes a plurality of semiconductor layers 102a, 102b, 102c, and 102d, and the semiconductor stack structure also includes a plurality of semiconductor layers 104a, 104b, 104c, and 104d. In some embodiments, as Figure 2A As shown, the semiconductor layers 102a-102d are arranged alternately with the semiconductor layers 104a-104d.

[0098] In some embodiments, the semiconductor layer 102a is used as a base layer and will be partially or completely transformed into a stressor structure in a subsequent process. In some embodiments, the semiconductor layer 104a serves as a protective layer to prevent the semiconductor layer 102a from being damaged during a subsequent manufacturing process. In some embodiments, the semiconductor layer 104a is thinner than the semiconductor layers 104b, 104c, or 104d. In some embodiments, the semiconductor layers 102b-102d serve as sacrificial layers that will be removed in a subsequent process to release the semiconductor layers 104b-104d. The semiconductor layers 104b-104d can serve as channel structures of one or more transistors.

[0099] like Figure 2A As shown, semiconductor layer 104a has a thickness T1, and semiconductor layer 104b has a thickness T2. In some embodiments, thickness T2 is greater than thickness T1. Thickness T1 may be in a range of about 2 nm to about 6 nm. For example, thickness T1 is about 4 nm. The ratio of thickness T1 to thickness T2 (T1 / T2) may be in a range of about 2 / 5 to about 2 / 3.

[0100] In some embodiments, each of the semiconductor layers 102a-102d and the semiconductor layers 104b-104d have substantially the same thickness. In some embodiments, each of the semiconductor layers 104b-104d is thicker than each of the semiconductor layers 102a-102d. In some other embodiments, each of the semiconductor layers 102a-102d is thicker than each of the semiconductor layers 104b-104d.

[0101] In some embodiments, the semiconductor layers 102a-102d and the semiconductor layers 104a-104d are formed of different materials. In some embodiments, the semiconductor layers 102a-102d are formed of or include silicon germanium or germanium, and the semiconductor layers 104a-104d are formed of or include silicon.

[0102] In some embodiments, the semiconductor layers 102a-102d and the semiconductor layers 104a-104d are formed using multiple epitaxial growth. Each of the semiconductor layers 102a-102d and the semiconductor layers 104a-104d may be formed using a selective epitaxial growth (SEG) process, a chemical vapor deposition (CVD) process (e.g., a vapor-phase epitaxy (VPE) process, a low pressure chemical vapor deposition (LPCVD) process, and / or an ultra-high vacuum chemical vapor deposition (UHV-CVD) process), a molecular beam epitaxy process, one or more other applicable processes, or a combination thereof. In some embodiments, the semiconductor layers 102a-102d and the semiconductor layers 104a-104d are grown in-situ in the same process chamber. In some embodiments, the growth of semiconductor layers 102a-102d and the growth of semiconductor layers 104a-104d are performed alternately and sequentially in the same process chamber to complete the formation of the semiconductor stack structure. In some embodiments, the vacuum of the process chamber is not destroyed before the epitaxial growth of the semiconductor stack structure is completed.

[0103] Afterwards, a hard mask element is formed on the semiconductor stack structure to assist in subsequent patterning of the semiconductor stack structure. Figure 2B As shown, one or more etching processes are used to pattern the semiconductor stack structure to form fin structures 106A and 106B. The semiconductor stack structure is partially removed to form trenches 112, such as Figure 2B As shown. Each of the fin structures 106A and 106B may include a portion of the semiconductor layers 102a-102d and 104a-104d and the semiconductor fins 101A and 101B. During the etching process for forming the fin structures 106A and 106B, the semiconductor substrate 100 may also be partially removed. The protruding portions of the remaining semiconductor substrate 100 form the semiconductor fins 101A and 101B.

[0104] Each of the hard mask elements may include a first mask layer 108 and a second mask layer 110. The first mask layer 108 and the second mask layer 110 may be formed of different materials. In some embodiments, the first mask layer 108 is formed of a material having good adhesion to the semiconductor layer 104d. The first mask layer 108 may be formed of silicon oxide, germanium oxide, silicon germanium oxide, one or more other suitable materials, or a combination thereof. In some embodiments, the second mask layer 110 is formed of a material having good etching selectivity to the semiconductor layers 102a-102d and 104a-104d. The second mask layer 110 is formed of silicon nitride, silicon oxynitride, silicon carbide, one or more other suitable materials, or a combination thereof.

[0105] Figure 1A-1B is a top view of various stages of a process for forming a semiconductor device structure according to some embodiments. In some embodiments, Figure 2B It is along Figure 1A A schematic cross-sectional view of a structure taken along section line 2B-2B. Figure 1A As shown, the extension directions of the fin structures 106A and 106B are substantially parallel to each other.

[0106] According to some embodiments, Figure 2C As shown, an isolation structure 114 is formed to surround lower portions of the fin structures 106A and 106B. In some embodiments, one or more dielectric layers are deposited on the fin structures 106A and 106B and the semiconductor substrate 100 to overfill the trench 112. The dielectric layer may be formed of silicon oxide, silicon oxynitride, borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), a low-k material, a porous dielectric material, one or more other suitable materials, or a combination thereof. The dielectric layer may be deposited using a flowable chemical vapor deposition (FCVD) process, an atomic layer deposition (ALD) process, a chemical vapor deposition process, one or more other suitable processes, or a combination thereof.

[0107] Thereafter, a planarization process is used to partially remove the dielectric layer. The hard mask element (including the first mask layer 108 and the second mask layer 110) may also serve as a stop layer for the planarization process. The planarization process may include a chemical mechanical polishing (CMP) process, a grinding process, a dry polishing process, an etching process, one or more other applicable processes, or a combination thereof. Thereafter, one or more etch-back processes are used to partially remove the dielectric layer. Thus, the remaining portion of the dielectric layer forms the isolation structure 114. The upper portions of the fin structures 106A and 106B protrude from the top surface of the isolation structure 114, as shown in FIG. Figure 2C Shown.

[0108] In some embodiments, Figure 2C As shown, the etch-back process for forming the isolation structure 114 is carefully controlled to ensure that the top surface of the isolation structure 114 is higher than the top surface of the semiconductor layer 102a. Therefore, the sidewalls of the semiconductor layer 102a are protected by the isolation structure 114. The isolation structure 114 and the semiconductor layer 104a together protect the semiconductor layer 102a to prevent the semiconductor layer 102a from being damaged during subsequent processes.

[0109] Then, according to some embodiments, such as Figure 1B As shown, dummy gate stack structures 120A and 120B are formed to extend across fin structures 106A and 106B. In some embodiments, Figure 2D It is along Figure 1B A schematic cross-sectional view of the structure taken along section line 2D-2D. Figure 3A-Figure 3N is a cross-sectional view of various stages of a process for forming a semiconductor device structure according to some embodiments. In some embodiments, Figure 3A It is along Figure 1B A schematic cross-sectional view of the structure taken along section line 3A-3A.

[0110] According to some embodiments, Figure 1B , Figure 2D and Figure 3A As shown, the dummy gate stack structures 120A and 120B are formed to partially cover and extend across the fin structures 106A and 106B. In some embodiments, the dummy gate stack structures 120A and 120B surround the fin structures 106A and 106B. Figure 2D As shown, the dummy gate stack structure 120B extends across and around the fin structures 106A and 106B.

[0111] like Figure 2D and Figure 3AAs shown, each of the dummy gate stack structures 120A and 120B includes a dummy gate dielectric layer 116 and a dummy gate electrode 118. The dummy gate dielectric layer 116 may be formed of or include silicon oxide. The dummy gate electrode 118 may be formed of or include polysilicon. In some embodiments, the dummy gate dielectric material layer and the dummy gate electrode layer are sequentially deposited on the isolation structure 114 and the fin structures 106A and 106B. Thereafter, the dummy gate dielectric material layer and the dummy gate electrode layer are patterned to form the dummy gate stack structures 120A and 120B.

[0112] In some embodiments, a hard mask element including mask layers 122 and 124 is used to assist in the patterning process for forming the dummy gate stack structures 120A and 120B. One or more etching processes are used to partially remove the dummy gate dielectric material layer and the dummy gate electrode layer using the hard mask element as an etching mask. As a result, the remaining portions of the dummy gate dielectric material layer and the dummy gate electrode layer form the dummy gate dielectric layer 116 and the dummy gate electrode 118 of the dummy gate stack structures 120A and 120B, respectively.

[0113] Then, according to some embodiments, such as Figure 3B As shown, spacer layers 126 and 128 are deposited on Figure 3A 120A and 120B. The spacer layers 126 and 128 extend along the sidewalls of the dummy gate stack structures 120A and 120B. The spacer layers 126 and 128 are formed of different materials. The spacer layer 126 may be formed of a dielectric material having a low dielectric constant. The spacer layer 126 may be formed of or include silicon carbide, silicon oxycarbide, silicon oxide, one or more other suitable materials, or a combination of the foregoing. The spacer layer 128 may be formed of a dielectric material that can provide more protection for the gate stack structure during subsequent processes. The spacer layer 128 may have a dielectric constant greater than the dielectric constant of the spacer layer 126. The spacer layer 128 may be formed of silicon nitride, silicon oxynitride, carbon-containing silicon nitride, carbon-containing silicon oxynitride, one or more other suitable materials, or a combination of the foregoing. The spacer layers 126 and 128 may be sequentially deposited using a chemical vapor deposition process, an atomic layer deposition process, a physical vapor deposition (PVD) process, one or more other applicable processes, or a combination thereof.

[0114] According to some embodiments, Figure 3CAs shown, the spacer layers 126 and 128 are partially removed. One or more anisotropic etching processes may be used to partially remove the spacer layers 126 and 128. As a result, the remaining portions of the spacer layers 126 and 128 form spacer elements 126' and 128', respectively. Figure 3C As shown, spacer elements 126 ′ and 128 ′ extend along sidewalls of the dummy gate stack structures 120A and 120B.

[0115] Afterwards, the fin structures 106A and 106B are partially removed to form a recess 130 for accommodating an epitaxial structure (eg, a source / drain structure) to be formed subsequently. Figure 3C As shown, the fin structure 106A is partially removed to form the notch 130. One or more etching processes are used to form the notch 130. In some embodiments, a dry etching process is used to form the notch 130. Alternatively, a wet etching process may be used to form the notch 130. In some embodiments, each of the notches 130 passes through the fin structure 106A. In some embodiments, as shown in FIG. Figure 3C As shown, the recess 130 extends further into the semiconductor fin 101A.

[0116] In some embodiments, each of the recesses 130 has a sloped sidewall. The upper portion of the recess 130 is larger (or wider) than the lower portion of the recess 130. In these cases, due to the profile of the recess 130, the upper semiconductor layer (e.g., semiconductor layer 104d) is shorter than the lower semiconductor layer (e.g., semiconductor layer 104b).

[0117] However, there are many variations of the present invention. In some other embodiments, the recess 130 has substantially vertical sidewalls. In these cases, due to the profile of the recess 130, the upper semiconductor layer (e.g., semiconductor layer 104d) and the lower semiconductor layer (e.g., semiconductor layer 104b) are substantially the same width.

[0118] According to some embodiments, Figure 3D As shown, the semiconductor layers 102a-102d are laterally etched. As a result, the edges of the semiconductor layers 102a-102d are retreated from the edges of the semiconductor layers 104a-104d. Figure 3D As shown, due to the lateral etching of the semiconductor layers 102a-102d, a recess 132 is formed. The recess 132 can be used to accommodate the inner spacers to be formed later. The semiconductor layers 102a-102d can be etched laterally using a wet etching process, a dry etching process, or a combination thereof.

[0119] During the lateral etching of the semiconductor layers 102a-102d, the semiconductor layers 104a-104d may also be slightly etched. Figure 3D As shown, edge portions of the semiconductor layers 104a-104d are partially etched and thus shrink to become edge elements 105a-105d. Figure 3D As shown, each of the edge elements 105a-105d of the semiconductor layers 104a-104d is thinner than its corresponding inner portion. In some embodiments, each of the edge elements 105a is thinner than the other upper edge elements (eg, edge elements 105b-105d).

[0120] According to some embodiments, Figure 3E As shown, a spacer layer 134 is deposited on the structure shown in 3D. The spacer layer 134 covers the dummy gate stack structures 120A and 120B and overfills the recess 132. The spacer layer 134 can be formed of or include carbon-containing silicon nitride (SiCN), carbon-containing silicon oxynitride (SiOCN), carbon-containing silicon oxide (SiOC), one or more other suitable materials, or a combination thereof. The spacer layer 134 can be deposited using a chemical vapor deposition process, an atomic layer deposition process, one or more other applicable processes, or a combination thereof.

[0121] According to some embodiments, Figure 3F As shown, an etching process is used to partially remove the spacer layer 134. Figure 3F As shown, the remaining portions of the spacer layer 134 form inner spacers 136. The etching process may include a dry etching process, a wet etching process, or a combination thereof.

[0122] The internal spacers 136 cover the edges of the semiconductor layers 102a-102d that were previously exposed by the recesses 132. In some embodiments, after the etching process for forming the internal spacers 136, the portion of the semiconductor fin 101A that was previously covered by the spacer layer 134 is exposed by the recesses 130. The internal spacers 136 can be used to prevent the subsequently formed epitaxial structure (which serves as, for example, a source / drain structure) from being damaged during a subsequent gate replacement process. The internal spacers 136 can also be used to reduce the parasitic capacitance between the subsequently formed source / drain structure and the gate stack structure.

[0123] According to some embodiments, Figure 3GAs shown, an epitaxial structure 138 is formed next to the dummy gate stack structures 120A and 120B. In some embodiments, as shown in FIG. 3G, the epitaxial structure 138 fills the recess 130. In some other embodiments, the epitaxial structure 138 overfills the recess 130. In these cases, the top surface of the epitaxial structure 138 can be higher than the top surface of the dummy gate dielectric layer 116. In some other embodiments, the epitaxial structure 138 partially fills the recess 130.

[0124] In some embodiments, epitaxial structure 138 is connected to semiconductor layers 104a-104d. Each of semiconductor layers 104a-104d is between two of epitaxial structures 138. In some embodiments, epitaxial structure 138 serves as a source / drain structure. In some embodiments, epitaxial structure 138 is an n-type doped region. Epitaxial structure 138 may include epitaxially grown silicon, epitaxially grown silicon carbide (SiC), epitaxially grown silicon phosphide (SiP), or other suitable epitaxially grown semiconductor materials.

[0125] In some embodiments, the epitaxial structure 138 is formed using a selective epitaxial growth (SEG) process, a chemical vapor deposition process (e.g., a vapor phase epitaxy (VPE) process, a low pressure chemical vapor deposition (LPCVD) process and / or an ultra-high vacuum chemical vapor deposition (UHV-CVD) process), a molecular beam epitaxy process, one or more other applicable processes, or a combination of the foregoing.

[0126] In some embodiments, the epitaxial structure 138 is doped with one or more suitable dopants. For example, the epitaxial structure 138 is a silicon (Si) source / drain feature doped with phosphorus (P), antimony (Sb), or other suitable dopants.

[0127] In some embodiments, the epitaxial structure 138 is doped in-situ during its epitaxial growth. In some other embodiments, the epitaxial structure 138 is not doped during its growth. Instead, the epitaxial structure 138 is doped in a subsequent process after the epitaxial structure 138 is formed. In some embodiments, the aforementioned doping is achieved using an ion implantation process, a plasma immersion ion implantation process, a gas phase and / or solid phase source diffusion process, one or more other applicable processes, or a combination of the above. In some embodiments, the epitaxial structure 138 is further exposed to one or more annealing processes to activate the dopants. For example, a rapid thermal annealing process is used.

[0128] According to some embodiments, Figure 3HAs shown, a contact etch stop layer 139 and a dielectric layer 140 are formed to cover the epitaxial structure 138 and surround the dummy gate stack structures 120A and 120B. The contact etch stop layer 139 may be formed of or include silicon nitride, silicon oxynitride, silicon carbide, aluminum oxide, one or more other suitable materials, or a combination thereof. The dielectric layer 140 may be formed of or include silicon oxide, silicon oxynitride, borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), a low dielectric constant material, a porous dielectric material, one or more other suitable materials, or a combination thereof.

[0129] In some embodiments, an etch stop material layer and a dielectric material layer are sequentially deposited on Figure 3G The structure shown. The etch stop material layer may be deposited using a chemical vapor deposition process, an atomic layer deposition process, a physical vapor deposition process, one or more other applicable processes, or a combination thereof. The dielectric material layer may be deposited using a flow chemical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, one or more other applicable processes, or a combination thereof.

[0130] Afterwards, a planarization process is used to partially remove the etch stop material layer and the dielectric material layer. In this way, the remaining portions of the etch stop material layer and the dielectric material layer form a contact etch stop layer 139 and a dielectric layer 140, respectively. The planarization process may include a chemical mechanical polishing process, a grinding process, an etching process, a dry grinding process, one or more other applicable processes, or a combination thereof. In some embodiments, the mask layers 122 and 124 are removed during the planarization process. In some embodiments, after the planarization process, the top surfaces of the contact etch stop layer 139, the dielectric layer 140, and the dummy gate electrode 118 are substantially coplanar.

[0131] According to some embodiments, Figure 2E and Fig. 3I As shown, one or more etching processes are used to remove the dummy gate stack structures 120A and 120B to form a trench 142. As shown in Figure 2E, the trench 142 exposes the semiconductor layers 102b-102d and 104b-104d previously covered by the dummy gate stack structures 120A and 120B. In some embodiments, as shown in Figure 2E, the semiconductor layers 102a and 104a remain covered by the semiconductor layer 102b and the isolation structure 114, and are not exposed by the trench 142.

[0132] According to some embodiments, Figure 2F and Figure 3JAs shown, the semiconductor layers 102b-102d (which serve as sacrificial layers) are removed to form the recess 144. In some embodiments, an etching process is used to remove the semiconductor layers 102b-102d. Due to the high etching selectivity, the semiconductor layers 104a-104d are not substantially (or only slightly) etched. Figure 2F and Figure 3J As shown, the remaining portions of the semiconductor layers 104a-104d form a plurality of semiconductor nanostructures 104a'-104d' of the fin structures 106A and 106B. The semiconductor nanostructures 104a'-104d' are formed from the remaining portions of the semiconductor layers 104a-104d.

[0133] In some embodiments, the etchant used to remove the semiconductor layers 102b-102d also slightly removes the semiconductor layers 104a-104d forming the semiconductor nanostructures 104a'-104d'. As a result, after the semiconductor layers 102b-102d are removed, the resulting semiconductor nanostructures 104a'-104d' become thinner. In some embodiments, each of the semiconductor nanostructures 104a'-104d' is thinner than the edge elements 105b-105d because other elements surround the edge elements 105b-105d, thereby preventing the etchant from reaching and etching the edge elements 105b-105d.

[0134] After removing the semiconductor layers 102b-102d (which serve as sacrificial layers), a recess 144 is formed. The recess 144 is connected to the trench 142 and surrounds each of the semiconductor nanostructures 104b'-104d'. Figure 3J As shown, even though recesses 144 are formed between semiconductor nanostructures 104a'-104d', semiconductor nanostructures 104b'-104d' are still supported by epitaxial structure 138. Therefore, after removing semiconductor layers 102b-102d (which serve as sacrificial layers), released semiconductor nanostructures 104b'-104d' may be prevented from falling.

[0135] During the removal of the semiconductor layers 102b-102d (which serve as sacrificial layers), the inner spacers 136 protect the epitaxial structure 138 from being etched or damaged, thereby improving the quality and reliability of the semiconductor device structure.

[0136] During the removal of the semiconductor layers 102b-102d (which serve as sacrificial layers), the nanostructures 104a' (which serve as protective layers) and the isolation structures 114 cover and protect the semiconductor layer 102a (which serves as a base layer), as shown in FIG. Figure 2F and Figure 3J As shown, in this way, the semiconductor layer 102a can be prevented from being etched or damaged.

[0137] According to some embodiments, Figure 2G and Figure 3K As shown, the nanostructure 104a' (which serves as a protective layer) is partially removed to expose the semiconductor layer 102a (which serves as a base layer). The nanostructure 104a' may be removed using a dry etching process, a wet etching process, or a combination thereof. During the removal of the nanostructure 104a', the semiconductor nanostructures 104b'-104d' may also be slightly etched.

[0138] After partially removing the nanostructure 104a', each of the edge elements 105a still remains between the two inner spacers 136. In some embodiments, each of the remaining edge elements 105a is thinner than each of the semiconductor nanostructures 104b'-104d', such as Figure 3K In some embodiments, the length of each of the remaining edge elements 105a is shorter than the length of each of the semiconductor nanostructures 104b'-104d', such as Figure 3K Shown.

[0139] As described above, in some embodiments, Figure 2A As shown, the ratio (T1 / T2) of the thickness T1 of the semiconductor layer 104a (which then serves as a protective layer for the semiconductor layer 102a) to the thickness T2 of the semiconductor layer 104b (which then becomes the semiconductor nanostructure 104b') may be in the range of about 2 / 5 to about 2 / 3. In some cases, if the thickness ratio (T1 / T2) is less than about 2 / 5, the semiconductor layer 104a having the thickness T1 may be too thin. Therefore, in the case of Figure 2F and Figure 3J During the removal of the semiconductor layers 102b-102d (which serve as sacrificial layers) shown, the semiconductor layer 104a may be completely removed or damaged, exposing the semiconductor layer 102a below the semiconductor layer 104a to the etchant. The semiconductor layer 102a may be damaged. In some other cases, if the thickness ratio (T1 / T2) is greater than about 2 / 3, the semiconductor layer 104a having a thickness T1 may be too thick. As a result, in the case of Figure 2G and Figure 3K During the illustrated partial removal of the nanostructure 104a' to expose the semiconductor layer 102a, the semiconductor nanostructures 104b'-104d' may be excessively consumed due to the relatively harsh etching process that may be used to remove the nanostructure 104a'. The performance of the semiconductor device structure may be negatively affected.

[0140] According to some embodiments, Figure 2H and Figure 3LAs shown, the semiconductor layer 102a (which serves as a base layer) is transformed into the stress structure 146. In some embodiments, the entirety of the semiconductor layer 102a is transformed into the stress structure 146. Figure 2H As shown, the stress structure 146 is surrounded by the isolation structure 114. In some embodiments, one of the inner spacers 136 (eg, the bottommost inner spacer 136) directly contacts the adjacent stress structure 146 and the epitaxial structure 138, such as Figure 3L Shown.

[0141] In some embodiments, the stress structure 146 may be formed by oxidizing the semiconductor layer 102a. A thermal operation may be used to form the stress structure 146. The thermal operation may be performed at a temperature in the range of about 400° C. to about 850° C. The thermal operation time may be in the range of about 0.5 hours to about 4 hours. The thermal operation may be performed in an oxygen-containing environment. The oxygen-containing environment may include oxygen or a gas mixture including oxygen.

[0142] After the thermal operation, the stress structures 304 may "expand" and transform into stress structures 146 formed of a semiconductor oxide material. The stress structures 146 may include oxygen and a semiconductor material other than silicon (e.g., germanium). The stress structures 146 may be formed of or include silicon germanium oxide, germanium oxide, one or more other suitable materials, or a combination thereof. In some embodiments, each of the stress structures 146 becomes thicker than the original semiconductor layer 102a that has not yet been transformed into the stress structures 146. In some embodiments, the top surface of the stress structures 146 is located at a higher position than the top surface of the semiconductor layer 102a. In some embodiments, the top surface of the stress structures 146 is substantially flush with the top surface of the edge element 105a.

[0143] Due to the expansion during the transformation of the semiconductor layer 102a into the stress structure 146, the stress structure 146 can apply compressive stress to the epitaxial structure 138, so that the epitaxial structure 138 can be slightly pushed away. In response, the epitaxial structure 138 can apply tensile stress to the semiconductor nanostructures 104b'-104d' as channel structures. In this way, the electron carrier mobility can be increased. Therefore, the performance of the semiconductor device structure is significantly improved. In some embodiments, the semiconductor nanostructures 104b'-104d' serve as channel structures of n-type metal oxide semiconductor field effect transistors.

[0144] According to some embodiments, Figure 2H and Figure 3LAs shown, during the thermal operation used to form the stress structure 146, the surface of the semiconductor nanostructures 104b'-104d' may also be partially oxidized to form oxide elements 148. The oxide elements 148 may be formed of a material different from the stress structure 146. The oxide elements 148 may be formed of or include silicon oxide, germanium oxide, one or more other suitable materials, or combinations thereof.

[0145] According to some embodiments, Fig.2I and Figure 3M As shown, the oxide element 148 is removed. After removing the oxide element 148, the semiconductor nanostructures 104b'-104d' may become thinner. The oxide element 148 may be removed using an etching process. The etching process may also partially remove the stress structure 146. Thus, according to some embodiments, the top surface of the stress structure 146 is located at a height position between the top surface and the bottom surface of the edge element 105a, such as Figure 3M In some embodiments, the top surface of the stress structure 146 is located at a lower height than the top surface of the isolation structure 114, such as Fig.2I The stress structure 146 may have a thickness in a range of about 10 nm to about 40 nm.

[0146] According to some embodiments, Figure 2J and Figure 3N As shown, metal gate stack structures 156A and 156B are formed to fill trench 142. Metal gate stack structures 156A and 156B extend into recess 144 to surround each of semiconductor nanostructures 104b'-104d'. Figure 2J and Figure 3N As shown, each of the stress structures 146 directly contacts the corresponding semiconductor fin 101A or 101B, the corresponding isolation structure 114 , and the corresponding metal gate stack structure 156A or 156B.

[0147] Each of the metal gate stack structures 156A and 156B includes a plurality of metal gate stack structure layers. Each of the metal gate stack structures 156A and 156B may include a gate dielectric layer 150, a work function layer 152, and a conductive filler 154. In some embodiments, the formation of the metal gate stack structures 156A and 156B includes depositing a plurality of metal gate stack structure layers on the dielectric layer 140 to fill the trench 142. The metal gate stack structure layers extend into the recess 144 to surround each of the semiconductor nanostructures 104b'-104d'.

[0148] In some embodiments, the gate dielectric layer 150 is formed of or includes a dielectric material having a high dielectric constant. The gate dielectric layer 150 may be formed of or include hafnium oxide, zirconium oxide, aluminum oxide, hafnium dioxide-alumina alloy, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, one or more other suitable high dielectric constant materials, or a combination thereof. The gate dielectric layer 150 may be deposited using an atomic layer deposition process, a chemical vapor deposition process, one or more other suitable processes, or a combination thereof.

[0149] In some embodiments, before forming the gate dielectric layer 150, an interfacial layer is formed on the surface of the semiconductor nanostructures 104b'-104d'. The interfacial layer is very thin and is formed of, for example, silicon oxide or germanium oxide. In some embodiments, the interfacial layer is formed by applying an oxidant on the surface of the semiconductor nanostructures 104b'-104d'. For example, a liquid containing hydrogen peroxide may be applied or provided on the surface of the semiconductor nanostructures 104b'-104d' to form the interfacial layer.

[0150] The work function layer 152 can be used to provide a desired work function of the transistor to enhance device performance, including improved threshold voltage. In some embodiments, the work function layer 152 is used to form an n-type metal oxide semiconductor (NMOS) device. The work function layer 152 is an n-type work function layer. The n-type work function layer can provide a work function value suitable for the device, for example, equal to or less than about 4.5 eV.

[0151] The n-type work function layer may include a metal, a metal carbide, a metal nitride, or a combination thereof. For example, the n-type work function layer includes titanium nitride, tantalum, tantalum nitride, one or more other suitable materials, or a combination thereof. In some embodiments, the n-type work function layer is an aluminum-containing layer. The aluminum-containing layer may be formed of or include titanium carbide (TiAlC), titanium oxide (TiAlO), titanium nitride (TiAlN), one or more other suitable materials, or a combination thereof.

[0152] The work function layer 152 may also be formed of or include hafnium, zirconium, titanium, tantalum, aluminum, metal carbides (hafnium carbide, zirconium carbide, titanium carbide, aluminum carbide), aluminides, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides, or combinations thereof. The thickness and / or composition of the work function layer 152 may be fine-tuned to adjust the work function level.

[0153] The work function layer 152 may be deposited on the gate dielectric layer 150 using an atomic layer deposition process, a chemical vapor deposition process, a physical vapor deposition process, an electroplating process, an electroless plating process, one or more other applicable processes, or a combination thereof.

[0154] In some embodiments, a barrier layer is formed before the work function layer 152 to serve as an interface between the gate dielectric layer 150 and the subsequently formed work function layer 152. The barrier layer may also be used to prevent diffusion between the gate dielectric layer 150 and the subsequently formed work function layer 152. The barrier layer may be formed of or include a metal-containing material. The metal-containing material may include titanium nitride, tantalum nitride, one or more other suitable materials, or a combination thereof. The barrier layer may be deposited using an atomic layer deposition process, a chemical vapor deposition process, a physical vapor deposition process, an electroplating process, an electroless plating process, one or more other applicable processes, or a combination thereof.

[0155] In some embodiments, the conductive filler 154 is formed of or includes a metal material. The metal material may include tungsten, aluminum, copper, cobalt, one or more other suitable materials, or a combination thereof. A conductive layer for forming the conductive filler 154 may be deposited on the work function layer 152 using a chemical vapor deposition process, an atomic layer deposition process, a physical vapor deposition process, an electroplating process, an electroless plating process, a spin coating process, one or more other applicable processes, or a combination thereof.

[0156] In some embodiments, a barrier layer is formed on the work function layer 152 before the conductive layer for forming the conductive filler 154 is formed. The barrier layer can be used to prevent the subsequently formed conductive layer from diffusing or penetrating into the work function layer 152. The barrier layer can be formed of or include tantalum nitride, titanium nitride, one or more other applicable materials, or a combination thereof. The barrier layer can be deposited using an atomic layer deposition process, a physical vapor deposition process, an electroplating process, an electroless plating process, one or more other applicable processes, or a combination thereof.

[0157] Then, according to some embodiments, a planarization process is performed to remove the portion of the metal gate stack structure layer outside the trench 142. As a result, the remaining portion of the metal gate stack structure layer forms the metal gate stack structures 156A and 156B. Figure 2J and Figure 3NAs shown. In some embodiments, since the recess 144 is very small and has been filled with other elements (e.g., the gate dielectric layer 150 and the work function layer 152), the conductive filler 154 does not extend into the recess 144. However, the embodiments of the present invention are not limited thereto. In some other embodiments, a portion of the conductive filler 154 extends into the recess 144, especially in the lower recess 144 which may have a larger space.

[0158] In some embodiments, the epitaxial structure 138 extends beyond the top surface of the stress structure 146. In some embodiments, the epitaxial structure 138 extends beyond the interface between the stress structure 146 and the metal gate stack structure 156A or 156B. In some embodiments, the epitaxial structure 138 further extends beyond the bottom surface of the stress structure 146. Therefore, the stress structure 146 can more easily apply compressive stress to the epitaxial structure 138. Therefore, the epitaxial structure 138 can apply tensile stress to the semiconductor nanostructures 104b'-104d' as channel structures. Thus, the performance of the semiconductor device structure is significantly improved.

[0159] In some embodiments, the top surface of the stress structure 146 is located between the top surface and the bottom surface of the edge element 105a. Figure 3N However, the embodiments of the present invention are not limited thereto. Many changes and / or modifications may be made to the embodiments of the present invention.

[0160] Figure 4A-4B is a cross-sectional schematic diagram of various stages of a process for forming a semiconductor device structure according to some embodiments. Figure 4A Show, form or receive Figure 3L In some embodiments, the stress structure 146 expands to exceed the top surface of the edge element 105a, such as Figure 4A Afterwards, Figure 3M-Figure 3N Thus, according to some embodiments, forming Figure 4B The semiconductor device structure shown. Figure 4B As shown, the top surface of the stress structure 146 is higher than the top surface of the edge element 105a.

[0161] Many variations and / or modifications may be made to the embodiments of the present invention. Figure 5 is a schematic cross-sectional view of a semiconductor device structure according to some embodiments. In some embodiments, a top surface of the stress structure 146 is substantially flush with a top surface of the edge element 105a.

[0162] Many variations and / or modifications may be made to the embodiments of the present invention. Figure 6is a schematic cross-sectional view of a semiconductor device structure according to some embodiments. In some embodiments, a top surface of the stress structure 146 is lower than a top surface of the edge element 105 a.

[0163] In some embodiments, each of the edge elements 105a is sandwiched between two internal spacers 136. In some embodiments, each of the edge elements 105a is not connected to the channel structure, such as Figure 3N As shown, each of the edge elements 105a is thinner than edge elements 105b, 105c or 105d.

[0164] However, the embodiments of the present invention are not limited thereto. Many variations and / or modifications may be made to the embodiments of the present invention. In some other embodiments, the semiconductor device structure does not include the edge element 105a.

[0165] Figure 7A-7C is a cross-sectional schematic diagram of various stages of a process for forming a semiconductor device structure according to some embodiments. Fig. 7A Show, form or receive Figure 3C The structures shown are the same or similar structures.

[0166] According to some embodiments, Figure 7B As shown, Figure 3D The process shown is the same or similar to the process for laterally etching the semiconductor layers 102a-102d to form the recess 132. As described above, during the laterally etching of the semiconductor layers 102a-102d, edge portions of the semiconductor layers 104a-104d may also be etched. In some embodiments, the semiconductor layer 104a is very thin. As such, during the laterally etching of the semiconductor layers 102a-102d, edge portions of the semiconductor layer 104a are completely removed (or consumed). The edge portions of the semiconductor layer 104a do not protrude from the sidewalls of the semiconductor layers 102a and 102b to form edge elements. Compare Figure 7B and Figure 3D In the embodiment shown, one difference is that Figure 7B The exemplary embodiment shown has no edge element 105 a .

[0167] Afterwards, conduct Figure 3M-Figure 3N Thus, according to some embodiments, forming Figure 7C The semiconductor device structure is shown.

[0168] In some embodiments, the semiconductor layer 102a is entirely oxidized to transform into a stress structure 146, such as Figure 3K and Figure 3LAs shown. However, the embodiments of the present invention are not limited thereto. Many variations and / or modifications may be made to the embodiments of the present invention. In some other embodiments, the semiconductor layer 102a is partially oxidized and / or transformed into the stress structure 146. In some embodiments, the upper portion of the semiconductor layer 102a is oxidized and / or transformed into the stress structure 146, while the lower portion of the semiconductor layer 102a is not oxidized and / or transformed.

[0169] Figures 8A-8C is a cross-sectional schematic diagram of various stages of a process for forming a semiconductor device structure according to some embodiments. Fig. 8A Show, form or receive Figure 3K The structures shown are the same or similar structures.

[0170] Then, according to some embodiments, such as Figure 8B Shown, similar to Figure 3L In the process shown, the semiconductor layer 102a is oxidized. In some embodiments, the upper portion of the semiconductor layer 102a is oxidized and / or converted into a stress structure 146. The lower portion of the semiconductor layer 102a is not oxidized and / or converted into a stress structure 146. The partial oxidation of the semiconductor layer 102a can be fine-tuned by adjusting the thermal operation temperature, the thermal operation time, and / or the thermal operation atmosphere. The lower portion of the semiconductor layer 102a that remains unoxidized forms a semiconductor device 102a', such as Figure 8B . In some embodiments, each of the semiconductor elements 102a' directly contacts the corresponding stress structure 146 located thereon. In some embodiments, the interface between one semiconductor element 102a' and one stress structure 146 is substantially flat. The semiconductor element 102a' may have a thickness in the range of about 2 nm to about 20 nm. The stress structure 146 located thereon may have a thickness in the range of about 5 nm to about 20 nm.

[0171] Afterwards, conduct Figure 3M-Figure 3N Thus, according to some embodiments, forming Figure 8C The semiconductor device structure is shown.

[0172] Fig. 9 is a cross-sectional view of a semiconductor device structure according to some embodiments. In some embodiments, Fig. 9 yes Figure 8C The structure shown is a schematic cross-sectional view taken along another direction. In some embodiments, Fig. 9is a cross-sectional view taken along the longer gate extension direction. In some embodiments, each of the semiconductor elements 102a' is disposed between the corresponding stress structure 146 located above it and the semiconductor substrate 100, such as Fig. 9 In some embodiments, each of the semiconductor elements 102 a ′ directly contacts the corresponding stress structure 146 , the isolation structure 114 and / or the corresponding semiconductor fin 101A or 101B located thereunder.

[0173] In some embodiments, the interface between each of the stress structures 146 and the corresponding semiconductor device 102a′ thereunder is substantially flat. Figure 8C and Fig. 9 However, the embodiments of the present invention are not limited thereto. Many changes and / or modifications may be made to the embodiments of the present invention. In some other embodiments, the interface between each of the stress structures 146 and the corresponding semiconductor element 102a' located thereunder is curved or has a curved portion.

[0174] Fig.10 1 is a schematic cross-sectional view of a semiconductor device structure according to some embodiments. The profile of the stress structure 146 and the semiconductor element 102a" located thereunder can be modified by fine-tuning the thermal operation. For example, the thermal operation temperature, thermal operation time and / or thermal operation pressure can be adjusted to modify the profile of the stress structure 146.

[0175] In some embodiments, the bottom of the stress structure 146 is curved, such as Fig.10 In some embodiments, the interface between the stress structure 146 and the semiconductor element 102 a ″ thereunder is a convex surface facing the semiconductor element 102 a ′.

[0176] Fig.11 is a cross-sectional view of a semiconductor device structure according to some embodiments. In some embodiments, Fig.11 yes Fig.10 The structure shown is a schematic cross-sectional view taken along another direction. In some embodiments, Fig.11 is a cross-sectional view taken along the longer gate extension direction. In some embodiments, each of the semiconductor elements 102a" is disposed between the corresponding stress structure 146 located above it and the semiconductor substrate 100, such as Fig.11 In some embodiments, each of the semiconductor elements 102 a ″ directly contacts the corresponding stress structure 146 , the isolation structure 114 and / or the corresponding semiconductor fin 101A or 101B located thereunder.

[0177] Fig.12is a schematic cross-sectional view of a semiconductor device structure according to some embodiments. Fig.13 is a cross-sectional view of a semiconductor device structure according to some embodiments. In some embodiments, Fig.13 yes Fig.12 The structure shown is a schematic cross-sectional view taken along another direction. For example, Fig.12 A schematic cross-sectional view of a "fin cut" of a semiconductor device structure is shown. Fig.13 A schematic cross-sectional view of a “gate cut” of a semiconductor device structure is shown. In some embodiments, there are a plurality of semiconductor elements 102a”′. Each of the semiconductor elements 102a”′ may be surrounded by a corresponding stress structure 146 and a corresponding internal spacer 136. In some embodiments, the stress structure 146 directly contacts the corresponding semiconductor fin 101A or 101B located therebelow, such as Fig.12 and Fig.13 In some embodiments, as shown Fig.12 and Fig.13 As shown, the bottom surface of the stress structure 146 and the bottom surface of the semiconductor element 102 a ′″ are substantially flush with each other.

[0178] In some embodiments, the bottom of the epitaxial structure 138 is formed directly on the semiconductor material (e.g., semiconductor fin 101A or 101B). However, the embodiments of the present invention are not limited thereto. Many variations and / or modifications may be made to the embodiments of the present invention. In some other embodiments, another element is formed between the bottom of the epitaxial structure 138 and the semiconductor substrate 100, and the other element is not formed of semiconductor material.

[0179] Figure 14A-Figure 14C is a cross-sectional schematic diagram of various stages of a process for forming a semiconductor device structure according to some embodiments. Fig.14A Show, form or receive Figure 3D The structure shown is the same or similar to the structure shown. Then, according to some embodiments, such as Fig.14A As shown, a spacer layer 134' is deposited. The material and formation method of the spacer layer 134' may be the same as Figure 3E The spacer layers 134 shown are the same or similar. In some embodiments, Fig.14A The bottom portion of the spacer layer 134' is shown to be thicker than Figure 3E The bottom portion of the spacer layer 134 is shown to be thicker. The profile of the recess 130 and / or the deposition process of the spacer layer 134' may cause the spacer layer 134' to have a thicker bottom.

[0180] Afterwards, conduct Figure 3F In this way, according to some embodiments, the process shown in FIG. Fig. 14B The structure shown. Fig. 14B As shown, Figure 3F Similarly, an inner spacer 136 and a bottom inner spacer 136' are formed. In some embodiments, the bottom inner spacer 136' covers the bottom portion of the recess 130, such as Fig. 14B A bottom portion of the bottom inner spacer 136 ′ located at the bottom of the corresponding recess 130 may have a thickness in a range of about 2 nm to about 10 nm.

[0181] Afterwards, conduct Figure 3G-Figure 3N In this way, according to some embodiments, the process shown in FIG. Fig. 14C The bottom inner spacers 136' can help reduce or prevent current leakage from the epitaxial structure 138. In some embodiments, each of the bottom inner spacers 136' directly contacts the corresponding epitaxial structure 138 located above it. In some embodiments, the bottom inner spacers 136' surround the bottom of the corresponding epitaxial structure 138 located above it, so that the entirety of the corresponding epitaxial structure 138 is located above the bottom inner spacers 136', such as Fig. 14C Shown.

[0182] Many variations and / or modifications may be made to the embodiments of the present invention. Fig.15 1 is a schematic cross-sectional view of a semiconductor device structure according to some embodiments. In some embodiments, epitaxial structure 138 is formed using an epitaxial growth process. In the epitaxial growth process, semiconductor material may tend to grow on the surface of the element formed by the semiconductor material. In the epitaxial growth process, semiconductor material may tend to grow on the surface of edge elements 105a-105d. Thus, according to some embodiments, Fig.15 As shown, a gap V is formed between the epitaxial structure 138 and the semiconductor substrate 100 .

[0183] Fig.16 is a schematic cross-sectional view of a semiconductor device structure according to some embodiments. Fig.15 The structure shown. Similar to Figure 8C , Fig.10 and Fig.12 In the illustrated embodiment, the semiconductor element 102a' is retained without being converted into the stress structure 146. In some embodiments, one of the bottom inner spacers 136' directly contacts the stress structure 146 and the semiconductor element 102a'. Fig.16 Shown.

[0184] Many variations and / or modifications may be made to the embodiments of the present invention. According to some embodiments, Figure 17A-17Cis a cross-sectional schematic diagram of various stages of a process for forming a semiconductor device structure according to some embodiments. Fig.17A As shown, a structure that is the same or similar to the structure shown in Figure 3K is formed.

[0185] Then, according to some embodiments, similar to Figure 3L In the illustrated embodiment, the semiconductor layer 102a (which serves as a base layer) is transformed into a stress structure 146. In some embodiments, the semiconductor layer 102a is annealed to form the stress structure 146. In some embodiments, after the annealing operation, the semiconductor layer 102a expands and transforms into the stress structure 146. The top surface of the stress structure 146 may protrude and have a mesa-like profile. In some embodiments, the stress structure 146 has a curved top surface, such as Fig. 17B Shown.

[0186] Then, according to some embodiments, Figure 3M-Figure 3N The process shown is the same or similar process. Fig. 17C The semiconductor device structure is shown.

[0187] In some embodiments, three semiconductor nanostructures 104b'-104d' are formed. However, the embodiments of the present invention are not limited thereto. Many variations and / or modifications may be made to the embodiments of the present invention. In some embodiments, the total number of semiconductor nanostructures is greater than three. In some other embodiments, the total number of semiconductor nanostructures is less than three. The total number of semiconductor nanostructures (or channel structures) of each semiconductor device structure may be adjusted as desired.

[0188] Some embodiments of the present invention form a semiconductor device structure having a stress structure located below a channel structure. A gate stack structure surrounds the channel structure. For example, the semiconductor device structure includes a stack structure of multiple channel structures, wherein these multiple channel structures are surrounded by a metal gate stack structure. Before the formation of the gate stack structure, the semiconductor element located below the channel structure is converted into a stress structure. The stress structure can induce an epitaxial structure located next to the channel structure to apply stress (e.g., tensile stress) to the channel structure. In this way, the carrier mobility in the channel structure can be improved. The performance and reliability of the semiconductor device structure are greatly improved.

[0189] According to some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a plurality of semiconductor nanostructures located above a substrate and two epitaxial structures located above the substrate. Each of the plurality of semiconductor nanostructures is located between the two epitaxial structures. The semiconductor device structure also includes a gate stack structure surrounding the plurality of semiconductor nanostructures. The semiconductor device structure also includes a stress structure between the gate stack structure and the substrate. The two epitaxial structures extend beyond the top surface of the stress structure.

[0190] In some embodiments, the gate stack structure surrounds each of the plurality of semiconductor nanostructures.

[0191] In some embodiments, the stress structure is formed of a semiconductor oxide material.

[0192] In some embodiments, the two epitaxial structures extend beyond a bottom surface of the stress structure.

[0193] In some embodiments, the semiconductor device structure further includes a plurality of internal spacers, wherein each of the plurality of internal spacers is located between the gate stack structure and one of the two epitaxial structures.

[0194] In some embodiments, one of the plurality of inner spacers directly contacts the stress structure and one of the two epitaxial structures.

[0195] In some embodiments, a bottom inner spacer of the plurality of inner spacers surrounds one of the two epitaxial structures, so that the entire epitaxial structure is located above the bottom inner spacer.

[0196] In some embodiments, the semiconductor device structure further includes an edge element located between two of the plurality of inner spacers, wherein the edge element and the plurality of semiconductor nanostructures are formed of the same material, and the edge element is thinner than each of the plurality of semiconductor nanostructures.

[0197] In some embodiments, the semiconductor device structure further comprises a semiconductor element located between the stress structure and the substrate, wherein the semiconductor element is formed of a semiconductor material, and the stress structure is formed of an oxide material of the semiconductor material.

[0198] In some embodiments, the semiconductor device directly contacts the stress structure.

[0199] According to some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a semiconductor fin located above a substrate, and a plurality of channel structures stacked above the semiconductor fin. The semiconductor device structure also includes a gate stack structure surrounding each of the plurality of channel structures. The semiconductor device structure also includes an epitaxial structure adjacent to the plurality of channel structures. The semiconductor device structure also includes a stress structure located between the substrate and the plurality of channel structures. The stress structure includes oxygen and a semiconductor material other than silicon.

[0200] In some other embodiments, the semiconductor device structure further includes an isolation structure surrounding the semiconductor fin and the stress structure.

[0201] In some other embodiments, the stress structure directly contacts the semiconductor fin, the isolation structure and the gate stack structure.

[0202] In some other embodiments, the semiconductor device structure further includes a semiconductor element located between the stress structure and the substrate, wherein an interface between the semiconductor element and the stress structure is a convex surface facing the semiconductor element.

[0203] According to some embodiments, a method for forming a semiconductor device structure is provided. The method for forming the semiconductor device structure includes forming a base layer on a semiconductor substrate, and forming a semiconductor stack structure on the base layer. The semiconductor stack structure has multiple sacrificial layers and multiple semiconductor layers arranged alternately. The method for forming the semiconductor device structure also includes patterning the semiconductor stack structure and the base layer to form a fin structure, and forming an isolation structure around the lower portion of the fin structure. The top surface of the isolation structure is higher than the top surface of the base layer. The method for forming the semiconductor device structure also includes removing the multiple sacrificial layers to release multiple semiconductor nanostructures. The multiple semiconductor nanostructures are composed of the remaining portions of the multiple semiconductor layers. The method for forming the semiconductor device structure also includes converting at least the upper portion of the base layer into a stress structure, and forming a metal gate stack structure to surround each of the multiple semiconductor nanostructures.

[0204] In some other embodiments, the method for forming the semiconductor device structure further includes forming a protective layer on the base layer before forming the semiconductor stacking structure, and partially removing the protective layer to expose the base layer after forming the semiconductor stacking structure.

[0205] In some other embodiments, in the method for forming the semiconductor device structure, the material of the protection layer is the same as the material of the plurality of semiconductor layers, and the material of the base layer is the same as the material of the sacrificial layer.

[0206] In some other embodiments, in the method for forming the semiconductor device structure, the stress structure is formed by at least partially oxidizing the base layer.

[0207] In some other embodiments, in the method for forming the semiconductor device structure, the lower portion of the base layer is not transformed into the stress structure.

[0208] In some other embodiments, the method for forming the semiconductor device structure further includes partially removing the fin structure to form a recess, wherein the recess exposes multiple side surfaces of the multiple semiconductor layers and multiple side surfaces of the multiple sacrificial layers. The method for forming the semiconductor device structure also includes forming multiple internal spacers to cover the multiple side surfaces of the multiple sacrificial layers; and after forming the multiple internal spacers, forming a source / drain structure to at least partially fill the recess.

[0209] The foregoing text summarizes the components of many embodiments so that those skilled in the art can better understand the embodiments of the present invention from various aspects. Those skilled in the art should understand and can easily design or modify other processes and structures based on the embodiments of the present invention to achieve the same purpose and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also understand that these equivalent structures do not depart from the spirit and scope of the invention of the present invention. Various changes, substitutions or modifications may be made to the present invention without departing from the spirit and scope of the invention of the present invention.

[0210] Although the present invention has been disclosed as above with several preferred embodiments, they are not intended to limit the present invention. Those skilled in the art may make any changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the attached claims.

Claims

1. A semiconductor device structure, comprising: A plurality of semiconductor nanostructures are disposed on a substrate; two epitaxial structures located above the substrate, wherein each of the plurality of semiconductor nanostructures is located between the two epitaxial structures; a gate stack structure surrounding the plurality of semiconductor nanostructures; as well as A stress structure is located between the gate stack structure and the substrate, wherein the two epitaxial structures extend beyond a top surface of the stress structure, and the two epitaxial structures extend beyond a bottom surface of the stress structure. 2 . The semiconductor device structure of claim 1 , wherein the gate stack structure surrounds each of the plurality of semiconductor nanostructures. 3 . The semiconductor device structure of claim 1 , wherein the stress structure is formed of a semiconductor oxide material. 4 . The semiconductor device structure as claimed in claim 1 , further comprising a semiconductor element located between the stress structure and the substrate, wherein an interface between the semiconductor element and the stress structure is a convex surface facing the semiconductor element. 5 . The semiconductor device structure as claimed in claim 1 , further comprising a plurality of inner spacers, wherein each of the plurality of inner spacers is located between the gate stack structure and one of the two epitaxial structures. 6 . The semiconductor device structure of claim 5 , wherein one of the plurality of inner spacers directly contacts the stress structure and one of the two epitaxial structures. 7 . The semiconductor device structure as claimed in claim 5 , wherein a bottom inner spacer of the plurality of inner spacers surrounds one of the two epitaxial structures, so that the entire epitaxial structure is located above the bottom inner spacer.

8. The semiconductor device structure of claim 5, further comprising an edge element located between two of the plurality of inner spacers, wherein the edge element and the plurality of semiconductor nanostructures are formed of the same material, and the edge element is thinner than each of the plurality of semiconductor nanostructures. 9 . The semiconductor device structure as claimed in claim 1 , further comprising a semiconductor element located between the stress structure and the substrate, wherein the semiconductor element is formed of a semiconductor material, and the stress structure is formed of an oxide material of the semiconductor material. 10 . The semiconductor device structure of claim 9 , wherein the semiconductor element directly contacts the stress structure.

11. A semiconductor device structure, comprising: a semiconductor fin located above a substrate; A plurality of channel structures are stacked above the semiconductor fin; a gate stack structure surrounding each of the plurality of channel structures; an epitaxial structure adjacent to the plurality of channel structures; a stress structure located between the substrate and the plurality of channel structures, wherein the stress structure comprises oxygen and a semiconductor material other than silicon; as well as A semiconductor element is located between the stress structure and the substrate, wherein an interface between the semiconductor element and the stress structure is a convex surface facing the semiconductor element. 12 . The semiconductor device structure as claimed in claim 11 , further comprising an isolation structure surrounding the semiconductor fin and the stress structure. 13 . The semiconductor device structure as claimed in claim 12 , wherein the stress structure directly contacts the semiconductor fin, the isolation structure and the gate stack structure. 14 . The semiconductor device structure of claim 11 , further comprising an inner spacer, wherein the inner spacer directly contacts the epitaxial structure and the stress structure. 15 . The semiconductor device structure of claim 11 , wherein the epitaxial structure extends beyond a top surface and a bottom surface of the stress structure.

16. A method for forming a semiconductor device structure, comprising: forming a base layer on a semiconductor substrate; forming a semiconductor stacking structure on the base layer, wherein the semiconductor stacking structure has a plurality of sacrificial layers and a plurality of semiconductor layers arranged alternately; Patterning the semiconductor stack structure and the base layer to form a fin structure; forming an isolation structure surrounding a lower portion of the fin structure, wherein a top surface of the isolation structure is higher than a top surface of the base layer; removing the plurality of sacrificial layers to release a plurality of semiconductor nanostructures, wherein the plurality of semiconductor nanostructures are formed by remaining portions of the plurality of semiconductor layers; transforming at least an upper portion of the base layer into a stressed structure; as well as forming a metal gate stack structure to surround each of the plurality of semiconductor nanostructures; Before forming the semiconductor stack structure, forming a protection layer on the base layer; as well as After forming the semiconductor nanostructure, the protective layer is partially removed to expose the base layer. 17 . The method for forming a semiconductor device structure as claimed in claim 16 , wherein a material of the protection layer is the same as a material of the plurality of semiconductor layers, and a material of the base layer is the same as a material of the sacrificial layer. 18 . The method for forming a semiconductor device structure as claimed in claim 16 , wherein the stress structure is formed by at least partially oxidizing the base layer. 19 . The method for forming a semiconductor device structure as claimed in claim 18 , wherein a lower portion of the base layer is not transformed into the stress structure.

20. The method for forming a semiconductor device structure according to claim 16, further comprising: Partially removing the fin structure to form a notch, wherein the notch exposes a plurality of side surfaces of the plurality of semiconductor layers and a plurality of side surfaces of the plurality of sacrificial layers; forming a plurality of inner spacers to cover the plurality of side surfaces of the plurality of sacrificial layers; as well as After forming the plurality of inner spacers, a source / drain structure is formed to at least partially fill the recess.

Images