Board test circuit, system and test method

Abstract

The present application relates to a board test circuit, system and test method. The board control circuit is connected to the board power supply control circuit. The multiple channel power supply control circuits are respectively connected to the board power supply control circuit and the board control circuit. The board control circuit is used to control the on and off of the channel power supply control circuit. The multiple board channel circuits are connected to the multiple channel power supply control circuits in a one-to-one correspondence. The multiple board channel circuits are also respectively connected to the board control circuit, and the board control circuit is used to control the on and off of the board channel circuits through the channel power supply control circuit. The board power supply control circuit can power on the board test circuit as needed. When the board test circuit is not in use, the system control circuit can control the board power supply control circuit not to power on. The board test circuit is in a power-off state, thereby saving energy consumption.

Description

Technical Field

[0001] The present application relates to the field of testing, and in particular to a board testing circuit, system and testing method. Background Art

[0002] During semiconductor device packaging testing, it's common for certain boards or channels to be unused within the same machine's board resource configuration for a specific device parameter. In practice, due to the small batch sizes of some devices under test, the same machine is often required to test different types of devices. Because different devices utilize different board resources, idle boards or channels are more likely to occur when testing multiple device types simultaneously on the same machine. However, these boards or channels are constantly powered, resulting in additional energy loss and overall temperature rise within the test system. Summary of the Invention

[0003] Based on this, it is necessary to provide a board test circuit, system and test method to address the above problems.

[0004] A board test circuit, comprising:

[0005] Board power supply control circuit, used for connecting to the power supply;

[0006] A board control circuit connected to the board power supply control circuit;

[0007] a plurality of channel power supply control circuits, connected to the board power supply control circuit and the board control circuit respectively, wherein the board control circuit is used to control the on and off of the channel power supply control circuit; and

[0008] Multiple board channel circuits are connected one-to-one with the multiple channel power supply control circuits. The multiple board channel circuits are also respectively connected to the board control circuit. The board control circuit is used to control the on and off of the board channel circuits through the channel power supply control circuit.

[0009] In one embodiment, the board power supply control circuit includes:

[0010] An isolation driving circuit for receiving a control signal;

[0011] a switch circuit connected to the isolation drive circuit and the power supply; and

[0012] The filter circuit is connected to the switch circuit and the channel power supply control circuit.

[0013] In one embodiment, the isolation driving circuit includes:

[0014] a photodiode output photocoupler circuit, wherein the photodiode output photocoupler circuit is used to receive the control signal;

[0015] The soft switching circuit is connected to the photodiode output photocoupler circuit, and the soft switching circuit is also connected to the switch switching circuit.

[0016] In one embodiment, the soft switching circuit includes a first capacitor C1, a second resistor R2, and a third resistor R3. The first capacitor C1 and the second resistor R2 are connected in series across the output photocoupler, and the third resistor R3 is connected in series across the first capacitor C1. The second resistor R2 is connected to the switching circuit.

[0017] In one embodiment, the switching circuit includes a first field-effect transistor Q1 and a second field-effect transistor Q2 connected in series, a first end of the first capacitor C1 is connected to the source of the first field-effect transistor Q1 and the source of the second field-effect transistor Q2, and a second end of the first capacitor C1 is connected to the gate of the first field-effect transistor Q1 and the gate of the second field-effect transistor Q2;

[0018] The drain of the first field effect transistor Q1 is used to connect to the power supply, and the drain of the second field effect transistor Q2 is connected to the filter circuit.

[0019] In one embodiment, it further includes a first branch and a second branch, the first branch is connected to the P1+ power line of the power supply and the channel power supply control circuit, the second branch is connected to the P1- power line of the power supply and the channel power supply control circuit, and the first field effect transistor Q1 and the second field effect transistor Q2 are connected in series to the first branch.

[0020] In one embodiment, the filtering circuit includes:

[0021] a first inductor L1 connected in series to the first circuit and located between the drain of the second field effect transistor Q2 and the channel power supply control circuit;

[0022] a second inductor L2 connected in series to the second branch and located between the first branch and the power supply and the channel power supply control circuit; and

[0023] A second capacitor C2, wherein a first end of the second capacitor C2 is connected between the first inductor L1 and the channel power supply control circuit, and a second end of the second capacitor C2 is connected between the second inductor L2 and the channel power supply control circuit.

[0024] A board test system, comprising:

[0025] A plurality of said board test circuits;

[0026] The power supply is connected to the board power supply control circuit of each board test circuit;

[0027] System control circuit; connected to the board power supply control circuit of each board test circuit, for controlling the on-off connection of each board power supply control circuit;

[0028] The system control circuit is also connected to the board control circuit of each board test circuit, and is used to control the on and off of multiple board channel circuits through the board control circuit, and

[0029] A host computer is connected to the system control circuit.

[0030] A board test system testing method is characterized by comprising:

[0031] The host computer controls the power supply to supply power to the plurality of board test circuits;

[0032] The host computer records resource usage of each board test circuit and the multiple board channel circuits in each board test circuit;

[0033] The host computer controls the on / off of the board test circuit and the multiple board channel circuits in each board test circuit based on the resource usage.

[0034] In one embodiment, the host computer controls the on / off of the board test circuit and the multiple board channel circuits in each board test circuit based on the resource usage, including:

[0035] For the board test circuit being used, the host computer controls the board power supply control circuit to be turned on, so that the power supply supplies power to the board control circuit and the channel power supply control circuit;

[0036] For the board channel circuit being used, the host computer controls the corresponding channel power supply control circuit through the board control circuit to be turned on, so that the board power supply control circuit supplies power to the board channel circuit being used through the channel power supply control circuit.

[0037] The board test circuit provided in an embodiment of the present application includes a board power supply control circuit, a board control circuit, multiple channel power supply control circuits, and multiple board channel circuits. The board power supply control circuit is connected to a power source. The board control circuit is connected to the board power supply control circuit. The multiple channel power supply control circuits are respectively connected to the board power supply control circuit and the board control circuit. The board control circuit is used to control the on / off of the channel power supply control circuit. The multiple board channel circuits are connected to the multiple channel power supply control circuits in a one-to-one correspondence. The multiple board channel circuits are also respectively connected to the board control circuit, and the board control circuit is used to control the on / off of the board channel circuits via the channel power supply control circuit. The board power supply control circuit can power on the board test circuit as needed. When the board test circuit is not in use, the system control circuit can control the board power supply control circuit to not power on. The board test circuit is in a powered-off state, thereby saving energy.

[0038] Furthermore, when certain card channel circuits in the card test circuit are in use, the card control circuit can control the channel power supply control circuit to supply power to the used card channel circuits. The card power supply control circuit supplies power to the used card channel circuits via the channel power supply control circuits. The card test circuit can adjust its power supply based on its own usage and the usage of each card channel circuit, thereby saving energy and reducing system temperature rise caused by heat generation. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 A schematic diagram of a board test circuit provided in an embodiment of the present application;

[0040] Figure 2 A schematic diagram of a board power supply control circuit provided in an embodiment of the present application;

[0041] Figure 3 A schematic diagram of a board power supply control circuit provided in another embodiment of the present application;

[0042] Figure 4 Schematic diagram of a board test system provided in an embodiment of the present application;

[0043] Figure 5 A schematic diagram of a test method for a board test system provided in one embodiment of the present application;

[0044] Figure 6 A flow chart of a board test system testing method provided in another embodiment of the present application.

[0045] Description of Reference Numerals

[0046] Board test circuit 10, board power supply control circuit 100, isolation drive circuit 110, photodiode output optocoupler circuit 112, soft switching circuit 114, first capacitor C1, second resistor R2, third resistor R3, switch switching circuit 120, first field effect transistor Q1, second field effect transistor Q2, filter circuit 130, first inductor L1, second inductor L2, second capacitor C2, board control circuit 200, channel power supply control circuit 300, board channel circuit 400, first branch 510, second branch 520, fuse 530, board test system 20, power supply 21, system control circuit 22, host computer 33. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solutions and advantages of this application more clearly understood, the present application is further described in detail below through embodiments and in conjunction with the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0048] The serial numbers assigned to the components herein, such as "first", "second", etc., are only used to distinguish the objects described and do not have any order or technical meaning. The "connection" and "coupling" mentioned in this application include direct and indirect connections (couplings) unless otherwise specified. In the description of this application, it should be understood that the orientations or positional relationships indicated by the terms "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", etc. are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to this application.

[0049] In this application, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Furthermore, when a first feature is "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0050] See Figure 1An embodiment of the present application provides a board test circuit 10. The board test circuit 10 includes a board power supply control circuit 100, a board control circuit 200, multiple channel power supply control circuits 300, and multiple board channel circuits 400. The board power supply control circuit 100 is used to connect to a power source 21. The board control circuit 200 is connected to the board power supply control circuit 100. The multiple channel power supply control circuits 300 are respectively connected to the board power supply control circuit 100 and the board control circuit 200. The board control circuit 200 is used to control the on / off of the channel power supply control circuit 300. The multiple board channel circuits 400 are connected to the multiple channel power supply control circuits 200 in a one-to-one correspondence. The multiple board channel circuits 400 are also respectively connected to the board control circuit 200, and the board control circuit 200 is used to control the on / off of the board channel circuits 400 through the channel power supply control circuit 300.

[0051] The board power supply control circuit 100 can control the power supply 21 to supply power to the board test circuit 10. When the resources of the board test circuit 10 are in use, the host computer can control the board power supply control circuit 100 to be turned on, and the power supply 21 can power the board test circuit 10. When the board test circuit 10 is not in use, the board power supply control circuit 100 can remain in the off state, thereby saving energy.

[0052] The power supply 21 may be a power supply 21 integrated into the board test circuit 10. The board power supply control circuit 100 may be controlled by a host computer 33. After being powered on, the board power supply control circuit 100 may supply power to the board control circuit 200 and the channel power supply control circuit 300. After the board control circuit 200 is powered on, the host computer 33 communicates with the board control circuit 200 via the system control circuit 22 to control the on / off state of the channel power supply control circuit 300.

[0053] The multiple channel power supply control circuits 300 are electrically connected to the multiple board channel circuits 400 in a one-to-one correspondence. When the board control circuit 200 controls the channel power supply control circuit 300 to be turned on, the board power supply control circuit 100 supplies power to the board channel circuit 400 corresponding to the channel power supply control circuit 300 through the channel power supply control circuit 300. Each of the board channel circuits 400 is connected to the board control circuit 200, so the board channel circuit 400 can exchange information with the host computer 33 through the board control circuit 200. Therefore, after the channel power supply control circuit 300 is powered on, the board control circuit 200 can control whether the channel power supply control circuit 300 is turned on, that is, it can control whether the channel power supply control circuit 300 supplies power to a certain board channel circuit 400. When the resources of certain card channel circuits 400 are in use, the card control circuit 200 controls the channel power control circuit 300 corresponding to the used card channel circuit 400 to turn on and supply power to the card channel circuit 400. At the same time, the card control circuit 200 controls the corresponding channel power control circuit 300 to power off unused card channel circuits 400. That is, the channel power control circuit 300 cannot supply power to the card channel circuit 400, thereby saving energy and reducing heat.

[0054] The board test circuit 10 provided in an embodiment of the present application includes a board power supply control circuit 100, a board control circuit 200, multiple channel power supply control circuits 300, and multiple board channel circuits 400. The board power supply control circuit 100 is connected to a power supply 21. The board control circuit 200 is connected to the board power supply control circuit 100. The multiple channel power supply control circuits 300 are connected to the board power supply control circuit 100 and the board control circuit 200, respectively. The board control circuit 200 is used to control the on / off of the channel power supply control circuit 300. The multiple board channel circuits 400 are connected to the multiple channel power supply control circuits 200 in a one-to-one correspondence. The multiple board channel circuits 400 are also respectively connected to the board control circuit 200, and the board control circuit 200 is used to control the on / off of the board channel circuits through the channel power supply control circuits 400. The board power supply control circuit 100 can power the board test circuit 10 as needed. When the board test circuit 10 is not in use, the system control circuit 21 can control the board power supply control circuit to not be powered on. The board test circuit 10 is in a power-off state, thereby saving energy consumption.

[0055] Furthermore, when some of the card channel circuits 400 in the card test circuit 10 are in use, the card control circuit 200 can control the channel power supply control circuit 300 to supply power to the used card channel circuits 400. The card power supply control circuit 100 supplies power to the used card channel circuits 400 via the channel power supply control circuit 300. The card test circuit 10 can adjust its power supply based on its own usage and the usage of each card channel circuit 400, thereby saving energy and reducing heat.

[0056] See Figure 2 In one embodiment, the board power supply control circuit 100 includes an isolation drive circuit 110, a switch circuit 120, and a filter circuit 130. The isolation drive circuit 110 is configured to receive a control signal. The control signal can be a high or low level signal. The switch circuit 120 is connected to the isolation drive circuit 110 and the power supply 21. The filter circuit 130 is connected to the switch circuit 120 and the channel power supply control circuit 300.

[0057] The isolated drive circuit 110 can be used to receive control signals from devices such as the host computer 33. The isolated drive circuit 110 can achieve electrical-to-photoelectric conversion, thereby achieving electrical isolation of the input and output circuits. Because the input and output circuits of the isolated drive circuit 110 are isolated from each other, and the electrical signals have advantages such as unidirectionality during transmission, the isolated drive circuit 110 has good electromagnetic interference resistance and electrical insulation capabilities. It is understood that the isolated drive circuit 110 can adopt optical isolation drive control or electromagnetic isolation drive control.

[0058] The switching circuit 120 can be turned on or off under the control of the isolation drive circuit 110, thereby controlling whether the switching circuit 120 is on. When the switching circuit 120 is on, the power supply 21 can supply power to the board control circuit 200 and the channel power control circuit 300 via the board power supply control circuit 100. The filter circuit 130 can filter the output of the switching circuit 120.

[0059] See Figure 3In one embodiment, the isolation driving circuit 110 includes a photodiode output photocoupler circuit 112 and a soft switching circuit 114. The photodiode output photocoupler circuit 112 is used to receive a control signal. The photodiode output photocoupler circuit 112 can receive the control signal issued by the system control circuit 22. The soft switching circuit 114 is connected to the photodiode output photocoupler circuit 112. The soft switching circuit 114 is also connected to the switch switching circuit 120. The photodiode output photocoupler circuit 112 can realize electrical-photoelectric conversion, thereby realizing electrical isolation of the input and output circuits, and has good anti-electromagnetic interference ability and electrical insulation ability. The soft switching circuit 114 can be turned on or off under the control of the high and low level signals output by the photodiode output photocoupler circuit 112. The soft switching circuit 114 reduces the speed of current rise to prevent the subsequent load from generating a large impact current.

[0060] In one embodiment, the board test circuit further includes a current limiting resistor R1 , and the photodiode output photocoupler circuit 112 can be connected to a power source through the current limiting resistor R1 .

[0061] In one embodiment, the switching circuit 120 includes a first field-effect transistor (FET) Q1 and a second field-effect transistor (FET) Q2 connected in series. A first end of a first capacitor (C1) is connected to the source of the first FET Q1 and the source of the second FET Q2. A second end of the first capacitor (C1) is connected to the gates of the first FET Q1 and the second FET Q2. The drain of the first FET Q1 is connected to the power supply 21, and the drain of the second FET Q2 is connected to the filter circuit 130.

[0062] In one embodiment, the soft switching circuit 114 includes a first capacitor C1, a second resistor R2, and a third resistor R3. The third resistor R3 is connected in parallel to both ends of the first capacitor C1. The first capacitor C1 and the second resistor R2 are connected in series to both ends of the output photocoupler. Both ends of the second resistor R2 are connected to the switching circuit 120. The first capacitor C1 and the second resistor R2 cooperate to reduce the current rise rate of the first field effect transistor Q1, preventing subsequent loads from generating large inrush currents. The third resistor R3 is used to automatically discharge C1 when it is turned off.

[0063] In one embodiment, when the photodiode output photocoupler circuit 112 inputs a high-level signal, the photodiode output photocoupler circuit 112 outputs a control signal to the first field-effect transistor Q1 and the second field-effect transistor Q2, thereby turning on the first field-effect transistor Q1 and the second field-effect transistor Q2. The power supply 21 can be powered by the first field-effect transistor Q1, the second field-effect transistor Q2, and the filter circuit 130.

[0064] In one embodiment, the first field-effect transistor Q1 and the second field-effect transistor Q2 are both N-channel field-effect transistors. In one embodiment, the board test circuit 10 further includes a safety device 530. The safety device 530 is connected between the power supply 21 and the switching circuit. The safety device 530 may be a fuse. The safety device 530 can be disconnected promptly when excessive current occurs.

[0065] In one embodiment, the board test circuit 10 further includes a first branch 510 and a second branch 520. The first branch 510 is connected to the P1+ power line of the power supply 21 and the channel power supply control circuit 300. The second branch 520 is connected to the P1- power line of the power supply 21 and the channel power supply control circuit 300. The first field-effect transistor Q1 and the second field-effect transistor Q2 are connected in series to the first branch 510. The first field-effect transistor Q1 and the second field-effect transistor Q2 can control the on / off state of the first branch 510, thereby controlling the power supply 21 to supply power to the channel power supply control circuit 300 and the board control circuit 200.

[0066] It is understood that for controlling the on / off of the AC power supply, the first FET Q1 and the second FET Q2 are used. For controlling the on / off of the DC power supply, if the potential of the P1+ power line is higher than the potential of the P1- power line, only the first FET Q1 may be used.

[0067] In one embodiment, the filter circuit 130 includes a first inductor L1, a second inductor L2, and a second capacitor C2. The first inductor L1 is connected in series with the first circuit and is located between the drain of the second field-effect transistor Q2 and the channel power supply control circuit 300. The second inductor L2 is connected in series with the second branch 520 and is located between the first branch 510, the power supply 21, and the channel power supply control circuit 300. The first end of the second capacitor C2 is connected between the first inductor L1 and the channel power supply control circuit 300. The second end of the second capacitor C2 is connected between the second inductor L2 and the channel power supply control circuit 300.

[0068] In one embodiment, the specific structure of the channel power supply control circuit 300 may be the same as or similar to that of the board power supply control circuit 100 , and will not be described in detail here.

[0069] See Figure 4 The present application also provides a board test system 20. The board test system 20 further includes a plurality of board test circuits 10, a power supply 21, and a system control circuit 22. The power supply 21 is connected to the board power supply control circuit 100 of each board test circuit 10. The power supply 21 can supply power to the board test circuit 10 via the board power supply control circuit 100 of each board test circuit 10. The system control circuit 22 is connected to the board power supply control circuit 100 of each board test circuit 10. The system control circuit 22 is configured to control the on / off state of each board power supply control circuit 100. Therefore, the system control circuit 22 can send control information to the active board test circuit 10, causing the power supply 21 to supply power to the board test circuit 10. The system control circuit 22 is also connected to the board control circuit 200 of each board test circuit 10, controlling the on / off state of the plurality of board channel circuits 400 via the board control circuit 200. That is, after each of the board channel circuits 400 sends its usage status to the host computer 33, the host computer 33 can control the corresponding board test circuit 10 to be powered on through the system control circuit 22, and further control the power on of the used board channel circuit 400 through the board control circuit 200.

[0070] In one embodiment, the board test system 20 further includes a host computer 33. The host computer 33 is connected to the system control circuit 22. The host computer 33 can exchange information with the system control circuit 22. The system control circuit 22 can also exchange information with each of the board test circuits 10. Specifically, the host computer 33 can exchange information with each of the board test circuits 10, thereby controlling the operating status of each of the board test circuits 10 and understanding the usage of each of the board test circuits 10.

[0071] See Figure 5 The embodiment of the present application also provides a test method for a board test system 20. The test method includes:

[0072] S10, the host computer 33 controls the power supply 21 to supply power to the plurality of board test circuits 10;

[0073] S20, the host computer 33 records resource usage of each board test circuit 10 and the multiple board channel circuits 400 in each board test circuit 10;

[0074] S30: The host computer 33 controls the on / off of the board test circuit 10 and the multiple board channel circuits 400 in each of the board test circuits 10 based on the resource usage.

[0075] See Figure 6 In S10, after the board test circuit 10 is powered on, the host computer 33 can first retrieve the test program, power on the board test circuit 10, and perform a self-test. The host computer 33 can then record the resource status of the board test circuit when it is performing normally, and further determine the resource usage of the test program. If the board test circuit resources are sufficient, S30 is executed. If the board test circuit 10 is determined to have insufficient resources, an exception pop-up message can be displayed.

[0076] In S20, after each board test circuit 10 performs a self-test, it can provide feedback to the host computer 33 via the board control circuit 200 and the system control circuit 22 regarding whether each board test circuit 10 is in use, as well as the usage of the board channel circuits 400 in the used board test circuit 10. The host computer 33 can record the resource usage of each board test circuit 10 and the multiple board channel circuits 400 in each board test circuit 10. The host computer 33 can also record whether the performance of the board test circuit 10 is normal and whether the corresponding program resources are complete.

[0077] In S30, the host computer 33 can power the board test circuit 10 that is detected to be in use, and confirm which board channel circuits 400 in the board test circuit 10 are in use. The host computer 33 can control the board power supply control circuit 100 in the corresponding board test circuit 10 to be turned on through the system control circuit 22, so that the power supply 21 supplies power to the board control circuit 200 and the channel power supply control circuit 300 through the board power supply control circuit 100. The board control circuit 200 can control the channel power supply control circuit 300 to be turned on, so that the board power supply control circuit 100 supplies power to the channel power supply control circuit 300. The host computer 33 can further control the board channel circuit 400 that is in use to be turned on through the system control circuit 22 and the board control circuit 200, so that the channel power supply control circuit 300 supplies power to the board channel circuit 400 that is in use.

[0078] In one embodiment, the S30 includes:

[0079] S31, for the board test circuit 10 being used, the host computer 33 controls the board power supply control circuit 100 to be turned on, so that the power supply 21 supplies power to the board control circuit 200 and the channel power supply control circuit 300;

[0080] S32, for the board channel circuit being used, the host computer controls the corresponding channel power supply control circuit through the board control circuit to be turned on, so that the board power supply control circuit supplies power to the board channel circuit being used through the channel power supply control circuit.

[0081] The board test system 20 can selectively power the used board test circuit 10 and the used board channel circuit 400. The unused board test circuit 10 and the unused board channel circuit 400 are not powered, thereby reducing energy consumption and heat generation.

[0082] In one embodiment, the S20 includes:

[0083] When the host computer 33 detects that the board test system 20 is running low on resources, it issues an alarm. This means that even if all resources in the board test circuit 10 of the board test system 20 are used, the test requirements cannot be met. The host computer 33 issues an alarm so that staff can adjust the equipment immediately.

[0084] After S30, the process of testing the device by the board test system 20 can be included. During the test, the board resources can be controlled by the program to test the device parameters and display them. After the test is completed, the host computer 33 can be reported.

[0085] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0086] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of this patent. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of this application. Therefore, the scope of protection of this patent application shall be determined by the appended claims.

Claims

1. A board test system, characterized in that: include: Multiple board test circuits, power supplies, system control circuits, and a host computer. The board test circuit includes a board power supply control circuit, a board control circuit, multiple channel power supply control circuits, and multiple board channel circuits, wherein: The board power supply control circuit includes an isolation drive circuit, a switch switching circuit and a filter circuit; The isolation driving circuit includes a photodiode output photocoupler circuit and a soft switching circuit; The photodiode outputs a photocoupler circuit for receiving a control signal; The soft switching circuit is connected to the photodiode output photocoupler circuit and is also connected to the switch switching circuit. The soft switching circuit includes a first capacitor C1, a second resistor R2, and a third resistor R3. The first capacitor C1 and the second resistor R2 are connected in series to both ends of the photodiode output photocoupler circuit. The third resistor R3 is connected in parallel to both ends of the first capacitor C1. Both ends of the third resistor R3 are connected to the switch switching circuit. The switching circuit includes a first field-effect transistor Q1 and a second field-effect transistor Q2 connected in series, a first end of the first capacitor C1 connected to the source of the first field-effect transistor Q1 and the source of the second field-effect transistor Q2, and a second end of the first capacitor C1 connected to the gate of the first field-effect transistor Q1 and the gate of the second field-effect transistor Q2; the drain of the first field-effect transistor Q1 is used to connect to the power supply, and the drain of the second field-effect transistor Q2 is connected to the filter circuit; The filtering circuit is connected to the switch circuit and the channel power supply control circuit; The board control circuit is connected to the board power supply control circuit; The channel power supply control circuit is connected to the board power supply control circuit and the board control circuit, and the board control circuit is used to control the on and off of the channel power supply control circuit; The board channel circuit is connected to the multiple channel power supply control circuits in a one-to-one correspondence. The multiple board channel circuits are also respectively connected to the board control circuit. The board control circuit is used to control the on and off of the board channel circuits through the channel power supply control circuit. The power supply is connected to the board power supply control circuit of each board test circuit; The system control circuit is connected to the board power supply control circuit of each board test circuit, and is used to control the on and off of the connection of each board power supply control circuit; The system control circuit is also connected to the board control circuit of each board test circuit, and is used to control the on and off of multiple board channel circuits through the board control circuit; The host computer is connected to the system control circuit.

2. The board test system according to claim 1, wherein: The board test circuit also includes a first branch and a second branch, the first branch is connected to the P1+ power line of the power supply and the channel power supply control circuit, the second branch is connected to the P1- power line of the power supply and the channel power supply control circuit, and the first field effect transistor Q1 and the second field effect transistor Q2 are connected in series to the first branch.

3. The board test system according to claim 2, wherein: The filtering circuit comprises: A first inductor L1 is connected in series to the first branch and is located between the drain of the second field effect transistor Q2 and the channel power supply control circuit; a second inductor L2 connected in series to the second branch and located between the power supply and the channel power supply control circuit; and A second capacitor C2, wherein a first end of the second capacitor C2 is connected between the first inductor L1 and the channel power supply control circuit, and a second end of the second capacitor C2 is connected between the second inductor L2 and the channel power supply control circuit.

4. The board test system according to claim 1, wherein: The board test circuit further includes a safety device connected between the power supply and the switch circuit.

5. The board test system according to claim 4, wherein: The safety device is a fuse.

6. A board test system testing method, characterized in that: The board test system according to claim 1 comprises: The host computer controls the power supply to supply power to the plurality of board test circuits; The host computer records resource usage of each board test circuit and the multiple board channel circuits in each board test circuit; The host computer controls the on / off of the board test circuit and the multiple board channel circuits in each board test circuit based on the resource usage.

7. The board test system testing method according to claim 6, wherein: The host computer controls the board test circuit and the plurality of board channel circuits in each board test circuit based on the resource usage, including: For the board test circuit being used, the host computer controls the board power supply control circuit to be turned on, so that the power supply supplies power to the board control circuit and the channel power supply control circuit; For the board channel circuit being used, the host computer controls the corresponding channel power supply control circuit through the board control circuit to be turned on, so that the board power supply control circuit supplies power to the board channel circuit being used through the channel power supply control circuit.

8. The board test system testing method according to claim 6, wherein: The host computer controls the power supply to supply power to the plurality of board test circuits, including: The host computer retrieves the test program and powers on each of the board test circuits respectively, so that the board test circuits perform self-test after powering on.

9. The board test system testing method according to claim 8, wherein: The host computer records resource usage of each board test circuit and the multiple board channel circuits in each board test circuit, including: After the board test circuit self-checks, whether the board test circuit is used and the usage status of the board channel circuit in the used board test circuit are fed back to the host computer through the board control circuit and the system control circuit; The host computer records resource usage of each of the board test circuits and the multiple board channel circuits in each of the board test circuits.

10. The board test system testing method according to claim 9, wherein: The method further comprises: The host computer records whether the performance of each board test circuit is normal and whether the program resources are complete.

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