Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device includes a substrate, a cell region, a boundary region, and a peripheral region arranged sequentially in a first direction, an active pattern extending in a second direction in the cell region, the second direction forming a first acute angle with respect to the first direction, and a boundary pattern in the cell region directly adjacent to the boundary region. The boundary pattern includes a first side surface extending in the second direction and a first boundary surface extending from the first side surface in a third direction perpendicular to the first direction, and the first boundary surface defines a boundary between the cell region and the boundary region.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0130587, filed on October 21, 2019, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to a semiconductor device and a method for manufacturing the same, and more specifically, to a semiconductor device comprising a cell region, a peripheral region and a boundary region between the two, and a method for manufacturing the semiconductor device. Background Technology

[0004] As semiconductor devices become highly integrated, individual circuit patterns are becoming smaller and smaller, in order to implement more semiconductor devices in the same area.

[0005] Semiconductor memory devices, such as dynamic random access memory (DRAM), may include cell regions and a peripheral region surrounding the cell regions. In the peripheral region, various circuits required to control the semiconductor memory cells formed in the cell regions may be disposed. Summary of the Invention

[0006] Because the boundary between the cell region and the boundary region is clearly defined, this disclosure provides a semiconductor device with improved product reliability.

[0007] Because the boundary between the cell region and the boundary region is clearly defined, this disclosure also provides a method for manufacturing a semiconductor device with improved product reliability.

[0008] However, the aspects of this disclosure are not limited to those set forth herein. The above and other aspects of this disclosure will become more apparent to those skilled in the art upon reference to the detailed description of this disclosure given below.

[0009] According to one aspect of the present invention, a semiconductor device is provided, comprising: a substrate including a cell region, a boundary region, and a peripheral region arranged sequentially along a first direction; an active pattern extending in the cell region along a second direction, the second direction forming a first acute angle with respect to the first direction; and a boundary pattern formed in the cell region and directly adjacent to the boundary region, wherein the boundary pattern includes a first side surface extending along the second direction and a first boundary surface extending from the first side surface along a third direction, the third direction being perpendicular to the first direction, and the first boundary surface defining a boundary between the cell region and the boundary region.

[0010] According to another aspect of the present application, there is provided a semiconductor device including: a substrate including a cell region, a peripheral region around the cell region, and a boundary region between the cell region and the peripheral region; a plurality of active patterns in the cell region; a first boundary pattern formed in the cell region and including a first boundary surface defining a first portion of a boundary between the cell region and the boundary region; and a gate electrode extending in a first direction and across the plurality of active patterns and the first boundary pattern, wherein, in a cut plane intersecting the first boundary surface and extending in the first direction, a first width of each of the active patterns is greater than a second width of the first boundary pattern.

[0011] According to still another aspect of the present application, there is provided a semiconductor device including: a substrate including a cell region, a peripheral region around the cell region, and a boundary region between the cell region and the peripheral region; a plurality of active patterns in the cell region; a first boundary pattern formed in the cell region and directly adjacent to the boundary region; a gate electrode extending in a first direction and across the plurality of active patterns and the first boundary pattern; a bit line extending in a second direction intersecting the first direction and connected to a first source / drain region of each of the plurality of active patterns; and a capacitor structure formed on the cell region and connected to a second source / drain region of each of the plurality of active patterns, wherein the first boundary pattern includes a first side surface extending in a third direction forming an acute angle with the first direction and a first boundary surface defining a first portion of a boundary between the cell region and the boundary region.

[0012] According to still another aspect of the present application, there is provided a method of manufacturing a semiconductor device, the method including: providing a substrate including a cell region, a boundary region, and a peripheral region sequentially arranged in a first direction; forming a first mask pattern on the substrate of the cell region, the first mask pattern extending in a second direction forming a first acute angle with the first direction, at least a portion of the first mask pattern extending to the boundary region; forming a first trench in the substrate by patterning the substrate using the first mask pattern as an etching mask, and forming a second trench in the substrate to define the boundary region. BRIEF DESCRIPTION OF DRAWINGS

[0013] These and / or other aspects will become apparent and more readily appreciated from the following description, taken in conjunction with the accompanying drawings in which:

[0014] Figure 1 is a layout view of a semiconductor device according to an embodiment.

[0015] Figure 2 is a layout view of a semiconductor device according to an embodiment. Figure 1 is a layout view of a semiconductor device according to an embodiment.

[0016] Figure 3is a sectional view taken along lines A-A and B-B of Figure 1

[0017] Figure 4 is a sectional view taken along lines C-C of Figure 2

[0018] Figure 5 is a sectional view taken along lines D-D of Figure 2

[0019] Figure 6 is an enlarged view of a region R2 of Figure 2

[0020] Figure 7 to Figure 9 are various sectional views of a semiconductor device according to an embodiment.

[0021] Figure 10 is a sectional view of a semiconductor device according to an embodiment.

[0022] Figure 11 is a layout view of a semiconductor device according to an embodiment.

[0023] Figure 12 is a sectional view taken along lines C-C of Figure 11

[0024] Figure 13 is a sectional view taken along lines D-D of Figure 11

[0025] Figure 14 to Figure 30 are diagrams showing steps of a method of manufacturing a semiconductor device according to an embodiment.

[0026] Figure 31 to Figure 39 are diagrams showing steps of a method of manufacturing a semiconductor device according to an embodiment. DETAILED DESCRIPTION

[0027] A semiconductor device according to an embodiment will now be described with reference to Figure 1 to Figure 13

[0028] Figure 1 is a layout view of a semiconductor device according to an embodiment. Figure 2 is an enlarged view of a region R1 of Figure 1 Figure 3 are sectional views taken along lines A-A and B-B of Figure 1 Figure 4 is a sectional view taken along lines C-C of Figure 2 Figure 5 is a sectional view taken along lines D-D of Figure 2 Figure 6 is an enlarged view of a region R2 of Figure 2 ​​​​​​​​​​​​

[0029] Reference Figure 1 to Figure 6 The semiconductor device according to the embodiment includes a plurality of active patterns AP, a plurality of first boundary patterns IP1, a plurality of second boundary patterns IP2, a first element isolation layer 110, a second element isolation layer 120, and a third element isolation layer 130.

[0030] The substrate 100 can have, but is not limited to, a structure in which a base substrate and an epitaxial layer are stacked. The substrate 100 can be a silicon substrate, a gallium arsenide substrate, a silicon germanium substrate, or a semiconductor-on-insulator (SOI) substrate. As an example, the substrate 100 will be described below as a silicon substrate.

[0031] The substrate 100 can include a cell region CELL, a peripheral region PERI, and a boundary region INTERFACE.

[0032] The active patterns AP can be formed in the cell region CELL. In the cell region CELL, semiconductor cells including the active patterns AP can be arranged in an array. For example, when a semiconductor to be formed is a semiconductor memory device, an array of semiconductor memory cells can be formed in the cell region CELL.

[0033] The peripheral region PERI can be disposed around the cell region CELL, or can be disposed in a separate region from the cell region CELL. For example, the peripheral region PERI can surround the cell region CELL. In the peripheral region PERI, circuits required to control semiconductor cells formed in the cell region CELL can be disposed. For example, control elements and dummy elements can be formed in the peripheral region PERI.

[0034] The boundary region INTERFACE can be interposed between the cell region CELL and the peripheral region PERI. For example, the boundary region INTERFACE can surround the cell region CELL, and the peripheral region PERI can surround the boundary region INTERFACE. An element isolation layer (for example, the third element isolation layer 130 of Figure 3 and Figure 5 ) can be formed in the boundary region INTERFACE. Accordingly, the boundary region INTERFACE can separate the cell region CELL and the peripheral region PERI.

[0035] In some embodiments, as Figure 2As shown in FIG. 1, the unit region CELL, a portion of the boundary region INTERFACE, and a portion of the peripheral region PERI can be sequentially arranged along a first direction D1 parallel to the upper surface of the substrate 100. Also, another portion of the unit region CELL, another portion of the boundary region INTERFACE, and another portion of the peripheral region PERI can be sequentially arranged along a second direction D2 parallel to the upper surface of the substrate 100. Here, the second direction D2 can be a direction intersecting the first direction D1. For example, the second direction D2 can be orthogonal to the first direction D1.

[0036] The active patterns AP can be formed in the shape of a plurality of bars extending in parallel to each other in one direction. In some embodiments, a center of one active pattern AP can be disposed adjacent to one end of another active pattern AP.

[0037] Each active pattern AP can be formed in the shape of a bar extending in a third direction D3 different from the first direction D1 and the second direction D2 in a plane extending in the first direction D1 and the second direction D2. Here, the third direction D3 can be parallel to the upper surface of the substrate 100, and can be any direction different from the first direction D1 and the second direction D2. In some embodiments, the third direction D3 can form a first acute angle θ1 with the first direction D1. The first acute angle θ1 can be, but is not limited to, 60 degrees. In an example embodiment, some active patterns AP arranged along the third direction D3 can be disposed between two boundary patterns (e.g., between two second dummy patterns IP2 or between a first dummy pattern IP1 and a second dummy pattern IP2). In an example embodiment, an area of each of the two boundary patterns can be smaller than an area of each of the active patterns AP.

[0038] For example, as shown in FIG. 1, each active pattern AP can include a first side surface SS1 and a second side surface SS2. The first side surface SS1 of each active pattern AP can extend in the third direction D3. The second side surface SS2 of each active pattern AP can be opposite to the first side surface SS1 and can extend in the third direction D3. Figure 6

[0039] In some embodiments, the active pattern AP can include impurities to form a source region and a drain region. For example, the active pattern AP can include p-type impurities or n-type impurities. The impurities can be implanted into the active pattern AP by, for example, an ion implantation process.

[0040] ​The first boundary pattern IP1 can be formed in a cell region CELL adjacent to the boundary region INTERFACE. For example, the first boundary pattern TP1 can be directly adjacent to the boundary region INTERFACE. The first boundary pattern IP1 can be interposed between the active pattern AP and the boundary region INTERFACE. For example, the active pattern AP, the first boundary pattern IP1, and the boundary region INTERFACE can be sequentially arranged along the first direction D1.

[0041] The first boundary pattern IP1 can be in the shape of a plurality of bars extending along a third direction in which the active pattern AP extends. In some embodiments, a center of one active pattern AP can be disposed adjacent to one end of the first boundary pattern IP1.

[0042] The first boundary pattern IP1 can be formed in the shape of a bar extending along a third direction D3 in a plane extending along the first direction D1 and the second direction D2. For example, as shown in FIG. 1A, each first boundary pattern IP1 can include a third side surface SS3 and a fourth side surface SS4. The third side surface SS3 of each first boundary pattern IP1 can extend along the third direction D3. The fourth side surface SS4 of each first boundary pattern IP1 can be opposite the third side surface SS3 and can extend along the third direction D3. Figure 6

[0043] The first boundary pattern IP1 can define a boundary between the cell region CELL and the boundary region INTERFACE. For example, each first boundary pattern IP1 can further include a first boundary surface CS1 defining a boundary between the cell region CELL and the boundary region INTERFACE. The first boundary surface CS1 of each first boundary pattern IP1 can extend along the second direction D2 to define a boundary between the cell region CELL and the boundary region INTERFACE.

[0044] In some embodiments, the first boundary surface CS1 of each first boundary pattern IP1 can extend along the second direction D2 to connect the third side surface SS3 and the fourth side surface SS4. Accordingly, the third side surface SS3 and the first boundary surface CS1 can form a first interior angle θ2, and the fourth side surface SS4 and the first boundary surface CS1 can form a second interior angle θ3.

[0045] In some embodiments, a sum of the first acute angle θ1 and the first interior angle θ2 can be 90 degrees. In some embodiments, a sum of the first interior angle θ2 and the second interior angle θ3 can be 180 degrees.

[0046] ​In some embodiments, the first boundary pattern IP1 can be arranged along the second direction D2. In this case, the first boundary surface CS1 of the first boundary pattern IP1 can be located in the same plane extending along the second direction D2.

[0047] In some embodiments, in a cutting plane intersecting the first boundary surface CS1 and extending along the first direction D1, a width of each active pattern AP can be greater than a width of the first boundary pattern IP1. For example, as shown in FIG. 1A, a first width W1 of each active pattern AP can be greater than a second width W2 of the first boundary pattern IP1. Figure 5

[0048] In some embodiments, in a cutting plane intersecting the first boundary surface CS1 and extending along the first direction D1, a height of each active pattern AP can be greater than a height of the first boundary pattern IP1. For example, as shown in FIG. 1A, a first height H1 of each active pattern AP can be greater than a second height H2 of the first boundary pattern IP1. Figure 5

[0049] The second boundary pattern IP2 can be formed in the cell region CELL adjacent to the boundary region INTERFACE. For example, the second boundary pattern IP2 can be directly adjacent to the boundary region INTERFACE. The second boundary pattern IP2 can be interposed between the active pattern AP and the boundary region INTERFACE. For example, the active pattern AP, the second boundary pattern IP2, and the boundary region INTERFACE can be sequentially arranged along the second direction D2.

[0050] The second boundary pattern IP2 can be in the shape of a plurality of bars extending along a third direction D3 along which the active pattern AP extends. In some embodiments, a center of one active pattern AP can be disposed adjacent to one end of the second boundary pattern IP2.

[0051] The second boundary pattern IP2 can be formed in the shape of a bar extending along the third direction D3 in a plane extending along the first direction D1 and the second direction D2. For example, as shown in FIG. 1A, each second boundary pattern IP2 can include a fifth side surface SS5 and a sixth side surface SS6. The fifth side surface SS5 of each second boundary pattern IP2 can extend along the third direction D3. The sixth side surface SS6 of each second boundary pattern IP2 can be opposite to the fifth side surface SS5 and can extend along the third direction D3. Figure 6

[0052] ​​​The second boundary pattern IP2 can define a boundary between the cell region CELL and the interface region INTERFACE. For example, each second boundary pattern IP2 can further comprise a second boundary surface CS2 defining a boundary between the cell region CELL and the interface region INTERFACE. The second boundary surface CS2 of each second boundary pattern IP2 can extend along the first direction D1 to define a boundary between the cell region CELL and the interface region INTERFACE.

[0053] In some embodiments, the second boundary surface CS2 of each second boundary pattern IP2 can extend along the first direction D1 to connect the fifth side surface SS5 and the sixth side surface SS6. Thus, the fifth side surface SS5 and the second boundary surface CS2 can form a third internal angle Θ4, and the sixth side surface SS6 and the second boundary surface CS2 can form a fourth internal angle Θ5.

[0054] In some embodiments, the third internal angle Θ4 can be equal to the first acute angle Θ1. In some embodiments, the sum of the third internal angle Θ4 and the fourth internal angle Θ5 can be 180 degrees.

[0055] In some embodiments, the second boundary pattern IP2 can be arranged along the first direction D1. In this case, the second boundary surface CS2 of the second boundary pattern IP2 can be located in the same plane extending along the first direction D1.

[0056] The first element isolation layer 110 can be formed in the cell region CELL. The first element isolation layer 110 can define the active pattern AP, the first boundary pattern IP1, and the second boundary pattern IP2 protruding from the cell region CELL. For example, the substrate 100 in the cell region CELL can comprise a first trench T1 defining the active pattern AP, the first boundary pattern IP1, and the second boundary pattern IP2. The first element isolation layer 110 can be formed to fill the first trench T1.

[0057] In Figure 4 and Figure 5 In some embodiments, the first trench T1 has a sloped sidewall. However, this is only a characteristic of the etching process for forming the first trench T1, and the present disclosure is not limited to this case.

[0058] The first trench T1 can define the first side surface SS1 and the second side surface SS2 of each active pattern AP, the third side surface SS3 and the fourth side surface SS4 of each first boundary pattern IP1, and the fifth side surface SS5 and the sixth side surface SS6 of each second boundary pattern IP2. Accordingly, the first element isolation layer 110 can contact and define the first side surface SS1 and the second side surface SS2 of each active pattern AP, the third side surface SS3 and the fourth side surface SS4 of each first boundary pattern IP1, and the fifth side surface SS5 and the sixth side surface SS6 of each second boundary pattern IP2.

[0059] The first element isolation layer 110 can include, but is not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof.

[0060] In some embodiments, the first element isolation layer 110 can be formed as a plurality of layers. For example, as shown in FIG. 1B, the first element isolation layer 110 can include a first insulating layer 112 and a second insulating layer 114 sequentially formed in the first trench T1. The first insulating layer 112 can extend along the profile of the first trench T1. The second insulating layer 114 can fill a portion of the first trench T1 remaining after the first trench T1 is filled with the first insulating layer 112. Figure 3

[0061] In some embodiments, the first insulating layer 112 and the second insulating layer 114 can include different materials. For example, the first insulating layer 112 can include silicon oxide, and the second insulating layer 114 can include silicon nitride.

[0062] The second element isolation layer 120 can be formed in the boundary region INTERFACE. The second element isolation layer 120 can define a boundary between the boundary region INTERFACE and the cell region CELL and a boundary between the boundary region INTERFACE and the peripheral region PERI. For example, the substrate 100 in the boundary region INTERFACE can include a second trench T2 defining the boundary region INTERFACE. The second element isolation layer 120 can be formed to fill the second trench T2.

[0063] In some embodiments, the second trench T2 has a sloped sidewall. However, this is a characteristic of the etching process for forming the second trench T2, and the present disclosure is not limited to this case. Figure 5

[0064] ​​The second trenches T2 can define the first boundary surfaces CS1 of each first boundary pattern IP1 and the second boundary surfaces CS2 of each second boundary pattern IP2. Thus, the second element isolation layer 120 can contact and define the first boundary surfaces CS1 of each first boundary pattern IP1 and the second boundary surfaces CS2 of each second boundary pattern IP2. The term "contact" as used herein refers to a direct connection (i.e., touching) unless otherwise indicated by context.

[0065] In some embodiments, the width of the second trenches T2 can be greater than the width of the first trenches T1. For example, as shown, the width of the second trenches T2 along the first direction D1 can be greater than the width of the first trenches T1 along the first direction D1. Figure 3

[0066] In some embodiments, the second trenches T2 can be formed deeper than the first trenches T1. For example, the bottom surface of the second trenches T2 can be lower than the bottom surface of the first trenches T1.

[0067] The second element isolation layer 120 can include, but is not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof.

[0068] The third element isolation layer 130 can be formed in the peripheral region PERI. The third element isolation layer 130 can define active regions in the substrate 100 that constitute control elements and dummy elements. For example, the substrate 100 in the peripheral region PERI can include third trenches T3. The third element isolation layer 130 can be formed to fill the third trenches T3. As used herein, the term "dummy" is used to refer to a component that has the same or similar structure and shape as other components but does not have a substantial function and exists in the device only as a pattern.

[0069] The third element isolation layer 130 can include, but is not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof.

[0070] In some embodiments, the second element isolation layer 120 and the third element isolation layer 130 can be formed at the same level. As used herein, the term "same level" means that the elements are formed by the same manufacturing process. For example, the second element isolation layer 120 and the third element isolation layer 130 can be made of the same material.

[0071] In some embodiments, each of the second element isolation layer 120 and the third element isolation layer 130 can be formed as multiple layers. For example, as shown, the second element isolation layer 120 can include a first layer 120a and a second layer 120b. The first layer 120a can be formed of a first material and the second layer 120b can be formed of a second material. Figure 3 ​As shown, each of the second element isolation layer 120 and the third element isolation layer 130 may include a third insulating layer 122, a fourth insulating layer 124, and a fifth insulating layer 126 sequentially formed in the second trench T2 or the third trench T3. The third insulating layer 122 may extend along the contour of each of the second trench T2 and the third trench T3. The fourth insulating layer 124 may be disposed on the third insulating layer 122 to extend along the contour of the third insulating layer 122. The fifth insulating layer 126 may fill a portion of each of the second trench T2 and the third trench T3 remaining after each of the second trench T2 and the third trench T3 has been filled with the third insulating layer 122 and the fourth insulating layer 124.

[0072] In some embodiments, the fourth insulating layer 124 may include a material different from the third insulating layer 122, and the fifth insulating layer 126 may include a material different from the fourth insulating layer 124. For example, the third insulating layer 122 may include silicon oxide, the fourth insulating layer 124 may include silicon nitride, and the fifth insulating layer 126 may include silicon oxide.

[0073] Because the boundary between the cell region and the boundary region INTERFACE is clearly defined in the semiconductor device according to the embodiment, product reliability can be improved. For example, a first boundary pattern IP1 including a first boundary surface CS1 can clearly define the boundary between the cell region CELL and the boundary region INTERFACE arranged along a first direction D1. Furthermore, a second boundary pattern IP2 including a second boundary surface CS2 can clearly define the boundary between the cell region CELL and the boundary region INTERFACE arranged along a second direction D2. Therefore, since short circuits between active regions adjacent to the boundary region INTERFACE can be prevented, a semiconductor device with improved product reliability can be provided.

[0074] Figure 7 to Figure 9 These are various cross-sectional views of the semiconductor device according to embodiments. For reference only. Figure 7 to Figure 9 It is along Figure 1 and Figure 2 Various cross-sectional views of line AA are shown. For ease of description, details related to the use of [the material] will be briefly given or omitted. Figure 1 to Figure 6 Redundant descriptions of components and features that are identical to those described.

[0075] refer to Figure 7 In the semiconductor device according to the embodiment, the bottom surface of the second trench T2 includes a wavy first bottom surface T2a and a flat second bottom surface T2b.

[0076] The first bottom surface T2a of the second trench T2 can be adjacent to the cell region CELL. The second bottom surface T2b of the second trench T2 can be farther from the cell region CELL than the first bottom surface T2a. For example, the second bottom surface T2b of the second trench T2 can be adjacent to the peripheral region PERI.

[0077] The first bottom surface T2a of the second trench T2 can have a wavy shape. Accordingly, a bottom surface in the second element isolation layer 120 formed on the first bottom surface T2a can have a wavy shape corresponding to the wavy shape of the first bottom surface T2a. When the second element isolation layer 120 is formed as a plurality of layers, the third insulating layer 122 and the fourth insulating layer 124 formed on the first bottom surface T2a can have a wavy shape corresponding to the wavy shape of the first bottom surface T2a.

[0078] The second bottom surface T2b of the second trench T2 can have a flat shape. Accordingly, a bottom surface in the second element isolation layer 120 formed on the second bottom surface T2b can have a flat shape corresponding to the flat shape of the second bottom surface T2b. When the second element isolation layer 120 is formed as a plurality of layers, the third insulating layer 122 and the fourth insulating layer 124 formed on the second bottom surface T2b can have a flat shape corresponding to the flat shape of the second bottom surface T2b.

[0079] Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. Figure 8 In the semiconductor device according to the embodiment, the first bottom surface T2a of the second trench T2 is lower than the second bottom surface T2b of the second trench T2.

[0080] For example, the height of the peak of the wavy first bottom surface T2a can be lower than the height of the flat second bottom surface T2b. In some embodiments, the second bottom surface T2b of the second trench T2 can be higher than the bottom surface of the first trench T1.

[0081] Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. Figure 9 In the semiconductor device according to the embodiment, the first bottom surface T2a of the second trench T2 is lower than the second bottom surface T2b of the second trench T2.

[0082] For example, the height of the peak of the wavy first bottom surface T2a can be lower than the height of the flat second bottom surface T2b. In some embodiments, the second bottom surface T2b of the second trench T2 can be higher than the bottom surface of the first trench T1.

[0083] Figure 7 to Figure 9 The shape of the second trench T2 shown in FIG. 2B can be due to the characteristics of the etching process used to form the second trench T2. This will be described in more detail later with reference to FIGS. 3A and 3B. Figure 26 to Figure 29 This will be described in more detail.

[0084] Figure 10is a cross-sectional view of a semiconductor device according to an embodiment. For reference, Figure 10 is a cross-sectional view taken along Figure 1 line A-A of FIG. 1A. Figure 2 For ease of description, redundant descriptions of elements and features identical to those described using Figure 1 to Figure 6 will be given or omitted briefly.

[0085] Referring to Figure 10 , in the semiconductor device according to an embodiment, the second element isolation layer 120 further includes a sixth insulating layer 128 in a fourth trench T4.

[0086] The fourth trench T4 can be adjacent to the cell region CELL. Also, the fourth trench T4 can be formed in an upper portion of the second element isolation layer 120. In some embodiments, a plurality of fourth trenches T4 can be formed in the second element isolation layer 120. The sixth insulating layer 128 can be formed to fill the fourth trench T4.

[0087] The sixth insulating layer 128 can include, but is not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof.

[0088] Figure 10 The shape of the sixth insulating layer 128 shown in FIG. 1C can be due to characteristics of an etching process for forming the fourth trench T4. This will be described in more detail later with reference to Figure 37 and Figure 38 .

[0089] Figure 11 is a layout view of a semiconductor device according to an embodiment. Figure 12 is a cross-sectional view taken along Figure 11 line C-C of FIG. 1A. Figure 13 is a cross-sectional view taken along Figure 11 line D-D of FIG. 1A. For reference, Figure 11 is an enlarged view of a region R1 of Figure 1 FIG. 1A. For ease of description, redundant descriptions of elements and features identical to those described using Figure 1 to Figure 10 will be given or omitted briefly.

[0090] In Figure 11 to Figure 13 , a dynamic random access memory (DRAM) is shown as an example of a semiconductor device according to an embodiment. However, this is merely an example. For example, the present disclosure is applicable to various semiconductor devices formed using the active pattern AP, the first boundary pattern IP1, and / or the second boundary pattern IP2 described above with reference to Figure 1 to Figure 10 .

[0091] Referring to Figure 11 to Figure 13According to embodiments, a semiconductor device includes word lines WL (gate electrodes 140), a gate dielectric layer 150, a gate capping pattern 160, bit lines BL, a first interlayer insulating film 200, a second interlayer insulating film 210, first contact structures 220, second contact structures 230, and a capacitor structure 300.

[0092] Each word line WL can span across a plurality of active patterns AP and the first boundary pattern IP1. For example, the word lines WL can extend along the first direction D1. The word lines WL can extend parallel to each other. Further, the word lines WL can be spaced apart from each other by an equal distance in the second direction D2. In some embodiments, some word lines WL can also extend across a plurality of second boundary patterns IP2 along the first direction D1.

[0093] In some embodiments, the word lines WL can be formed in the substrate 100. For example, the substrate 100 can include gate trenches GT. The gate trenches GT can span across the active patterns AP, the first boundary pattern IP1, the second boundary pattern IP2, and the first element isolation layer 110. For example, the gate trenches GT can extend along the first direction D1. The gate electrodes 140 can be formed in the gate trenches GT. Thus, the gate electrodes 140 can be buried in the active patterns AP, the first boundary pattern IP1, the second boundary pattern IP2, and the first element isolation layer 110 to function as the word lines WL.

[0094] In Figure 12 each gate trench GT has a sloped sidewall. However, this is a characteristic of the etching process for forming the gate trenches GT, and the present disclosure is not limited to this case.

[0095] In some embodiments, the word lines WL can extend beyond the cell region CELL to the interface region INTERFACE. For example, as shown in FIG. 1B, a portion of each word line WL can be disposed in the interface region INTERFACE. Thus, as shown in FIG. 1C, a portion of each gate electrode 140 can span across the second element isolation layer 120. Figure 11 Figure 13

[0096] The gate electrodes 140 can include a conductive material. For example, the gate electrodes 140 can include at least one of metals such as titanium (Ti), tantalum (Ta), aluminum (Al), and cobalt (Co), and combinations thereof. Alternatively, for example, the gate electrodes 140 can include polysilicon or silicon germanium, which are different from the metals.

[0097] In some embodiments, a bottom surface of the gate trenches GT in the active patterns AP, the first boundary pattern IP1, and the second boundary pattern IP2 can be higher than a bottom surface of the gate trenches GT in the first element isolation layer 110. For example, as shown in FIG. 1D, the gate trenches GT in the active patterns AP, the first boundary pattern IP1, and the second boundary pattern IP2 can have a higher bottom surface than the gate trenches GT in the first element isolation layer 110. Figure 13 ​​As shown, the first depth DT1 of the gate electrode 140 overlapping with the active pattern AP and the second depth DT2 of the gate electrode 140 overlapping with the first boundary pattern IP1 can be less than the third depth DT3 of the gate electrode 140 overlapping with the first element isolation layer 110.

[0098] In some embodiments, the bottom surface of the gate trench GT in the active pattern AP may be higher than the bottom surface of the gate trench GT in the first boundary pattern IP1 and the second boundary pattern IP2. For example, as Figure 13 As shown, the first depth DT1 of the gate electrode 140 overlapping with the active pattern AP can be less than the second depth DT2 of the gate electrode 140 overlapping with the first boundary pattern IP1.

[0099] The gate dielectric layer 150 may be located between the active pattern AP and the gate electrode 140, between the first boundary pattern IP1 and the gate electrode 140, and between the second boundary pattern IP2 and the gate electrode 140. For example, the gate dielectric layer 150 may extend conformally along the side and bottom surfaces of the gate trench GT.

[0100] The gate dielectric layer 150 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and a high dielectric constant (high k) material having a higher dielectric constant than silicon oxide.

[0101] A gate capping pattern 160 may be formed on the gate electrode 140. For example, the gate capping pattern 160 may fill a portion of each gate trench GT remaining after the gate trench GT has been filled with the gate dielectric layer 150 and the gate electrode 140.

[0102] The gate capping layer 160 may include, but is not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof.

[0103] In some embodiments, each active pattern AP may include a first source / drain region 105a and a second source / drain region 105b. The first source / drain region 105a and the second source / drain region 105b may be formed in the active pattern AP on both sides of the gate electrode 140.

[0104] For example, such as Figure 11 and Figure 12 As shown, a first source / drain region 105a may be formed at the center of each active pattern AP, and a second source / drain region 105b may be formed at both ends of the active pattern AP. In some embodiments, two gate electrodes 140 may share a first source / drain region 105a.

[0105] The bit lines BL can intersect the word lines WL. For example, the bit lines BL can extend along the second direction D2. The bit lines BL can extend parallel to each other. Also, the bit lines BL can be spaced apart from each other by an equal distance in the first direction D1. In an example embodiment, the bit lines BL can be disposed between the two first border patterns IP1 spaced apart from each other along the first direction D1. For example, each bit line BL can overlap a corresponding column of the active pattern AP between the two first border patterns IP1.

[0106] In some embodiments, the bit lines BL can extend beyond the cell region CELL to the border region INTERFACE. For example, as shown in FIG. 1, a portion of each bit line BL can be disposed in the border region INTERFACE. Thus, a portion of each bit line BL can be formed on the second element isolation layer 120. Figure 11

[0107] Each bit line BL can be a single layer made of one type of conductive material, or can be a multi-layer made of a combination of multiple types of conductive materials. For example, each bit line BL can be a multi-layer including a polysilicon layer, a nitride layer (e.g., TiSiN), and a metal layer (e.g., tungsten (W)) sequentially stacked on the active pattern AP.

[0108] The first interlayer insulating film 200 and the second interlayer insulating film 210 can be sequentially stacked on the active pattern AP, the first border pattern IP1, and the second border pattern IP2. In Figure 12 and Figure 13 In the example embodiment, only two interlayer insulating films 200 and 210 are formed. However, this is merely an example. For example, three or more interlayer insulating films can be formed on the active pattern AP, the first border pattern IP1, and the second border pattern IP2.

[0109] The first interlayer insulating film 200 and the second interlayer insulating film 210 can include, but are not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k material having a dielectric constant lower than that of silicon oxide.

[0110] The first contact structure 220 can be connected to the first source / drain region 105a. For example, the first contact structure 220 can pass through the first interlayer insulating film 200, thereby being connected to the first source / drain region 105a.

[0111] The second contact structure 230 can be spaced apart from the first contact structure 220. The second contact structure 230 can be connected to the second source / drain region 105b. For example, the second contact structure 230 can pass through the first interlayer insulating film 200 and the second interlayer insulating film 210, so as to be connected to the second source / drain region 105b.

[0112] ​Each of the first contact structures 220 and the second contact structures 230 can include an electrically conductive material. For example, each of the first contact structures 220 and the second contact structures 230 can include at least one of a metal such as titanium (Ti), tantalum (Ta), tungsten (W), aluminum (Al), and cobalt (Co), and combinations thereof. Alternatively, for example, each of the first contact structures 220 and the second contact structures 230 can include polysilicon or silicon germanium in addition to the metal.

[0113] Each of the first contact structures 220 and the second contact structures 230 can be a single layer made of one type of electrically conductive material, or can be a multi-layer made of a combination of multiple types of electrically conductive materials. For example, each second contact structure 230 can be a multi-layer including a polysilicon layer and a metal layer (e.g., tungsten (W)) sequentially stacked on the second source / drain region 105b.

[0114] The bit line BL can be connected to the first contact structures 220. For example, the bit line BL can be formed on an upper surface of the first interlayer insulating film 200 and an upper surface of the first contact structures 220. Thus, the bit line BL can be electrically connected to the first source / drain region 105a.

[0115] The capacitor structure 300 can be connected to the second contact structures 230. For example, the capacitor structure 300 can be formed on an upper surface of the second interlayer insulating film 210 and an upper surface of the second contact structures 230. Thus, the capacitor structure 300 can be electrically connected to the second source / drain region 105b.

[0116] The capacitor structure 300 can store information in a semiconductor device (e.g., a semiconductor memory device) according to an embodiment. For example, each capacitor structure 300 can include a lower electrode 310, a capacitor dielectric layer 320, and an upper electrode 330. Each capacitor structure 300 can store an electric charge in the capacitor dielectric layer 320 by using a potential difference between the lower electrode 310 and the upper electrode 330.

[0117] Each of the lower electrode 310 and the upper electrode 330 can include, but is not limited to, doped polysilicon, a metal, or a metal nitride. The capacitor dielectric layer 320 can include, but is not limited to, at least one of silicon oxide and a high-k material having a higher dielectric constant than silicon oxide.

[0118] In some embodiments, the first acute angle θ1 can be 60 degrees. In this case, the capacitor structure 300 can be arranged in a honeycomb shape. However, this is merely an example, and the capacitor structure 300 can be arranged in various shapes.

[0119] A semiconductor device according to an embodiment will now be described with reference to Figure 1 to Figure 39 A semiconductor device according to an embodiment will now be described with reference to

[0120] Figure 14 to Figure 30 is a diagram illustrating steps of a method of manufacturing a semiconductor device according to an embodiment. For convenience of description, redundant descriptions of elements and features identical to those described above will be omitted or briefly given. Figure 1 to Figure 10 Redundant descriptions of elements and features identical to those described above will be omitted or briefly given.

[0121] Referring to Figure 14 , a first material layer 20, a first mask layer 21, a second material layer 22, a second mask layer 23, a third material layer 24, a third mask layer 25, and a first photoresist 26 are sequentially formed on a substrate 100.

[0122] The substrate 100 can have, but is not limited to, a structure in which a base substrate and an epitaxial layer are stacked. The substrate 100 can be a silicon substrate, a gallium arsenide substrate, a silicon germanium substrate, or a semiconductor-on-insulator (SOI) substrate. As an example, the substrate 100 will be described below as a silicon substrate.

[0123] The first material layer 20 can be formed on the substrate 100. The first material layer 20 can include a material having etching selectivity with respect to the substrate 100. For example, when the substrate 100 includes silicon, the first material layer 20 can include a silicon oxide layer.

[0124] The first mask layer 21 can be formed on the first material layer 20. The first mask layer 21 can include a material having etching selectivity with respect to the first material layer 20. For example, when the first material layer 20 includes a silicon oxide layer, the first mask layer 21 can include a polysilicon layer.

[0125] The second material layer 22 can be formed on the first mask layer 21. The second material layer 22 can include, for example, a carbon-based material layer. For example, the second material layer 22 can include an amorphous carbon layer (ACL) or a spin-on hard mask (SOH) material layer.

[0126] The second mask layer 23 can be formed on the second material layer 22. The second mask layer 23 can include a material having etching selectivity with respect to the second material layer 22. For example, when the second material layer 22 includes a carbon-based material layer, the second mask layer 23 can include a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

[0127] The third material layer 24 can be formed on the second mask layer 23. The third material layer 24 can include, for example, a carbon-based material layer. For example, the third material layer 24 can include an ACL or a SOH material layer.

[0128] The third mask layer 25 can be formed on the third material layer 24. The third mask layer 25 can include a material having etching selectivity with respect to the third material layer 24. For example, when the third material layer 24 includes a carbon-based material layer, the third mask layer 25 can include a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

[0129] A first photoresist 26 can be formed on the third mask layer 25. The first photoresist 26 can be a photoresist pattern formed by, for example, a photolithography process.

[0130] The substrate 100 can include a cell region CELL, a peripheral region PERI, and a boundary region INTERFACE. In some embodiments, the first photoresist 26 on the cell region CELL can have a shape of a plurality of bars extending in parallel with each other in one direction (e.g., a third direction D3). Figure 2 Figure 14 In some embodiments, only cross sections of the plurality of bars taken in a first direction D1 are illustrated. However, portions extending in a third direction D3 between the first direction D1 and a second direction D2 are omitted for simplicity of the drawings. In some embodiments, at least a portion of the first photoresist 26 can expose the boundary region INTERFACE. In some embodiments, the first photoresist 26 can cover the peripheral region PERI.

[0131] Referring to Figure 15 , the third mask layer 25 and the third material layer 24 are patterned to form a first mask pattern 25P and a first material pattern 24P.

[0132] For example, the first mask pattern 25P can be formed by patterning the third mask layer 25 using the first photoresist 26 as an etching mask. Then, the first material pattern 24P can be formed by patterning the third material layer 24 using the first mask pattern 25P as an etching mask. Patterning the third mask layer 25 and the third material layer 24 can be performed by, for example, an anisotropic etching process.

[0133] Next, a first spacer 27 is formed on side surfaces of the first mask pattern 25P and / or the first material pattern 24P.

[0134] For example, a primary spacer layer can be formed to extend along contours of the second mask layer 23, the first mask pattern 25P, and the first material pattern 24P. Then, an anisotropic etching process can be performed on the primary spacer layer. Accordingly, the first spacer 27 can be formed on side surfaces of the first mask pattern 25P and the first material pattern 24P.

[0135] The first spacer 27 can include, but is not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof.

[0136] Referring to Figure 16 , the second mask layer 23 and the second material layer 22 are patterned to form a second mask pattern 23P and a second material pattern 22P.

[0137] ​For example, a second mask pattern 23P can be formed by patterning the second mask layer 23 using the first spacer 27 as an etching mask. Then, a second material pattern 22P can be formed by patterning the second material layer 22 using the second mask pattern 23P as an etching mask. The patterning of the second mask layer 23 and the second material layer 22 can be performed, for example, by an anisotropic etching process.

[0138] Next, a second spacer 28A is formed on the opposite side surfaces of the second mask pattern 23P and / or the second material pattern 22P.

[0139] For example, the primary spacer layer can be formed to extend along the contours of the first mask layer 21, the second mask pattern 23P, and the second material pattern 22P. An anisotropic etching process can then be performed on the primary spacer layer. Therefore, the second spacer 28A can be formed on the opposing side surfaces of the second mask pattern 23P and / or the second material pattern 22P.

[0140] The second spacer 28A may include, but is not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof.

[0141] In some embodiments, the sacrificial pattern 28B may be further formed on the first mask layer 21 to cover a portion of the boundary region INTERFACE and the peripheral region PERI.

[0142] refer to Figure 17 and Figure 18 The first mask layer 21 is patterned to form the third mask pattern 21P.

[0143] For example, the third mask pattern 21P can be formed by patterning the first mask layer 21 using the second spacer 28A as an etching mask. For example, in some embodiments, the third mask pattern 21P can be formed by quadruple patterning (QPT).

[0144] In some embodiments, due to the first photoresist 26 on the cell region CELL (see...) Figure 14 The third mask pattern 21P on the cell region CELL can also be in the shape of multiple stripes extending from the third direction to D3. Figure 18 In order to simplify the accompanying drawings, the extension of the third mask pattern 21P along the third direction D3 is omitted, and only the cross-sectional view of the third mask pattern 21P taken along the first direction D1 is shown.

[0145] In some embodiments, the third mask pattern 21P can expose at least a portion of the boundary region INTERFACE. For example, as... Figure 17As illustrated, at least a portion of the third mask pattern 21P in the shape of a bar extending in the third direction D3 can extend to the boundary region INTERFACE adjacent to the cell region CELL.

[0146] Referring to Figure 19 and Figure 20 The fourth material layer 30, the fourth mask layer 31, and the second photoresist 32 are sequentially formed on the third mask pattern 21P.

[0147] The fourth material layer 30 can be formed on the third mask pattern 21P. The fourth material layer 30 can include, for example, a carbon-based material layer. For example, the fourth material layer 30 can include an ACL or SOH material layer.

[0148] The fourth mask layer 31 can be formed on the fourth material layer 30. The fourth mask layer 31 can include a material having etching selectivity with respect to the fourth material layer 30. For example, when the fourth material layer 30 includes a carbon-based material layer, the fourth mask layer 31 can include a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

[0149] The second photoresist 32 can be formed on the fourth mask layer 31. The second photoresist 32 can be a photoresist pattern formed by, for example, a photolithography process.

[0150] In some embodiments, the second photoresist 32 can expose a portion of the third mask pattern 21P. For example, the second photoresist 32 can include a plurality of first openings 320 overlapping a portion of the third mask pattern 21P. Although each first opening 320 is illustrated as a circle, this is merely an example, and the present disclosure is not limited to such a case.

[0151] Referring to Figure 21 and Figure 22 The third mask pattern 21P is patterned to form a fourth mask pattern 21PP.

[0152] For example, the fourth mask layer 31 can be patterned using the second photoresist 32 as an etching mask. Then, the fourth material layer 30 can be patterned using the patterned fourth mask layer 31 as an etching mask. Then, the fourth mask pattern 21PP can be formed by patterning the third mask pattern 21P using the patterned fourth material layer 30 as an etching mask.

[0153] Accordingly, the third mask pattern 21P in the shape of a bar extending in the third direction D3 can be cut into the fourth mask pattern 21PP in the shape of a plurality of bars extending in the third direction D3 in parallel with each other. In some embodiments, a center of one of the fourth mask patterns 21PP can be disposed at a position adjacent to one end of another fourth mask pattern 21PP.

[0154] Next, the first material layer 20 is patterned using the fourth mask pattern 21PP as an etching mask, thereby forming a third material pattern 20P.

[0155] Referring to Figure 23 and Figure 24 the substrate 100 is patterned using the third material pattern 20P as an etching mask.

[0156] For example, an etching process using the third material pattern 20P as an etching mask can be performed to form a first trench T1 in the substrate 100. Accordingly, a plurality of active patterns AP defined by the first trench T1 can be formed in the cell region CELL.

[0157] In some embodiments, since the third material pattern 20P can expose at least a portion of the boundary region INTERFACE, the first trench T1 can also be formed in at least a portion of the boundary region INTERFACE. For example, at least a portion of the first trench T1 can be formed in the boundary region INTERFACE adjacent to the cell region CELL. Accordingly, a plurality of dummy patterns DP defined by the first trench T1 can be formed in the boundary region INTERFACE.

[0158] Referring to Figure 25 the first element isolation layer 110 is formed in the first trench T1.

[0159] For example, the first insulating layer 112 and the second insulating layer 114 can be sequentially formed on the substrate 100 to fill the first trench T1. Accordingly, the first element isolation layer 110 can be formed in the substrate 100 to define the active patterns AP and the dummy patterns DP.

[0160] In some embodiments, the first insulating layer 112 can include silicon oxide, and the second insulating layer 114 can include silicon nitride.

[0161] Referring to Figure 26 and Figure 27 a fifth material layer 40, a fifth mask layer 41, and a third photoresist 42 are formed on the substrate 100.

[0162] The fifth material layer 40 can include, for example, a carbon-based material layer. For example, the fifth material layer 40 can include an ACL or SOH material layer.

[0163] The fifth mask layer 41 can be formed on the fifth material layer 40. The fifth mask layer 41 can include a material having etching selectivity with respect to the fifth material layer 40. For example, when the fifth material layer 40 includes a carbon-based material layer, the fifth mask layer 41 can include a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

[0164] The third photoresist layer 42 can be formed on the fifth mask layer 41. The third photoresist layer 42 can be a photoresist pattern formed by, for example, a photolithography process.

[0165] In some embodiments, the third photoresist 42 may expose a portion of the peripheral region PERI and the boundary region INTERFACE. For example, the third photoresist 42 may include a second opening 420 that exposes a portion of the peripheral region PERI and the boundary region INTERFACE.

[0166] refer to Figure 28 and Figure 29 The substrate 100 is patterned using a third photoresist 42 as an etching mask.

[0167] For example, the third photoresist 42 can be used as an etching mask to pattern the fifth mask layer 41. Then, the patterned fifth mask layer 41 can be used as an etching mask to pattern the fifth material layer 40. Then, the patterned fifth material layer 40 can be used as an etching mask to pattern the dummy pattern DP and the first element isolation layer 110.

[0168] Therefore, a second trench T2 can be formed in the substrate 100 of the boundary region INTERFACE to define the boundary region INTERFACE. Due to the second trench T2, the dummy pattern DP in the boundary region INTERFACE can be formed as a first boundary pattern IP1 including a first boundary surface CS1 and a second boundary pattern IP2 including a second boundary surface CS2.

[0169] Furthermore, a third trench T3 can be formed in the substrate 100 of the peripheral region PERI to define the active region of the peripheral region PERI. For example, in some embodiments, the second trench T2 and the third trench T3 can be formed after the first trench T1 is formed.

[0170] Since forming the second trench T2 may include etching a dummy pattern DP (see...) Figure 26 Therefore, in some embodiments, the traces of the dummy pattern DP can be retained in the second trench T2. For example, due to the difference in etch rates between the dummy pattern DP and the first element isolation layer 110, the bottom surface of the second trench T2 may include a wavy first bottom surface T2a (see...). Figure 7 ) and the flat second bottom surface T2b (see Figure 7 ).

[0171] In some embodiments, the first bottom surface T2a of the second trench T2 (see...) Figure 8 It can be lower than the second bottom surface T2b of the second trench T2 (see...) Figure 8). Alternatively, in some embodiments, the first bottom surface T2a (see Figure 9 ) of the second trench T2 can be higher than the second bottom surface T2b (see Figure 9 ) of the second trench T2. This can be due to a difference between etching rates between the boundary region INTERFACE in which the dummy pattern DP is formed and the boundary region INTERFACE in which the dummy pattern DP is not formed in an etching process for forming the second trench T2, but embodiments are not limited to this case.

[0172] Referring to Figure 30 , the third insulating layer 122, the fourth insulating layer 124, and the fifth insulating layer 126 are sequentially formed in the second trench T2 and the third trench T3.

[0173] In some embodiments, the third insulating layer 122 can include silicon oxide, the fourth insulating layer 124 can include silicon nitride, and the fifth insulating layer 126 can include silicon oxide.

[0174] Next, referring to Figure 2 and Figure 3 , the second element isolation layer 120 is formed in the second trench T2, and the third element isolation layer 130 is formed in the third trench T3.

[0175] For example, a planarization process can be performed to expose the upper surface of the active pattern AP. The planarization process can include, but is not limited to, a chemical mechanical polishing (CMP) process.

[0176] Accordingly, the second element isolation layer 120 can be formed in the substrate 100 of the boundary region INTERFACE to define the boundary region INTERFACE. Further, the third element isolation layer 130 can be formed in the substrate 100 of the peripheral region PERI to define the active region of the peripheral region PERI, which constitutes the control element and the dummy element.

[0177] Figure 31 to Figure 39 is a diagram illustrating steps of a method of manufacturing a semiconductor device according to an embodiment. For ease of description, redundant descriptions of elements and features identical to those described using Figure 1 to Figure 30 will be briefly given or omitted.

[0178] Referring to Figure 31 , the fifth material layer 40, the fifth mask layer 41, and the third photoresist 42 are formed on the substrate 100.

[0179] The formation of the fifth material layer 40, the fifth mask layer 41, and the third photoresist 42 is similar to the formation described above using Figure 26 and Figure 27 , and thus detailed descriptions thereof will be omitted.

[0180] Referring to Figure 32 , the substrate 100 is patterned using the third photoresist 42 as an etching mask.

[0181] Patterning the substrate 100 using the third photoresist 42 as an etching mask is similar to the patterning described above using the first photoresist 10 as an etching mask, and thus a detailed description thereof will be omitted. Figure 28 and Figure 29 Therefore, the second trench T2 can be formed in the substrate 100 of the boundary area INTERFACE to define the boundary area INTERFACE. Also, the third trench T3 can be formed in the substrate 100 of the peripheral area PERI to define the active area of the peripheral area PERI.

[0182] Referring to Figure 33 , the third insulating layer 122, the fourth insulating layer 124, and the fifth insulating layer 126 are sequentially formed in the second trench T2 and the third trench T3.

[0183] The formation of the third insulating layer 122, the fourth insulating layer 124, and the fifth insulating layer 126 is similar to the formation described above using the first insulating layer 12, and thus a detailed description thereof will be omitted. Figure 30

[0184] Referring to Figure 34 , the second element isolation layer 120 is formed in the second trench T2, and the third element isolation layer 130 is formed in the third trench T3.

[0185] For example, a planarization process can be performed to expose the upper surface of the third insulating layer 122. The planarization process can include, but is not limited to, a CMP process.

[0186] In some embodiments, the upper surface of the fourth insulating layer 124 can be recessed below the upper surfaces of the third insulating layer 122 and the fifth insulating layer 126.

[0187] Referring to Figure 35 , the first material layer 20, the first mask layer 21, the second material layer 22, the second mask layer 23, the third material layer 24, the third mask layer 25, and the first photoresist 26 are sequentially formed on the substrate 100.

[0188] The formation of the first material layer 20, the first mask layer 21, the second material layer 22, the second mask layer 23, the third material layer 24, the third mask layer 25, and the first photoresist 26 is similar to the formation described above using the first material layer 2, and thus a detailed description thereof will be omitted. Figure 14

[0189] Referring to Figure 36 , the first mask layer 21 is patterned to form a third mask pattern 21P.

[0190] ​​For example, QPT can be used to form a third mask pattern 21P. The formation of the third mask pattern 21P is similar to the above. Figure 15 to Figure 18 The formations described are similar, so their detailed descriptions will be omitted.

[0191] In some embodiments, the third mask pattern 21P may expose at least a portion of the boundary region INTERFACE. For example, at least a portion of the third mask pattern 21P may extend to the boundary region INTERFACE adjacent to the cell region CELL. Therefore, at least a portion of the third mask pattern 21P may overlap with a portion of the second element isolation layer 120.

[0192] refer to Figure 37 The fourth material layer 30, the fourth mask layer 31, and the second photoresist 32 are sequentially formed on the third mask pattern 21P.

[0193] A fourth material layer 30, a fourth mask layer 31, and a second photoresist 32 are formed on the third mask pattern 21P, and are used above. Figure 19 and Figure 20 The formations described are similar, so their detailed descriptions will be omitted.

[0194] refer to Figure 38 The third mask pattern 21P is patterned to form the fourth mask pattern 21PP.

[0195] The formation of the fourth mask pattern 21PP and its above use Figure 21 and Figure 22 The formations described are similar, so their detailed descriptions will be omitted.

[0196] Next, the first material layer 20 is patterned using the fourth mask pattern 21PP as an etching mask to form the third material pattern 20P.

[0197] In some embodiments, a portion of the second element isolation layer 120 may be patterned simultaneously with the formation of the third material pattern 20P. For example, at least a portion of the fourth mask pattern 21PP may overlap with a portion of the second element isolation layer 120. Therefore, the second element isolation layer 120 may be partially etched while the first material layer 20 is patterned. Consequently, the fourth trench T4 may be formed in the upper portion of the second element isolation layer 120 adjacent to the cell region CELL.

[0198] refer to Figure 39 The substrate 100 is patterned using a third material pattern 20P as an etching mask.

[0199] For example, an etching process using the third material pattern 20P as an etching mask can be performed to form the first trench T1 in the substrate 100. Accordingly, a plurality of active patterns AP defined by the first trench T1 can be formed in the cell region CELL. For example, in some embodiments, the second trench T2 and the third trench T3 can be formed before the first trench T1 is formed.

[0200] Next, referring to Figure 10 , the first element isolation layer 110 is formed in the first trench T1, and the sixth insulating layer 128 is formed in the fourth trench T4.

[0201] For example, the first insulating layer 112 and the second insulating layer 114 can be sequentially formed on the substrate 100 to fill the first trench T1 and the fourth trench T4. Accordingly, the first element isolation layer 110 can be formed in the substrate 100 to define the active pattern AP. Further, the sixth insulating layer 128 can be formed to fill the fourth trench T4.

[0202] While the present inventive concept has been shown and described with reference to exemplary embodiments thereof, it will be apparent to those of ordinary skill in the art that various changes in form and details can be made thereto without departing from the spirit and scope of the present inventive concept as defined by the appended claims.

Claims

1. A semiconductor device, comprising: The substrate includes a cell region, a boundary region, and a peripheral region arranged sequentially along a first direction; An active pattern extends along a third direction in the cell region, the third direction forming a first acute angle with respect to the first direction; as well as A boundary pattern is formed in the unit region and is directly adjacent to the boundary region. The boundary pattern includes a third side surface extending along the third direction and a first boundary surface extending from the third side surface along a second direction, wherein the second direction is perpendicular to the first direction. Wherein, the first boundary surface defines the boundary between the unit region and the boundary region, and The semiconductor device further includes: a first element isolation layer formed in the cell region to define the third side surface of the boundary pattern and the side surface of the active pattern; and A second element isolation layer is formed in the boundary region to define the first boundary surface of the boundary pattern.

2. The semiconductor device according to claim 1, further comprising: The third element isolation layer, in the peripheral region The second element isolation layer and the third element isolation layer are formed at the same vertical height.

3. The semiconductor device according to claim 1, in, The third side surface intersects with the first boundary surface to form a first interior angle, and Wherein, the sum of the first acute angle and the first interior angle is 90 degrees.

4. The semiconductor device according to claim 1, in, The boundary pattern also includes a fourth side surface that is opposite to the third side surface and extends along the third direction.

5. The semiconductor device according to claim 4, in, The third side surface intersects with the first boundary surface to form a first interior angle. Wherein, the fourth side surface intersects with the first boundary surface to form a second interior angle, and The sum of the first interior angle and the second interior angle is 180 degrees.

6. The semiconductor device according to claim 1, in, In a cutting plane that intersects the first boundary surface and extends along the first direction, the first width of the active pattern is greater than the second width of the boundary pattern.

7. A semiconductor device, comprising: The substrate includes a cell region, a peripheral region surrounding the cell region, and a boundary region between the cell region and the peripheral region; Multiple active patterns are present in the unit region; A first boundary pattern is formed in the unit region and includes a first boundary surface, the first boundary surface defining a first portion of the boundary between the unit region and the boundary region; as well as The gate electrode extends along a first direction and spans the plurality of active patterns and the first boundary pattern. In the cutting plane that intersects the first boundary surface and extends along the first direction, the first width of each of the plurality of active patterns is greater than the second width of the first boundary pattern, and the height of each of the plurality of active patterns is greater than the height of the first boundary pattern.

8. The semiconductor device according to claim 7, in, The first depth of the gate electrode that overlaps with each of the plurality of active patterns is less than the second depth of the gate electrode that overlaps with the first boundary pattern.

9. The semiconductor device according to claim 7, in, Each of the plurality of active patterns includes a first side surface extending along a third direction and a second side surface opposite the first side surface and extending along the third direction, the third direction forming an acute angle with respect to the first direction, and The first boundary pattern includes a third side surface extending from the first boundary surface along the third direction.

10. The semiconductor device according to claim 9, in, The first width is the distance between the first side surface and the second side surface in the first direction, and The second width is the distance between the third side surface and the first boundary surface in the first direction.

11. The semiconductor device according to claim 7, further comprising: A second boundary pattern is formed in the unit region and spaced apart from the first boundary pattern in the first direction. The second boundary pattern includes a second boundary surface that defines a second portion of the boundary between the unit region and the boundary region.

12. The semiconductor device according to claim 11, in, The plurality of active patterns are configured in a third direction between the first boundary pattern and the second boundary pattern, wherein each of the plurality of active patterns extends along the third direction, and The area of ​​each of the plurality of active patterns is smaller than the area of ​​the first boundary pattern.

13. The semiconductor device according to claim 11, in, The first boundary surface and the second boundary surface are located in the same plane.

14. The semiconductor device according to claim 11, in, The first boundary surface extends along a second direction perpendicular to the first direction, and The second boundary surface extends along the first direction.

15. A semiconductor device, comprising: The substrate includes a cell region, a peripheral region surrounding the cell region, and a boundary region between the cell region and the peripheral region; Multiple active patterns are present in the unit region; A first boundary pattern is formed in the unit region and is directly adjacent to the boundary region. A gate electrode extends along a first direction and spans the plurality of active patterns and the first boundary pattern; Bit lines extend along a second direction intersecting the first direction and connect to the first source / drain region of each of the plurality of active patterns; as well as A capacitor structure, formed on the cell region and connected to a second source / drain region of each of the plurality of active patterns. Wherein, the first boundary pattern includes a third side surface and a first boundary surface, the third side surface extending along a third direction forming an acute angle with the first direction, and the first boundary surface defining a first portion of the boundary between the unit region and the boundary region, and The substrate includes: A first trench is formed in the cell region and defines the third side surface of the first boundary pattern and the side surface of each of the plurality of active patterns; A second groove is formed in the boundary region and defines the first boundary surface of the first boundary pattern; and A third groove is formed in the peripheral region and is spaced apart from the second groove.

16. The semiconductor device of claim 15, further comprising: A first element isolation layer fills the first trench; A second element isolation layer fills the second trench; as well as A third element isolation layer fills the third trench.

17. The semiconductor device according to claim 15, in, The first boundary surface extends along the second direction.

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