Terminal structure of a power semiconductor device and power semiconductor device

Abstract

The present application relates to the technical field of semiconductor devices, and discloses a terminal structure of a power semiconductor device and a power semiconductor device. The terminal structure of the power semiconductor device includes: a substrate and an epitaxial layer located on the substrate; a breakdown voltage ring located within the epitaxial layer, a cutoff ring located within the epitaxial layer and outside the breakdown voltage ring, a dielectric layer, a metal layer, and a passivation layer sequentially disposed on the breakdown voltage ring and the cutoff ring. The breakdown voltage ring, the cutoff ring, the dielectric layer, the metal layer, and the passivation layer form a breakdown voltage terminal structure. Among them, a scribing groove is provided on the outer side of the cutoff ring, a depression is provided at the position between the cutoff ring and the scribing groove, and the passivation layer extends into the depression to cover the cutoff ring and the metal layer. The terminal structure of the power semiconductor structure disclosed in the present application ensures the reliability of the device, can further reduce the leakage current level of the device, and effectively reduces the device loss.

Description

Technical Field

[0001] This application relates to the technical field of semiconductor devices, and particularly relates to a terminal structure of a power semiconductor device and a power semiconductor device. Background Art

[0002] Power semiconductor devices represented by IGBTs (Insulated Gate Bipolar Transistors) and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) are the mainstream devices in the current field of power electronics. They are key devices for controlling strong electricity with weak electricity and are widely used in various power control circuits, drive circuits, etc. In particular, they play an irreplaceable role in various fields such as variable-frequency motors, photovoltaic inverters, smart grids, new energy vehicles, and electric locomotive traction drives.

[0003] The reason why power semiconductor devices can quickly replace traditional components such as electron tubes and become the current mainstream power electronic devices is because of their characteristics such as light weight, small volume, low power consumption, and high reliability. During the R & D process of power semiconductor devices, the power consumption and reliability of the devices are often required as important performance indicators. Therefore, when designing and manufacturing power semiconductor devices, how to make the forward conduction loss of power semiconductor devices as small as possible, and at the same time, the leakage current during reverse cut-off is also as small as possible, is a problem that needs to be solved. Summary of the Invention

[0004] This application provides a terminal structure of a power semiconductor device, which can further reduce the leakage level of the device, effectively reduce the device loss, and at the same time ensure the reliability of the device.

[0005] To achieve the above object, this application provides a terminal structure of a power semiconductor device, including:

[0006] A substrate and an epitaxial layer located on the substrate;

[0007] A breakdown voltage ring located in the epitaxial layer, a cut-off ring located in the epitaxial layer and outside the breakdown voltage ring, a dielectric layer, a metal layer, and a passivation layer sequentially disposed on the breakdown voltage ring and the cut-off ring. The breakdown voltage ring, the cut-off ring, the dielectric layer, the metal layer, and the passivation layer form a breakdown voltage terminal structure; wherein,

[0008] A dicing groove is provided on the outer side of the cut-off ring, a recess is provided at the position between the cut-off ring and the dicing groove, and the passivation layer extends into the recess to cover the cut-off ring and the metal layer.

[0009] The terminal structure of the power semiconductor device in this application forms multiple breakdown voltage rings for improving the lateral breakdown voltage and a termination ring located outside the breakdown voltage rings within the epitaxial layer, and forms a dielectric layer, a metal layer, and a passivation layer to form a breakdown voltage terminal structure, which can ensure that the leakage current of the power semiconductor device is as small as possible; at the same time, the passivation layer can improve the reliability of the power semiconductor device. In addition, in this application, a depression is formed at a position outside the termination ring and close to the dicing slot area, and the passivation layer extends into the depression, so that the side of the metal layer and the termination ring facing the outer edge of the breakdown voltage ring region is covered by the passivation layer, which can further reduce the possibility of device leakage current.

[0010] Therefore, the terminal structure of the power semiconductor device in this application can further reduce the device leakage current level, effectively reduce the device loss, and ensure the reliability of the device at the same time.

[0011] Preferably, the breakdown voltage ring includes a main junction and multiple voltage-dividing rings.

[0012] Preferably, one end of the termination ring is located at the top of the epitaxial layer, and the other end is located at the side of the depression.

[0013] Preferably, each of the breakdown voltage ring structures is one of a field limiting ring structure, a field limiting ring plus field plate structure, an end terminal extension structure, and a lateral variable doping structure.

[0014] Preferably, the depth of the depression is 0.1 - 10 μm.

[0015] Preferably, the material of the passivation layer is one or more of silicon oxide, silicon nitride, and polyimide.

[0016] This application also provides a power semiconductor device, including the terminal structure of the power semiconductor device according to any one of the above.

[0017] This application also provides a preparation method for the terminal structure of a power semiconductor device, including:

[0018] Forming a substrate, an epitaxial layer, a breakdown voltage ring, a termination ring, a dielectric layer, a metal layer, and a dicing slot;

[0019] Etching the part of the dielectric layer located at the outer edge of the termination ring, and partially etching the part of the epitaxial layer located between the termination ring and the dicing slot to form a depression in the epitaxial layer;

[0020] Partially etching and removing the metal layer located at the outer edge of the termination ring;

[0021] Depositing a passivation layer on the dielectric layer, the metal layer, and within the depression. Description of the Drawings

[0022] Figure 1 It is a schematic diagram of the terminal structure of a power semiconductor device in the prior art;

[0023] Figure 2 It is a schematic diagram of the terminal structure of a power semiconductor device in the present application;

[0024] Figure 3 It is a schematic flow diagram of the preparation method of the terminal structure of the power semiconductor device in the present application.

[0025] In the figure:

[0026] 1 - epitaxial layer; 2 - main junction; 3 - voltage - dividing ring; 4 - cut - off ring; 5 - dielectric layer; 6 - metal layer; 7 - passivation layer; 8 - depression. Detailed implementation manners

[0027] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0028] In the existing terminal structure of a power semiconductor device, as Figure 1 shown, the passivation layer 7 only covers above the epitaxial layer 1, but there is no passivation layer 7 protection on the side of the voltage - resistant terminal structure in the epitaxial layer 1. Due to the large potential difference between the cut - off ring 4 and the edge of the epitaxial layer 1, this part is prone to leakage.

[0029] Please refer to Figure 2 , an embodiment of the present application provides a terminal structure of a power semiconductor device, including: a substrate and an epitaxial layer 1 located on the substrate; a voltage - resistant ring located in the epitaxial layer 1, a cut - off ring 4 located in the epitaxial layer 1 and outside the voltage - resistant ring, a dielectric layer 5, a metal layer 6 and a passivation layer 7 sequentially arranged on the voltage - resistant ring and the cut - off ring 4, and the voltage - resistant ring, the cut - off ring 4, the dielectric layer 5, the metal layer 6 and the passivation layer 7 form a voltage - resistant terminal structure; wherein, a dicing groove (not shown in the figure) is provided outside the cut - off ring 4, a depression 8 is provided at the part between the cut - off ring 4 and the dicing groove, and the passivation layer 7 extends into the depression 8 to cover the cut - off ring 4 and the metal layer 6.

[0030] The terminal structure of the power semiconductor device in this application forms multiple breakdown voltage rings for improving the lateral breakdown voltage and a cutoff ring 4 located outside the breakdown voltage rings within the epitaxial layer 1, and forms a dielectric layer 5, a metal layer 6, and a passivation layer 7 to form a breakdown voltage terminal structure, which can ensure that the leakage current of the power semiconductor device is as small as possible; at the same time, the passivation layer 7 can improve the reliability of the power semiconductor device. In addition, in this application, a recess 8 is formed at a position outside the cutoff ring 4 and close to the dicing slot area, and the passivation layer 7 is made to extend into the recess 8, so that the metal layer 6 and the side of the cutoff ring 4 facing the outer edge of the breakdown voltage ring area are covered by the passivation layer 7, which can further reduce the possibility of device leakage current.

[0031] Therefore, the terminal structure of the power semiconductor device in this application can further reduce the device leakage current level, effectively reduce the device loss, and ensure the reliability of the device at the same time.

[0032] In an optional manner, one end of the cutoff ring 4 is located at the top of the epitaxial layer 1, and the other end is located at the side of the recess 8, that is, in this application, a recess 8 is provided outside the cutoff ring 4, and the passivation layer 7 is made to cover the cutoff ring 4, isolating the cutoff ring 4 from the silicon material, so that a better protection effect is achieved on the breakdown voltage terminal structure and the device leakage current level is reduced.

[0033] As Figure 2 shown, the breakdown voltage ring in this application can include a main junction 2 and multiple voltage-dividing rings 3, both of which can improve the lateral breakdown voltage of the device. The number of voltage-dividing rings 3 can be set according to actual needs, and each breakdown voltage ring structure can be any one of a field limiting ring structure, a field limiting ring plus field plate structure, an end terminal extension structure, and a lateral variable doping structure, all of which can improve the lateral breakdown voltage of the power semiconductor device.

[0034] In an optional manner, the recess 8 can be formed by an etching method during production, and the etching depth can be between 0.1 and 10 μm.

[0035] Preferably, the material of the passivation layer 7 is one or more of silicon oxide, silicon nitride, and polyimide. The above materials can make the polarization charges generated on the surface of the passivation layer 7 less, can achieve a higher breakdown voltage, and at the same time generate less leakage current.

[0036] This application also provides a power semiconductor device, including the terminal structure of the power semiconductor device with any of the above features. The power semiconductor device in the embodiments of this application can not only further reduce the device leakage current level and effectively reduce the device loss, but also ensure the reliability of the device.

[0037] In addition, based on the same inventive concept, see Figure 3 , this application also provides a preparation method for the terminal structure of a power semiconductor device, including the following steps:

[0038] S1: Form a substrate, an epitaxial layer 1, a breakdown voltage ring, a cut-off ring 4, a dielectric layer 5, a metal layer 6, and a scribing groove;

[0039] S2: Etch the part of the dielectric layer 5 located at the outer peripheral edge of the cut-off ring 4, and partially etch the part of the epitaxial layer 1 located between the cut-off ring 4 and the scribing groove so that a recess 8 is formed in the epitaxial layer 1;

[0040] S3: Partially etch and remove the metal layer 6 located at the outer peripheral edge of the cut-off ring 4;

[0041] S4: Deposit a passivation layer 7 on the dielectric layer 5, the metal layer 6, and in the recess 8.

[0042] The above preparation method is the same as the existing manufacturing method in step S1. The breakdown voltage ring structure can be one or more of a field limiting ring structure, a field limiting ring plus field plate structure, an end terminal extension structure, and a lateral variable doping structure; when etching the epitaxial layer 1 to form the recess 8, the etching depth can be controlled within a few micrometers or zero point a few micrometers; when etching the metal layer 6, the inner side near the device cell can be reserved and the outer side can be etched away; when depositing the passivation layer 7, first fill the entire wafer surface with the passivation layer 7, and then etch the passivation layer 7. This step will open an opening at the place where wire bonding is required in the cell area, and no opening will be made in the entire breakdown voltage terminal area. Above, the formed passivation layer 7 fills the entire cut-off ring 4 and the recess 8, forming a good protection effect.

[0043] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention is also intended to include these changes and modifications.

Claims

1. A terminal structure of a power semiconductor device, characterized in that, Comprising: A substrate and an epitaxial layer located on the substrate; A breakdown voltage ring located within the epitaxial layer, a cutoff ring located within the epitaxial layer and outside the breakdown voltage ring, a dielectric layer, a metal layer, and a passivation layer sequentially disposed on the breakdown voltage ring and the cutoff ring, and the breakdown voltage ring, cutoff ring, dielectric layer, metal layer, and passivation layer form a breakdown voltage terminal structure; wherein, A scribing groove is provided outside the cutoff ring, and a recess is provided at the position between the cutoff ring and the scribing groove, and the passivation layer extends into the recess to cover the cutoff ring and the metal layer.

2. The terminal structure of the power semiconductor device according to claim 1, wherein The breakdown voltage ring includes a main junction and a plurality of voltage-dividing rings.

3. The terminal structure of the power semiconductor device according to claim 1, characterized in that, One end of the cutoff ring is located at the top of the epitaxial layer, and the other end is located at the side of the recess.

4. The terminal structure of the power semiconductor device according to claim 1, characterized in that Each of the breakdown voltage rings is one of a field limiting ring structure, a field limiting ring plus field plate structure, an end terminal extension structure, and a lateral variable doping structure.

5. The terminal structure of the power semiconductor device according to claim 1, characterized in that, The depth of the recess is 0.1 - 10 μm.

6. The terminal structure of the power semiconductor device according to claim 1, characterized in that, The material of the passivation layer is one or more of silicon oxide, silicon nitride, and polyimide.

7. A power semiconductor device, characterized in that, Comprising a terminal structure of a plurality of power semiconductor devices as described in any one of claims 1 - 6.

8. A method for preparing a terminal structure of a power semiconductor device, characterized in that, Comprising: Forming a substrate, an epitaxial layer, a breakdown voltage ring, a cutoff ring, a dielectric layer, a metal layer, and a scribing groove; Etching the portion of the dielectric layer located at the outer peripheral edge of the cutoff ring, and partially etching the portion of the epitaxial layer located between the cutoff ring and the scribing groove to form a recess within the epitaxial layer; Partially etching and removing the metal layer located at the outer peripheral edge of the cutoff ring; Depositing a passivation layer on the dielectric layer, the metal layer, and within the recess.

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