Memory and method of forming the same

Abstract

A memory and a method for forming the same, the method comprising: providing a substrate; forming a first mask layer on the substrate, wherein the first mask layer has a plurality of parallel long strip-shaped patterns located above an array region, and the ends of each long strip-shaped pattern are connected to the first mask layer on the peripheral region of the substrate; forming a second mask layer on the first mask layer, wherein the second mask layer has a plurality of first patterns, wherein the plurality of first patterns are arranged in an array and overlap with the long strip-shaped patterns, and are used to form segmentation grooves in the substrate to segment the continuous active region into a plurality of discrete discrete active regions; using the second mask layer and the first mask layer as masks, etching layer by layer, transferring the long strip-shaped patterns and the first patterns into the substrate to form discrete active regions arranged in an array, and one end of the discrete active region located at the edge of the array region is connected to the peripheral region of the substrate. The memory formed by the above method has improved reliability.

Description

Technical Field

[0001] The present invention relates to the field of memory technology, and in particular to a memory and a forming method thereof. Background Art

[0002] The memory includes a plurality of memory cells arranged in an array, and each memory cell is formed on an active area (AA). In the formation process of the memory in the prior art, it is usually necessary to etch the substrate to form the active area arranged in an array.

[0003] As the storage capacity and storage density of the memory increase, the line width of the active area gradually decreases. When a plurality of array-arranged mask patterns are formed on the surface of the substrate as masks of the active area, a double patterning process (SADP) is required to form an AA mask with a smaller line width pattern for forming a long strip of AA; and then an STI mask is formed on the AA mask to cut off the long strip of AA, thereby forming an array-arranged active area.

[0004] When the SADP process is used to form the active area of ​​the memory array region, since the size of the AA mask is very small, the size of the formed active area is very small, and the edge of the active area array may be prone to collapse and stress, which affects the yield of the product.

[0005] How to improve the edge problem of the active area array of the memory is an issue that needs to be solved urgently. Summary of the invention

[0006] The technical problem to be solved by the present invention is to provide a memory and a method for forming the same, which can improve the edge problem of the active area array of the memory.

[0007] In order to solve the above problems, the present invention provides a method for forming a memory, comprising: providing a substrate, the substrate comprising an array area and a peripheral area surrounding the array area; forming a first mask layer on the substrate, wherein the first mask layer is provided with a plurality of parallel long strip-shaped patterns located above the array area, and the ends of each long strip-shaped pattern are connected to the first mask layer on the peripheral area of ​​the substrate, so as to form a plurality of parallel long strip-shaped continuous active areas in the array area of ​​the substrate, and the ends of the continuous active areas are connected to the substrate of the peripheral area; forming a second mask layer on the first mask layer, wherein the second mask layer is provided with a plurality of first patterns, the plurality of first patterns are arranged in an array and overlap with the long strip-shaped patterns, so as to form dividing grooves in the substrate, so as to divide the continuous active area into a plurality of discrete active areas; using the second mask layer and the first mask layer as masks, etching layer by layer, transferring the long strip-shaped patterns and the first patterns into the substrate, so as to form discrete active areas arranged in an array, and one end of the discrete active area located at the inner edge of the array area is connected to the substrate of the peripheral area.

[0008] Optionally, the method for forming the long strip-shaped pattern includes: forming a third mask layer on an unpatterned first mask layer, wherein a plurality of discrete and parallel arranged long strip-shaped initial long strip-shaped patterns are formed in the third mask layer; forming a fourth mask layer on the third mask layer, wherein the fourth mask layer covers the peripheral area of ​​the third mask layer and covers the end of the initial long strip-shaped pattern; using the fourth mask layer and the third mask layer as masks, etching the first mask layer to form a long strip-shaped pattern in the first mask layer, wherein the end of the long strip-shaped pattern is connected to the peripheral area of ​​the first mask layer; and removing the third mask layer and the fourth mask layer.

[0009] Optionally, a second pattern is formed in the second mask layer and is located on the peripheral area of ​​the substrate and surrounds the long strip pattern. The second pattern is used to form a peripheral groove surrounding the array area in the peripheral area of ​​the substrate.

[0010] Optionally, there is a certain distance between the second graphic and the first graphic at the outermost edge.

[0011] Optionally, the side wall of the peripheral groove facing the array region is a curved surface.

[0012] Optionally, the method further includes: filling insulating material in the dividing trenches and the peripheral trenches to form a shallow trench isolation structure.

[0013] Optionally, a portion of the fourth mask layer covering an end of the initial long strip-shaped pattern has a straight edge.

[0014] To solve the above problems, the technical solution of the present invention also provides a memory, comprising: a substrate, the substrate comprising an array area and a peripheral area surrounding the array area; a plurality of discrete active areas arranged in an array within the array area of ​​the substrate, one end of the discrete active area located at the edge of the array area is connected to the substrate of the peripheral area; and each discrete active area is isolated by a shallow trench isolation structure.

[0015] Optionally, a peripheral shallow trench isolation structure is formed in a peripheral area of ​​the substrate, and the peripheral shallow trench isolation structure is arranged around the array area.

[0016] Optionally, there is a certain distance between the peripheral shallow trench isolation structure and the array area.

[0017] Optionally, a side wall of the peripheral shallow trench isolation structure facing the array region is a curved surface.

[0018] Optionally, the shallow trench isolation structure includes a first shallow trench isolation structure and a second shallow trench isolation structure; the first shallow trench isolation structure is in the shape of a long strip, dividing the array area into a plurality of parallel arranged long strip-shaped continuous active areas, and the second shallow trench isolation structure is in the shape of a block, dividing the long strip-shaped continuous active area into a plurality of discrete active areas.

[0019] Optionally, end surfaces of the first shallow trench isolation structure located on the same side of the array region are flush.

[0020] The method for forming the memory of the present invention can avoid the problem of the discrete active areas at the edge of the array area collapsing after the continuous active area is divided into a number of discrete active areas by connecting the end of the formed continuous active area with the peripheral area during the process of forming the long strip continuous active area, and can also release the stress of the peripheral structure on the discrete active areas located at the edge, thereby improving the reliability of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figures 1 to 7 It is a structural schematic diagram of the formation process of the memory according to a specific embodiment of the present invention. DETAILED DESCRIPTION

[0022] The specific implementation of the memory and the method for forming the memory provided by the present invention will be described in detail below with reference to the accompanying drawings.

[0023] Please refer to Figure 1 , which is a structural schematic diagram of the formation process of a memory according to a specific embodiment of the present invention.

[0024] Please refer to Figure 1 , providing a substrate 100 , wherein the substrate 100 includes an array region 101 and a peripheral region 102 surrounding the array region 101 .

[0025] The array region 101 is used to form an active area array of the memory, while the peripheral region 102 is used to form peripheral devices of the memory, such as a logic control circuit.

[0026] Please refer to Figure 2a and Figure 2b, an unpatterned first mask layer 200 is formed on the substrate 100 and a third mask layer 210 is formed on the unpatterned first mask layer 200, wherein a plurality of parallel long strip-shaped initial long strip-shaped patterns are formed in the third mask layer 210, including a long strip-shaped pattern 201a and a long strip-shaped pattern 201b, wherein the initial long strip-shaped pattern 201 is a shielding pattern, and is used to form a plurality of discrete and parallel long strip-shaped continuous active regions in the array region 101 of the substrate 100. An opening 202 is provided between the initial long strip-shaped patterns 201a and 201b, and the initial long strip-shaped patterns 201a and 201b are separated. Figure 2a A top view diagram is shown. Figure 2b along Figure 2a Schematic cross-sectional view of the secant line AA' Before forming the first mask layer 200, a hard mask layer 101 or other buffer layer may be formed on the surface of the substrate 100 to improve the accuracy of pattern transfer in the subsequent etching process.

[0027] The strip-shaped pattern is formed by a double patterning method. For details, please refer to Figure 3a to Figure 3f , is a structural schematic diagram of a method for forming a first mask layer according to a specific embodiment of the present invention.

[0028] Please refer to Figure 3a and 3b , forming a mask pattern 301 on the substrate 300, Figure 3a is a schematic top view of the mask pattern 301, Figure 3b along Figure 3a Schematic cross-sectional view of the midline BB'. The mask pattern 301 has a long strip pattern and is arranged in parallel. In this specific embodiment, the mask pattern 301 is arranged obliquely to increase the arrangement density of the discrete active regions formed subsequently. In other specific embodiments, the mask pattern 301 can also be arranged horizontally or vertically.

[0029] Please refer to Figure 3c and Figure 3d , a sidewall 302 is formed on the sidewall of the mask pattern 301 , and the sidewall 302 surrounds the sidewall of the mask pattern 301 .

[0030] Please refer to Figure 3e , a first mask material 310 is filled on the surface of the substrate 300 , and the surface of the first mask material 310 is flush with the surface of the mask pattern 301 .

[0031] Please refer to Figure 3f , remove the side wall 302 to form an opening 303 (corresponding to Figure 2a and Figure 2b The mask patterns 301 on both sides of the opening (corresponding to Figure 2a and Figure 2b The initial strip-shaped pattern 201a) and the mask pattern 311 (corresponding to Figure 2a and Figure 2b The initial strip pattern 201b) is used as a strip pattern to define the width and length of the continuous active area subsequently formed in the substrate. Through the above double patterning method, the spacing between adjacent strip patterns can be reduced and the density of the strip patterns can be increased.

[0032] Please refer to Figure 4a and Figure 4b , a patterned fourth mask layer 400 is formed on the patterned third mask layer 210, and the fourth mask layer 400 covers the peripheral area of ​​the third mask layer 210 and covers the ends of the initial long strip patterns 201a and 201b. In this specific embodiment, the portion of the fourth mask layer 400 covering the ends of the initial long strip patterns has a straight edge. Before forming the fourth mask layer 400, it also includes forming a filling layer 410 that fills the opening 202 in the third mask layer 210 and has a flat surface, and forming the fourth mask layer 400 on the surface of the filling layer 410 with a flat surface. The material of the filling layer 410 can be an organic anti-reflection layer, silicon oxide, etc.

[0033] Please refer to Figure 5a and Figure 5b , with the fourth mask layer 400 (please refer to Figure 4a and 4b ) and the third mask layer 210 (please refer to Figure 4a and 4b ) is used as a mask, the first mask layer 200 is etched, and a long strip pattern 502 is formed in the first mask layer 200, and the end of the long strip pattern 502 is connected to the outer area of ​​the first mask layer 200; there is an opening 501 between adjacent long strip patterns 502; then the third mask layer 210 and the fourth mask layer 400 are removed.

[0034] During the process of etching the first mask layer 200, the opening 202 located at the end of the initial continuous active area 201a in the third mask layer 210 is covered by the fourth mask layer 400 and is therefore not transferred into the first mask layer 200, thereby making the ends of all the long strip-shaped graphics 502 formed in the first mask layer 200 connected to the peripheral area.

[0035] Please refer to Figure 6A second mask layer 600 is formed on the first mask layer 200, and a plurality of first patterns 601 are formed in the second mask layer 600. The plurality of first patterns 601 are arranged in an array and overlap with the long strip pattern 502, and are used to form dividing grooves in the substrate 100, thereby dividing the continuous active area into a plurality of discrete discrete active areas.

[0036] In this specific embodiment, the second mask layer 600 also forms a second graphic 602 located on the peripheral area of ​​the substrate and surrounding the long strip graphic 502. There is a certain distance between the second graphic 602 and the first graphic 601 at the edge. The second graphic 602 is used to form a peripheral groove surrounding the array area in the peripheral area of ​​the substrate.

[0037] Figure 6 In the figure, only the first graphic 601 and the second graphic 602 in the second mask layer 600 are shown. The first graphic 601 and the second graphic 602 are both opening graphics, and other areas are shielding graphics (not shown in the figure).

[0038] Since the first pattern 601 is an opening pattern and the strip-shaped pattern 502 is a shielding pattern, after etching the substrate 100 along the first pattern 601, the strip-shaped pattern 502 is used to cut off the continuous active area formed in the substrate 100 corresponding to the continuous active area formed in the substrate 100 to form a dividing groove. In this specific embodiment, the third pattern 602 is also an opening pattern, which is used to form a peripheral groove in the substrate.

[0039] In order to improve storage density, the first patterns 601 are arranged in a staggered manner, so that the discrete active areas formed after segmentation are arranged in a staggered manner to increase the number of active areas.

[0040] The first pattern 601 at the outermost edge is at a certain distance from the end of the long strip pattern 502 to prevent the connection between the end of the continuous active region subsequently formed in the substrate and the peripheral region from being cut off.

[0041] Please refer to Figure 7, using the first mask layer 200 and the second mask layer 600 as masks, etching into the substrate 100 layer by layer, transferring the long strip pattern 502, the opening 501, the first pattern 601 and the second pattern 602 into the substrate 100, forming a split groove and a peripheral groove, splitting the continuous active area into a plurality of discrete and array-arranged discrete active areas 720, and connecting one end of the discrete active area 720 located at the edge to the substrate 100 of the peripheral area 102; and then filling the split groove and the peripheral groove with insulating material to form a shallow trench isolation structure. The discrete active area 720 located at the edge of the array area is connected to the substrate of the peripheral area 102, preventing the discrete active area 720 at the edge from collapsing due to its small size, and can effectively release the stress caused by the isolation structure or device in the peripheral area to the edge of the array area 101, thereby improving the edge problem of the array area.

[0042] Each discrete active area 720 is isolated by a shallow trench isolation structure. In this specific embodiment, the shallow trench isolation structure includes: a first shallow trench isolation structure 711 in the form of a long strip and a second shallow trench isolation structure 712 in the form of a block; the first shallow trench isolation structure 711 divides the array area 101 into a plurality of parallel long strip continuous active areas, and the second shallow trench isolation structure 712 is in the form of a block, dividing the continuous active area into a plurality of discrete active areas 720; the end faces of the first shallow trench isolation structure 711 on the same side of the array area are flush, which can reduce the influence of stress.

[0043] The peripheral shallow trench isolation structure 713 corresponds to the second pattern 602 in the second mask layer 600 (please refer to Figure 6 ); the second shallow trench isolation structure 712 corresponds to the first pattern 601 in the second mask layer 600 (please refer to Figure 6 ); The first shallow trench isolation structure 711 corresponds to the opening 501 in the first mask layer 200 (please refer to Figure 5a ).

[0044] In another specific embodiment, the second pattern 602 in the second mask layer 600 is curved on the side facing the array area, so that the side wall of the formed peripheral shallow trench isolation structure 713 facing the array area is a curved surface, which can increase the total length of the side wall, improve stability, further relieve the stress generated by the peripheral shallow trench isolation structure 713, and reduce the stress impact on the discrete active area 720 located at the edge.

[0045] In the above specific implementation manner, after forming multiple layers of mask layers with different patterns, the substrate is etched to directly form a discrete active area array in the substrate.

[0046] In a specific embodiment of the present invention, another method for forming a memory is also provided.

[0047] The method comprises the following steps: providing a substrate, wherein the substrate comprises an array region and a peripheral region surrounding the array region; forming a plurality of parallel-arranged long strip-shaped continuous active regions in the array region of the substrate, and the ends of the continuous active regions are all connected to the substrate of the peripheral region; dividing the continuous active region into a plurality of independent discrete active regions, and the discrete active regions at the outermost edges are connected to the substrate of the peripheral region.

[0048] By forming a Figure 5a and Figure 5b The first mask layer 200 shown has a strip-shaped pattern 502 and an opening 501 . The substrate 100 is etched using the first mask layer 200 as a mask to form a strip-shaped continuous active region in the substrate 100 .

[0049] Then, after removing the first mask layer 200, a film is formed on the substrate as follows: Figure 6 The second mask layer 600 having the first pattern 601 and the second pattern 602 shown in the figure is used as a mask to etch the substrate 100, and the first pattern 601 and the second pattern 602 are transferred into the substrate, so that the continuous active area in the substrate is divided into a plurality of discrete active areas through dividing grooves, and a peripheral groove is formed in the peripheral area. The side wall of the peripheral groove facing the array area can be a curved surface to reduce the influence of stress and improve stability.

[0050] Finally, insulating material is filled in the dividing trenches and the peripheral trenches to form a shallow trench isolation structure.

[0051] In the memory formation process of this specific implementation, the substrate is etched once each time a mask layer is formed, and an active area array is formed by etching the substrate multiple times.

[0052] The specific implementation of the present invention also provides a memory formed by using the above specific implementation.

[0053] Please refer to Figure 7 , which is a schematic diagram of the structure of a memory according to a specific embodiment of the present invention.

[0054] The memory includes a substrate 100, and the substrate 100 includes an array area 101 and a peripheral area 102 surrounding the array area 101; a plurality of discrete active areas 720 are formed in the array area 101 and arranged in an array, and one end of the discrete active area 720 located at the edge of the array area is connected to the substrate 100 of the peripheral area 102; each discrete active area 720 is isolated by a shallow trench isolation structure.

[0055] The shallow trench isolation structure includes a first shallow trench isolation structure 711 and a second shallow trench isolation structure 712; the first shallow trench isolation structure 711 is in the shape of a long strip, dividing the array area 101 into a plurality of parallel continuous active areas, and the second shallow trench isolation structure 712 is in the shape of a block, dividing the continuous active area into a plurality of discrete active areas 720; the end faces of the first shallow trench isolation structure 711 located on the same side of the array area 101 are flush.

[0056] A peripheral shallow trench isolation structure 713 is formed in the peripheral region 102 of the substrate 100, and the peripheral shallow trench isolation structure 713 is arranged around the array region 101. There is a certain distance between the peripheral shallow trench isolation structure 713 and the array region 101, which serves as an electrical isolation structure between the array region 101 and the peripheral region 102 of the substrate 100.

[0057] In this specific embodiment, the sidewall of the peripheral shallow trench isolation structure 713 facing the array region 101 is a flat surface. In another specific embodiment, the sidewall of the peripheral shallow trench isolation structure 713 facing the array region 101 is a curved surface to reduce the stress effect on the discrete active region 720 located at the edge and improve stability.

[0058] The discrete active area 720 located at the edge of the active area array is connected to the substrate of the peripheral area 102 to prevent the discrete active area 720 at the edge from collapsing due to its small size, and can effectively release the stress caused by the isolation structure or devices in the peripheral area to the edge of the array area 101, thereby improving the edge problem of the array area.

[0059] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A method for forming a memory, characterized in that: include: Providing a substrate, the substrate comprising an array region and a peripheral region surrounding the array region; A first mask layer is formed on the substrate, wherein a plurality of parallel long strip patterns are formed in the first mask layer and are located above the array region, and the ends of each long strip pattern are connected to the first mask layer on the peripheral region of the substrate, so as to form a plurality of parallel long strip continuous active regions in the array region of the substrate, and the ends of the continuous active regions are connected to the substrate in the peripheral region; Forming a second mask layer on the first mask layer, wherein a plurality of first patterns are formed in the second mask layer, wherein the plurality of first patterns are arranged in an array and overlap with the long strip pattern, and are used to form dividing grooves in the substrate to divide the continuous active area into a plurality of discrete active areas; Using the second mask layer and the first mask layer as masks, etching is performed layer by layer to transfer the long strip-shaped pattern and the first pattern into the substrate to form discrete active areas arranged in an array, and one end of each of the discrete active areas located at the edge of the array area is connected to the substrate in the peripheral area.

2. The forming method according to claim 1, characterized in that: The method for forming the long strip-shaped pattern includes: forming a third mask layer on an unpatterned first mask layer, wherein a plurality of discrete and parallel long strip-shaped initial long strip-shaped patterns are formed in the third mask layer; forming a fourth mask layer on the third mask layer, wherein the fourth mask layer covers the peripheral area of ​​the third mask layer and covers the end of the initial long strip-shaped pattern; using the fourth mask layer and the third mask layer as masks, etching the first mask layer to form a long strip-shaped pattern in the first mask layer, wherein the end of the long strip-shaped pattern is connected to the peripheral area of ​​the first mask layer; and removing the third mask layer and the fourth mask layer.

3. The forming method according to claim 1, characterized in that: The second mask layer also has a second pattern formed in the peripheral region of the substrate and surrounding the long strip pattern. The second pattern is used to form a peripheral groove surrounding the array region in the peripheral region of the substrate.

4. The forming method according to claim 3, characterized in that: There is a certain distance between the second figure and the first figure at the outermost edge.

5. The forming method according to claim 3, characterized in that: The side wall of the peripheral groove facing the array region is a curved surface.

6. The forming method according to claim 3, characterized in that: Also includes: Insulating materials are filled in the dividing trenches and the peripheral trenches to form a shallow trench isolation structure.

7. The forming method according to claim 2, characterized in that: The portion of the fourth mask layer covering the end of the initial long strip pattern has a straight edge.

8. A memory, characterized in that: include: A substrate, the substrate comprising an array region and a peripheral region surrounding the array region; A plurality of discrete active regions arranged in an array in an array region of the substrate, wherein the discrete active regions are arranged in a staggered manner, and one end of each of the discrete active regions located at an edge of the array region is connected to the substrate in the peripheral region; Each discrete active area is isolated by a shallow trench isolation structure.

9. The memory according to claim 8, characterized in that: A peripheral shallow trench isolation structure is formed in the peripheral region of the substrate, and the peripheral shallow trench isolation structure is arranged around the array region.

10. The memory according to claim 9, characterized in that: There is a certain distance between the peripheral shallow trench isolation structure and the array area.

11. The memory according to claim 9, characterized in that: The side wall of the peripheral shallow trench isolation structure facing the array region is a curved surface.

12. The memory according to claim 8, characterized in that: The shallow trench isolation structure includes a first shallow trench isolation structure and a second shallow trench isolation structure; the first shallow trench isolation structure is in the shape of a long strip, dividing the array area into a plurality of parallel arranged long strips of continuous active areas, and the second shallow trench isolation structure is in the shape of a block, dividing the long strips of continuous active areas into a plurality of discrete active areas.

13. The memory according to claim 12, characterized in that: End surfaces of the first shallow trench isolation structure located on the same side of the array region are flush.

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