Semiconductor structure and method for manufacturing the same

Abstract

The present invention relates to a semiconductor structure and a method for preparing the same; the steps include: providing a wafer, the wafer having a cutting path, the cutting path having a test pad, a first test structure and a second test structure; the second test structure is located below the first test structure, and the lateral spacing between the second test structure and the first test structure is at least the width of the test pad; forming a protective layer on the wafer, the protective layer at least covering the cutting path; exposing and developing the protective layer, so that the thickness of the protective layer retained above the first test structure is greater than the thickness of the protective layer retained above the second test structure. The method for preparing the semiconductor structure removes and thins the protective layer above the second test structure, which can reduce the amount of the protective layer in the cutting path, and when a saw is used to cut the wafer, the protective layer can be prevented from sticking to the saw, thereby increasing production capacity and saving manufacturing costs.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor device manufacturing, and in particular to a semiconductor structure and a preparation method thereof. Background Art

[0002] During semiconductor wafer manufacturing, cutting paths are involved to separate the chips in the wafer, and after completing the wafer-level front-end process and wafer thinning, wafer cutting (blade sawing) is often performed with a saw. At this time, if there is a large amount of protective layer (e.g., Polyimide) remaining in the cutting path, it is easy for the protective layer to stick to the saw blade during wafer cutting, requiring additional frequency of saw blade maintenance and cleaning, resulting in reduced production capacity and increased manufacturing costs. Summary of the invention

[0003] Based on this, it is necessary to provide a semiconductor structure and a preparation method thereof to address the problem that a large amount of protective layer remains in the cutting path of the existing semiconductor structure technology, and the protective layer will stick to the saw blade when the wafer is cut, requiring an additional increase in the frequency of saw blade maintenance and cleaning, thereby leading to reduced production capacity and increased manufacturing costs.

[0004] In order to achieve the above object, on the one hand, the present invention provides a method for preparing a semiconductor structure, comprising the following steps:

[0005] A wafer is provided, wherein a dicing path is provided in the wafer, wherein a test pad, a first test structure and a second test structure are provided in the dicing path; the second test structure is located below the first test structure, and a lateral spacing between the second test structure and the first test structure is at least equal to a width of the test pad;

[0006] forming a protective layer on the wafer, wherein the protective layer at least covers the dicing line;

[0007] The protective layer is exposed and developed so that the thickness of the protective layer remaining above the first test structure is greater than the thickness of the protective layer remaining above the second test structure.

[0008] The preparation method of the semiconductor structure above removes and thins the protective layer above the second test structure, which can reduce the amount of the protective layer in the cutting path. When using a saw blade to cut the wafer, the protective layer can be prevented from sticking to the saw blade, thereby improving production capacity and saving manufacturing costs.

[0009] In one embodiment, exposing and developing the protective layer comprises the following steps:

[0010] Placing a first photomask above the protective layer, wherein the first photomask forms a first light-transmitting area in an area outside the first test structure in the cutting path;

[0011] Performing a first exposure on the protective layer at a first exposure dose or a first exposure energy based on a first photomask;

[0012] removing the first photomask; placing a second photomask above the protective layer, wherein the second photomask has a second light-transmitting area formed at least in an area corresponding to the test pad;

[0013] The protective layer is exposed for the second time based on the second photomask at a second exposure dose or a second exposure energy; the second exposure dose is a minimum exposure dose at which the protective layer in the exposure area of ​​the second exposure is completely removed after subsequent development, and the second exposure energy is a minimum exposure energy at which the protective layer in the exposure area of ​​the second exposure is completely removed after subsequent development; the second exposure dose is greater than the first exposure dose, and the second exposure energy is greater than the first exposure energy;

[0014] The exposed protective layer is developed; after the development, the thickness of the protective layer retained above the first test structure is greater than the thickness of the protective layer retained above the second test structure.

[0015] In one embodiment, exposing and developing the protective layer comprises the following steps:

[0016] Placing a photomask above the protective layer, wherein the photomask has a plurality of first light-transmitting regions formed in a region corresponding to the cutting path outside the first test structure, and a second light-transmitting region formed in a region of the photomask at least corresponding to the test pad;

[0017] exposing the protective layer based on the mask;

[0018] The exposed protective layer is developed; after the development, the thickness of the protective layer retained above the first test structure is greater than the thickness of the protective layer retained above the second test structure.

[0019] In the above example, the protection layer above the first test structure will not be thinned and removed, which can ensure that the thickness of the protection layer covering the first test structure can meet the test requirements, thereby avoiding the risk of poor test quality.

[0020] In one embodiment, a plurality of first light-transmitting regions are arranged in strips, grids, or randomly.

[0021] In one embodiment, before forming a protective layer on the upper surface of the wafer, the step of forming a passivation layer on the upper surface of the wafer is also included; the protective layer is formed on the upper surface of the passivation layer; after development, the following steps are also included: curing the protective layer; etching to remove the passivation layer and part of the wafer above the test pad to expose the test pad.

[0022] In one embodiment, the thickness of the protection layer retained on the first test structure is 1.5 to 4 times the thickness of the protection layer retained on the second test structure.

[0023] The present invention also provides a semiconductor structure, comprising:

[0024] A wafer, wherein the wafer has a dicing path, and a test pad is formed in the dicing path;

[0025] A first test structure, the first test structure is located in the cutting path;

[0026] A second test structure, the second test structure is located in the cutting path and below the first test structure; a lateral spacing between the second test structure and the first test structure is at least the width of the test pad;

[0027] The protection layer is located above the first test structure and the second test structure, and the thickness of the protection layer above the first test structure is greater than the thickness of the protection layer above the second test structure.

[0028] The thickness of the protective layer above the second test structure in the cutting path in the above-mentioned semiconductor structure is less than the thickness of the protective layer above the first test structure, which can reduce the amount of the protective layer in the cutting path. When using a saw to cut the wafer, the protective layer can be prevented from sticking to the saw, thereby improving production capacity and saving manufacturing costs.

[0029] In one embodiment, the protection layer includes a polyimide layer or a polybenzoxazole layer.

[0030] In one embodiment, the semiconductor structure further includes a passivation layer, and the passivation layer is located on the upper surface of the wafer; and the protection layer is located on the upper surface of the passivation layer.

[0031] In one embodiment, an opening is formed in the protection layer, and the opening exposes the test pad.

[0032] In one embodiment, the thickness of the protection layer above the first test structure is 1.5 to 4 times the thickness of the protection layer above the second test structure.

[0033] In the above example, by not thinning and removing the protection layer above the first test structure in the scribe line, it can be ensured that the thickness of the protection layer covering the first test structure can meet the test requirements, thereby avoiding the risk of poor test quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 A flowchart of a method for preparing a semiconductor packaging structure according to an embodiment of the present invention;

[0035] Figure 2 A schematic diagram of a top view of a structure obtained after providing a wafer in a method for preparing a semiconductor packaging structure in one embodiment of the present invention;

[0036] Figure 3 For along Figure 2 Schematic diagram of the cross-sectional structure along the AA direction;

[0037] Figure 4 It is a schematic diagram of the cross-sectional structure of a structure obtained after a passivation layer is formed on the upper surface of a wafer in a method for preparing a semiconductor packaging structure in one embodiment of the present invention;

[0038] Figure 5 A schematic diagram of a top view of a structure obtained after a protective layer is formed on an upper surface of a passivation layer in a method for preparing a semiconductor packaging structure in one embodiment of the present invention;

[0039] Figure 6 For along Figure 5 Schematic diagram of the cross-sectional structure along the AA direction;

[0040] Figure 7 A schematic top view of a first photomask used in a method for preparing a semiconductor packaging structure in one embodiment of the present invention;

[0041] Figure 8 A schematic top view of a second photomask provided in a method for preparing a semiconductor packaging structure according to an embodiment of the present invention;

[0042] Fig. 9 A schematic diagram of a top view of a structure obtained after double exposure using a first photomask and a second photomask and development in a method for preparing a semiconductor package structure in one embodiment of the present invention;

[0043] Fig.10 For along Fig. 9 Schematic diagram of the cross-sectional structure along the AA direction;

[0044] Fig.11 It is a schematic diagram of the cross-sectional structure of a structure obtained after etching to form an opening 161 in a method for preparing a semiconductor package structure in one embodiment of the present invention;

[0045] Fig.12 The diagram is a top view of a photomask used in a method for preparing a semiconductor packaging structure in another embodiment of the present invention.

[0046] Description of reference numerals:

[0047] 10 Wafer

[0048] 101 Cutting Road

[0049] 102 Chip Area

[0050] 111 Test pad

[0051] 112 First Test Structure

[0052] 113 Second test structure

[0053] 12. Protective layer

[0054] 121 Thinning area

[0055] 122 Thickness area

[0056] 123 Opening area

[0057] 13 First mask

[0058] 131, 151 First light-transmitting area

[0059] 14 Second mask

[0060] 141, 152 Second light transmission area

[0061] 15 Photomask

[0062] 16 Passivation layer

[0063] 161 Opening DETAILED DESCRIPTION

[0064] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0065] It should be noted that when an element is considered to be "connected" to another element, it may be directly connected to another element and integrated therewith, or there may be an intermediate element at the same time. The terms "installed", "one end", "the other end" and similar expressions used herein are for illustrative purposes only.

[0066] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0067] In one embodiment, Figure 1 As shown, the present invention provides a method for preparing a semiconductor structure, comprising the following steps:

[0068] S11: providing a wafer, wherein a dicing path is formed in the wafer, wherein the dicing path has a test pad, a first test structure, and a second test structure; the second test structure is located below the first test structure, and a lateral spacing between the second test structure and the first test structure is at least the width of the pad;

[0069] S12: forming a protective layer on the wafer, wherein the protective layer covers the dicing road;

[0070] S13: exposing and developing the protective layer, so that the thickness of the protective layer remaining above the first test structure is greater than the thickness of the protective layer remaining above the second test structure.

[0071] The preparation method of the above-mentioned semiconductor structure removes and thins the protective layer 12 above the second test structure 113 in the cutting path 101, which can reduce the amount of the protective layer 12 in the cutting path 101. When using a saw blade to cut the wafer, the protective layer 12 can be prevented from sticking to the saw blade, thereby improving production capacity and saving manufacturing costs.

[0072] In one example, if Figure 2 and Figure 3 As shown, the wafer 10 provided in step S11 may include but is not limited to a silicon wafer. The cutting lanes 101 divide the wafer 10 into a plurality of chip regions 102; the number of cutting lanes 101 in the wafer and the number of chip regions 102 isolated by the cutting lanes 101 can be set according to actual needs and are not limited here.

[0073] In one example, a chip (not shown) may be formed in the chip area 102; the first test structure 112 may be used for partial electrical testing (e.g., WAT, wafer acceptance test) and quality testing (e.g., EM, Electro-Migration, electro-migration test or SM, Stress-Migration, stress migration test, etc.).

[0074] In one example, after step S11, the following steps are further included: forming a passivation layer 16 on the upper surface of the wafer 10, such as Figure 4 As shown. The passivation layer 16 covers the cutting road 101 and the chip area 102. The passivation layer 16 may include a single layer structure or a stacked layer structure including multiple material layers. The passivation layer 16 may include but is not limited to at least one of a silicon oxide layer, a silicon nitride layer and a silicon oxynitride layer.

[0075] In one example, if Figure 5 and Figure 6 As shown, the protective layer 12 may be formed on the upper surface of the passivation layer 16 by a spin coating process but is not limited thereto.

[0076] In one example, the protective layer 12 may include any integrated circuit protective layer that can be exposed, developed and removed, such as a photosensitive material layer; specifically, the protective layer 12 may include but is not limited to a polyimide layer or a polybenzoxazole (PBO) layer.

[0077] In one example, the protective layer 12 may include a thinning area 121, a thick area 122 and an opening area 123, wherein the thick area 122 is the area of ​​the protective layer 12 corresponding to the first test structure 112, the thinning area 121 is at least the area of ​​the protective layer 12 corresponding to the second test structure 113, and the opening area 123 is the area of ​​the protective layer 12 corresponding to the test pad 111 and between the thinning area 121 and the edge of the cutting path 101.

[0078] In an optional example, step S13 may include the following steps:

[0079] S131: placing a first photomask 13 above the protective layer 12, wherein the first photomask 13 forms a first light-transmitting region 131 in a region corresponding to the first test structure 112 in the cutting path 101, that is, the first photomask 13 forms a first light-transmitting region 131 in a region corresponding to at least the thinning region 121; Figure 7 As shown; after the first mask 13 is placed on the protective layer 12, the orthographic projection of the mask 13 on the upper surface of the protective layer 12 can completely cover the upper surface of the mask 13;

[0080] S132: performing a first exposure on the protective layer 12 at a first exposure dose or a first exposure energy based on the first mask 13;

[0081] S133: remove the first photomask 13; place the second photomask 14 above the protective layer 12, wherein the second photomask 14 has a second light-transmitting area 141 formed in at least the area corresponding to the test pad 111, that is, the second photomask 14 has a second light-transmitting area 141 formed in the area corresponding to the opening area 123; the second photomask 14 is as shown in FIG. Figure 8 As shown; after the second mask 14 is placed above the protective layer 12, the orthographic projection of the second mask 14 on the upper surface of the protective layer 12 can completely cover the upper surface of the protective layer 12;

[0082] S134: performing a second exposure on the protective layer 12 based on the second photomask 14 at a second exposure dose or a second exposure energy; the second exposure dose is a minimum exposure dose for completely removing the protective layer 12 in the exposure area of ​​the second exposure after subsequent development, and the second exposure energy is a minimum exposure energy for completely removing the protective layer 12 in the exposure area of ​​the second exposure after subsequent development; the second exposure dose is greater than the first exposure dose, and the second exposure energy is greater than the first exposure energy;

[0083] S135 : developing the exposed protective layer 12 ; after the development, the thickness of the protective layer 12 retained in the thinned area 121 is less than the thickness of the protective layer 12 .

[0084] Based on the first exposure performed by the first photomask 13 at the first exposure dose or the first exposure energy, since the first exposure dose or the first exposure energy is relatively small, the exposure depth of the first light-transmitting area 131 is less than the thickness of the protective layer 12, that is, only a part of the depth of the protective layer 12 in the exposed area after the first exposure is removed during development; based on the second photomask 14 at the second exposure dose or the second exposure energy, since the second exposure dose or the second exposure energy is relatively large, the protective layer 12 in the exposed area after the second exposure can be completely removed during the development process, that is, the protective layer 12 in the opening area 123 can be completely removed after development. In addition, since the protective layer 12 in the thick area 122 is blocked and not exposed during the two exposure processes, the thickness of the protective layer 12 in the thick area 122 after development does not change from that before exposure and development.

[0085] In the above example, by setting a thick area 122 and an opening area 123 in the protective layer 12 within the cutting road 101, during the photolithography development process, the protective layer 12 in the thick area 122 will not be thinned and removed, that is, the protective layer 12 above the first test structure 112 will not be thinned and removed, which can ensure that the thickness of the protective layer 12 covering the first test structure 112 can meet the test needs, so as to avoid the risk of poor test quality.

[0086] It should be noted that the first light-transmitting area 131 corresponds to the opening area 123 in addition to the thinned area 121 .

[0087] In one example, a top view of the structure obtained after development is shown in FIG. Fig. 9 The local cross-sectional structure diagram is shown in Fig.10 shown.

[0088] In one example, the protective layer 12 also covers the chip area 102; the thickness of the protective layer 12 retained above the first test structure 112 is 1.5 to 4 times the thickness of the protective layer 12 retained above the second test structure 113, that is, the thickness of the protective layer 12 in the thick area 122 is the same as the thickness of the protective layer 12 covering the chip area 102, and is 1.5 to 4 times the thickness of the protective layer 12 in the thinned area 121.

[0089] In one example, step S13 further includes the following steps:

[0090] S14: curing the protective layer 12; specifically, the protective layer 12 may be cured by, but not limited to, a baking technique;

[0091] S15: etching and removing the passivation layer 16 and a portion of the wafer 10 in the area corresponding to the test pad 111 to form an opening 161 exposing the test pad 111, such as Fig.11 Specifically, the passivation layer 16 and a portion of the wafer 10 in the area corresponding to the test pad 111 may be etched away by, but not limited to, an etching process.

[0092] In another alternative example, Fig.12 As shown, step S13 may also include the following steps:

[0093] S131: placing the photomask 15 above the protective layer 12, wherein the photomask 15 forms a plurality of first light-transmitting regions 151 in the region outside the first test structure 112 in the cutting path 101, and the photomask 15 forms a second light-transmitting region 152 in at least the region corresponding to the test pad 111, that is, the photomask 15 forms a plurality of first light-transmitting regions 151 in the region corresponding to the thinning region 121, and the photomask 15 further forms a second light-transmitting region 152 in the region corresponding to the opening region 123; after the photomask 15 is placed above the protective layer 12, the orthographic projection of the photomask 15 on the upper surface of the protective layer 12 can completely cover the upper surface of the protective layer 12;

[0094] S132: exposing the protective layer 12 based on the mask 15;

[0095] S133: developing the exposed protective layer 12; after development, the thickness of the protective layer 12 retained above the first test structure 112 is greater than the thickness of the protective layer 12 retained above the second test structure 113, that is, the thickness of the protective layer 12 retained in the thinned area 121 is less than the thickness of the protective layer 12.

[0096] Since the size of the first light-transmitting area 151 is very small, during the exposure process, due to the diffraction of the exposure light and other factors, the depth of the protective layer 12 exposed in the first light-transmitting area 151 is smaller than the depth of the protective layer 12 itself. During the development process, only a partial depth of the protective layer 12 in the exposure area of ​​the first light-transmitting area 151 is removed.

[0097] In one example, a plurality of first light-transmitting regions 131 may be arranged in strips, in a cross shape, or randomly distributed; specifically, the irregular arrangement of the plurality of first light-transmitting regions 131 may be that the first light-transmitting regions 131 have the same shape, but the plurality of first light-transmitting regions 131 are randomly arranged; or the first light-transmitting regions 131 may have different shapes, and the plurality of first light-transmitting regions 131 are randomly arranged, and so on.

[0098] In another optional embodiment, please continue to refer to Figures 2 to 12The present invention also provides a semiconductor structure, which includes: a wafer 10, wherein the wafer 10 has a cutting path 101, and wherein the cutting path 101 has a test pad 111; a first test structure 112, wherein the first test structure 112 is located within the cutting path 101; a second test structure 113, wherein the second test structure 113 is located within the cutting path 101 and below the first test structure 112, wherein a lateral spacing between the second test structure 113 and the first test structure 112 is at least the width of the test pad 111; and a protective layer 12, wherein the protective layer 12 is located on the first test structure 112 and the second test structure 113, wherein a thickness of the protective layer 12 above the first test structure 112 is greater than a thickness of the protective layer 12 above the second test structure 113.

[0099] By removing and thinning the protective layer 12 above the second test structure 113 in the cutting path 101 in the above-mentioned semiconductor structure, the amount of the protective layer 12 in the cutting path 101 can be reduced. When using a saw blade to cut the wafer, the protective layer can be prevented from sticking to the saw blade, thereby improving production capacity and saving manufacturing costs.

[0100] In one example, if Figure 2 and Figure 3 As shown, the wafer 10 provided in step S11 may include but is not limited to a silicon wafer. The cutting lanes 101 divide the wafer 10 into a plurality of chip regions 102; the number of cutting lanes 101 in the wafer and the number of chip regions 102 isolated by the cutting lanes 101 can be set according to actual needs and are not limited here.

[0101] In one example, a chip (not shown) may be formed in the chip area 102; the first test structure 112 may be used for partial electrical testing (e.g., WAT, wafer acceptance test) and quality testing (e.g., EM, Electro-Migration, electro-migration test or SM, Stress-Migration, stress migration test, etc.).

[0102] In one example, the protective layer 12 may include any integrated circuit protective layer that can be exposed, developed and removed, such as a photosensitive material layer; specifically, the protective layer 12 may include but is not limited to a polyimide layer or a polybenzoxazole (PBO) layer.

[0103] In one example, the protective layer 12 may include a thinning area 121, a thick area 122 and an opening area 123, wherein the thick area 122 is the area of ​​the protective layer 12 corresponding to the first test structure 112, the thinning area 121 is at least the area of ​​the protective layer 12 corresponding to the second test structure 113, and the opening area 123 is the area of ​​the protective layer 12 corresponding to the test pad 111 and between the thinning area 121 and the edge of the cutting path 101.

[0104] In one example, the semiconductor structure further includes a passivation layer 16, which is located on the upper surface of the wafer 10; the protective layer 12 is located on the upper surface of the passivation layer 16. The passivation layer 16 covers the cutting road 101 and the chip area 102. The passivation layer 16 may include a single-layer structure or a stacked structure including multiple material layers. The passivation layer 16 may include but is not limited to at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

[0105] In one example, an opening 161 is further formed in the protection layer 12 ; the opening 161 penetrates the protection layer 12 and the passivation layer 16 and extends into the wafer 10 to expose the test pad 111 .

[0106] In one example, the thickness of the protective layer 12 above the first test structure 112 is 1.5 to 4 times the thickness of the protective layer 12 above the second test structure 113, that is, the thickness of the protective layer 12 in the thick area 122 is the same as the thickness of the protective layer 12 covering the chip area 102, and is 1.5 to 4 times the thickness of the protective layer 12 in the thinned area 121.

[0107] In the above example, the thickness of the protective layer 12 above the first test structure 112 is the same as the thickness of the protective layer 12 in the chip area 102, that is, the thickness of the protective layer 12 in the thick area 122 is the same as the thickness of the protective layer 12 covering the chip area 102, which can ensure that the thickness of the protective layer 12 covering the first test structure 112 can meet the test needs to avoid the risk of poor test quality.

[0108] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0109] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: The steps include: A wafer is provided, wherein a scribe line is provided in the wafer, wherein a test pad, a first test structure, and a second test structure are provided in the scribe line; a plane where the second test structure is located is located below a plane where the first test structure is located, the second test structure is offset relative to the first test structure along an extension direction of the scribe line, and a spacing between the second test structure and the first test structure along an extension direction of the scribe line is at least equal to a width of the test pad; forming a protective layer on the wafer, wherein the protective layer at least covers the dicing road; The protective layer is exposed and developed so that a thickness of the protective layer remaining above the first test structure is greater than a thickness of the protective layer remaining above the second test structure.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The exposure and development of the protective layer comprises the following steps: placing a first photomask above the protective layer, wherein the first photomask forms a first light-transmitting area in an area outside the first test structure in the cutting path; Performing a first exposure on the protective layer at a first exposure dose or a first exposure energy based on the first photomask; removing the first photomask; placing a second photomask above the protective layer, wherein the second photomask has a second light-transmitting area formed at least in an area corresponding to the test pad; exposing the protective layer for a second time at a second exposure dose or a second exposure energy based on the second photomask; The second exposure dose is the minimum exposure dose at which the protective layer in the exposure area of ​​the second exposure is completely removed after subsequent development, and the second exposure energy is the minimum exposure energy at which the protective layer in the exposure area of ​​the second exposure is completely removed after subsequent development; the second exposure dose is greater than the first exposure dose, and the second exposure energy is greater than the first exposure energy; developing the exposed protective layer; After development, the thickness of the protective layer remaining on the first test structure is greater than the thickness of the protective layer remaining on the second test structure.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that: The exposure and development of the protective layer comprises the following steps: Placing a photomask above the protective layer, wherein the photomask has a plurality of first light-transmitting regions formed in a region corresponding to the cutting path outside the first test structure, and the photomask has a second light-transmitting region formed in a region at least corresponding to the test pad; exposing the protective layer based on the photomask; developing the exposed protective layer; After development, the thickness of the protective layer remaining on the first test structure is greater than the thickness of the protective layer remaining on the second test structure.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that: A plurality of the first light-transmitting areas are arranged in strips, grids or irregularly.

5. The method for preparing a semiconductor structure according to claim 1, characterized in that: Before forming the protective layer on the upper surface of the wafer, the method further includes forming a passivation layer on the upper surface of the wafer; the protective layer is formed on the upper surface of the passivation layer; and after developing, the method further includes the following steps: curing the protective layer; The passivation layer and a portion of the wafer above the test pad are removed by etching to expose the test pad.

6. The method for preparing a semiconductor structure according to any one of claims 1 to 5, characterized in that: The thickness of the protection layer retained above the first test structure is 1.5 to 4 times the thickness of the protection layer retained above the second test structure.

7. A semiconductor structure, characterized in that: include: A wafer, wherein the wafer has a dicing path, and a test pad is provided in the dicing path; a first test structure, the first test structure being located within the dicing street; a second test structure, the second test structure is located in the cutting path, and the plane where the second test structure is located is located below the plane where the first test structure is located; the second test structure is offset relative to the first test structure along the extension direction of the cutting path, and the spacing between the second test structure and the first test structure along the extension direction of the cutting path is at least the width of the test pad; A protection layer is located above the first test structure and the second test structure, and a thickness of the protection layer above the first test structure is greater than a thickness of the protection layer above the second test structure.

8. The semiconductor structure according to claim 7, characterized in that: The protective layer includes a polyimide layer or a polybenzoxazole layer.

9. The semiconductor structure according to claim 7, characterized in that: The semiconductor structure further includes a passivation layer, which is located on the upper surface of the wafer; and the protection layer is located on the upper surface of the passivation layer.

10. The semiconductor structure according to any one of claims 7 to 9, characterized in that: An opening is formed in the protection layer, and the opening exposes the test pad.

11. The semiconductor structure according to claim 10, characterized in that: The thickness of the protection layer above the first test structure is 1.5 to 4 times the thickness of the protection layer above the second test structure.

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