Semiconductor Structure and Processing

Abstract

A semiconductor structure is provided, comprising a semiconductor fin portion (14P) having an end wall (15W) and extending upward from a substrate (10). A gate structure (16) spans a portion of the semiconductor fin portion (14P). A first set of gate spacers (24P / 50P) is located on opposite sidewall surfaces of the gate structure (16L / 16R); and a second set of gate spacers (32P) is located on the sidewalls of the first set of gate spacers (24P / 50P). One gate spacer of the second set of gate spacers (32P) has a lower portion that directly contacts the end wall (15W) of the semiconductor fin portion (14P).

Description

[0001] This application is a divisional application of an application filed on May 6, 2016, with application number 201680029745.8 and invention name “Semiconductor Structure and Processing”. Technical Field

[0002] The present application relates to a semiconductor structure including a semiconductor fin and a method for forming the same. Embodiments of the present invention relate to a semiconductor structure including a semiconductor fin tip (ie, end portion) and a method for forming the same. The semiconductor fin tip is tucked into a gate structure in a self-aligned manner. Background Art

[0003] For more than three decades, the continued miniaturization of metal-oxide-semiconductor field-effect transistors (MOSFETs) has driven the global semiconductor industry. Various disruptions to continued scaling have been predicted for decades, and despite numerous challenges, the history of innovation has sustained Moore's Law. However, today, there are growing signs that MOSFETs are beginning to reach traditional scaling limits. As further scaling increases the difficulty of improving MOSFETs, and therefore complementary metal-oxide-semiconductor (CMOS) performance, further methods for improving performance beyond scaling have become crucial.

[0004] The use of non-planar semiconductor devices, such as semiconductor fin field-effect transistors (FinFETs), is the next step in the evolution of CMOS devices. FinFETs are non-planar semiconductor devices that include at least one semiconductor fin protruding from the surface of a substrate. FinFETs can increase the on-state current per unit area compared to planar field-effect transistors.

[0005] In prior art processes, semiconductor fins are first provided and then cut using a patterning process. A gate structure is then formed across each cut semiconductor fin, and gate spacers are thereafter formed. In such a process, the semiconductor fin tip (i.e., the end of the cut semiconductor fin) is tucked under one of the gate structures, and there is typically a gate spacer that does not physically tuck the semiconductor fin tip, and any error in the relative positioning of the gate to the fin tip may result in a gate spacer that does not physically tuck the semiconductor fin tip. In such a case, and during formation of the source / drain regions by epitaxial growth, “poor quality epitaxial semiconductor material portions” may be formed from the non-tucked semiconductor fin tips. This problem becomes increasingly problematic as the critical dimensions (CDs) of the gate structure and gate spacing become smaller.

[0006] In addition to the above, prior art processes of folding semiconductor fins under gate structures may create a free surface that relaxes a pre-stressed substrate and thus loosens mobility-enhanced surfaces.

[0007] In view of the above-mentioned problems of the prior art in which the tip of the semiconductor fin is retracted under the gate structure, a new method is needed to be provided, which can retract the tip of the semiconductor fin under the gate structure while avoiding or reducing the problems associated with the prior art. Summary of the Invention

[0008] In one aspect of the present application, a semiconductor structure is provided. In one embodiment of the present application, the semiconductor structure includes a semiconductor fin portion having an end wall and extending upward from a substrate. A gate structure spans a portion of the semiconductor fin portion. A first set of gate spacers (i.e., inner gate spacers) is located on opposing sidewall surfaces of the gate structure; and a second set of gate spacers (i.e., outer gate spacers) is located on the sidewalls of the first gate spacers. One of the gate spacers of the second set of gate spacers has a lower portion that directly contacts the end wall of the semiconductor fin portion.

[0009] In another aspect of the present application, a method for forming a semiconductor structure is provided. In one embodiment, the method may include forming a gate structure spanning a semiconductor fin. Next, a dielectric material is formed on the semiconductor fin and at least on the sidewalls of the gate structure, and thereafter a patterned material stack having an opening is formed on the dielectric material. The semiconductor fin is then cut using the patterned material stack and the portion of the dielectric material within the opening as an etch mask to provide a semiconductor fin portion containing the gate structure and having an exposed end wall. Gate spacers are then formed, wherein one gate spacer has a lower portion that directly contacts the exposed end wall of the semiconductor fin portion.

[0010] In another embodiment, the method may include forming a gate structure that spans a portion of the semiconductor fin. Next, a first set of gate spacers is formed on opposite sidewalls of the gate structure and spans another portion of the semiconductor fin, and thereafter a sacrificial dielectric liner is formed over the first set of gate spacers and the gate structure and spans the remaining portion of the semiconductor fin. A patterned material stack having an opening is formed over the sacrificial dielectric liner. The semiconductor fin is then cut using the patterned material stack, a portion of the sacrificial dielectric liner within the opening, and one of the first set of gate spacers as an etch mask to provide a semiconductor fin portion containing the gate structure and having an end wall. A side etch is then performed to pull the end wall of the semiconductor fin portion back below one of the first set of gate spacers within the opening or vertically align with the side wall of the one of the first set of gate spacers within the opening. Next, a second set of gate spacers is formed, wherein one of the gate spacers of the second set of gate spacers contains a lower portion that directly contacts the exposed end wall of the semiconductor fin portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Embodiment(s) of the present invention will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0012] Figure 1A is a top view of an exemplary semiconductor structure after semiconductor fins are formed on a surface of a substrate according to an embodiment of the present application.

[0013] Figure 1B is an exemplary semiconductor structure along Figure 1A A vertical cross-sectional view of the vertical plane BB.

[0014] Figure 2A yes Figure 1A A top view of an exemplary semiconductor structure after forming a gate structure spanning different portions of a semiconductor fin.

[0015] Figure 2B is an exemplary semiconductor structure along Figure 2A A vertical cross-sectional view of the vertical plane BB.

[0016] Figure 3 yes Figures 2A-2B A cross-sectional view of an exemplary semiconductor structure after forming a dielectric material liner.

[0017] Figure 4 yes Figure 3 A cross-sectional view of an exemplary semiconductor structure after forming a pattern material stack.

[0018] Figure 5 yes Figure 4 A cross-sectional view of the exemplary semiconductor structure after cutting the semiconductor fin using a portion of the patterned material stack and the dielectric material liner as an etch mask.

[0019] Figure 6 yes Figure 5 Cross-sectional view of an exemplary semiconductor structure after removal of the patterned material stack.

[0020] Figure 7 yes Figure 6 Cross-sectional view of an exemplary semiconductor structure after gate spacer deposition and etching.

[0021] Figure 8 According to another embodiment of the present application Figure 2B A cross-sectional view of an exemplary semiconductor structure after forming a first set of gate spacers, etching, and depositing a sacrificial dielectric liner.

[0022] Figure 9 yes Figure 8 Cross-sectional view of an exemplary semiconductor structure after forming a patterned material stack and performing a punch-through etch of a sacrificial dielectric liner.

[0023] Figure 10 yes Figure 9 A cross-sectional view of the exemplary semiconductor structure after cutting the semiconductor fin using the patterned material stack, one gate spacer of the first set of gate spacers, and the remaining portion of the sacrificial dielectric liner as an etch mask.

[0024] Figure 11 yes Figure 10 A cross-sectional view of an exemplary semiconductor structure after side etching is performed to pull back an end wall of each cut semiconductor fin.

[0025] Figure 12 yes Figure 11 A cross-sectional view of an exemplary semiconductor structure after removing the remaining portion of the patterned material stack and the sacrificial dielectric liner.

[0026] Figure 13 yes Figure 12 A cross-sectional view of the exemplary semiconductor structure after forming a second set of gate spacers. DETAILED DESCRIPTION

[0027] In the following description, it should be noted that the drawings are for illustration purposes only and are not drawn to scale. It should also be noted that similar and corresponding elements are denoted by the same reference numerals.

[0028] In the following description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps, and techniques, in order to provide an understanding of the various embodiments of the present application. However, one of ordinary skill in the art will appreciate that the various embodiments of the present application can be practiced without these specific details. In other cases, well-known structures or processing steps are not described in detail to avoid obscuring the present application.

[0029] Now refer to Figures 1A-1B , various views of an exemplary semiconductor structure after forming semiconductor fins 14P on a surface of a substrate according to an embodiment of the present application are shown. Although a single semiconductor fin 14P is described and shown, the present application contemplates embodiments in which multiple semiconductor fins 14P may be formed on different portions of the substrate. In such embodiments, each semiconductor fin is oriented parallel to each other.

[0030] In one embodiment of the present application, and as shown, the substrate comprises, from bottom to top, a handle substrate 10 and an insulator layer 12. In another embodiment (not shown), the substrate comprises the remainder of a bulk semiconductor substrate. When used in conjunction with the phrase "semiconductor substrate," the term "bulk" indicates that the entire substrate is composed of at least one semiconductor material.

[0031] Figures 1A-1BThe exemplary semiconductor structure shown can be formed by first providing a bulk semiconductor substrate or a semiconductor-on-insulator (SOI) substrate. When a bulk semiconductor substrate is used in the present application, the at least one semiconductor material providing the bulk semiconductor substrate may include, but is not limited to, Si, Ge, SiGe, SiC, SiGeC, III / V compound semiconductors, such as InAs, InP, InAsP and GaAs, and II / VI compound semiconductor materials. In such an embodiment, the uppermost semiconductor material layer portion of the bulk semiconductor substrate may be used as each semiconductor fin 14P, while the remaining portion of the bulk semiconductor substrate may be used as a substrate. In some embodiments of the present application, the bulk semiconductor substrate may be a single crystalline semiconductor material. In other embodiments of the present application, the bulk semiconductor substrate may be a polycrystalline semiconductor material or an amorphous semiconductor material. The crystal orientation of the bulk semiconductor substrate may be {100}, {110} or {111}. Other crystal orientations other than those specifically mentioned may also be used in the present application.

[0032] When an SOI substrate is used, the SOI substrate comprises, from bottom to top, a handle substrate 10, an insulator layer 12, and an uppermost semiconductor layer. The uppermost semiconductor layer of the SOI substrate will provide Figures 1A-1B The semiconductor fins 14P of the structure shown. In some embodiments of the present application, the handle substrate 10 and the topmost semiconductor layer of the SOI substrate may include the same semiconductor material. In other embodiments of the present application, the handle substrate 10 and the topmost semiconductor layer of the SOI substrate may include different semiconductor materials. The (one or more) semiconductor materials that can be used as the handle substrate 10 and the topmost semiconductor layer include one of the semiconductor materials described above for the bulk semiconductor substrate. In one embodiment, the handle substrate 10 and the topmost semiconductor layer of the SOI substrate both include silicon. In some embodiments, the handle substrate 10 is a non-semiconductor material including, for example, a dielectric material and / or a conductive material.

[0033] The handle substrate 10 and the topmost semiconductor layer of the SOI substrate can have the same or different crystal orientation as any of the bulk semiconductor substrates described above. The handle substrate 10 and / or the topmost semiconductor layer of the SOI substrate can be a single crystal semiconductor material, a polycrystalline material, or an amorphous material. Typically, at least the topmost semiconductor layer of the SOI substrate is a single crystal semiconductor material. The insulator layer 12 of the SOI substrate can be a crystalline or amorphous oxide or nitride. In one embodiment, the insulator layer 12 is an oxide, such as silicon dioxide.

[0034] The SOI substrate can be formed using standard processes including, for example, SIMOX (separation by ion implantation of oxygen) or layer transfer. When a layer transfer process is used, an optional thinning step can be performed after the two semiconductor wafers are bonded. The optional thinning step reduces the thickness of the semiconductor layer to a layer of a more desired thickness.

[0035] The thickness of the top semiconductor layer of the SOI substrate is typically 10 nm to 100 nm, but other thicknesses less than or greater than the above thickness ranges can also be used for the thickness of the top semiconductor layer of the SOI. The insulator layer 12 of the SOI substrate typically has a thickness of 1 nm to 200 nm, but other thicknesses less than or greater than the above thickness ranges of the insulator layer 12 of the SOI substrate can be used. The thickness of the handle substrate 10 of the SOI substrate is not critical for this application.

[0036] In some embodiments of the present application, a hard mask layer (not shown) may be formed on the uppermost surface of a bulk semiconductor substrate or an SOI substrate. The hard mask layer that may be used is a continuous layer covering the uppermost surface of a bulk semiconductor substrate or an SOI substrate. The hard mask layer that may be used in the present application may comprise a semiconductor oxide, a semiconductor nitride and / or a semiconductor oxynitride. In one embodiment, the hard mask material that may be used to provide the hard mask layer may be composed of silicon dioxide. In another embodiment, the hard mask material that may be used to provide the hard mask layer may be composed of silicon nitride. In another embodiment, the hard mask material that may be used to provide the hard mask layer may be a stack of silicon dioxide and silicon nitride in any order.

[0037] In some embodiments of the present application, the hard mask material that can be used to provide the hard mask layer can be formed by a deposition process such as chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD). In other embodiments, the hard mask material that can be used to provide the hard mask layer can be formed by a thermal treatment such as thermal oxidation and / or thermal nitridation. In other embodiments, the hard mask material that can be used to provide the hard mask layer can be formed by a combination of a deposition process and a thermal treatment. The thickness of the hard mask material that can be used to provide the hard mask layer can be in the range of 50nm to 50nm, but thicknesses less than or greater than the above thickness ranges can be used for the hard mask layer.

[0038] Next, the bulk semiconductor substrate or SOI substrate, with or without a hard mask layer, may be patterned to provide Figures 1A-1BThe semiconductor fin 14P shown. In one embodiment, the patterning process for defining the semiconductor fin 14P may include a sidewall image transfer (SIT) process. The SIT process includes forming a continuous mandrel material layer (not shown) on the uppermost surface of a hard mask layer, a bulk semiconductor substrate, or an SOI substrate. The continuous mandrel material layer (not shown) may include any material (semiconductor, dielectric, conductor, or organic) that can be selectively removed from the structure during a subsequent etching process. In one embodiment, the continuous mandrel material layer (not shown) may be composed of amorphous silicon, amorphous carbon, or polycrystalline silicon. In another embodiment, the continuous mandrel material layer (not shown) may be composed of a metal such as Al, W, or Cu. The continuous mandrel material layer (not shown) may be formed, for example, by chemical vapor deposition or plasma enhanced chemical vapor deposition. The thickness of the continuous mandrel material layer (not shown) may be 50 nm to 300 nm, but smaller and larger thicknesses may also be used. After the continuous mandrel material layer (not shown) is deposited, the continuous mandrel material layer (not shown) may be patterned by photolithography and etching to form a plurality of mandrel structures (also not shown).

[0039] SIT continues by forming a dielectric spacer on each sidewall of each mandrel structure. The dielectric spacers can be formed by depositing a dielectric spacer material and then etching the deposited dielectric spacer material. The dielectric spacer material can include any dielectric spacer material, such as silicon dioxide, silicon nitride, or a dielectric metal oxide. Examples of deposition processes that can be used to provide the dielectric spacer material include, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD). Examples of etches that can be used to provide the dielectric spacers include any etching process, such as reactive ion etching. Because the dielectric spacers are used as an etch mask in the SIT process, a dielectric spacer can be used.

[0040] The width of each dielectric spacer determines the width of each semiconductor fin 14P.

[0041] After forming the dielectric spacers, the SIT process continues by removing each mandrel structure. Each mandrel structure can be removed by an etching process that selectively removes the mandrel material. After the mandrel structures are removed, the SIT process continues by transferring the pattern provided by the dielectric spacers to the semiconductor material that provides the semiconductor fins 14P. The pattern transfer can be achieved by an etching process. Examples of etching processes that can be used to transfer the pattern can include dry etching (i.e., reactive ion etching, plasma etching, ion beam etching, or laser ablation) and / or chemical wet etching processes. In one example, the etching process for transferring the pattern can include one or more reactive ion etching steps. After the pattern transfer is complete, the SIT process is terminated by removing the dielectric spacers from the structure. Each dielectric spacer can be removed by etching or planarization.

[0042] In some embodiments, semiconductor fins may be defined using photolithography and etching. Photolithography includes depositing a photoresist material (not shown) over a bulk semiconductor substrate or SOI substrate, patterning the photoresist material by exposing the photoresist material to a desired illumination pattern, and developing the exposed photoresist material using a conventional resist developer. Etching may include dry etching (i.e., reactive ion etching, ion beam etching, plasma etching, or laser ablation) or a chemical wet etching process. After forming the semiconductor fins 14P, the patterned photoresist material may be removed using a resist stripping process (e.g., ashing).

[0043] In some embodiments and after formation of semiconductor fins 14P, the hard mask material may be removed from over semiconductor fins 14P by a planarization process or by etching. In other embodiments (not shown), the hard mask material may remain over each semiconductor fin 14P that is formed.

[0044] As used herein, a "semiconductor fin" refers to a continuous semiconductor structure extending upward from the surface of a substrate. In one embodiment, the substrate comprises an insulator layer 12 and a handle substrate 10. In other embodiments, the substrate is the remainder of a bulk semiconductor substrate. Each fin structure is formed to include a pair of vertical sidewalls that are parallel to each other. As used herein, a surface is considered "vertical" if there is no deviation from a vertical plane from which the surface deviates by more than three times the root mean square roughness of the surface.

[0045] Now refer to Figures 2A-2B , which shows Figures 1A-1BVarious views of an exemplary semiconductor structure after forming gate structures 16L, 16R that span different portions of semiconductor fin 14P. The term "spanning" indicates that each gate structure 16L, 16R is formed across semiconductor fin 14P such that a first portion of each gate structure 16L, 16R exists on one side of semiconductor fin 14P and a second portion of each gate structure 16L, 16R exists on the other side of semiconductor fin 14P. Portions of each gate structure 16L, 16R also reside on exposed portions of the substrate (in the illustrated embodiment, gate structures 16L, 16R include portions that reside on insulator layer 12).

[0046] In some embodiments of the present application, as shown in the figure, the gate structures 16L and 16R are functional gate structures. A "functional gate structure" refers to a permanent gate structure used to control the output current of a semiconductor device (i.e., the flow of carriers in the channel) through an electric field or a magnetic field. Each functional gate structure 16L and 16R is formed to include a gate material stack consisting of a gate dielectric portion 18L and 18R, a gate conductor portion 20L and 20R, and a gate cap portion (not shown) from bottom to top. In some embodiments, the gate cap portion can be omitted.

[0047] Each gate dielectric portion 18L, 18R includes a gate dielectric material. The gate dielectric material providing each gate dielectric portion 18L, 18R may be an oxide, a nitride, and / or an oxynitride. In one example, the gate dielectric material providing each gate dielectric portion 18L, 18R may be a high-k material having a dielectric constant greater than that of silicon dioxide. Exemplary high-k dielectric materials include HfO2, ZrO2, La2O3, Al2O3, TiO2, SrTiO3, LaAlO3, Y2O3, HfOxNy, ZrOxNy, La2OxNy, Al2OxNy, TiOxNy, SrTiOxNy, LaAlOxNy, Y2OxNy, SiON, SiNx, silicates thereof, and alloys thereof. Each value of x is independently 0.5 to 3, and each value of y is independently 0 to 2. In some embodiments, a multi-layer gate dielectric structure including different gate dielectric materials (eg, silicon dioxide) and a high-k gate dielectric may be formed and used as each gate dielectric portion 18L, 18R.

[0048] The gate dielectric material used to provide each gate dielectric portion 18L, 18R can be formed by any deposition process, including, for example, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), sputtering, or atomic layer deposition. In some embodiments, a thermal process including, for example, thermal oxidation and / or thermal nitridation can be used to form the gate dielectric material of each gate dielectric portion 18, 18R. In some embodiments, each gate dielectric portion 18L, 18R comprises the same gate dielectric material. In other embodiments, gate dielectric portion 18L can comprise a first gate dielectric material, while gate dielectric portion 18R can comprise a second gate dielectric material having a different composition than the first gate dielectric material. When different gate dielectric materials are used for gate dielectric portions 18L, 18R, a block mask technique can be used. In one embodiment of the present application, the thickness of the gate dielectric material used to provide each gate dielectric portion 18L, 18R can be in the range of 1 nm to 10 nm. Other thicknesses less than or greater than the aforementioned thickness ranges can also be used for the gate dielectric material.

[0049] Each gate conductor portion 20L, 20R comprises a gate conductor material. The gate conductor material used to provide each gate conductor portion 20L, 20R can include any conductive material, such as doped polysilicon, an elemental metal (e.g., tungsten, titanium, tantalum, aluminum, nickel, ruthenium, palladium, and platinum), an alloy of at least two elemental metals, an elemental metal nitride (e.g., tungsten nitride, aluminum nitride, and titanium nitride), an elemental metal silicide (e.g., tungsten silicide, nickel silicide, and titanium silicide), or a multilayered combination thereof. In some embodiments, each gate conductor portion 20L, 20R can comprise an nFET gate metal. In other embodiments, each gate conductor portion 20L, 20R can comprise a pFET gate metal. In other embodiments, gate conductor portion 20L comprises an nFET gate metal, while gate conductor portion 20R comprises a pFET gate metal. In another embodiment, gate conductor portion 20L comprises a pFET gate metal, while gate conductor portion 20R comprises an nFET gate metal.

[0050] The gate conductor material used to provide each gate conductor portion 20L, 20R can be formed using a deposition process, including, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), sputtering, atomic layer deposition (ALD), or other similar deposition processes. When forming a metal silicide, a conventional silicidation process is used. When different gate conductor materials are used for the gate conductor portions 20L, 20R, a block mask technique can be used. In one embodiment, the gate conductor material used to provide each gate conductor portion 20L, 20R has a thickness of 1 nm to 100 nm. Other thicknesses less than or greater than the above-mentioned thickness ranges can also be used for the gate conductor material used to provide each gate conductor portion 20L, 20R.

[0051] Each gate cap portion includes a gate cap material. The gate cap material providing each gate cap portion may include one of the dielectric materials described above for the hard mask material. In one embodiment, each gate cap portion includes silicon dioxide, silicon nitride and / or silicon oxynitride. The dielectric material providing each gate cap portion may be formed using a conventional deposition process (e.g., chemical vapor deposition or plasma enhanced chemical vapor deposition). The dielectric material providing each gate cap portion may have a thickness of 5 nm to 20 nm. Other thicknesses less than or greater than the above thickness ranges may also be used as the thickness of the dielectric material providing each gate cap portion.

[0052] Each functional gate structure can be formed by providing a functional gate material stack comprising, from bottom to top, a gate dielectric material, a gate conductor material, and a gate cap material (if present). The functional gate material stack can then be patterned. In one embodiment of the present application, the patterning of the functional gate material stack can be performed using photolithography and etching.

[0053] In other embodiments of the present application, the gate structures 16L and 16R are sacrificial gate structures. A "sacrificial gate structure" refers to a material or material stack that serves as a placeholder for a subsequently formed functional gate structure. In such a process, a functional gate structure is formed after the semiconductor fin is cut by replacing the sacrificial gate structure with a functional gate structure as described above. In such an embodiment, the gate dielectric portion of the functional gate structure can be U-shaped. "U-shaped" refers to a material that includes a bottom horizontal surface and sidewall surfaces extending upward from the bottom horizontal surface. When employed, the sacrificial gate structure can include a sacrificial gate dielectric portion, a sacrificial gate material portion, and a sacrificial gate cap portion. In some embodiments, the sacrificial gate dielectric portion and / or the sacrificial gate cap portion can be omitted. The sacrificial gate dielectric portion includes one of the dielectric materials described above for the gate dielectric portions 18L and 18R. The sacrificial gate material portion includes one of the gate conductor materials described above for the gate conductor portions 20L and 20R. The sacrificial gate cap portion includes one of the gate cap materials described above for the gate cap portion. The sacrificial gate structure may be formed by depositing various layers of material and then patterning the resulting sacrificial material pockets by using, for example, photolithography and etching.

[0054] In the following figures, only the vertical cross-section of the exemplary semiconductor structure along the vertical plane BB is shown. The vertical plane BB is a plane passing through the semiconductor fin 14P. Now referring to Figure 3 , showing the formation of dielectric material liner 24 Figures 2A-2B 16R. As shown, the dielectric material liner 24 is a conformal layer covering the exposed surfaces of the semiconductor fin 14P and each gate structure 16L, 16R. The dielectric material liner 24 may include any dielectric material, including, for example, a dielectric material oxide, a dielectric material nitride, and / or a dielectric material oxynitride. In one embodiment, the dielectric material liner 24 may be composed of silicon dioxide. In another embodiment, the dielectric material liner 24 may be composed of silicon nitride. In another embodiment, the dielectric material liner 24 may be a stack composed of silicon dioxide and silicon nitride in any order. In further embodiments, the dielectric material liner 24 may include SiBCN or SiOCN materials.

[0055] In some embodiments of the present application, the dielectric material liner 24 can be formed by a deposition process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or plasma enhanced chemical vapor deposition (PECVD). The thickness of the dielectric material liner 24 can be in the range of 2 nm to 10 nm, but thicknesses less than or greater than the above thickness ranges can be used for the dielectric material liner 24.

[0056] In some embodiments (not shown), the dielectric material liner 24 can be etched at this point in the present application to form gate spacers (i.e., a first set of gate spacers described below) on the vertical sidewalls of each gate structure 16L, 16R. In one embodiment, the etch for providing the first set of gate spacers can include reactive ion etching. In such an embodiment, the dielectric material liner 24 will be removed from the uppermost surface of each gate structure 16L, 16R and from the uppermost horizontal surface of the semiconductor fin 14P.

[0057] Now refer to Figure 4 , showing Figure 3 FIG2 is a cross-sectional view of an exemplary semiconductor structure after forming a patterned material stack. The patterned material stack includes an opening 30 located between gate structure 16L and gate structure 16R. Opening 30 is defined as an opening into which semiconductor fin 14P is subsequently cut. According to the present application, a portion of opening 30 is located above each gate structure 16L, 16R.

[0058] According to one embodiment of the present application, the patterned material stack comprises, from bottom to top, an optical planarization layer portion 26P and an anti-reflective coating portion 28P. A photoresist material portion (not shown) may be present on top of each anti-reflective coating portion 28P.

[0059] The optical planarizing layer (OPL) portion 26P of the patterned material stack that can be employed in the present application includes a self-planarizing material. In one example, the optical planarizing layer portion 26P can be an organic material containing C, O, and H, and optionally containing Si and / or F. In another example, the optical planarizing layer portion 26P can be amorphous carbon. The self-planarizing material that can provide the optical planarizing layer portion 26P can be formed by spin coating, chemical vapor deposition, plasma enhanced chemical vapor deposition, evaporation, or chemical solution deposition. The thickness of the optical planarizing layer portion 26P can be 10 nm to 300 nm, but lesser or greater thicknesses can also be employed.

[0060] The anti-reflective coating portion 28P of the patterned material stack includes any anti-reflective coating material that can reduce the image distortion associated with the reflection of the underlying structure surface. In one example, the anti-reflective coating portion 28P of the patterned material stack includes an anti-reflective coating material containing silicon (Si). The anti-reflective coating material providing the anti-reflective coating portion 28P can be formed by spin coating, chemical vapor deposition, plasma enhanced chemical vapor deposition, evaporation or chemical solution deposition. The thickness of the anti-reflective coating portion 28P can be 10nm to 150nm, but a smaller or larger thickness can also be adopted.

[0061] Figure 4 The exemplary semiconductor structure shown can be formed by first providing a material stack comprising, from bottom to top, a capping layer of self-planarizing material (as described above), a capping layer of anti-reflective coating material (as described above), and a capping layer of photoresist material. The capping layer of self-planarizing material and the capping layer of anti-reflective coating material can be formed using one of the above-described deposition processes. The photoresist material that can provide a capping layer of photoresist material can include a positive tone photoresist, a negative tone, or a hybrid photoresist material. The capping layer of photoresist material can be deposited using one of the above-described deposition processes to provide an anti-reflective coating material. After providing this material stack, the material stack is then patterned by photolithography and etching (as described above in patterning semiconductor materials) to provide semiconductor fins 14P. After the etching process, the remaining photoresist material portion is stripped using a resist stripping process (e.g., ashing).

[0062] Now refer to Figure 5 , shows the semiconductor fin 14P after cutting using the patterned material stack (26P, 28P) and a portion of the dielectric material liner 24 located in the opening 30 as a mask. Figure 4 The cut portions of semiconductor fin 14P are now referred to as semiconductor fin portions 14L, 14R.

[0063] According to the embodiments of the present application, Figure 5 The exemplary semiconductor structure shown can be formed using one or more anisotropic etching processes. In one example, one or more reactive ion etching processes can be used. Typically, the anisotropic etching first penetrates the exposed portion of the dielectric material liner 24 that is not protected by the patterned material stack (26P, 28P) to expose the horizontal uppermost surface of each gate structure 16L, 16R, and then the etching continues (or a separate etch is used) to cut the semiconductor fin 14P. The "penetration" etching forms one gate spacer of the first set of gate spacers 24P along one of the sidewall surfaces of each gate structure 16L, 16R. One gate spacer of the first set of gate spacers 24P formed within the opening is vertically aligned with the end wall 15W of each semiconductor fin portion 14L, 14R. In some embodiments in which the dielectric material liner is pre-formed into the gate spacer, the "penetration" etching is omitted. As Figure 5 As shown, end walls 15W of each semiconductor fin portion 14L, 14R are exposed beneath the first gate spacer of the first set of gate spacers 24P formed within opening 30. According to the present application, end walls 15W of semiconductor fin portion 14L face end walls 15W of semiconductor fin portion 14R.

[0064] Now refer to Figure 6, showing the patterned material stack (26P, 28P) after removal Figure 5 The patterned material stack (26P, 28P) can be removed by first removing the anti-reflective coating portion 28P through a planarization process (such as chemical mechanical planarization and / or grinding) or etching. The exposed OPL portion 26P can then be removed using an etch-back process or a stripping process that is selective in removing the self-planarizing material that provides the OPL portion 26P.

[0065] After removing the patterned material stack, the remaining portion of the dielectric material liner 24 may be etched to form another gate spacer of the first set of gate spacers 24P on the opposite side of each gate structure 16L, 16R from where the fin cut occurs. This step is now shown in detail.

[0066] Now refer to Figure 7 , showing the second set of gate spacers 32P after formation Figure 6 An exemplary semiconductor structure is shown. As shown, each gate spacer of the second group of gate spacers 32P resides on the sidewall of a gate spacer of the first group of gate spacers 24P. As further shown, a gate spacer of the second group of gate spacers 32P covers the exposed end wall 15W of each semiconductor fin 14L, 14R. One gate spacer of the first group of gate spacers 24P and one gate spacer of the second group of gate spacers 32P are formed on the side of the gate structure 16L, 16R opposite to where the fin cut occurs, and the gate spacers span the surface of each semiconductor fin portion 14L, 14R. In the area where the fin cut occurs, the gate spacers of the first and second groups of gate spacers 24P span the surface of the semiconductor fin portion 14L, 14R, while the gate spacers of the second group of gate spacers 32P cover the exposed end wall 15W of the semiconductor fin portion 14L, 14R.

[0067] The second set of gate spacers 32P is formed by first forming a dielectric material layer and then performing a spacer etch. During the spacer etch, another gate spacer is formed for the first set of gate spacers 24P, if not previously formed. The dielectric material used to provide the second set of gate spacers 32P may include one of the dielectric materials described above for dielectric liner 24. In one embodiment, the dielectric material used to provide the second set of gate spacers 32P may include the same dielectric material used to provide dielectric liner 24. In one example, both the dielectric material used to provide the second set of gate spacers 32P and the dielectric material used to provide dielectric liner 24 include silicon dioxide. In another embodiment, the dielectric material used to provide the second set of gate spacers 32P may include a different dielectric material than the dielectric material used to provide dielectric liner 24. In one example, the dielectric material used to provide the second set of gate spacers 32P includes silicon nitride, while the dielectric material used to provide dielectric liner 24 includes SiBCN or SiCON. The dielectric material providing the second set of gate spacers 32P may be formed using one of the deposition processes described above when forming the dielectric material liner 24. The spacer etch may include an anisotropic etch, such as a reactive ion etch.

[0068] Source / drain regions (not shown) are formed on exposed portions of the semiconductor fin portions 14L, 14R that are not covered by the gate structures 16L, 16R. The source / drain regions can be formed using conventional techniques, such as epitaxial growth, which is well known to those skilled in the art. As is known, the source region will be located on one side of the functional gate structure, and the drain region will be located on the other side of the functional gate structure. In some embodiments, the source / drain regions may be unmerged. In other embodiments, the source / drain regions may be merged. The source / drain regions include a semiconductor material and n-type or p-type dopants. In some embodiments, the source / drain regions may include the same semiconductor material as the semiconductor fin portions 14L, 14R. In some embodiments, the source / drain regions may include a semiconductor material different from the semiconductor fin portions 14L, 14R. In some embodiments, and when a sacrificial gate structure is formed, the sacrificial gate structure can now be replaced with a functional gate structure.

[0069] Now refer to Figure 8 , showing the structure of the first gate spacer 50P and the sacrificial dielectric liner 52 after forming the first set of gate spacers 50P and the sacrificial dielectric liner 52 according to another embodiment of the present application Figure 2B An exemplary semiconductor structure of FIG.

[0070] Each gate spacer of the first set of gate spacers 50P is formed on the sidewall of each gate structure 16L, 16R. In addition, the first set of gate spacers 50P is formed across a portion of the semiconductor fin 14P. The first set of gate spacers 50P can be formed by depositing a dielectric material and then performing a spacer etch. The dielectric material that can be used to provide the first set of gate spacers 50P can include one of the above-mentioned dielectric materials that provide the dielectric material liner 24. In one example, the dielectric material that provides the first set of gate spacers 50P can be SiBCN or SiOCN dielectric material. The deposition of the dielectric material that provides the first set of gate spacers 50P can include chemical vapor deposition, plasma enhanced chemical vapor deposition, or atomic layer deposition. The spacer etch can include isotropic etching, such as reactive ion etching.

[0071] The sacrificial dielectric liner 52 may comprise one of the dielectric materials described above for providing the dielectric material liner 24, provided that the dielectric material selected for providing the sacrificial dielectric liner 52 has a different etch rate than the dielectric material used to provide the first set of gate spacers 50P. In one example, and when the first gate spacers comprise SiBCN material, the sacrificial dielectric liner 52 may comprise silicon dioxide and / or silicon nitride. The sacrificial insulating liner 52 will cover all exposed surfaces of the first gate spacers 50P, the uppermost surface of each gate structure 16L, 16R, and all exposed surfaces of the semiconductor fins 14P (not specifically visible in the cross-sectional view shown). The sacrificial dielectric liner 52 may be formed using a deposition process such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, or atomic layer deposition. The sacrificial dielectric liner 52 may have a thickness of 1 nm to 20 nm. Other thicknesses less than or greater than the aforementioned thickness ranges may also be used for the thickness of the sacrificial dielectric liner 52.

[0072] Now refer to Figure 9 , showing the structure after forming the patterned material stack (26P, 28P) and performing a punch-through etch of the sacrificial dielectric liner 52 Figure 8 As shown, and after the punch-through etch is performed, a portion of the uppermost surface of each gate structure 16L, 16R is exposed, as is all of the surface of the semiconductor fin 14P located between the gate structures 16L, 16R. The sacrificial dielectric liner 52 that remains after the punch-through etch may be referred to herein as a sacrificial dielectric liner portion 52P.

[0073] The patterned material stack (26P, 28P) used in this embodiment of the present application is the same as the patterned material stack in the previous embodiment of the present application. Therefore, the patterned material stack (26P, 28P) of this embodiment of the present application includes materials and can be formed as discussed above in the previous embodiment of the present application. Element 30 represents an opening formed therein during the formation of the patterned material stack (26P, 28P). The through etch includes an anisotropic etch that is selective in removing the dielectric material that provides the sacrificial dielectric liner 52.

[0074] Now refer to Figure 10 , shows the semiconductor fin 14P after cutting using the patterned material stack (26P, 28P), one of the first gate spacers 50P (within the opening 30), and the remaining portion of the sacrificial dielectric liner (i.e., the sacrificial dielectric liner portion 52P) as an etch mask Figure 9 The exemplary semiconductor structure of FIG. The cutting of semiconductor fins 14P to provide semiconductor fin portions 14L, 14R can be performed using an anisotropic etch that selectively removes the semiconductor material that provides semiconductor fins 14P. The cutting of semiconductor fins 14P exposes end walls 15W of each remaining semiconductor fin 14L, 14R. In some embodiments, each end wall 15W is vertically aligned with a sidewall of sacrificial dielectric liner portion 52P located within opening 30. According to the present application, end walls 15W of semiconductor fin portion 14L face end walls 15W of semiconductor fin portion 14R.

[0075] Now refer to Figure 11 , showing the end wall of each semiconductor fin portion 14L, 14R after side etching is performed to pull back Figure 10 The side etching provides an undercut region below one of the sacrificial dielectric liner portions 52P so that the end wall 15W is located below one of the first gate spacers 50P or is vertically aligned with the sidewall of one of the first set of gate spacers 50P located within the opening 30. The side etching includes wet or dry isotropic chemical etching.

[0076] Now refer to Figure 12 , showing the structure after removing the patterned material stack (26P, 28P) and then removing the remaining portion of the sacrificial dielectric liner (i.e., sacrificial dielectric liner portion 52P) Figure 11 The patterned material stack (26P, 28P) can be removed as described in the previous embodiments of the present application. Each sacrificial dielectric liner portion 52P can be removed using an etch that is selective in removing the dielectric material that provides each sacrificial dielectric liner portion 52P.

[0077] Now refer to Figure 13 , showing the second set of gate spacers 32P after formation Figure 12 . The second set of gate spacers 32P used in this embodiment of the present application includes one of the dielectric materials described above for providing the second set of gate spacers 32P in the previous embodiments of the present application. The second set of gate spacers 32P can be formed by deposition, followed by spacer etching. The second set of gate spacers 32P is formed on the exposed sidewalls of the first set of gate spacers 50P and a portion of each semiconductor fin portion 14L, 14R. As shown, one of the gate spacers of the second set of gate spacers 32P located at the end of the semiconductor fin portion 14L, 14R covers the exposed sidewall of the semiconductor fin portion 14L, 14R. Another gate spacer of the second set of gate spacers 32P located on the side of the gate structure 16L, 16R opposite to where the semiconductor fin is cut spans the semiconductor fin portion 14L, 14R.

[0078] Source / drain regions (not shown) are formed on exposed portions of the semiconductor fin portions 14L, 14R that are not covered by the gate structures 16L, 16R. The source / drain regions can be formed using conventional techniques, such as epitaxial growth, which is well known to those skilled in the art. As is known, the source region will be located on one side of the functional gate structure, and the drain region will be located on the other side of the functional gate structure. In some embodiments, the source / drain regions may be unmerged. In other embodiments, the source / drain regions may be merged. The source / drain regions include a semiconductor material and n-type or p-type dopants. In some embodiments, the source / drain regions may include the same semiconductor material as the semiconductor fin portions 14L, 14R. In some embodiments, the source / drain regions may include a semiconductor material different from the semiconductor fin portions 14L, 14R. In some embodiments, and when a sacrificial gate structure is formed, the sacrificial gate structure can now be replaced with a functional gate structure.

[0079] Although the present application has been particularly shown and described with respect to its preferred embodiments, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made without departing from the spirit and scope of the present invention. Therefore, the present application is not limited to the exact forms and details described and shown, but falls within the scope of the appended claims.

Claims

1. A semiconductor structure comprising: a semiconductor fin portion having end walls and extending upwardly from the substrate; a gate structure spanning a portion of the semiconductor fin portion; a first set of gate spacers located on opposing sidewall surfaces of the gate structure; as well as a second set of gate spacers positioned on outer sidewalls of the first set of gate spacers, wherein one gate spacer of the second set of gate spacers has an inner sidewall surface having an upper portion that directly contacts the outer sidewall of one gate spacer of the first set of gate spacers, Among the second group of gate spacers, only one gate spacer of the second group of gate spacers has a lower portion that directly contacts and covers the entire end wall of the semiconductor fin portion, and another gate spacer of the second group of gate spacers spans another portion of the semiconductor fin portion.

2. The semiconductor structure of claim 1, wherein the gate structure is a functional gate structure.

3. The semiconductor structure of claim 2 , wherein a bottom portion of each gate spacer of the first set of gate spacers is located on an uppermost surface of the semiconductor fin portion, and wherein one gate spacer of the first set of gate spacers has an outer edge that is vertically aligned with the end wall of the semiconductor fin portion. 4 . The semiconductor structure of claim 1 , wherein the another gate spacer of the second set of gate spacers spans an uppermost surface of the semiconductor fin portion. 5 . The semiconductor structure of claim 2 , wherein each gate spacer of the first set of gate spacers spans across the semiconductor fin portion. The semiconductor structure of claim 1 , wherein the substrate is an insulator layer.

7. The semiconductor structure of claim 1 wherein said first set of gate spacers comprises the same dielectric material as said second set of gate spacers.

8. The semiconductor structure of claim 1 wherein said first set of gate spacers comprises a different material than said second set of gate spacers.

9. The semiconductor structure of claim 1, wherein at least one gate spacer in the first set of gate spacers or the second set of gate spacers is composed of SiBCN or SiOCN material.

10. A method of forming a semiconductor structure, the method comprising: forming a gate structure spanning the semiconductor fin; forming a first dielectric material over the semiconductor fin and on sidewall surfaces of the gate structure; forming a patterned material stack over the first dielectric material, the patterned material stack having an opening exposing the first dielectric material on one side of the gate structure; etching the first dielectric material in the opening to form an internal gate spacer; cutting the semiconductor fin using the patterned material stack and the internal gate spacer as an etch mask to provide a semiconductor fin portion including the gate structure and having exposed endwalls; as well as depositing a second dielectric material on the fin portion including the gate structure; etching the second dielectric material on the fin portion including the gate structure to form a first outer gate spacer and a second outer gate spacer, wherein: the first external gate spacer covering the end wall of the semiconductor fin portion; The second outer gate spacer spans another portion of the semiconductor fin portion. The method of claim 10 , wherein the inner spacer comprises SiBCN. The method of claim 10 , wherein the outer spacer comprises SiBCN.

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