Switching regulators and power management ICs

Abstract

The present invention provides a switching regulator and a power management integrated circuit. The switching regulator includes a first switching circuit, a second switching circuit and a protection circuit. The first switching circuit has a first connection node coupled to a first reference voltage and a second connection node coupled to one end of an inductor. The second switching circuit has a first connection node coupled to a second reference voltage and a second connection node coupled to one end of the inductor. The protection circuit senses a voltage level at a first connection node of the first switching circuit and selectively enables an auxiliary current path in response to the sensed voltage level, wherein the auxiliary current path and at least the first switching circuit are connected in parallel.

Description

Technical Field

[0001] The present invention relates to voltage regulator design, and more particularly to a switching regulator using a protection circuit to avoid voltage stress and a related power management integrated circuit (PMIC). Background Art

[0002] Switching regulators are widely used in various electronic devices to provide appropriate voltages to electronic circuits within the electronic devices. For example, a switching regulator is a regulator that uses a switching element to convert an input power supply into a pulse voltage and then uses passive components (such as inductors, capacitors and / or resistors) to smooth the pulse voltage. The switching element can be implemented by a metal-oxide-semiconductor (MOS) transistor. The safe operating area (SOA) is the voltage and current conditions under which a MOS transistor operates without being permanently damaged or degraded. MOS transistors should not be exposed to conditions outside the safe operating area, even for a moment. However, there are parasitic resistors, inductors and capacitors in the power path. During switching, the MOS transistor implemented in the switching regulator may violate the SOA due to voltage bouncing caused by parasitic resistors, inductors and capacitors in the power path. A typical solution is to protect the switching regulator from violating the SOA at the expense of power efficiency. Furthermore, the typical solution requires complex hardware detectors and it is difficult to determine the optimal control settings for protecting the switching elements. Therefore, there is a need for an innovative switching regulator with a simple detector design that can maintain power efficiency while meeting SOA requirements. Summary of the invention

[0003] One of the objects of the present invention is to provide a switching regulator and a related power management integrated circuit (PMIC) using a protection circuit to avoid voltage stress.

[0004] According to a first aspect of the present invention, an exemplary switching regulator is disclosed. The switching regulator includes a first switching circuit, a second switching circuit and a protection circuit. The first switching circuit has a first connection node coupled to a first reference voltage and a second connection node coupled to one end of an inductor. The second switching circuit has a first connection node coupled to a second reference voltage different from the first reference voltage and a second connection node coupled to the one end of the inductor. The protection circuit is configured to receive an auxiliary reference voltage and the first reference voltage (sensing a voltage level at the first connection node of the first switching circuit), and selectively enable an auxiliary current path in response to the auxiliary reference voltage and the first reference voltage (i.e., the voltage level at the first connection node of the first switching circuit), wherein the auxiliary current path and at least the first switching circuit are arranged in a parallel connection. Wherein, the auxiliary reference voltage is constant, or the auxiliary reference voltage is a reference voltage provided to a controller, wherein the controller is used to control the on and off of the first switching circuit and the second switching circuit.

[0005] In one embodiment, the protection circuit comprises an auxiliary transistor, whose control node is arranged to receive the auxiliary reference voltage, whose first connection node is coupled to the first connection node of the first switch circuit, and whose second connection node is coupled to the first end of the inductor. In one embodiment, the voltage level at the control node of the auxiliary transistor (i.e., the auxiliary reference voltage) is constant.

[0006] According to a second aspect of the present invention, an exemplary power management integrated circuit (PMIC) is disclosed. The exemplary PMIC includes a first pin, a second pin, a third pin and a switching regulator. The first pin is used to receive a first reference voltage. The second pin is used to receive a second reference voltage different from the first reference voltage. The third pin is used to output a pulse voltage. The switching regulator is used to generate a pulse voltage. The switching regulator includes a first switching circuit, a second switching circuit and a protection circuit. The first switching circuit has a first connection node coupled to the first pin and a second connection node coupled to the third pin. The second switching circuit has a first connection node coupled to the second pin and a second connection node coupled to the third pin. The protection circuit is used to receive an auxiliary reference voltage and the first reference voltage (sensing a voltage level at the first connection node of the first switching circuit), and selectively enable an auxiliary current path in response to the auxiliary reference voltage and the first reference voltage (the voltage level at the first connection node of the first switching circuit), wherein the auxiliary current path and at least the first switching circuit are arranged in a parallel connection manner. Wherein, the auxiliary reference voltage is constant, or the auxiliary reference voltage is a reference voltage provided to a controller, wherein the controller is used to control the on and off of the first switching circuit and the second switching circuit.

[0007] The protection circuit proposed by the present invention has a simple design, can automatically enable the auxiliary current path according to the sensed voltage level at the first connection node of the switch circuit, and can maintain the power efficiency of the switching regulator under the condition of satisfying the SOA requirement.

[0008] These and other objects of the present invention will no doubt become apparent to those skilled in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the various drawings and figures. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In the following detailed description, for the purpose of explanation, numerous specific details are set forth in order to provide a thorough understanding of the disclosed embodiments. However, it is apparent that one or more embodiments may be practiced without these specific details. In other cases, well-known structures and devices are schematically shown to simplify the drawings.

[0010] Figure 1 is a schematic diagram showing a power management integrated circuit (PMIC) according to an embodiment of the present invention.

[0011] Figure 2 is a circuit diagram illustrating a first switching regulator with high-side SOA protection according to an embodiment of the present invention.

[0012] Figure 3 According to an embodiment of the present invention, Figure 2 Waveforms of various voltages and auxiliary currents in a switching regulator are shown.

[0013] Figure 4 It is shown Figure 2 FIG. 4 is a schematic diagram of a switching regulator in FIG. 1 operating during a first time period t1 - t2 within a voltage regulation cycle.

[0014] Figure 5 It is shown Figure 2 FIG. 4 is a schematic diagram showing the operation of the switching regulator during a second time period t2 - t3 within a voltage regulation cycle.

[0015] Figure 6 is a schematic diagram showing a second switching regulator with high-side SOA protection according to an embodiment of the present invention.

[0016] Figure 7is a schematic diagram showing a third switching regulator with high-side SOA protection according to an embodiment of the present invention.

[0017] Figure 8 According to an embodiment of the present invention, Figure 7 Waveforms of various voltages and auxiliary currents in a switching regulator are shown.

[0018] Fig. 9 is a schematic diagram illustrating a fourth switching regulator with high-side SOA protection according to an embodiment of the present invention.

[0019] Fig.10 is a circuit diagram illustrating a first switching regulator with low-side SOA protection according to an embodiment of the present invention.

[0020] Fig.11 It is shown Fig.10 Schematic diagram of the switching regulator in operation during a first period in a voltage regulation cycle.

[0021] Fig.12 It is shown Fig.10 Schematic diagram of the switching regulator in operation during a second period within a voltage regulation cycle.

[0022] Fig.13 is a schematic diagram illustrating a second switching regulator with low-side SOA protection according to an embodiment of the present invention.

[0023] Fig.14 is a schematic diagram illustrating a third switching regulator with low-side SOA protection according to an embodiment of the present invention.

[0024] Fig.15 is a schematic diagram illustrating a fourth switching regulator with low-side SOA protection according to an embodiment of the present invention. DETAILED DESCRIPTION

[0025] Certain words are used in the specification and claims to refer to specific components. It should be understood by those skilled in the art that electronic equipment manufacturers may use different terms to refer to the same component. The specification and claims do not use differences in names as a way to distinguish components, but rather use differences in the functions of the components as a basis for distinction. The term "including" mentioned throughout the specification and claims is an open-ended term and should be interpreted as "including but not limited to". In addition, the term "coupled" is used herein to include any direct and indirect electrical connection means. Therefore, if the text describes a first device electrically connected to a second device, it means that the first device can be directly connected to the second device, or indirectly connected to the second device through other devices or connection means.

[0026] Figure 1 1 is a schematic diagram showing a power management integrated circuit (PMIC) according to an embodiment of the present invention. PMIC 100 is a chip used by an electronic device to provide a stable voltage to other components in the same electronic device. In this embodiment, PMIC 100 is used by a mobile device such as a cellular phone, a tablet computer, or a wearable device. Therefore, the mobile device is powered by a battery 10. Figure 1 As shown, the PMIC 100 includes a switching regulator 102, wherein the switching regulator 102 includes a controller 104 and a power stage 106. The controller 104 is a control circuit that can use a pulse width modulation (PWM) scheme or other control schemes to control the conductive state (i.e., on / off state) of a switching element (e.g., transistor) in the power stage 106. In addition to the switching element (e.g., transistor), the power stage 106 also includes the proposed protection circuit 108 to ensure that the switching element (e.g., transistor) can meet the SOA requirements.

[0027] The power supply voltage of the controller 104 and the power supply voltage of the power stage 106 may be provided separately. Similarly, the ground voltage of the controller 104 and the ground voltage of the power stage 106 may be provided separately. The PMIC 100 has a plurality of pins 112, 114, 116, 118 to receive a plurality of reference voltages V AVDD 、V AGND 、V PVDD 、V PGND Specifically, pin 112 is a power pin for receiving a power supply voltage (eg, V AVDD Pin 114 is a ground pin for receiving a ground voltage (eg, V AGND Pin 116 is another power supply pin for receiving the power supply voltage required by the power stage 106 (eg, V PVDD Pin 118 is another ground pin for receiving the ground voltage required by power stage 106 (eg, V PGND The power supply voltage V is provided via the circuit components on the first printed circuit board 12 (indicated by “PCB1”). AVDD , a power supply voltage V is provided via a circuit component on a second printed circuit board 14 (indicated by “PCB2”). PVDD , a ground voltage V is provided via a circuit component on a third printed circuit board 16 (indicated by “PCB3”). AGND , a ground voltage V is provided via a circuit component on a fourth printed circuit board 18 (indicated by “PCB4”). PGNDThe PMIC 100 further includes a pin 120, which is a voltage output pin for outputting the pulse voltage V generated by the power stage 106. LX Output to a load circuit. For example, the load circuit may be connected to pin 120 via an inductor.

[0028] Power supply voltage V AVDD and V PVDD can be designed to have the same steady-state voltage value, ground voltage V AGND and V PGND can be designed to have the same steady-state voltage value. However, due to the inherent characteristics of the controller 104 and the power stage 106, the power supply voltage V AVDD The noise level is lower than the power supply voltage V PVDD The noise level, ground voltage V AGND The noise level is below the ground voltage V PGND In other words, the power supply voltage V AVDD Ratio of power supply voltage V PVDD Much cleaner, ground voltage V AGND Ratio to ground voltage V PGND In an exemplary SOA protection design, the protection circuit 108 can use the power supply voltage V AVDD As a reference, the voltage bounce on the power supply voltage at the monitoring pin 116 is monitored. In another exemplary SOA protection design, the protection circuit 108 can use the ground voltage V AGND As a reference, to monitor the voltage bouncing on the ground voltage at pin 118. However, these are only for illustration and are not meant to limit the present invention. In fact, any switching regulator design using the proposed SOA protection design falls within the protection scope of the present invention. For example, the protection circuit 108 can use a higher steady-state reference voltage level to monitor the voltage bouncing on the power supply voltage at pin 116. For another example, the protection circuit 108 can use a lower steady-state reference voltage level to monitor the voltage bouncing on the ground voltage at pin 118. More details of the proposed SOA protection design will be described with reference to the accompanying drawings.

[0029] Figure 2 is a circuit diagram illustrating a first switching regulator with high-side SOA protection according to an embodiment of the present invention. Figure 1 The illustrated switching regulator 102 may be implemented using the switching regulator 200. For the sake of clarity and simplicity, Figure 2 Only circuit components related to the present invention are shown. In practice, the switching regulator 200 may also include other circuit components. Figure 2As shown, the switching regulator 200 includes a plurality of switch circuits 202 and 204 and a protection circuit 206. The switch circuits 202 and 204 are used as switch elements of the power stage 106, and the protection circuit 108 of the power stage 106 can be implemented by the protection circuit 206. The switch circuit 202 is a high-side (HS) switch having a first reference voltage (e.g., a power supply voltage V PVDD ) and a second connection node coupled to one end of an off-chip inductor L, wherein the switch circuit 202 receives a power supply voltage V through the pin 116. PVDD , the off-chip inductor L is coupled to the switch circuit 202 via the pin 120. In addition, the conduction state (ie, the on / off state) of the switch circuit 202 is controlled by a switch control signal S1. Figure 1 The controller 104 is shown generating the switch control signal S1.

[0030] The switch circuit 204 is a low-side (LS) switch having a voltage coupled to a second reference voltage (eg, a ground voltage V PGND ) and a second connection node coupled to one end of the off-chip inductor L, the second reference voltage is connected to the first reference voltage (eg, the power supply voltage V PVDD ) is different, wherein the switch circuit 204 receives the ground voltage V via the pin 118 PGND In addition, the conduction state (ie, on / off state) of the switch circuit 204 is controlled by another switch control signal S2. Figure 1 The controller 104 is shown generating the switch control signal S2.

[0031] The protection circuit 206 is configured to sense a voltage level V at the first connection node of the switch circuit 202. PVDD,IN , and in response to the voltage level V at the first connection node of the switch circuit 202 PVDD,IN The auxiliary current path 208 is selectively enabled, wherein the auxiliary current path 208 and the switch circuit 202 are arranged in parallel connection.

[0032] In this embodiment, the switch circuit 202 is composed of a P-channel metal-oxide-semiconductor (PMOS) transistor M HS The source is coupled to the pin 116, the drain is coupled to the pin 120, and the gate is coupled to the controller (eg, Figure 1The controller 104 shown in FIG. 1 ); the switch circuit 204 is composed of an N-channel metal-oxide-semiconductor (NMOS) transistor M LS The source is coupled to pin 118, the drain is coupled to pin 120, and the gate is coupled to a controller (eg, Figure 1 The controller 104 shown); the protection circuit 206 is composed of a PMOS transistor M as an auxiliary transistor AUX The source is coupled to the pin 116 , the drain is coupled to the pin 120 , and the gate is coupled to the pin 112 .

[0033] The parasitic inductance generated by the PCB and semiconductor package can be represented by L HS,par and L LS,par The parasitic capacitors generated by the PCB, semiconductor package, and switching circuits 202 and 204 are represented by C HS,par and C LS,par express.

[0034] Please combine Figure 3 to Figure 4 refer to Figure 2 . Figure 3 According to an embodiment of the present invention, Figure 2 Waveform diagrams of various voltages and auxiliary currents in the switching regulator 200 are shown. Figure 4 It is shown Figure 2 FIG. 2 is a schematic diagram of the switching regulator 200 in FIG. 1 operating during a first period t1-t2 in a voltage regulation cycle. AUX The absolute value of the gate-source voltage is given by |V GS,AUX | indicates. PMOS transistor M HS The absolute value of the gate-source voltage is given by |V GS,P | indicates. NMOS transistor M LS The absolute value of the gate-source voltage is given by |V GS,N | indicates. PMOS transistor M HS The absolute value of the drain-source voltage is given by |V DS,P | indicates.

[0035] During the first period t1-t2, the switch circuit 202 (specifically, the PMOS transistor M HS ) is turned on, the switch circuit 204 (specifically, the NMOS transistor M LS ) is turned off. Therefore, the switching regulator 200 generates a current flowing through the parasitic inductor L HS,par , switch circuit 202 (specifically, PMOS transistor M HS ) and a current IL Therefore, the pulse voltage V LX Since the voltage level V at the first connection node of the switch circuit 202 is PVDD,IN is approximately equal to the power supply voltage V received by the protection circuit 206 AVDD Therefore, the protection circuit 206 (specifically, the PMOS transistor M AUX ) is turned off, meaning that the auxiliary current path 208 is not enabled between the first connection node and the second connection node of the switch circuit 202.

[0036] Please combine Figure 3 and Figure 5 refer to Figure 2 . Figure 5 It is shown Figure 2 FIG. 2 is a schematic diagram of the switching regulator 200 in FIG. 2 operating during a second period t2-t3 in a voltage regulation cycle. During the second period t2-t3 immediately following the first period t1-t2, the switch control signal S1 is set to turn off the switch circuit 202 (specifically, the PMOS transistor M HS ), the switch control signal S2 is set to turn on the switch circuit 204 (specifically, the NMOS transistor M LS ). Therefore, the switching regulator 200 generates a current flowing through the parasitic inductor L LS,par , switch circuit 204 (specifically, NMOS transistor M LS ) and the current I of the inductor L L Therefore, the pulse voltage V LX From a high voltage level to a low voltage level. Since the switch circuit 202 (specifically, the PMOS transistor M HS ) is controlled to be off and flows through the parasitic inductor L HS,par The current should be continuous, so the parasitic inductor L HS,par There is still current I HS,par , thus increasing the voltage level V at the first connection node of the switch circuit 202. PVDDIN In the case where the proposed protection circuit 206 is omitted, the voltage level V at the first connection node of the switch circuit 202 is PVDD,IN is significantly improved, as shown by dashed line 302. As shown by dashed line 304, the PMOS transistor M HS The absolute value of the drain-source voltage (given by |V DS,P | indicates) will exceed the SOA voltage V SOA , which causes the PMOS transistor M HS damage.

[0037] To solve this problem, the proposed protection circuit 206 can provide SOA protection. HS,par Through the parasitic inductor L HS,par When the voltage level V at the first connection node of the switch circuit 202 is PVDD,IN increases to above that as the PMOS transistor M AUX The gate voltage is the power supply voltage V AVDD , and the PMOS transistor M AUX The absolute value of the gate-source voltage (given by |V GS,AUX | indicates) increases accordingly. Once the PMOS transistor M AUX The absolute value of the gate-source voltage (given by |V GS,AUX | indicates) exceeds the PMOS transistor M AUX The absolute value of the threshold voltage |V TH |, protection circuit 206 (specifically, PMOS transistor M AUX ) is automatically turned on, thereby enabling the auxiliary current path 208 between the first connection node and the second connection node of the switch circuit 202. In other words, the protection circuit 206 is I HS,par Provides another current path. Since the current I HS,par Part of (by I AUX denoted by the solid line 306) flows through the auxiliary current path 208, thereby alleviating the voltage bounce at the first connection node of the switch circuit 202. HS The absolute value of the drain-source voltage (given by |V DS,P | indicates) will not exceed the SOA voltage V SOA , as shown by the solid line 308.

[0038] exist Figure 2 In the above embodiment shown in FIG. 1 , the protection circuit 206 is composed of a PMOS transistor M AUX However, this is for illustrative purposes only and is not intended to limit the present invention. Alternatively, the protection circuit 206 may be configured to provide a voltage source that can be controlled based on an auxiliary reference voltage (e.g., V AVDD ) and the voltage level V at the first connection node of the switch circuit 202 PVDD,IN This is achieved by selectively turning on a PNP bipolar transistor or other transistor by the difference between the two.

[0039] The proposed protection circuit 206 has a simple design and can be used according to the auxiliary reference voltage (eg, V AVDD ) and the voltage level V at the first connection node of the switch circuit 202 PVDDIN The difference between the current paths 204 and 205 automatically enables the auxiliary current path 208. In addition, there is no need to reduce the current consumption of the PMOS transistor M HSThe slew rate of the PMOS transistor M can be used for SOA protection. HS The power efficiency of the switching regulator 200 is maintained while meeting the SOA requirement.

[0040] Current I HS,par The maximum value depends on the current I required by the load circuit L The maximum value of the PMOS transistor M is also dependent on the parasitic inductors, capacitors and resistors generated by the PCB and the semiconductor package. HS SOA requirements are met, so there is no need to limit the maximum current capability for SOA protection, and / or it is unnecessary to restrict the design rules of the PCB and the semiconductor package for SOA protection.

[0041] about Figure 2 In the illustrated embodiment, the protection circuit 206 is configured to selectively enable an auxiliary current path 208 coupled between the first connection node of the switch circuit 202 and one end of the inductor L. LX is the output of the switching regulator 200 and is provided to the inductor L via pin 120. The parasitic inductor L HS,par The power on the switching regulator 200 can be recycled to the output of the switching regulator 200 through the auxiliary current path 208. However, this is for illustration purposes only and is not meant to be a limitation of the present invention. By enabling the PMOS transistor M coupled to the switching circuit 202 (specifically, HS ) is connected to a reference voltage (eg, ground voltage V PGND ) between the auxiliary current path 208, which can be implemented as a switch circuit 202 (specifically, a PMOS transistor M HS ) provides the same purpose of SOA protection.

[0042] Figure 6 2 is a schematic diagram showing a second switching regulator with high-side SOA protection according to an embodiment of the present invention. The main difference between the switching regulators 200 and 600 is that the switching regulator 600 has a protection circuit 606 implemented by an auxiliary transistor, which is a PMOS transistor M′. AUX , whose source is coupled to pin 116, whose drain is coupled to pin 118, and whose gate is coupled to pin 112. Therefore, when the auxiliary current path 608 is enabled, the parasitic inductor L HS,par The power on the switching regulator 600 will not be circulated to the output of the switching regulator 600. Alternatively, the protection circuit 606 can be composed of a circuit that can be based on an auxiliary reference voltage (e.g., V AVDD ) and the voltage level V at the first connection node of the switch circuit 202 PVDD,INThis is achieved by selectively turning on a PNP bipolar transistor or other transistor by the difference between the two.

[0043] Figure 7 2 is a schematic diagram showing a third switching regulator with high-side SOA protection according to an embodiment of the present invention. The main difference between the switching regulators 200 and 700 is that the protection circuit 706 of the switching regulator 700 includes a resistor-capacitor (RC) circuit 707 and the aforementioned auxiliary transistor (e.g., PMOS transistor M). AUX ). The RC circuit 707 includes a resistor R and a capacitor C. A first end of the resistor R is coupled to an auxiliary reference voltage (eg, a power supply voltage V AVDD ), the second end of the resistor R is coupled to the auxiliary transistor (eg, PMOS transistor M AUX ). The first end of the capacitor C is coupled to the auxiliary transistor (eg, PMOS transistor M AUX ), and the second end of the capacitor C is coupled to one end of the inductor L. Figure 3 and Figure 5 As shown, during the second period t2-t3, the switch control signal S1 is set to turn off the switch circuit 202 (specifically, the PMOS transistor M HS ), the switch control signal S2 is set to turn on the switch circuit 204 (specifically, the NMOS transistor M LS ). Therefore, the pulse voltage V LX From a high voltage level to a low voltage level. Due to the pulse voltage V LX The auxiliary transistor (eg, PMOS transistor M) is coupled to the auxiliary transistor through the RC circuit 707. AUX ) control node, therefore, the auxiliary transistor (eg, PMOS transistor M AUX )'s control node voltage level V AVDD,RC Since the pulse voltage V LX and is temporarily pulled low. At voltage level V AVDD,RC Since the pulse voltage V LX After being temporarily pulled low, it will be replaced by the auxiliary reference voltage (for example, the power supply voltage V AVDD ) is pulled high.

[0044] Alternatively, an auxiliary transistor (eg, a PMOS transistor M2) in the protection circuit 706 may be used. AUX ) can be determined by the voltage level V at the control node of the auxiliary transistor AVDD,RC and the voltage level V at the first connection node of the switch circuit 202 PVDD,IN This is achieved by selectively turning on a PNP bipolar transistor or other transistor by the difference between the two.

[0045] Please combine Figure 8 refer to Figure 7 . Figure 8 According to an embodiment of the present invention, Figure 7 The waveforms of various voltages and auxiliary currents in the switching regulator 700 are shown. AVDD,RC Pulse voltage V LX After being temporarily pulled low, the PMOS transistor M AUX The gate-source voltage of the auxiliary current path 208 increases, thereby causing a higher current density on the auxiliary current path 208. Therefore, the current I flowing through the auxiliary current path 208 AUX increases, thereby causing the voltage level V at the first connection node of the switch circuit 202 to PVDD,IN The smaller voltage increase is shown by the dashed line 806. HS The absolute value of the drain-source voltage of the switch circuit 202 is small, thereby reducing the voltage bounce at the first connection node of the switch circuit 202, as shown by the dotted line 808. Compared with the design of the protection circuit 206, the design of the protection circuit 706 can be the switch circuit 202 (specifically, the PMOS transistor M HS ) provides better SOA protection.

[0046] Fig. 9 1 is a schematic diagram showing a fourth switching regulator with high-side SOA protection according to an embodiment of the present invention. The main difference between the switching regulators 600 and 900 is that the protection circuit 906 of the switching regulator 900 includes a resistor-capacitor (RC) circuit 907 and the auxiliary transistor (e.g., PMOS transistor M′) described above. AUX ). The RC circuit 907 includes a resistor R' and a capacitor C'. A first end of the resistor R' is coupled to an auxiliary reference voltage (eg, a power supply voltage V AVDD ), the second end of the resistor R' is coupled to the auxiliary transistor (eg, PMOS transistor M' AUX ) control node. The first end of the capacitor C' is coupled to the auxiliary transistor (eg, PMOS transistor M') AUX ), the second end of the capacitor C' is coupled to a reference voltage (eg, ground voltage V PGND ). After reading the above paragraphs about the protection circuit 706, those skilled in the art can easily understand the principle of the protection circuit 906. For the sake of brevity, further description is omitted here.

[0047] Alternatively, the auxiliary transistor (eg, PMOS transistor M′) in the protection circuit 906 may be AUX ) can be determined by the voltage level V at the control node of the auxiliary transistor AVDD,RC and the voltage level V at the first connection node of the switch circuit 202PVDD,IN This is achieved by selectively turning on a PNP bipolar transistor or other transistor by the difference between the two.

[0048] about Figure 2 , Figure 6 , Figure 7 and Fig. 9 In the embodiment shown in FIG. 1 , each of the proposed protection circuits 206, 606, 706, and 906 is designed to provide SOA protection to the high-side (HS) switch circuit 202. However, these are for illustrative purposes only and are not meant to be limiting of the present invention. The same SOA protection design can be used to provide SOA protection to the low-side (LS) switch circuit 204.

[0049] Fig.10 is a circuit diagram illustrating a first switching regulator with low-side SOA protection according to an embodiment of the present invention. Figure 1 The illustrated switching regulator 102 may be implemented using a switching regulator 1000. The main difference between the switching regulators 200 and 1000 is that the switching regulator 1000 includes a protection circuit 1006 arranged to sense a voltage level V at a first connection node of the switching circuit 204. PGND,IN And in response to the voltage level V at the first connection node of the switch circuit 204 PGND,IN The auxiliary current path 1008 is selectively enabled, wherein the auxiliary current path 1008 and the switch circuit 204 are arranged in a parallel connection. In this embodiment, the protection circuit 1006 is implemented by an auxiliary transistor, which is an NMOS transistor MN AUX , with its source coupled to pin 118 , its drain coupled to pin 120 , and its gate coupled to pin 114 .

[0050] Please combine Fig.11 refer to Fig.10 . Fig.11 It is shown Fig.10 FIG. 1 is a schematic diagram of a switching regulator 1000 operating during a first period in a voltage regulation cycle. During the first period in the voltage regulation cycle, the switch circuit 204 (specifically, the NMOS transistor M LS ) is turned on, and the switch circuit 202 (specifically, the PMOS transistor M HS ) is turned off. Therefore, the switching regulator 1000 generates a current flowing through the inductor L, the switch circuit 204 (specifically, the NMOS transistor M LS ) and parasitic inductor L LS,par The current I L In this way, the pulse voltage VLX Since the voltage level V at the first connection node of the switch circuit 204 is PGND,IN is approximately equal to the ground voltage V received by the protection circuit 1006 AGND Therefore, the protection circuit 1006 (specifically, the NMOS transistor MN AUX ) is turned off, meaning that the auxiliary current path 1008 between the first connection node and the second connection node of the switch circuit 204 is not enabled.

[0051] Please combine Fig.12 refer to Fig.10 . Fig.12 It is shown Fig.10 Schematic diagram of the switching regulator 1000 in FIG. 1000 operating during a second period in a voltage regulation cycle. During the second period immediately following the first period, the switch control signal S2 is set to turn off the switch circuit 204 (specifically, the NMOS transistor M LS ), the switch control signal S1 is set to turn on the switch circuit 202 (specifically, the PMOS transistor M HS Therefore, the switching regulator 1000 generates a current flowing through the inductor L, the switch circuit 202 (specifically, the PMOS transistor M HS ) and parasitic inductor L HS,par The current I L Therefore, the pulse voltage V LX From a low voltage level to a high voltage level. Since the switch circuit 204 (specifically, the NMOS transistor M LS ) is controlled to be off and flows through the parasitic inductor L LS,par The current should be continuous, so the parasitic inductor L LS,par There is still current I LS,par Thus, the voltage level V at the first connection node of the switch circuit 204 is reduced. PGND,IN In the case where the proposed protection circuit 1006 is omitted, the voltage level V at the first connection node of the switch circuit 204 is PGND,IN is significantly pulled low. Therefore, the NMOS transistor M LS The absolute value of the drain-source voltage of the NMOS transistor M will exceed the SOA voltage, causing LS damage.

[0052] To solve this problem, the proposed protection circuit 1006 is implemented to provide SOA protection. LS,par Through the parasitic inductor L LS,par When the voltage level V at the first connection node of the switch circuit 204 is PGND,IN reduced to below that of the NMOS transistor MN AUXThe gate voltage is the ground voltage V AGND , and the NMOS transistor MN AUX The absolute value of the gate-source voltage of the NMOS transistor MN increases accordingly. AUX The absolute value of the gate-source voltage of the NMOS transistor MN AUX Threshold voltage |V TH | absolute value, the protection circuit 1006 (specifically, the NMOS transistor MN AUX ) is automatically turned on, thereby enabling the auxiliary current path 1008 between the first connection node and the second connection node of the switch circuit 204. In other words, the protection circuit 1006 is I LS,par Provides another current path. Due to the auxiliary current I AUX (Current I LS,par A portion of the current (i) flows through the auxiliary current path 1008, thereby alleviating the voltage bounce at the first connection node of the switch circuit 204. In this way, the NMOS transistor M LS The absolute value of the drain-source voltage will not exceed the SOA voltage.

[0053] exist Fig.10 In the above embodiment shown in FIG. 1 , the protection circuit 1006 is composed of an NMOS transistor MN AUX However, this is for illustrative purposes only and is not intended to limit the present invention. Alternatively, the protection circuit 1006 may be configured to be able to provide a voltage level according to the auxiliary reference voltage (e.g., V AGND ) and the voltage level V at the first connection node of the switch circuit 204 PVDD,IN This is achieved by selectively turning on a PNP bipolar transistor or other transistor by the difference between the two.

[0054] Fig.13 1 is a schematic diagram showing a second switching regulator with low-side SOA protection according to an embodiment of the present invention. The main difference between the switching regulators 1000 and 1300 is that the switching regulator 1300 has a protection circuit 1306 implemented by an auxiliary transistor, which is an NMOS transistor MN′. AUX , whose source is coupled to pin 118, drain is coupled to pin 116 and gate is coupled to pin 114. Therefore, when auxiliary current path 1308 is enabled, parasitic inductor L LS,par The power on the switching regulator 1300 will not be circulated to the output of the switching regulator 1300. Alternatively, the protection circuit 1306 can be composed of a circuit that can be based on an auxiliary reference voltage (e.g., V AGND ) and the voltage level V at the first connection node of the switch circuit 204 PVDD,IN This is achieved by selectively turning on a PNP bipolar transistor or other transistor by the difference between the two.

[0055] Fig.14 1 is a schematic diagram showing a third switching regulator with low-side SOA protection according to an embodiment of the present invention. The main difference between the switching regulators 1000 and 1400 is that the switching regulator 1400 has a protection circuit 1406, which includes a resistor-capacitor (RC) circuit 1407 and the aforementioned auxiliary transistor (e.g., NMOS transistor MN AUX ). The RC circuit 1407 includes a resistor R and a capacitor C. A first end of the resistor R is coupled to an auxiliary reference voltage (eg, a ground voltage V AGND ), the second end of the resistor R is coupled to an auxiliary transistor (eg, an NMOS transistor MN AUX ) control node. The first end of the capacitor C is coupled to the auxiliary transistor (eg, NMOS transistor MN AUX ), and the second end of the capacitor C is coupled to one end of the inductor L. Alternatively, the auxiliary transistor (eg, NMOS transistor MN) in the protection circuit 1406 AUX ) can be determined by the voltage level V at the control node of the auxiliary transistor AGND,RC The voltage level V at the first connection node of the switch circuit 204 PVDD,IN This is achieved by selectively turning on a PNP bipolar transistor or other transistor by the difference between the two.

[0056] During the second period of the voltage regulation cycle, the switch control signal S2 is set to turn off the switch circuit 204 (specifically, the NMOS transistor M2). LS ), the switch control signal S1 is set to turn on the switch circuit 202 (specifically, the PMOS transistor M HS ). Therefore, the pulse voltage V LX Has a transition from a low voltage level to a high voltage level. Due to the pulse voltage V LX The RC circuit 1407 is coupled to the auxiliary transistor (eg, NMOS transistor MN AUX ) of the control node, therefore, the auxiliary transistor (eg, NMOS transistor MN AUX )'s control node voltage level V AGND,RC Since the pulse voltage V LX At voltage level V AGND,RC Pulse voltage V LX After being temporarily pulled high, it will be connected to the auxiliary reference voltage (for example, the ground voltage V AGND ) is pulled low.

[0057] When the voltage level V AGND,RC Pulse voltage V LX When temporarily pulled high, the NMOS transistor MNAUX The gate-source voltage of the switch circuit 204 increases, resulting in a higher current density on the auxiliary current path 1008. Therefore, the current flowing through the auxiliary current path 1008 increases, resulting in a voltage level V PGND,IN Therefore, due to the small voltage reduction of the NMOS transistor M LS The smaller absolute value of the drain-source voltage of the switch circuit 204 reduces the voltage bounce at the first connection node of the switch circuit 204. Compared with the design of the protection circuit 1006, the design of the protection circuit 1406 can be the switch circuit 204 (especially the NMOS transistor M LS ) provides better SOA protection.

[0058] Fig.15 1 is a schematic diagram showing a fourth switching regulator with low-side SOA protection according to an embodiment of the present invention. The main difference between the switching regulators 1300 and 1500 is that the switching regulator 1500 has a protection circuit 1506, which includes a resistor-capacitor (RC) circuit 1507 and the above-mentioned auxiliary transistor (e.g., NMOS transistor M′). AUX ). The RC circuit 1507 includes a resistor R' and a capacitor C'. A first end of the resistor R' is coupled to an auxiliary reference voltage (eg, a ground voltage V AGND ), the second end of the resistor R' is coupled to the auxiliary transistor (eg, NMOS transistor MN' AUX ) control node. The first end of the capacitor C' is coupled to the auxiliary transistor (eg, NMOS transistor MN') AUX ), the second end of the capacitor C' is coupled to a reference voltage (eg, a power supply voltage V PVDD Alternatively, the auxiliary transistor (eg, NMOS transistor MN′) in the protection circuit 1506 may be AUX ) can be determined by the voltage level V at the control node of the auxiliary transistor AGND,RC The voltage level V at the first connection node of the switch circuit 204 PVDD,IN The invention can be realized by a PNP bipolar transistor or other transistor that is selectively turned on according to the difference between the protection circuit 1406 and the protection circuit 1506. After reading the above paragraphs about the protection circuit 1406, those skilled in the art will easily understand the principle of the protection circuit 1506. For the sake of brevity, further description is omitted here.

[0059] In the above embodiments, the switch circuits 202 and 204 can be implemented by MOS transistors. However, these are only for illustration and are not meant to limit the present invention. Alternatively, at least one of the switch circuits 202 and 204 can be implemented by a diode or a Schottky diode. In short, the present invention has no restrictions on the implementation of the switch circuits 202 and 204. Therefore, each switch circuit 202 and 204 can be implemented by any circuit element with a switchable conductive state. These alternative designs all fall within the scope of the present invention.

[0060] Those skilled in the art will readily recognize that various modifications and variations can be made to the apparatus and method while maintaining the teachings of the present invention. Therefore, the above disclosure should be interpreted as being limited only by the appended claims.

Claims

1. A switching regulator, comprising: A first switch circuit, a first connection node of which is coupled to a first reference voltage, and a second connection node of which is coupled to a first end of the inductor; a second switch circuit having a first connection node coupled to a second reference voltage different from the first reference voltage and a second connection node coupled to the first end of the inductor; as well as a protection circuit arranged to receive an auxiliary reference voltage and the first reference voltage and selectively enable an auxiliary current path in response to the auxiliary reference voltage and the first reference voltage, wherein the auxiliary current path and at least the first switch circuit are arranged in a parallel connection; The auxiliary reference voltage is constant, or the auxiliary reference voltage is a reference voltage provided to a controller, wherein the controller is used to control the on and off of the first switch circuit and the second switch circuit.

2. The switching regulator according to claim 1, wherein: The first reference voltage is a power supply voltage, and the second reference voltage is a ground voltage.

3. The switching regulator according to claim 1, wherein: The first reference voltage is a ground voltage, and the second reference voltage is a power supply voltage.

4. The switching regulator according to claim 1, wherein: The protection circuit automatically enables the auxiliary current path according to a difference between the auxiliary reference voltage and the first reference voltage.

5. The switching regulator according to claim 4, wherein: The switching regulator is implemented in a chip, the protection circuit receives the auxiliary reference voltage through one pin of the chip, and the first switch circuit receives the first reference voltage through another pin of the chip.

6. The switching regulator according to claim 5, wherein: A noise level of the auxiliary reference voltage is lower than a noise level of the first reference voltage.

7. The switching regulator according to claim 1, wherein: The protection circuit comprises: An auxiliary transistor has a control node arranged to receive the auxiliary reference voltage, a first connection node coupled to the first connection node of the first switch circuit, and a second connection node coupled to the first end of the inductor.

8. The switching regulator according to claim 7, wherein: The auxiliary transistor is a PMOS transistor.

9. The switching regulator according to claim 7, wherein: The protection circuit further comprises: A resistor-capacitor RC circuit having a resistor and a capacitor, wherein a first end of the resistor is coupled to the auxiliary reference voltage, a second end of the resistor is coupled to the control node of the auxiliary transistor, a first end of the capacitor is coupled to the control node of the auxiliary transistor, and a second end of the capacitor is coupled to the first end of the inductor.

10. The switching regulator according to claim 4, wherein: The protection circuit comprises: An auxiliary transistor, a control node of which is arranged to receive the auxiliary reference voltage, a first connection node of which is coupled to the first connection node of the first switch circuit, and a second connection node of which is coupled to the second reference voltage.

11. A power management integrated circuit, comprising: A first pin, used for receiving a first reference voltage; A second pin, used to receive a second reference voltage different from the first reference voltage; The third pin is used to output pulse voltage; as well as A switching regulator, used to generate the pulse voltage, wherein the switching regulator comprises: A first switch circuit, a first connection node of which is coupled to the first pin, and a second connection node of which is coupled to the third pin; a second switch circuit, a first connection node of which is coupled to the second pin, and a second connection node of which is coupled to the third pin; and a protection circuit for receiving an auxiliary reference voltage and the first reference voltage and selectively enabling an auxiliary current path in response to the auxiliary reference voltage and the first reference voltage, wherein the auxiliary current path and at least the first switch circuit are arranged in a parallel connection; The auxiliary reference voltage is constant, or the auxiliary reference voltage is a reference voltage provided to a controller, wherein the controller is used to control the on and off of the first switch circuit and the second switch circuit.

12. The power management integrated circuit according to claim 11, wherein: The first reference voltage is a power supply voltage, and the second reference voltage is a ground voltage.

13. The power management integrated circuit according to claim 11, wherein: The first reference voltage is a ground voltage, and the second reference voltage is a power supply voltage.

14. The power management integrated circuit according to claim 11, further comprising: A fourth pin, used for receiving the auxiliary reference voltage; The protection circuit is further coupled to the fourth pin, and automatically enables the auxiliary current path according to a difference between the auxiliary reference voltage and a voltage level at the first connection node of the first switch circuit.

15. The power management integrated circuit according to claim 14, wherein: A noise level of the auxiliary reference voltage is lower than a noise level of the first reference voltage.

16. The power management integrated circuit according to claim 14, wherein: The protection circuit comprises: The auxiliary transistor has a control node coupled to the fourth pin, a first connection node coupled to the first connection node of the first switch circuit, and a second connection node coupled to the third pin.

17. The power management integrated circuit according to claim 16, wherein: The auxiliary transistor is a PMOS transistor.

18. The power management integrated circuit according to claim 16, wherein: The protection circuit further comprises: A resistor-capacitor RC circuit having a resistor and a capacitor, wherein a first end of the resistor is coupled to the fourth pin, a second end of the resistor is coupled to the control node of the auxiliary transistor, a first end of the capacitor is coupled to the control node of the auxiliary transistor, and a second end of the capacitor is coupled to the third pin.

19. The power management integrated circuit according to claim 14, wherein: The protection circuit comprises: An auxiliary transistor has a control node coupled to the fourth pin, a first connection node coupled to the first connection node of the first switch circuit, and a second connection node coupled to the second pin.

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