A driving circuit, a chip, a load driving circuit and a lighting device

Abstract

The present invention discloses a driving circuit, a chip, a load driving circuit and a lighting device, belonging to the field of driving circuits. Aiming at the problems of complex circuits and the need for jumper wires in the prior art, the present solution provides a driving circuit, a chip, a load driving circuit and a lighting device. The driving circuit includes at least one corresponding first end and second end, and further includes at least one power terminal. The power terminal outputs a power current for driving an external load. At least one of the first end, the second end, and between the first end and the second end receives an excitation signal, and a current monotonically changing with the excitation signal is generated at the power terminal. The chip formed by the driving circuit includes at least one power pin, a chip ground, at least one first pin and / or at least one second pin. Through the optimized configuration of the chip pins, it is used for the load driving circuit and the lighting device, realizing a simple circuit, reducing jumper wires, and lowering the costs of the circuit and the device.

Description

Technical Field

[0001] The present invention relates to the field of driving circuits, and more specifically, to a driving circuit, a chip, a load driving circuit, and a lighting device. Background Art

[0002] In the existing high-power LED lighting driving circuit, the rated power of a single linear constant-current driving chip usually cannot meet the usage requirements, and multiple linear constant-current driving chips often need to be connected in parallel to form a multi-chip parallel LED lighting circuit to expand the power.

[0003] In the existing multi-chip parallel LED lighting circuit, the linear constant-current driving chip ensures that the current flowing through each light-emitting diode is a constant current. Considering the heat dissipation of the linear constant-current driving chip, multiple linear constant-current driving chips are usually surface-mounted and soldered on the same single-sided copper-clad aluminum substrate, so that jumper wires are required at the multi-chip wire crossing points, increasing the cost and the circuit board area, and at the same time reducing the reliability of the multi-chip parallel LED lighting circuit and being prone to short circuits. And because the working peripheral circuits are diverse, common ones such as current setting circuits, loop compensation circuits, filtering circuits, detection circuits, and abnormal protection circuits, etc., correspondingly, the peripheral circuits corresponding to multiple groups of chips also need to be used together, which results in a very complex peripheral circuit. How to improve the problem of the existing complex peripheral circuit is an urgent problem to be solved. Summary of the Invention

[0004] 1. Technical Problems to be Solved

[0005] Aiming at the problems of complex circuits, the need for jumper wires, high power consumption, etc. in the prior art, the present invention provides a driving circuit, a chip, a load driving circuit, and a lighting device. The driving circuit in the present invention can reduce the jumper wires of the driving circuit. Through the designed driving circuit and corresponding chip, the application circuit is made simpler and the cost is lower.

[0006] The present invention also provides a chip. Through the reasonable design of the chip pins, when using this solution, there are fewer jumper wires in the overall external circuit, reducing the process load and the design and manufacturing costs. For the load driving circuit and the lighting device, based on the overall cost reduction of the driving circuit and the chip.

[0007] 2. Technical Solutions

[0008] The object of the present invention is achieved by the following technical solutions.

[0009] A driving circuit includes at least one corresponding pair of a first terminal and a second terminal, and also includes at least one power terminal. The power terminal outputs a power current for driving an external load. At least one of the first terminal, the second terminal, and between the first terminal and the second terminal receives an excitation signal, and the excitation signal is a voltage signal, a current signal, or a combination of a voltage signal and a current signal. The power terminal generates a current that has a monotonic variation relationship with the excitation signal.

[0010] Further, the first terminal is connected to the second terminal through an electrical connection part, and the electrical connection part is at least one of three cases: a wire, a combination of one resistor or multiple resistors, and a combination of one transistor or multiple transistors.

[0011] Further, the current of the power terminal is generated by a voltage-controlled current source or a current mirror, and the voltage-controlled current source or the current mirror samples the excitation signal from the first terminal and / or the second terminal.

[0012] A cascaded driving circuit includes a first driving circuit, a last driving circuit, and n intermediate driving circuits. The first driving circuit, the last driving circuit, and the intermediate driving circuits are based on any one of the above-mentioned driving circuits, where n is a natural number. The power terminals corresponding to the first driving circuit, the last driving circuit, and the intermediate driving circuits are respectively connected in parallel;

[0013] The second terminal of the first driving circuit is connected to the first terminal of the first intermediate driving circuit. The second terminal of the previous intermediate driving circuit and the first terminal of the next intermediate driving circuit are connected in series in sequence. The second terminal of the last intermediate driving circuit is connected to the first terminal of the last driving circuit to form an electrical path. Each driving circuit obtains the excitation signal on the electrical path and outputs a current at the power terminal.

[0014] A chip uses any one of the above-mentioned driving circuits, and the chip includes a chip ground.

[0015] Further, there is at least one power pin, and the power pin is internally connected to the corresponding power terminal of the driving circuit; and,

[0016] There is at least one first pin, and each first pin is internally connected to the corresponding first terminal of the driving circuit

[0017] and / or

[0018] It includes at least one second pin, and each second pin is internally connected to the corresponding second terminal of the driving circuit.

[0019] Further, when the chip includes both the first pin and the second pin at the same time, the geometric connection line between the first pin and the corresponding second pin is a first geometric connection line. Several groups of first pins and second pins form several first geometric connection lines, and each first geometric connection line and at least one of the other first geometric connection lines do not cross each other;

[0020] When there is one power pin, the power pin is the first power pin, and the first power pin is arranged on one side of all the first geometric connections;

[0021] Or

[0022] When there are two power pins, one power pin is the first power pin and the other is the second power pin. The first power pin and the second power pin are respectively internally connected to two power terminals of the drive circuit, and the first power pin and the second power pin are respectively arranged on both sides of all the first geometric connections;

[0023] Or

[0024] When the drive circuit of the chip has more than three power terminals, the chip includes at least one intermediate power pin and / or at least one corresponding auxiliary intermediate power pin;

[0025] When including both the intermediate power pins and the auxiliary intermediate power pins at the same time, each group of intermediate power pins and auxiliary intermediate power pins are jointly connected to one power terminal inside the chip. The intermediate power pin and the corresponding auxiliary intermediate power pin form a second geometric connection. Several groups of intermediate power pins and corresponding auxiliary intermediate power pins form several second geometric connections. At least one of all the second geometric connections does not cross at least one of all the first geometric connections. A third geometric connection is formed between the first power pin and the second power pin, and the second geometric connection crosses the third geometric connection.

[0026] Furthermore, it also includes a first jumper pin and / or a second jumper pin. The first jumper pin and / or the second jumper pin are connected to the chip ground or are floating. When including both the first jumper pin and the second jumper pin at the same time, a fourth geometric connection is formed between the first jumper pin and the second jumper pin;

[0027] The fourth geometric connection does not cross at least one of all the first geometric connections;

[0028] When there is at least one second geometric connection formed by an intermediate power pin and a corresponding auxiliary intermediate power pin, the fourth geometric connection does not cross at least one of all the second geometric connections;

[0029] When there is a third geometric connection formed between the first power pin and the second power pin, the fourth geometric connection crosses the third geometric connection.

[0030] Furthermore, the chip also includes at least a part of an excitation circuit for generating an excitation signal.

[0031] A load drive circuit

[0032] It includes a first chip, a last chip and n intermediate chips. The first chip, the last chip and the intermediate chips are any one of the above-mentioned chips, and n is a natural number.

[0033] The chip grounds of the first chip, the last chip and the intermediate chips are connected in parallel; the power pins corresponding to the first chip, the last chip and the intermediate chips are respectively connected in parallel for driving an external load.

[0034] The intermediate chip includes at least one group of first pins and second pins. The first chip includes at least one second pin. The last chip includes at least one first pin. The second pin of the first chip is connected to the first pin of the first intermediate chip. The second pin of the previous intermediate chip and the first pin of the next intermediate chip are connected in series in sequence. The second pin of the last intermediate chip is connected to the first pin of the last chip to form an electrical path. The excitation signal generates excitation for the first end and the second end of the drive circuits in all the chips on the electrical path.

[0035] Furthermore, the second jumper pin of the first chip is connected to the chip ground.

[0036] and / or

[0037] The second jumper pin of the last chip is floating or grounded.

[0038] Furthermore, the load includes at least one LED unit group, and the LED unit group is composed of one LED or multiple LEDs.

[0039] A lighting device includes any one of the above-mentioned drive circuits, cascaded drive circuits, chips or load drive circuits.

[0040] The aforementioned voltage-controlled current source functions to receive an input voltage signal and generate one or more current signals that vary monotonically with the input voltage signal, and the same applies hereinafter.

[0041] The aforementioned current mirror functions to receive an input current signal and generate one or more current signals that vary monotonically with the input current signal, and the same applies hereinafter.

[0042] The aforementioned monotonic variation relationship includes positive monotonic variation and inverse monotonic variation. Positive monotonic variation means that when the input signal increases, the output signal increases accordingly, or when the input signal decreases, the output signal decreases accordingly; inverse monotonic variation means that when the input signal increases, the output signal decreases accordingly, or when the input signal decreases, the output signal increases accordingly. For example, the output signal is configured as a linear function of the input signal. The same applies hereinafter.

[0043] 3. Advantageous Effects

[0044] Compared with the prior art, the advantages of the present invention are as follows:

[0045] Through the reasonable configuration of the internal circuit of the chip, all the first terminals IM and the second terminals IO on the electrical path are excited by the excitation signal, effectively driving the overall load circuit, especially the LED load driving circuit. When actually wiring, the situation of jumper wires is avoided as much as possible. In the most ideal case, jumper wires can be eliminated, making the design of the overall application layer based on this driving circuit and chip simpler, and greatly reducing the material cost, production cost and labor cost. The overall application board has good compactness and is more suitable for market demand. Brief Description of the Drawings

[0046] Figure 1 It is a schematic structural diagram of a driving circuit of the present invention;

[0047] Figure 2 It is another schematic structural diagram of a driving circuit of the present invention;

[0048] Figure 3 It is still another schematic structural diagram of a driving circuit of the present invention;

[0049] Figure 4 It is a schematic structural diagram of a cascade driving circuit of the present invention;

[0050] Figure 5 It is another schematic structural diagram of a cascade driving circuit of the present invention;

[0051] Figure 6 It is still another schematic structural diagram of a cascade driving circuit of the present invention;

[0052] Figure 7 It is a schematic structural diagram of a chip of the present invention;

[0053] Figure 8 It is another schematic structural diagram of a chip of the present invention;

[0054] Figure 9 It is still another schematic structural diagram of a chip of the present invention;

[0055] Figure 10 It is a schematic diagram of a geometric connection for explaining the pin arrangement position of the present invention;

[0056] Figure 11 It is another schematic diagram of a geometric connection for explaining the pin arrangement position of the present invention;

[0057] Figure 12 It is a schematic structural diagram of a load driving circuit of the present invention;

[0058] Figure 13 It is the second schematic structural diagram of a load driving circuit of the present invention;

[0059] Figure 14 This is the third structural schematic diagram of the load driving circuit of the present invention;

[0060] Figure 15 This is the schematic diagram of the load additional structure of the present invention. Detailed implementation manners

[0061] The present invention will be described in detail below in conjunction with the accompanying drawings of the specification and specific embodiments.

[0062] Embodiment

[0063] The content described below is not restrictive. Without departing from the spirit or basic characteristics of the present invention, the present invention can be implemented in other specific forms. What is shown in the drawings is only one of the implementation manners of the present invention, and the actual structure is not limited thereto. Any reference numeral in the claims should not limit the claimed claim. Therefore, if those skilled in the art are inspired by it and design similar structural manners and embodiments without creative efforts without departing from the purpose of this creation, they shall fall within the protection scope of this patent. The word "comprising" does not exclude other elements or steps, and the word "a" before an element does not exclude including "a plurality of" such elements. The plurality of elements stated in the product claims can also be implemented by one element through software or hardware. First, second, etc. are used to represent names and do not represent any specific order.

[0064] This solution proposes a corresponding driving circuit, including at least one set of corresponding first end and second end, further including at least one power terminal, outputting at least one path of power current to drive an external load. At least one of the first end, the second end, and between the first end and the second end receives an excitation signal, and the excitation signal is a voltage signal, a current signal, or a combination of a voltage signal and a current signal. The power terminal generates a current that changes monotonically with the excitation signal. In actual work, the first end is used to detect various external signals and reflect them to the second end. The first end is connected to the second end through an electrical connection part, and the electrical connection part is at least one of three cases: a wire, a resistor, or a series connection of multiple resistors, a transistor, or a combination of multiple transistors.

[0065] Embodiment 1

[0066] As Figure 1As shown, the structure of a driving circuit of the present invention includes a first terminal IM and a second terminal IO. Among them, IM and IO are short-circuited, and at this time, the electrical connection part is a wire. IO completely reflects the signal of IM, and the two are the same voltage signal VOM. VOM is an externally applied excitation signal. Voltage-controlled current sources VI1, VI2, and VI3 sample the excitation signal VOM from the first terminal and / or the second terminal, and generate currents that have a monotonic change relationship with VOM at the power terminals D1, D2, and DN respectively. That is, when the voltage signal VOM increases, the currents of the power terminals D1, D2, and DN all increase. Conversely, when the voltage signal VOM decreases, the currents of the power terminals D1, D2, and DN all decrease.

[0067] Embodiment 2

[0068] As Figure 2 As shown, another structure of the driving circuit of the present invention includes a first terminal IM and a second terminal IO. Among them, IM and IO are connected through a resistor, or a combination of multiple resistors in series and parallel is used. An excitation signal is applied across IM and IO to form a voltage difference between the first terminal and the second terminal, that is, a voltage signal VD is generated across the resistor R. Voltage-controlled current sources VIA-1, VIA-2, and VIA-3 sample the voltage signal VD from the first terminal and / or the second terminal, and generate currents that have a monotonic change relationship with VD at the power terminals D1, D2, and DN respectively. That is, when the voltage signal VD increases, the currents of the power terminals D1, D2, and DN all increase. Conversely, when the voltage signal VD decreases, the currents of the power terminals D1, D2, and DN all decrease. Figure 2 It can also be explained that the resistor R and the voltage-controlled current sources VIA-1, VIA-2, and VIA-3 constitute a current mirror. The excitation signal passes through a current signal IR between the first terminal and the second terminal. The resistor R detects the current signal IR, forms a voltage difference VD, and then, through the voltage-controlled current sources VIA-1, VIA-2, and VIA-3, generates currents that have a monotonic change relationship with IR at the power terminals D1, D2, and DN. That is, when the current IR increases, the currents at the power terminals D1, D2, and DN all increase. Conversely, when the voltage IR decreases, the currents at the power terminals D1, D2, and DN all decrease.

[0069] Embodiment 3

[0070] As Figure 3As shown, another structure of the driving circuit of the present invention includes a first terminal IM and a second terminal IO. Among them, the electrical part between IM and IO is the input terminal IA of the current mirror, and IA can be composed of one or more transistors. When an excitation signal generates a current on IA, the currents of the power terminals D1, D2, and DN are converted through the output terminals IA-1, IA-2, and IA-3 of the current mirror, and a current showing a monotonic change relationship with IA is output. That is, when the current IA increases, the currents output by the power terminals D1, D2, and DN all increase; conversely, when the current IA decreases, the currents output by the power terminals D1, D2, and DN all decrease.

[0071] For Embodiment 1 and its corresponding Figure 1 、Embodiment 2 and its corresponding Figure 2 and Embodiment 3 and its corresponding Figure 3 , it only illustrates the monotonic change relationship between the power terminal current and the signals at the first terminal and the second terminal, and does not limit the specific implementation circuit. Those skilled in the art can use any other scheme to achieve the same effect without departing from the protection scope of the present invention. In addition, for a better understanding of the above embodiments, the following supplementary explanations are provided:

[0072] In the actual product design, the currents of the power terminals D1, D2, and D3 can also be controlled by other signals or circuits. For example, a signal related to temperature is sampled. When the temperature exceeds a predetermined value, the currents of D1, D2, and D3 are directly or indirectly reduced or turned off to avoid overheating.

[0073] The number of power terminals is not limited to 3, and can be one, two, or more. In addition, in some applications, some power terminals need to be output through the intermediate power terminals and auxiliary power terminals connected thereto, such as Figure 1 、 Figure 2 and 3 DN and DN1 in.

[0074] According to needs, there can be multiple groups of first terminals and second terminals to receive multiple excitation signals, and the excitation signals are converted by multiple groups of voltage-controlled current sources or current mirrors to generate currents at the power terminals. There can also be multiple groups of power terminals, and each group can be one or more. The number of multiple groups of excitation signals and multiple groups or multiple power terminals can be designed in multiple corresponding modes, which is not limited by the embodiments of the present invention.

[0075] The beneficial effects of the above embodiments are as follows: Through the above embodiments, the current of the power terminal can be controlled by any one of the excitation signals such as the voltage signal, current signal, and / or the combined signal of the two applied between the first terminal, the second terminal, and between the first terminal and the second terminal. Through the above circuit forms, corresponding driving circuits, cascaded driving circuits, chips, and load driving circuits can be selectively constructed directly in terms of circuits.

[0076] Embodiment 4

[0077] As shown in Figure 4 , based on the above driving circuit, a corresponding cascaded driving circuit can be designed, including a first driving circuit, a last driving circuit, and an intermediate driving circuit. Among them, the power terminals corresponding to all driving circuits are connected in parallel; the first terminal IM and the second terminal IO are connected in series in sequence. The second terminal IO of the first driving circuit is connected to the first terminal IM of the intermediate driving circuit, the second terminal IO of the intermediate driving circuit is connected to the first terminal IM of the last driving circuit, and the second terminal IO of the last driving circuit is left floating, forming an electrical path starting from the first terminal IM of the first driving circuit and ending at the second terminal IO of the last driving circuit. All the first terminals IM and second terminals IO on this electrical path are connected in series to receive an excitation signal; the excitation signal A1 is a circuit unit, whose output is a voltage with one end connected to one end of the electrical path and the other end grounded, generating the same excitation voltage signal on the first terminal IM and the second terminal IO of each driving circuit. Each driving circuit generates a current that has a monotonic variation relationship with the excitation signal at each power terminal according to Figure 1 the working principle described above.

[0078] Embodiment 5

[0079] As shown in Figure 5 , another structure of the cascaded driving circuit includes a first driving circuit, a last driving circuit, and an intermediate driving circuit. Among them, the power terminals corresponding to all driving circuits are connected in parallel; the first terminal IM and the second terminal IO are connected in series in sequence. The second terminal of the first driving circuit is connected to the first terminal of the intermediate driving circuit, and the second terminal of the intermediate driving circuit is connected to the first terminal of the last driving circuit, forming an electrical path starting from the first terminal of the first driving circuit and ending at the second terminal of the last driving circuit. All the first terminals IM and second terminals IO on this electrical path are connected in series to receive an excitation signal; the excitation signal S1 is a circuit unit, whose output can be a voltage signal, a current signal, or a combination of both, and is connected in parallel across the electrical path, generating an excitation current and an excitation voltage on the first terminal IM and the second terminal IO of each driving circuit. Each driving circuit generates a current that has a monotonic variation relationship with the excitation signal at each power terminal according to Figure 2 the working principle described above.

[0080] In specific applications, the excitation signal can also be generated by multiple circuit units. For example, Figure 6 shows another structural schematic diagram of a decentralized configuration scheme. Based on Figure 5 , a voltage source V2 is additionally set accordingly. Of course, there are more variations, mainly configured adaptively according to requirements and schemes. For example, a current source can be alternately connected in parallel to the first terminal and the second terminal of each driving circuit to alternately change the current at the power terminal of each driving circuit.

[0081] Example 4 and its corresponding Figure 4 , Example 5 and its corresponding Figure 5 and Figure 6 , may also not include an intermediate drive circuit, or include more stages of drive circuits.

[0082] In practical applications, the excitation signal can be designed to be related to the bus voltage, so that the current shape at the power terminal of each drive circuit follows the shape of the bus voltage, which can optimize the power factor in applications powered by the mains supply; for another example, the output signal can also be designed to be controlled by a device such as a CPU to achieve a preset function.

[0083] Correspondingly, corresponding designs are made, and the above circuit is applied to a chip. The chip adopts any one of the above drive circuits, and the chip includes a chip ground.

[0084] The chip is configured in a form with pins on both sides, or can also be set in other types of package structures, such as a form with pins on two adjacent sides or even three sides or four sides;

[0085] Among them, the chip structure includes at least one power pin, and the power pin is internally connected to the corresponding power terminal of the drive circuit; and,

[0086] at least one first pin, and each first pin is internally connected to the corresponding first end of the drive circuit

[0087] and / or

[0088] includes at least one second pin, and each second pin is internally connected to the corresponding second end of the drive circuit.

[0089] The specific pin method can be set according to requirements. When it is the first chip of an overall circuit, there can be only second pins and no first pins. When it is the last chip of an overall circuit, there can be only first pins and no second pins. The intermediate chips have both first pins and second pins.

[0090] Example 6

[0091] For the above embodiments of the drive circuit, the pins with different designs are respectively applicable to the chips at different positions in the overall circuit. Figure 7 The chip setting in Figure 8 is applicable to the first chip of a cascaded circuit for driving a load. Figure 9 is applicable to the intermediate chip.

[0092] Figure 7In [the figure], it is a schematic diagram of a chip with a certain structure, including a second pin IO, a first power pin D1, a second power pin D2, an intermediate power pin DN, and a second jumper pin JP2, a total of 5 pins. The chip contains part or all of the excitation circuits. In theory, if the chip contains all the excitation circuits, the first pin IM of the chip can exist only inside the chip without being led out by the chip pins. In practice, usually part of the excitation circuits need to be designed outside to use the chip flexibly. Therefore, Figure 7 the remaining pins other than the above 5 pins are not given in [the figure], and the remaining pin configurations can be designed according to the actual situation.

[0093] Figure 8 In [the figure], it is a schematic diagram of another chip structure, including a first jumper pin JP1, a second jumper pin JP2, a first pin IM, a second pin IO, a first power pin D1, a second power pin D2, an intermediate power pin DN, and an auxiliary intermediate power pin DN1; a first jumper pin JP1 and a second jumper pin JP2, a first pin IM and a second pin IO, the intermediate power terminal and the auxiliary intermediate power pin form three groups of pins, and the geometric connections formed by the three groups of pins do not cross each other, which is beneficial to the copper foil routing at the circuit board level when multiple chips are cascaded. Regarding the geometric connections, other parts of this specification have detailed descriptions.

[0094] Figure 9 The chip structure of [the invention] adopts Figure 4 the cascaded drive circuit form shown in [the figure], the second pin IO of the tail chip is floating, and this pin can be omitted; when adopting Figure 5 and Figure 6 the cascaded drive circuit forms shown in [the figure], the second pin IO of the tail chip needs to be connected to the chip ground, or can also be connected to a fixed level. Through internal settings of the chip, this pin can also be omitted; in addition, one of the purposes of the first jumper pin and the second jumper pin set in the present invention is to use it on the circuit board to connect the chip grounds between the chips corresponding to each cascaded drive circuit, which is applicable to the occasions where the connection of the chip grounds of different chips on the circuit board is restricted, such as a circuit board with single-sided wiring or an application where there is a heat dissipation metal under the chip package and it is not conducive to wiring. The intermediate chips especially need this function, but the tail chip can not use this function. In other words, the second jumper pin of the tail chip can not be used, and therefore, this pin can also be omitted. Figure 9 In [the figure], it includes a first jumper pin JP1, a first pin IM, an intermediate power pin DN, an auxiliary intermediate power pin DN1, a first power pin D1, and a second power pin D2. The second pin IO and the second jumper pin JP2 are not given. When the number of chip pins is limited, it is necessary to omit these two pins.

[0095] Of course, the tail chip can also adopt the same pin setting as the middle chip, and also includes a second jumper pin JP2 and a second pin IO. At this time, the IO of the tail chip can be connected to the chip ground or configured as a fixed level, which can be achieved either through an external circuit or by changing the connection method of the second jumper pin JP2 of the tail chip. When the second jumper pin JP2 of the tail chip is configured to be connected to the chip ground, the chip internally recognizes this state and does not change the state of the second pin IO. At this time, the chip is suitable for the head chip or the middle chip; when the second jumper pin JP2 of the tail chip is configured to be floating, the chip internally recognizes this state, and the second pin IO is set to be connected to the chip ground or a fixed level inside the chip. At this time, the chip is suitable for the head chip or the middle chip.

[0096] The aforementioned floating means that the pin is not connected to other electrical signals, or even if it is connected, it does not affect the circuit function. The same applies hereinafter.

[0097] Figure 7 、 Figure 8 and Figure 9 Only a relatively simple idea of chip pin design is given. During actual design, it can be optimized separately according to requirements. For example, in order to reduce the types of chips, both the head chip and the tail chip can be designed in the form of the middle chip.

[0098] The chip can also be provided with a heat sink HT, and HT can also be used as a pin. Usually, in order to reduce the number of pins used, Figure 7 、 Figure 8 and Figure 9 at least one of the heat sink, the first jumper pin, and the second jumper pin in [[ ]] is configured as the chip ground.

[0099] In this embodiment, the chip is provided with three power pins. Of course, specifically, as long as more than one power pin meets the solution of the present invention, for example, the middle power pin DN and the auxiliary middle power pin DN1 can be not set.

[0100] The first pin IM, the second pin IO, the middle power pin DN, and the auxiliary middle power pin DN1 can all be configured into more groups.

[0101] When the chip is designed as the head chip and one or more of the first jumper pin, the first pin, and the first middle power pin are omitted, and when the chip is designed as the tail chip and one or more of the second jumper pin and the second pin are omitted while maintaining the pin arrangement order corresponding to the middle chip, there is still no jumper when multiple chips are cascaded, and the technical effect of the present solution can still be achieved. Figure 7 、 Figure 8 and Figure 9Among them, the outer shape of the chip can adopt a dual in-line package shape, such as SOP-8 or ESOP-8 with a heat sink. In these three figures, the serial numbers marked on the pins and the position order of the pins are an optimized design implementation method. Of course, those skilled in the art should know that there are other optimized design methods that do not deviate from the scope of the present invention.

[0102] Regarding the arrangement of the chip pins, the present invention has a specific setting. In order to better describe the positional relationship of the chip pin arrangement, the term "geometric connection" is introduced. The geometric connection is virtual and not any actual existing connection. Its specific meaning is as follows:

[0103] The definition of the geometric connection is as follows: The chip is soldered on a planar circuit board. Within the plane range occupied by the chip plastic package and the chip pins on the circuit board, a virtual line segment of any shape is created. One end of the line segment starts from a pin of the chip, and the other end terminates at another pin of the chip. The line segment is defined as the geometric connection. As Figure 10 shown, line segment A, line segment B, line segment C, and line segment D are geometric connections, and line segment E is not a geometric connection. Geometric connection A and geometric connection B do not cross each other. Geometric connection A, geometric connection C, and geometric connection D do not cross each other. Geometric connection B and geometric connection C cross each other, and geometric connection B and geometric connection D cross each other.

[0104] Next, taking the dual in-line package as an example, the implementation scheme of the present invention regarding the chip pin arrangement will be described, as Figure 11 .

[0105] When the chip includes a first pin IM and a second pin IO, the geometric connection between the first pin IM and the corresponding second pin IO is the first geometric connection. Several groups of first pins and second pins form several first geometric connections. Each first geometric connection does not cross at least one of the other first geometric connections. As Figure 11 shown, the geometric connection between the first group of first pin IM and the second pin IO, and the geometric connection between the second group of first pin IM2 and the second pin IO2 do not cross each other;

[0106] When there is a power pin, the power pin is the first power pin D1, and the first power pin D1 is arranged on one side of all the first geometric connections. As Figure 11, the first power pin D1 is set on the upper right side of all the first geometric connections. All the first geometric connections include the geometric connections between the first group of first pins IM and the second pins IO, and the geometric connections between the second group of first pins IM2 and the second pins IO2. When there are two power pins, one power pin is the first power pin D1, and the other is the second power pin D2. The first power pin D1 and the second power pin D2 are respectively internally connected to two power terminals of the driving circuit. The first power pin D1 and the second power pin D2 are respectively set on both sides of all the first geometric connections, as Figure 11 , all the first geometric connections include: the geometric connections between the first group of first pins IM and the second pins IO, and the geometric connections between the second group of first pins IM2 and the second pins IO2. The first power pin D1 and the second power pin D2 are respectively located on both sides of all the first geometric connections: the upper right side and the lower left side.

[0107] When the driving circuit of the chip has three or more power terminals, the chip includes at least one intermediate power pin and / or at least one corresponding auxiliary intermediate power pin; when both the intermediate power pin and the auxiliary intermediate power pin are included, each group of the intermediate power pin and the auxiliary intermediate power pin are jointly connected to a power terminal inside the chip. The intermediate power pin and the corresponding auxiliary intermediate power pin form a second geometric connection. Several groups of the intermediate power pin and the corresponding auxiliary intermediate power pin form several second geometric connections. At least one of all the second geometric connections does not cross at least one of all the first geometric connections. A third geometric connection is formed between the first power pin D1 and the second power pin D2. All the second geometric connections cross the third geometric connection; Figure 11 There are two groups of second geometric connections, which are respectively: the first group, the geometric connection between the intermediate power pin DN and the corresponding auxiliary intermediate power pin DN1; the second group, the geometric connection between the intermediate power pin DM and the corresponding auxiliary intermediate power pin DM1.

[0108] Figure 11 When the chip includes both the first jumper pin JP1 and the second jumper pin JP2, a fourth geometric connection is formed between the first jumper pin JP1 and the second jumper pin JP2. The fourth geometric connection does not cross at least one of all the first geometric connections;

[0109] When there is at least one second geometric connection formed by the intermediate power pin and the corresponding auxiliary intermediate power pin, the fourth geometric connection does not cross at least one of all the second geometric connections;

[0110] When there is a third geometric connection formed between the first power pin and the second power pin, the fourth geometric connection crosses the third geometric connection.

[0111] In the above solution, the geometric connections are designed to be non-crossing, which is beneficial for the copper plating traces of multiple cascaded chips on the circuit board, achieving the effect of being able to be connected without jumper resistors. Those skilled in the art should know that when at least two lines are non-crossing, at least one jumper can be omitted. The more non-crossing lines there are, the more jumpers can be omitted, and more costs can be reduced. Of course, the most ideal way is that all lines are non-crossing, and specific designs will be made according to the actual situation.

[0112] The above description for Figure 11 can be simplified to Figure 8 When the first geometric connection and the second geometric connection are both in a group, it can be simplified to Figure 8 form.

[0113] Through the above restrictive design of the pins, it can be ensured that when multiple chips are cascaded, the need for jumpers is less or even non-existent, as can be seen in the application circuit.

[0114] Embodiment 7

[0115] The following specifically describes the load driving circuit of the present invention with respect to specific embodiments.

[0116] It includes a first chip, a last chip, and n intermediate chips. The first chip, the last chip, and the intermediate chips use the chips of any of the above embodiments, and n is a natural number;

[0117] The chip grounds of the first chip, the last chip, and the intermediate chips are connected in parallel; the power pins corresponding to the first chip, the last chip, and the intermediate chips are respectively connected in parallel for driving an external load;

[0118] The intermediate chip includes at least one group of first pins and second pins. The first chip includes at least one second pin, the last chip includes at least one corresponding first pin. The second pin of the first chip is connected to the corresponding first pin of the first intermediate chip. The corresponding second pin of the previous intermediate chip and the corresponding first pin of the next intermediate chip are connected in series in sequence. The corresponding second pin of the last intermediate chip is connected to the corresponding first pin of the last chip, forming an electrical path; the excitation signal generates excitation for the first end and the second end of the driving circuits in all chips on the electrical path;

[0119] The load is at least one LED unit group, and the LED unit group is composed of one or more single LED chips connected in series and in parallel;

[0120] This embodiment is described by taking n = 1 intermediate chip as an example:

[0121] Figure 12Among them, each chip includes a power pin D1, two groups of first pins IM and second pins IO. The excitation signal 1 and the excitation signal 2 respectively excite two electrical paths. Each electrical path is formed by sequentially connecting the first pin IM and the corresponding second pin IO located on each chip.

[0122] The geometric connections between the two groups of first pins IM and second pins IO do not cross each other.

[0123] It can be clearly seen from the circuit diagram that the load driving circuit is composed of multiple chips in cascade. There are no jumpers between the cascaded chips, and only one of the chips, the first chip, is connected to the excitation circuit that generates the excitation signal.

[0124] Figure 13 Among them, each chip includes a first power pin D1, a second power pin D2, a first jumper pin JP1 (sharing a pin with the chip ground GND, marked as GND here), a second jumper pin JP2 (the second jumper pin is floating here and not marked), and a group of first pins IM and second pins IO. The excitation signal excites the electrical path, and the electrical path is formed by sequentially connecting the first pin IM and the corresponding second pin IO located on each chip.

[0125] The geometric connection between the first pin IM and the second pin IO, and the geometric connection formed by the first jumper pin (GND) and the floating second jumper pin do not cross each other; at the same time, they both cross the geometric connection formed by the first power pin D1 and the second power pin D2.

[0126] It can be clearly seen from the circuit diagram that the load driving circuit is composed of multiple chips in cascade. There are no jumpers between the cascaded chips, and in one of the chips, the first chip, is connected to the excitation circuit that generates the excitation signal.

[0127] Figure 12 and Figure 13 The chips in and all include a heat sink, which is commonly connected to the chip ground with the first jumper pin. Moreover, the first chip and the intermediate chips adopt the same pin design method. At least a part of the excitation circuit is not included inside the chip. The second jumper pin and the second pin IO of the last chip are not electrically connected to external devices in the embodiment and can be omitted in the chip pin design.

[0128] Figure 14 Among them, the intermediate chip includes a first power pin D1, a second power pin D2, an intermediate power terminal DN and an auxiliary intermediate power pin DN1 that is short-circuited to it inside the chip, a first jumper pin JP1, a second jumper pin JP2, a first pin IM and a second pin IO;

[0129] The first chip integrates an excitation circuit that generates an excitation signal. Compared with the middle chip, it does not include the first jumper pin JP1, the first pin IM, and the auxiliary middle power pin DN1;

[0130] The last chip adopts the same pin design method as the middle chip, and its second pin IO and second jumper pin JP2 are both connected to the chip ground.

[0131] The excitation circuit in the first chip generates an excitation signal to excite the electrical path, which is formed by sequentially connecting the first end and the second end on the drive circuits located on each chip in series.

[0132] The geometric connection formed by the first pin IM and the second pin IO, the geometric connection formed by the first jumper pin JP1 and the second jumper pin JP2, and the geometric connection formed by the middle power pin DN and the auxiliary middle power pin DN1 do not cross each other; at the same time, they all cross the geometric connection formed by the first power pin D1 and the second power pin D2.

[0133] It can be clearly seen from the circuit diagram that the load drive circuit is formed by cascading multiple chips. There is no jumper between the cascaded chips, and in one of the chips, the first chip, an excitation circuit that generates an excitation signal is integrated. When there are two or more middle chips, the connection method is similar, and only all the middle chips need to be placed in the middle for connection, which will not be elaborated here.

[0134] The above-mentioned LED unit includes at least one LED. Preferably, it can be configured with a storage capacitor in parallel with the LED to reduce the current ripple of the LED. Preferably, it can be configured with a current source in series with it to reduce the current ripple of the LED. Preferably, each single or all of the LED units can be configured with a unidirectional switch, and the unidirectional switch can be a diode or other solutions to block the discharge of the storage capacitor to the electrical path other than the LED.

[0135] As Figure 15 shown, the load LED unit includes three LEDs, namely LED1, LED2, and LEDN. A current source is connected in series above each LED, corresponding to I1, I2, and IN respectively. Energy storage capacitors, namely C1, C2, and CN respectively, are connected in parallel at both ends of the series branch of the LED and the corresponding current source. And blocking diodes D1, D2, and DN are connected in series outside the combination of the LED, the corresponding current source, and the corresponding energy storage capacitor.

[0136] The above-mentioned drive circuit, chip, and application can be set in the lighting device. As long as the lighting device includes the above solutions, it is within the scope of our protection.

Claims

1. A chip, characterized in that, the chip includes a driving circuit, and the chip includes a chip ground; the driving circuit includes at least one corresponding first end and second end, and further includes at least one power terminal, the power terminal outputs a power current for driving an external load, characterized in that at least one of the first end, the second end, and between the first end and the second end receives an excitation signal, the excitation signal is a voltage signal, a current signal, or a combination of a voltage signal and a current signal, and the power terminal generates a current that has a monotonic change relationship with the excitation signal; when the chip includes a first pin and a second pin at the same time, the geometric connection line between the first pin and the corresponding second pin is a first geometric connection line, and several groups of first pins and second pins form several first geometric connection lines; when the chip has one power pin, the power pin is the first power pin, and the first power pin is disposed on one side of all the first geometric connection lines; when there are two power pins, one power pin is the first power pin, and the other is the second power pin, the first power pin and the second power pin are respectively internally connected to two power terminals of the driving circuit, and the first power pin and the second power pin are respectively disposed on both sides of all the first geometric connection lines; when the driving circuit of the chip has more than three power terminals, the chip includes at least one intermediate power pin and / or at least one corresponding auxiliary intermediate power pin; when including an intermediate power pin and an auxiliary intermediate power pin at the same time, each group of intermediate power pins and auxiliary intermediate power pins are commonly connected to a power terminal inside the chip, the intermediate power pin and the corresponding auxiliary intermediate power pin form a second geometric connection line, and several groups of intermediate power pins and corresponding auxiliary intermediate power pins form several second geometric connection lines, at least one of all the second geometric connection lines does not cross at least one of all the first geometric connection lines, a third geometric connection line is formed between the first power pin and the second power pin, and the second geometric connection line crosses the third geometric connection line.

2. The chip according to claim 1, characterized in that, the first end of the driving circuit is connected to the second end through an electrical connection part, and the electrical connection part is at least one of three cases: a wire, a combination of one resistor or multiple resistors, and a combination of one transistor or multiple transistors.

3. The chip according to claim 1 or 2, characterized in that, the current of the power terminal of the driving circuit is generated by a voltage-controlled current source or a current mirror, and the voltage-controlled current source or the current mirror samples the excitation signal from the first end and / or the second end.

4. The chip according to claim 1, characterized in that, at least one power pin, the power pin is internally connected to the corresponding power terminal of the driving circuit; and, at least one first pin, each first pin is internally connected to the corresponding first end of the driving circuit and / or includes at least one second pin, each second pin is internally connected to the corresponding second end of the driving circuit.

5. The chip according to claim 1, characterized in that, each first geometric connection line does not cross at least one of the other first geometric connection lines.

6. The chip according to claim 5, characterized in that, It further includes a first jumper pin and / or a second jumper pin, the first jumper pin and / or the second jumper pin are connected to the chip ground or left floating. When both the first jumper pin and the second jumper pin are included, a fourth geometric connection line is formed between the first jumper pin and the second jumper pin; The fourth geometric connection line does not cross at least one of all the first geometric connection lines; When there is at least one second geometric connection line formed by an intermediate power pin and a corresponding auxiliary intermediate power pin, the fourth geometric connection line does not cross at least one of all the second geometric connection lines; When there is a third geometric connection line formed between a first power pin and a second power pin, the fourth geometric connection line crosses the third geometric connection line.

7. The chip according to claim 1, wherein, the chip further includes at least a part of an excitation circuit for generating an excitation signal.

8. A load driving circuit, wherein, it includes a first chip, a last chip and n intermediate chips, the first chip, the last chip and the intermediate chips are the chips according to any one of claims 1-7, n is a natural number, the chip grounds of the first chip, the last chip and the intermediate chips are connected in parallel; the power pins corresponding to the first chip, the last chip and the intermediate chips are respectively connected in parallel for driving an external load; the intermediate chip includes at least one group of a first pin and a second pin, the first chip includes at least one second pin, the last chip includes at least one first pin, the second pin of the first chip is connected to the first pin of the first intermediate chip, the second pin of the previous intermediate chip and the first pin of the next intermediate chip are connected in series in sequence, and the second pin of the last intermediate chip is connected to the first pin of the last chip to form an electrical path; the excitation signal generates excitation for the first end and the second end of the driving circuits in all the chips on the electrical path.

9. The load driving circuit according to claim 8, wherein, the second jumper pin of the first chip is connected to the chip ground, and / or the second jumper pin of the last chip is left floating or grounded.

10. The load driving circuit according to claim 9, wherein, the load includes at least one LED unit group, and the LED unit group is composed of one LED or multiple LEDs.

11. A lighting device, wherein, it includes the chip according to any one of claims 1-7 or the load driving circuit according to any one of claims 8-10.

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