A display panel and a manufacturing method thereof, and a display device

Abstract

The present invention provides a display panel and a manufacturing method thereof, and a display device. It relates to the field of display technology, and aims to solve the problem of low fingerprint recognition accuracy when a fingerprint recognition module is integrated inside a display panel. The display panel includes a substrate, a driving circuit layer arranged on the substrate, and a plurality of pixel units arranged on the side of the driving circuit layer facing away from the substrate; each pixel unit includes at least two sub-pixels; the display panel also includes: a shading layer arranged on the substrate, a plurality of imaging pinholes are arranged on the shading layer, and the orthographic projection of the imaging pinholes on the substrate is located within a preset range around the orthographic projection of the target sub-pixel on the substrate, and the luminous efficiency of the target sub-pixel is less than a threshold value. The display panel provided by the present invention is used for display.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a manufacturing method thereof, and a display device. Background Art

[0002] In the field of electronic devices, especially mobile phones, it has become standard to use biometrics, especially fingerprint recognition technology, for identity authentication and other operations. Currently, fingerprint recognition modules are usually external and are usually set on the back of the phone or integrated on the HOME button of the phone. The method of setting it on the back of the phone is not conducive to the convenience of operation, and the method of setting it on the HOME button does not achieve full-screen display.

[0003] Therefore, the relevant technology has proposed a solution to integrate the fingerprint recognition module inside the display panel. The main principle is to use the self-luminescence of the organic light-emitting diode (OLED) display panel as the light source for fingerprint recognition. When the light shines on the finger, the light reflected by the finger passes through the small holes set in the back panel and is received by the fingerprint recognition module. The fingerprint recognition module synthesizes and analyzes the image formed by each small hole to obtain the fingerprint pattern information. Although the solution of integrating the fingerprint recognition module inside the display panel increases the screen-to-body ratio, it still has the problem of low fingerprint recognition accuracy. Therefore, how to improve the fingerprint recognition accuracy has become an urgent problem to be solved. Summary of the invention

[0004] The object of the present invention is to provide a display panel and a manufacturing method thereof, and a display device, which are used to solve the problem of low fingerprint recognition accuracy when a fingerprint recognition module is integrated inside a display panel.

[0005] In order to achieve the above object, the present invention provides the following technical solutions:

[0006] A first aspect of the present invention provides a display panel, comprising a substrate, a driving circuit layer disposed on the substrate, and a plurality of pixel units disposed on a side of the driving circuit layer facing away from the substrate;

[0007] Each of the pixel units includes at least two sub-pixels;

[0008] The driving circuit layer includes sub-pixel driving circuits corresponding to the sub-pixels one by one;

[0009] The sub-pixel comprises an anode pattern, an organic light-emitting unit and a cathode layer which are sequentially stacked in a direction from close to the substrate to far away from the substrate;

[0010] The display panel further includes a metal pattern corresponding to the anode pattern one by one, wherein the metal pattern is located between the corresponding sub-pixel driving circuit and the corresponding anode pattern in a direction perpendicular to the substrate, and the anode pattern is electrically connected to the corresponding sub-pixel driving circuit through the corresponding metal pattern;

[0011] The display panel also includes: a shading layer arranged on the substrate, a plurality of imaging pinholes are arranged on the shading layer, the orthographic projections of the imaging pinholes on the substrate are located within a preset range around the orthographic projection of the target sub-pixel on the substrate, and the luminous efficiency of the target sub-pixel is less than a threshold value.

[0012] Optionally, the light shielding layer and the metal pattern are provided in the same layer and with the same material.

[0013] Optionally, each of the pixel units includes a first color sub-pixel, a second color sub-pixel and a third color sub-pixel; wherein the luminous efficiency of the first color sub-pixel is greater than the luminous efficiency of the second color sub-pixel, and the luminous efficiency of the second color sub-pixel is greater than the luminous efficiency of the third color sub-pixel;

[0014] The target sub-pixel includes the second color sub-pixel and / or the third color sub-pixel;

[0015] There is a first distance between the orthographic projection of the imaging pinhole on the substrate and the orthographic projection of the first color sub-pixel on the substrate, there is a second distance between the orthographic projection of the imaging pinhole on the substrate and the orthographic projection of the second color sub-pixel on the substrate, there is a third distance between the orthographic projection of the imaging pinhole on the substrate and the orthographic projection of the third color sub-pixel on the substrate, the second distance is smaller than the first distance, and / or the third distance is smaller than the first distance.

[0016] Optionally, the first color sub-pixel includes a green sub-pixel, the second color sub-pixel includes a red sub-pixel, and the third color sub-pixel includes a blue sub-pixel;

[0017] The plurality of pixel units are distributed in an array, and each of the pixel units includes a red sub-pixel, a blue sub-pixel and two green sub-pixels.

[0018] Optionally, in pixel units located in the same row, the red sub-pixels and the blue sub-pixels included in each pixel unit are distributed in one row, and the green sub-pixels included in each pixel unit are distributed in another row;

[0019] And there is one green sub-pixel between the red sub-pixel and the blue sub-pixel adjacent to each other in a direction parallel to the row.

[0020] Optionally, the two green sub-pixels included in each of the pixel units form a green sub-pixel group, and the two green sub-pixels in the green sub-pixel group are arranged in a direction perpendicular to the row;

[0021] In the pixel units located in the same row, the red sub-pixel, the blue sub-pixel and the green sub-pixel group included in each pixel unit are all distributed in one row.

[0022] Optionally, the display panel further includes:

[0023] a reflective light shielding layer located on a side of the imaging pinhole facing away from the substrate, wherein an orthographic projection of the reflective light shielding layer on the substrate is located between an orthographic projection of the target sub-pixel on the substrate and an orthographic projection of at least one non-target sub-pixel on the substrate;

[0024] The orthographic projection of the imaging pinhole on the substrate is located between the orthographic projection of the target sub-pixel on the substrate and the orthographic projection of the reflective light shielding layer on the substrate.

[0025] Optionally, a reflective light shielding layer is located on a side of the imaging pinhole facing away from the substrate, and an orthographic projection of the reflective light shielding layer on the substrate is located between an orthographic projection of the target sub-pixel on the substrate and an orthographic projection of at least one non-target sub-pixel on the substrate;

[0026] The orthographic projection of the target sub-pixel on the substrate is located between the orthographic projection of the imaging pinhole on the substrate and the orthographic projection of the reflective light shielding layer on the substrate.

[0027] Optionally, the orthographic projection of the reflective light shielding layer on the substrate is located between the orthographic projections of the pixel units in adjacent rows on the substrate.

[0028] Optionally, the display panel also includes a signal line extending along the extension direction of the row, the signal line is located between the imaging hole and the reflective light shielding layer, the reflective light shielding layer and the signal line extend in the same direction, and the reflective light shielding layer is connected in parallel with the signal line.

[0029] Optionally, there is an overlapping area between the orthographic projection of the reflective light shielding layer on the substrate and the orthographic projection of the signal line on the substrate, and the reflective light shielding layer and the signal line are connected in parallel through a via hole arranged in the overlapping area.

[0030] Optionally, the display panel includes a display area and a non-display area arranged around the display area, and the via hole is located in the display area or the non-display area.

[0031] Optionally, the signal line includes an initialization signal line.

[0032] Optionally, the display panel further includes:

[0033] a light emitting control signal line extending in the same direction as the initialization signal line, and a power supply signal line extending in a direction perpendicular to the initialization signal line;

[0034] The sub-pixel driving circuits are arranged in an array, and are divided into a plurality of rows of sub-pixel driving circuits along the extension direction of the rows, and are divided into a plurality of columns of sub-pixel driving circuits along the column direction perpendicular to the extension direction of the rows. The initialization signal lines and the light-emitting control signal lines correspond one-to-one to the plurality of rows of sub-pixel driving circuits, and the sub-pixel driving circuits in the same row share a corresponding light-emitting control signal line and a corresponding initialization signal line; the power signal lines correspond one-to-one to the plurality of columns of sub-pixel driving circuits, and the sub-pixel driving circuits in the same column share a corresponding power signal line;

[0035] The orthographic projection of the imaging pinhole on the substrate is located between the orthographic projection of the light emitting control signal line corresponding to the sub-pixel driving circuit of the previous row on the substrate and the orthographic projection of the initialization signal line corresponding to the sub-pixel driving circuit of the next adjacent row on the substrate; and / or,

[0036] The orthographic projection of the imaging pinhole on the substrate is located between the orthographic projection of the metal pattern corresponding to the target sub-pixel on the substrate and the orthographic projection of the power signal line corresponding to the target sub-pixel on the substrate.

[0037] Optionally, the minimum distance between the orthographic projection of the imaging pinhole on the substrate and the orthographic projection of the light-emitting control signal line on the substrate, the minimum distance between the orthographic projection of the imaging pinhole on the substrate and the orthographic projection of the initialization signal on the substrate, the minimum distance between the orthographic projection of the imaging pinhole on the substrate and the orthographic projection of the power signal line on the substrate, and the minimum distance between the orthographic projection of the imaging pinhole on the substrate and the orthographic projection of the metal pattern on the substrate are all greater than a preset reference value.

[0038] Optionally, the reflective light shielding layer and the anode pattern are provided in the same layer and with the same material.

[0039] Optionally, the plurality of imaging pinholes are distributed in an array, and the imaging pinholes are located in any local area within the display area of ​​the display panel; or, the imaging pinholes are distributed throughout the display area.

[0040] Based on the technical solution of the above display panel, a second aspect of the present invention provides a display device including the above display panel.

[0041] Based on the technical solution of the above display panel, a third aspect of the present invention provides a method for manufacturing a display panel, the manufacturing method comprising:

[0042] A light shielding layer is formed on the substrate, wherein a plurality of imaging pinholes are arranged on the light shielding layer;

[0043] Manufacturing a driving circuit layer on the substrate, wherein the driving circuit layer includes a plurality of sub-pixel driving circuits;

[0044] Making a metal pattern corresponding to the sub-pixel driving circuit on a side of the driving circuit layer facing away from the substrate;

[0045] A plurality of pixel units are made on the side of the metal pattern facing away from the substrate, each of the pixel units includes at least two sub-pixels, and the sub-pixels correspond to the sub-pixel driving circuits one by one; the positive projection of the imaging hole on the substrate is located within a preset range around the positive projection of the target sub-pixel on the substrate, and the luminous efficiency of the target sub-pixel is less than a threshold; the sub-pixel includes an anode pattern, an organic light-emitting unit and a cathode layer which are sequentially stacked in a direction away from the substrate, and the anode pattern is electrically connected to the corresponding sub-pixel driving circuit through the corresponding metal pattern.

[0046] Optionally, the manufacturing method further includes:

[0047] A reflective light shielding layer is formed on the side of the imaging pinhole facing away from the substrate, wherein the orthographic projection of the reflective light shielding layer on the substrate is located between the orthographic projection of the target sub-pixel on the substrate and the orthographic projection of at least one non-target sub-pixel on the substrate;

[0048] The orthographic projection of the imaging pinhole on the substrate is located between the orthographic projection of the target sub-pixel on the substrate and the orthographic projection of the reflective light shielding layer on the substrate; or,

[0049] The orthographic projection of the target sub-pixel on the substrate is located between the orthographic projection of the imaging pinhole on the substrate and the orthographic projection of the reflective light shielding layer on the substrate.

[0050] Optionally, the step of forming a reflective light shielding layer on a side of the imaging pinhole facing away from the substrate specifically includes:

[0051] The reflective light shielding layer and the anode pattern are formed simultaneously through one patterning process.

[0052] In the technical solution provided by the present invention, by setting the imaging holes on the shading layer around the target sub-pixels whose luminous efficiency is less than a threshold value, when fingerprint recognition is performed, most or all of the light passing through the imaging holes is emitted by the target sub-pixels, and the luminous efficiency of the target sub-pixels is less than the threshold value, so that when the same data signal is input to each sub-pixel, the luminous brightness of the target sub-pixels is darker than the luminous brightness of the non-target pixels, that is, the brightness of the light emitted by the target sub-pixels is more suitable for the recognition ability of the fingerprint recognition module, so that when the fingerprint recognition module performs fingerprint recognition based on the light emitted by the target sub-pixels, the fingerprint recognition accuracy is higher; it can be seen that in the technical solution provided by the present invention, by controlling the light component passing through the imaging holes, the brightness of the light used for fingerprint recognition is moderate, thereby effectively improving the fingerprint recognition accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0054] Figure 1 A first arrangement mode of the imaging pinhole in the first pixel structure provided in an embodiment of the present invention;

[0055] Figure 2 A second arrangement method of the imaging pinhole in the first pixel structure provided in an embodiment of the present invention;

[0056] Figure 3 A schematic diagram of a reflective light shielding layer in a first pixel structure provided by an embodiment of the present invention;

[0057] Figure 4 A first arrangement mode of the imaging pinhole in the second pixel structure provided in an embodiment of the present invention;

[0058] Figure 5 A second arrangement mode of the imaging pinhole in the second pixel structure provided in an embodiment of the present invention;

[0059] Figure 6 A schematic diagram of a reflective light shielding layer in a second pixel structure provided by an embodiment of the present invention;

[0060] Figure 7 A schematic diagram of fingerprint recognition performed on a display panel provided by an embodiment of the present invention;

[0061] Figure 8 A schematic diagram of a fingerprint recognition area provided in an embodiment of the present invention being set in a designated area of ​​a display panel;

[0062] Fig. 9A schematic diagram of an imaging pinhole provided on a light shielding layer provided in an embodiment of the present invention;

[0063] Fig.10 A schematic diagram of the structure of a sub-pixel driving circuit provided by an embodiment of the present invention;

[0064] Fig.11 A working timing diagram of a sub-pixel driving circuit provided by an embodiment of the present invention;

[0065] Fig.12 A schematic diagram of the layout of a sub-pixel driving circuit corresponding to each sub-pixel provided in an embodiment of the present invention;

[0066] Figures 13-16 for Fig.12 Schematic diagram of each membrane layer corresponding to the layout method in . DETAILED DESCRIPTION

[0067] In order to further illustrate the display panel and its manufacturing method, and the display device provided by the embodiments of the present invention, a detailed description is given below in conjunction with the accompanying drawings.

[0068] The present invention provides a display panel, in which a fingerprint recognition module is integrated inside the display panel, and an imaging hole corresponding to the fingerprint recognition module is arranged inside the back plate of the display panel. When fingerprint recognition is performed in the display area, the light emitted by the display panel is used as the light source for fingerprint recognition. The light is irradiated to the finger used for fingerprint recognition and then reflected by the finger. The reflected light can pass through the imaging hole arranged in the back plate of the display panel and be received by the fingerprint recognition module (the fingerprint recognition module usually adopts a charge coupled device image sensor CCD). The fingerprint recognition module synthesizes and analyzes the image formed by each imaging hole to obtain fingerprint pattern information. The display panel provided by the present invention can use the display area for fingerprint recognition, and there is no need to separately arrange a fingerprint recognition area on the display surface, which is conducive to achieving full-screen display.

[0069] Although the solution of integrating the fingerprint recognition module inside the display panel increases the screen-to-body ratio, there is still the problem of low fingerprint recognition accuracy. Therefore, how to improve the fingerprint recognition accuracy has become an urgent problem to be solved.

[0070] Based on the existence of the above-mentioned problems, the inventors of the present invention have discovered through research that, under the premise that the accuracy of the fingerprint recognition module remains unchanged, the key to improving the fingerprint recognition accuracy lies in the optimization design of the recognition optical path. For this reason, some solutions have been invented in the related technology to improve the design of the optical path, but these solutions mainly focus on the selection of the position of the shading layer, stray light processing, etc., and there is no solution combined with specific devices for improvement and optimization.

[0071] The inventor of the present invention further discovered that, taking an OLED display panel as an example, since the OLED display panel is self-luminous, and the luminous efficiency and luminous brightness corresponding to the sub-pixels of different colors it includes are significantly different, illustratively, the display panel includes: a red sub-pixel, a green sub-pixel and a blue sub-pixel, wherein the luminous efficiency of the green sub-pixel is higher, and the luminous efficiency of the red sub-pixel and the blue sub-pixel is lower, which results in that when the display panel is actually displayed, the luminous brightness of the green sub-pixel is higher, and the luminous brightness of the red sub-pixel and the blue sub-pixel is lower; and when performing fingerprint recognition, reflected light of a certain brightness is required to illuminate the photosensitive element in the fingerprint recognition module, and then the image information of the fingerprint is formed through analysis, but light with too high brightness may exceed the recognition capability of the fingerprint recognition module or cause a decrease in the fingerprint recognition accuracy, therefore, the imaging pinhole can be set around the sub-pixel with lower luminous efficiency, and the imaging pinhole can be kept away from other sub-pixels with higher luminous efficiency, so that by controlling the composition of the light passing through the imaging pinhole, the light passing through the imaging pinhole can have a moderate brightness, thereby improving the recognition accuracy of the fingerprint recognition module.

[0072] See also Figure 1 , Figure 2 and Figure 7 The embodiment of the present invention provides a display panel, comprising a substrate 40, a driving circuit layer arranged on the substrate 40, and a plurality of pixel units arranged on a side of the driving circuit layer facing away from the substrate 40; each of the pixel units comprises at least two sub-pixels; the driving circuit layer comprises a sub-pixel driving circuit corresponding to the sub-pixel one by one; the sub-pixel comprises an anode pattern, an organic light-emitting unit and a cathode layer which are sequentially stacked in a direction from close to the substrate 40 to far away from the substrate 40; the display panel further comprises a metal pattern corresponding to the anode pattern one by one, in a direction perpendicular to the substrate 40, the metal pattern is located between the corresponding sub-pixel driving circuit and the corresponding anode pattern, and the anode pattern is electrically connected to the corresponding sub-pixel driving circuit through the corresponding metal pattern; the display panel further comprises: a light shielding layer 90 arranged on the substrate 40, a plurality of imaging pinholes 91 are arranged on the light shielding layer 90, the positive projection of the imaging pinholes 91 on the substrate 40 is located within a preset range around the positive projection of the target sub-pixel on the substrate 40, and the luminous efficiency of the target sub-pixel is less than a threshold value.

[0073] Specifically, the display panel includes a plurality of pixel units that are distributed in an array on a substrate, and each pixel unit may include a plurality of sub-pixels. The colors of the sub-pixels may be set according to actual needs. For example, each pixel unit includes at least a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B. Among the sub-pixels of various colors included in the pixel unit, a sub-pixel whose luminous efficiency is less than a threshold value is defined as a target sub-pixel (e.g., Figure 1 and Figure 2 The red sub-pixel R and the blue sub-pixel B in the image are defined as non-target sub-pixels (such as Figure 1 and Figure 2 The green sub-pixel G in the image), the size of the threshold can be determined according to actual needs, as long as the brightness of the light emitted by the target sub-pixel when passing through the imaging hole 91 for fingerprint recognition does not exceed the recognition capability of the fingerprint recognition module and can improve the accuracy of fingerprint recognition.

[0074] The display panel also includes a light shielding layer 90 having a plurality of imaging pinholes 91. The light shielding layer 90 can be formed on a substrate using a metal material, and can be specifically located on the surface of the substrate, or on the side of the sub-pixel driving circuit facing away from the substrate, but is not limited thereto. When the imaging pinholes 91 are formed on the light shielding layer 90, the positions of the imaging pinholes 91 can be set according to actual needs. For example, the positive projection of the imaging pinhole 91 on the substrate 40 is set to be within a preset range around the positive projection of the target sub-pixel on the substrate 40. This setting method can satisfy that most of the light passing through the imaging pinhole 91 is light emitted by the target sub-pixel, and only a small part of the light emitted by the non-target sub-pixel passes through the imaging pinhole 91; or, it can satisfy that the light passing through the imaging pinhole 91 is light emitted by the target sub-pixel, that is, no light emitted by the non-target sub-pixel passes through the imaging pinhole 91; thereby ensuring that the light emitted from the pinhole Via is neither too weak nor too strong.

[0075] When the above-mentioned display panel is actually used, the display panel realizes the display function. When a finger touches the surface of the display side of the display panel, the light emitted by the display panel can be used as a light source for fingerprint recognition. The light is reflected by the finger after being irradiated to the finger used for fingerprint recognition. The reflected light passes through the imaging hole 91 and is received by the fingerprint recognition module in the display panel. The fingerprint recognition module synthesizes and analyzes the image formed by each imaging hole 91 to obtain the fingerprint pattern information.

[0076] According to the specific structure and application process of the display panel provided in the above-mentioned embodiment, it can be known that in the display panel provided in the embodiment of the present invention, by setting the imaging pinhole 91 on the shading layer 90 around the target sub-pixel whose luminous efficiency is less than the threshold, when fingerprint recognition is performed, most or all of the light passing through the imaging pinhole 91 is emitted by the target sub-pixel, and the luminous efficiency of the target sub-pixel is less than the threshold, so that when the same data signal is input to each sub-pixel, the luminous brightness of the target sub-pixel is darker than the luminous brightness of the non-target pixel, that is, the brightness of the light emitted by the target sub-pixel is more suitable for the recognition ability of the fingerprint recognition module, so that when the fingerprint recognition module performs fingerprint recognition based on the light emitted by the target sub-pixel, the fingerprint recognition accuracy is higher; it can be seen that in the display panel provided in the embodiment of the present invention, by controlling the light component passing through the imaging pinhole 91, the brightness of the light used for fingerprint recognition is moderate, thereby effectively improving the fingerprint recognition accuracy.

[0077] In addition, in the display panel provided by the embodiment of the present invention, the shading layer 90 can be specifically arranged between the driving circuit layer and the substrate, so that the shading layer 90 will not affect the various film layers included in the driving circuit layer, thereby ensuring that the various conductive patterns and wirings in the driving circuit layer have sufficient arrangement space.

[0078] Furthermore, if Fig.10 , Figure 12 to Figure 16 As shown, each sub-pixel driving circuit included in the driving circuit layer may include: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and a storage capacitor Cst.

[0079] Taking the sub-pixel driving circuit located in the nth row and the nth column as an example, each transistor included in the sub-pixel driving circuit adopts a P-type transistor, wherein the source S4 of the fourth transistor T4 is connected to the power signal line VDD(n), the drain D4 of the fourth transistor T4 is connected to the source S1 of the first transistor T1, the gate G4 of the fourth transistor T4 is connected to the light emitting control signal line EM(n), the gate G2 of the second transistor T2 is connected to the gate control signal line G(n), the source S2 of the second transistor T2 is connected to the data signal line D(n), the drain D2 of the second transistor T2 is connected to the source S1 of the first transistor T1, the gate G3 of the third transistor T3 is connected to the gate control signal line G(n), the source S3 of the third transistor T3 is connected to the drain D1 of the first transistor T1, the drain D3 of the third transistor T3 is connected to the gate G1 of the first transistor T1, the gate G5 of the fifth transistor T5 is connected to the light emitting control signal line EM(n), and the gate G2 of the second transistor T2 is connected to the gate control signal line G(n). The source S5 of the transistor T5 is connected to the drain D1 of the first transistor T1, the drain D5 of the fifth transistor T5 is connected to the anode pattern of the corresponding sub-pixel, the gate G6 of the sixth transistor T6 is connected to the nth reset signal line RST(n), the source S6 of the sixth transistor T6 is connected to the nth initialization signal line VINT(n), the drain D6 of the sixth transistor T6 is connected to the gate G1 of the first transistor T1, the gate G7 of the seventh transistor T7 is connected to the n+1th reset signal line RST(n+1), the source S7 of the seventh transistor T7 is connected to the n+1th initialization signal line VINT(n+1), or the source S7 of the seventh transistor T7 is connected to the negative power supply VSS, the drain D7 of the seventh transistor T7 is connected to the anode pattern of the corresponding sub-pixel, the first plate Cstb of the storage capacitor Cst is connected to the gate G1 of the first transistor T1, and the second plate Csta of the storage capacitor Cst is connected to the power supply signal line VDD(n).

[0080] like Fig.11 As shown, when the sub-pixel driving circuit of the above structure is working, each working cycle includes a reset period P1, a write compensation period P2 and a light-emitting period P3. In the reset period P1, the nth reset signal input by the nth reset signal line RST(n) is at a valid level, the sixth transistor T6 is turned on, and the gate G1 of the first transistor T1 is reset.

[0081] During the write compensation period P2, the nth reset signal is at a non-valid level, the sixth transistor T6 is turned off, the n+1th reset signal input by the n+1th reset signal line RST(n+1) is at a valid level, the seventh transistor T7 is turned on, and the anode of the light-emitting element OLED is reset; the gate control signal input by the gate control signal line G(n) is at a valid level, controlling the second transistor T2 and the third transistor T3 to be turned on, the data signal line D(n) writes the data signal, and the first transistor T1, the second transistor T2 and the third transistor T3 work together to achieve threshold voltage compensation for the first transistor T1.

[0082] In the light-emitting period P3, the n+1th reset signal is at a non-valid level, the seventh transistor T7 is turned off, the gate control signal is at a non-valid level, the second transistor T2 and the third transistor T3 are both turned off, the light-emitting control signal written into the light-emitting control signal line EM(n) is at a valid level, the fourth transistor T4 and the fifth transistor T5 are turned on, and the first transistor T1 is turned on at the same time, and the generated leakage current flows to the corresponding anode pattern, driving the corresponding organic light-emitting unit to emit light.

[0083] When manufacturing the above sub-pixel driving circuit, the layout of each film layer corresponding to the sub-pixel driving circuit is as follows:

[0084] The active film layers (such as Fig.13 As shown, generally a low temperature polysilicon layer), a gate insulating layer, a first gate metal layer (such as Fig.14 As shown), a first interlayer insulating layer, a second gate metal layer (as shown Fig.15 As shown), a second interlayer insulating layer, a first source-drain metal layer (as shown Fig.16 As shown), a third interlayer insulating layer and a second source-drain metal layer; wherein the first gate metal layer is used to form the gate of each transistor in the sub-pixel driving circuit, and the gate control signal line, the light emitting control signal line and the reset signal line included in the driving circuit layer, wherein the gate G1 of the first transistor T1 in each sub-pixel driving circuit is reused as the first electrode Cstb of the storage capacitor Cst in the sub-pixel driving circuit; the second gate metal layer is used to form the second electrode Csta of the storage capacitor Cst, and the initialization signal line VINT(n) included in the driving circuit layer; the first source-drain metal layer is used to form the source and drain of each transistor in the sub-pixel driving circuit, and the connecting part for conducting the two transistors, and the data signal line D(n) and the power signal line VDD(n) included in the driving circuit layer; the second source-drain metal layer is used to form a light shielding layer 90.

[0085] For more details, please refer to Figure 12 to Figure 16, the source S4 of the fourth transistor T4 is located in the source region 90S4, the drain D4 of the fourth transistor T4 is located in the drain region 90D4, the gate G4 of the fourth transistor T4 is connected to the light emitting control signal line EM(n), the gate G2 of the second transistor T2 is connected to the gate control signal line G(n), the source S2 of the second transistor T2 is located in the source region 90S2, the drain D2 of the second transistor T2 is located in the drain region 90D2, the gate G3 of the third transistor T3 is connected to the gate control signal line G(n), the source S3 of the third transistor T3 is located in the source region 90S3, the drain D3 of the third transistor T3 is located in the drain region 90D3, the gate G5 of the fifth transistor T5 is connected to the light emitting control signal line EM(n), the source S5 of the fifth transistor T5 is located in the source region 90S5, the fifth transistor T 5 is located in the drain area 90D5, the gate G6 of the sixth transistor T6 is connected to the nth reset signal line RST(n), the source S6 of the sixth transistor T6 is located in the source area 90S6, the drain D6 of the sixth transistor T6 is located in the drain area 90D6, the gate G7 of the seventh transistor T7 is connected to the n+1th reset signal line RST(n+1), the source S7 of the seventh transistor T7 is located in the source area 90S7, the drain D7 of the seventh transistor T7 is located in the drain area 90D7, the source of the first transistor T1 is located in the source area 90S1, the drain of the first transistor T1 is located in the drain area 90D1, the first plate Cstb of the storage capacitor Cst is connected to the gate G1 of the first transistor T1, and the second plate Csta of the storage capacitor Cst is connected to the power signal line VDD(n).

[0086] It is worth noting that among the transistors included in the sub-pixel driving circuit, there are some transistors whose source and drain are not made of source-drain metal layers, that is, the source and drain of these transistors can be directly made of active film layers, and it is only necessary to make the active film layers used as the source and drain have conductive properties after being doped. In this case, when it is necessary to connect the source or drain of two transistors to the source or drain of another transistor, the corresponding active film layers can be directly connected.

[0087] It should be noted that the multiple sub-pixel driving circuits may be distributed in an array, and the nth (n is an integer greater than or equal to 1) row of sub-pixel driving circuits share the nth initialization signal line VINT(n), the nth reset signal line RST(n), the gate control signal line G(n), and the light emitting control signal line EM(n); the nth column of sub-pixel driving circuits share the nth power signal line VDD(n) and the nth data signal line D(n). In addition, Fig.12RST(n+1) is the n+1th reset signal line RST(n+1) applied by the n+1th row sub-pixel driving circuit, G(n+1) is the gate control signal line applied by the n+1th row sub-pixel driving circuit, and EM(n+1) is the light emission control signal line applied by the n+1th row sub-pixel driving circuit. In addition, Fig.12 The small rectangular boxes with cross lines in the figure represent vias.

[0088] In addition, the above-mentioned reset signal line, gate control signal line and light-emitting control signal line can all be coupled to the output end of the corresponding shift register, and the corresponding signal is generated by the corresponding shift register and output to the corresponding signal line. For example, the reset shift register RST GOA generates a reset signal and transmits it to the corresponding reset signal line; the gate control shift register Gate GOA generates a gate control signal and transmits it to the corresponding gate control signal line; the light-emitting control shift register EM GOA generates a light-emitting control signal and transmits it to the corresponding light-emitting control signal line.

[0089] At the same time, in order to further improve the screen-to-body ratio, the present invention integrates RST GOA and Gate GOA, omits RSTGOA, and cascades at the output end of Gate GOA, connects the gate control signal line G(n) of this row with the upstream reset signal line RST(n-1), and uses the gate control signal output by the gate control signal line G(n) of this row as the upstream reset signal.

[0090] The substrate used in the above display panel may be a polyimide (PI) substrate, which may be a single-layer PI substrate or a double-layer PI substrate with a barrier layer added in the middle; in addition, Figure 7 As shown, a buffer layer 50 may be introduced between the substrate 40 and the driving circuit layer (formed in the display device 60), a cover plate 70 may be provided on the side of the display device 60 facing away from the substrate 40, and a fingerprint recognition module 80 may be provided on the side of the substrate 40 facing away from the cover plate.

[0091] After the driving circuit layer is manufactured, a stacked anode layer, a pixel defining layer, a light-emitting layer and a cathode layer may be sequentially formed on the side of the driving circuit layer facing away from the substrate 40, wherein the anode layer includes anode patterns corresponding one-to-one to the sub-pixel driving circuits, and the pixel defining layer defines opening areas corresponding one-to-one to each anode pattern on the side of the anode layer facing away from the substrate 40; the light-emitting layer includes a plurality of organic light-emitting units corresponding one-to-one to the opening areas, and each of the organic light-emitting units is printed in the corresponding opening area; the cathode layer may be formed as a whole layer structure covering all the opening areas, that is, each sub-pixel may reuse the same cathode layer.

[0092] In the above embodiment, the display panel is provided to include a metal pattern corresponding one to one with the anode pattern, and in a direction perpendicular to the substrate, the metal pattern is located between the corresponding sub-pixel driving circuit and the corresponding anode pattern, and can be specifically made of a second source-drain metal layer, and the anode pattern is electrically connected to the corresponding sub-pixel driving circuit through the corresponding metal pattern, so that the metal pattern can be electrically connected to the drain D5 of the fifth transistor T5 in the corresponding sub-pixel driving circuit, which can not only reduce the resistance of the drain D5 of the fifth transistor T5, but also realize the electrical connection between the drain D5 of the fifth transistor T5 and the corresponding anode pattern.

[0093] In some embodiments, the light shielding layer and the metal pattern are provided in the same layer and with the same material.

[0094] It is worth noting that the above-mentioned "same layer" refers to a layer structure formed by using the same film-forming process to form a film layer for forming a specific pattern, and then using the same mask through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses.

[0095] When the light shielding layer 90 and the metal pattern are provided in the same layer and with the same material, the steps of manufacturing the light shielding layer 90 and the metal pattern may specifically include: first forming a whole layer of the second source-drain metal layer, then forming a photoresist on the second source-drain metal layer, exposing the photoresist using a mask including a light-transmitting area and a non-light-transmitting area to form a photoresist retaining area and a photoresist removing area, wherein the photoresist retaining area corresponds to an area where the first part of the metal pattern and the light shielding layer 90 not including the imaging pinhole 91 is located, and the photoresist removing area corresponds to other areas except the area where the metal pattern and the first part are located, then developing the exposed photoresist to remove the photoresist located in the photoresist removing area to expose the second source-drain metal layer located in the photoresist removing area, then etching the second source-drain metal layer exposed in the photoresist removing area to completely remove the second source-drain metal layer exposed in the photoresist removing area, and finally stripping the photoresist in the photoresist retaining area to form the light shielding layer 90 (i.e. including the first part and the imaging pinhole 91) and the metal pattern.

[0096] The light shielding layer 90 and the metal pattern are arranged in the same layer and with the same material, so that the light shielding layer 90 and the metal pattern can be formed simultaneously through one patterning process, avoiding the need to add an additional patterning process, and better simplifying the manufacturing process of the display panel.

[0097] In some embodiments, each of the pixel units provided in the above embodiments includes a first color sub-pixel, a second color sub-pixel and a third color sub-pixel; wherein the luminous efficiency of the first color sub-pixel is greater than the luminous efficiency of the second color sub-pixel, and the luminous efficiency of the second color sub-pixel is greater than the luminous efficiency of the third color sub-pixel; the target sub-pixel includes the second color sub-pixel and / or the third color sub-pixel; there is a first distance between the orthographic projection of the imaging pinhole on the substrate and the orthographic projection of the first color sub-pixel on the substrate, there is a second distance between the orthographic projection of the imaging pinhole on the substrate and the orthographic projection of the second color sub-pixel on the substrate, there is a third distance between the orthographic projection of the imaging pinhole on the substrate and the orthographic projection of the third color sub-pixel on the substrate, the second distance is less than the first distance, and / or the third distance is less than the first distance.

[0098] Specifically, in the display panel provided by the above embodiment, the specific color of the sub-pixel included in each pixel unit can be set according to actual needs, and because the types of organic light-emitting material layers corresponding to sub-pixels of different colors are different, the luminous efficiency corresponding to sub-pixels of different colors is different.

[0099] Exemplarily, each pixel unit includes a first color sub-pixel, a second color sub-pixel and a third color sub-pixel. When the luminous efficiency of the first color sub-pixel is greater than the luminous efficiency of the second color sub-pixel and the luminous efficiency of the second color sub-pixel is greater than the luminous efficiency of the third color sub-pixel, the target sub-pixel can be set to include the second color sub-pixel and / or the third color sub-pixel.

[0100] Furthermore, in the case where the target sub-pixel includes the second color sub-pixel and / or the third color sub-pixel, the distances between the imaging pinhole 91 and the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel may have the following relationship:

[0101] There is a first distance between the orthographic projection of the imaging pinhole on the substrate and the orthographic projection of the first color sub-pixel on the substrate, there is a second distance between the orthographic projection of the imaging pinhole on the substrate and the orthographic projection of the second color sub-pixel on the substrate, there is a third distance between the orthographic projection of the imaging pinhole on the substrate and the orthographic projection of the third color sub-pixel on the substrate, the second distance is smaller than the first distance, and / or the third distance is smaller than the first distance.

[0102] Therefore, when the imaging hole 91 is set within the preset range around the second color sub-pixel and / or the third color sub-pixel in the above manner, most of the light passing through the imaging hole 91 is light emitted by the second color sub-pixel and / or the third color sub-pixel, and only a small part of the light emitted by the first color sub-pixel passes through the imaging hole 91; or, the light passing through the imaging hole 91 is all light emitted by the second color sub-pixel and / or the third color sub-pixel, and no light emitted by the first color sub-pixel passes through the imaging hole 91; since the luminous efficiency of the second color sub-pixel and / or the third color sub-pixel is low, the brightness of the light emitted by the second color sub-pixel and / or the third color sub-pixel is more adapted to the recognition capability of the fingerprint recognition module, thereby being more conducive to improving the accuracy of fingerprint recognition.

[0103] In some embodiments, the first color sub-pixel includes a green sub-pixel, the second color sub-pixel includes a red sub-pixel, and the third color sub-pixel includes a blue sub-pixel; the multiple pixel units are distributed in an array, and each of the pixel units includes a red sub-pixel, a blue sub-pixel and two green sub-pixels.

[0104] Specifically, each pixel unit can be arranged to include four sub-pixels, which are specifically a red sub-pixel R, a blue sub-pixel B and two green sub-pixels G, so that the pixel unit is formed into an RGBG structure; since the luminous efficiency of the green organic light-emitting material layer included in the green sub-pixel is higher than the luminous efficiency of the red organic light-emitting material layer included in the red sub-pixel, and the luminous efficiency of the red organic light-emitting material layer is higher than the luminous efficiency of the blue organic light-emitting material layer included in the blue sub-pixel, therefore, when the same data signal is written to the green sub-pixel, the red sub-pixel and the blue sub-pixel, the luminous brightness of the green sub-pixel is higher than the luminous brightness of the red sub-pixel, and the luminous brightness of the red sub-pixel is higher than the luminous brightness of the blue sub-pixel.

[0105] When the imaging pinhole 91 is set within the preset range around the blue sub-pixel, most or all of the light passing through the imaging pinhole 91 is blue light. Since the luminous brightness of the blue light is low, the fingerprint recognition has a higher recognition accuracy. When the imaging pinhole 91 is set within the preset range around the red sub-pixel, since the luminous brightness of the red sub-pixel is higher than the luminous brightness of the blue sub-pixel and lower than the luminous brightness of the green sub-pixel, it is possible to ensure that there is light of sufficient brightness as the reflected light for fingerprint recognition while avoiding the influence of excessive brightness on the fingerprint recognition accuracy. Therefore, setting the imaging pinhole 91 within the preset range around the red sub-pixel can further improve the fingerprint recognition accuracy.

[0106] When the above pixel unit is formed into an RGBG structure, there are various specific pixel arrangement methods, and two specific structures are given as examples below.

[0107] The first structure, such as Figure 1 and Figure 2 As shown, in the pixel units located in the same row, the red sub-pixel R and the blue sub-pixel B included in each pixel unit are distributed in one row, and the green sub-pixel G included in each pixel unit is distributed in another row; and there is one green sub-pixel G between the red sub-pixel R and the blue sub-pixel B adjacent to each other in a direction parallel to the row.

[0108] The second structure, such as Figure 4 and Figure 5 As shown, the two green sub-pixels G included in each pixel unit form a green sub-pixel group, and the two green sub-pixels G in the green sub-pixel group are arranged in a direction perpendicular to the row; in the pixel units located in the same row, the red sub-pixel R, the blue sub-pixel B and the green sub-pixel group included in each pixel unit are all distributed in a row.

[0109] In the above two pixel structures, when the imaging hole 91 is set at a position close to the red sub-pixel R and / or the blue sub-pixel B, the imaging hole 91 can be far away from the green sub-pixel G, so that during the fingerprint recognition process, the light passing through the imaging hole 91 is basically red light or blue light, so that the brightness of the light used for fingerprint recognition is moderate, thereby better ensuring the accuracy of fingerprint recognition.

[0110] like Figure 3 and Figure 6 As shown, in some embodiments, the display panel provided in the above embodiments further includes:

[0111] The reflective light shielding layer 20 is located on the side of the imaging pinhole 91 facing away from the substrate, and the orthographic projection of the reflective light shielding layer 20 on the substrate is located between the orthographic projection of the target sub-pixel on the substrate and the orthographic projection of at least one non-target sub-pixel on the substrate; the orthographic projection of the imaging pinhole 91 on the substrate is located between the orthographic projection of the target sub-pixel on the substrate and the orthographic projection of the reflective light shielding layer 20 on the substrate.

[0112] Specifically, a reflective light shielding layer 20 may be provided on the side of the imaging pinhole 91 facing away from the substrate, and the reflective light shielding layer 20 is used to block light emitted by non-target sub-pixels from passing through the imaging pinhole 91 after being reflected by the fingerprint. The specific position of the reflective light shielding layer 20 can be set according to actual needs. For example, the orthographic projection of the reflective light shielding layer 20 on the substrate is set to be located between the orthographic projection of the target sub-pixel on the substrate and the orthographic projection of at least one non-target sub-pixel on the substrate, and the orthographic projection of the imaging hole 91 on the substrate is set to be located between the orthographic projection of the target sub-pixel on the substrate and the orthographic projection of the reflective light shielding layer 20 on the substrate. This setting method ensures that when performing fingerprint recognition, the light emitted by the target sub-pixel will not be blocked by the reflective light shielding layer 20 after being reflected by the fingerprint, and can directly pass through the imaging hole 91 to be received by the fingerprint recognition module, thereby ensuring a high-precision fingerprint recognition function. At the same time, the light emitted by the non-target sub-pixel will be blocked by the reflective light shielding layer 20 after being reflected by the fingerprint, and cannot pass through the imaging hole 91 to be received by the fingerprint recognition module.

[0113] It can be seen that setting the above-mentioned reflective light shielding layer 20 in the display panel can ensure that when the display panel performs fingerprint recognition, the reflected light passing through the imaging hole 91 is only the light emitted by the target sub-pixel, or most of the reflected light passing through the imaging hole 91 is the light emitted by the target sub-pixel, so that the brightness of the reflected light used for fingerprint recognition is more in line with the recognition capability of the fingerprint recognition module, further improving the fingerprint recognition accuracy.

[0114] In some embodiments, the display panel further comprises:

[0115] The reflective light shielding layer 20 is located on the side of the imaging hole 91 facing away from the substrate, and the orthographic projection of the reflective light shielding layer 20 on the substrate is located between the orthographic projection of the target sub-pixel on the substrate and the orthographic projection of at least one non-target sub-pixel on the substrate; the orthographic projection of the target sub-pixel on the substrate is located between the orthographic projection of the imaging hole 91 on the substrate and the orthographic projection of the reflective light shielding layer 20 on the substrate.

[0116] Specifically, the above-mentioned setting method ensures that when performing fingerprint recognition, the light emitted by the target sub-pixel will not be blocked by the reflective light shielding layer 20 after being reflected by the fingerprint, and can directly pass through the imaging hole 91 to be received by the fingerprint recognition module, thereby ensuring a high-precision fingerprint recognition function; at the same time, the light emitted by the non-target sub-pixel will be blocked by the reflective light shielding layer 20 after being reflected by the fingerprint, and cannot pass through the imaging hole 91 to be received by the fingerprint recognition module.

[0117] It can be seen that by arranging the reflective light shielding layer 20 and the imaging pinhole 91 in the display panel in the above manner, it can be ensured that when the display panel performs fingerprint recognition, the reflected light passing through the imaging pinhole 91 is only the light emitted by the target sub-pixel, thereby making the brightness of the reflected light used for fingerprint recognition more consistent with the recognition capability of the fingerprint recognition module, further improving the fingerprint recognition accuracy.

[0118] For further information, please refer to Figure 3 and Figure 6 The orthographic projection of the reflective light shielding layer 20 on the substrate can be set to be located between the orthographic projections of the pixel units in adjacent rows on the substrate; the orthographic projection of the imaging pinhole 91 on the substrate is located between the orthographic projection of the target sub-pixel included in the pixel unit in the adjacent row on the substrate and the orthographic projection of the reflective light shielding layer 20 on the substrate.

[0119] Specifically, the specific setting positions of the above-mentioned reflective light shielding layer 20 are various. In a specific embodiment, the orthographic projection of the reflective light shielding layer 20 on the substrate can be set between the orthographic projections of the pixel units in adjacent rows on the substrate, and the orthographic projection of the imaging pinhole 91 on the substrate is set between the orthographic projection of the target sub-pixel included in the pixel unit in the adjacent row on the substrate and the orthographic projection of the reflective light shielding layer 20 on the substrate. This setting method can better ensure the shading function of the reflective light shielding layer 20 for the reflected light corresponding to the non-target sub-pixel.

[0120] In some embodiments, the display panel also includes a signal line extending along the extension direction of the row, the signal line is located between the imaging hole 91 and the reflective light shielding layer 20, the reflective light shielding layer 20 has the same extension direction as the signal line, and the reflective light shielding layer 20 is connected in parallel with the signal line.

[0121] Specifically, the display panel also includes some signal lines, which are used to transmit corresponding signals to ensure that the display panel realizes normal display function. Among these signal lines, some signal lines have a longer length, which makes their own resistance larger. In this way, when using the signal line to transmit signals, the loss generated is larger. In order to reduce the loss of the signal line, the reflective light shielding layer 20 can be extended in the same extension direction as the signal line, and the reflective light shielding layer 20 and the signal line are connected in parallel, so that the resistance of the signal line is reduced, and the energy loss in the signal transmission process is effectively reduced. It is also worth noting that the above-mentioned connection of the reflective light shielding layer 20 and the signal line in parallel, in addition to reducing the resistance of the signal line, the reflective light shielding layer 20 also has a multiplexing function, that is, the reflective light shielding layer 20 can be multiplexed as the signal line.

[0122] Furthermore, the reflective light shielding layer 20 can be arranged in the same layer or in a different layer as the signal line. When the reflective light shielding layer 20 and the signal line are arranged in the same layer, the reflective light shielding layer 20 and the signal line can be directly connected to achieve parallel connection of the two. When the reflective light shielding layer 20 and the signal line are arranged in different layers, an overlapping area can be set between the orthographic projection of the reflective light shielding layer 20 on the substrate and the orthographic projection of the signal line on the substrate, and the reflective light shielding layer 20 and the signal line are connected in parallel through a via set in the overlapping area.

[0123] Specifically, when the reflective light shielding layer 20 and the signal line are connected in parallel through a via, the specific position of the via can be set according to actual needs. For example, the display panel includes a display area and a non-display area arranged around the display area, and the via is located in the display area or the non-display area.

[0124] In some embodiments, the signal line may include an initialization signal line.

[0125] Specifically, the display panel includes a variety of signal lines, such as power signal lines, data signal lines, initialization signal lines, etc. In order to reduce the resistance of the signal lines and reduce the energy loss during signal transmission, the reflective light shielding layer 20 can be connected in parallel with any of the above signal lines while ensuring the normal operating performance of the display panel.

[0126] In some embodiments, the sub-pixel includes an anode pattern, an organic light-emitting unit, and a cathode layer stacked in sequence from close to the substrate to away from the substrate; the reflective light shielding layer 20 is arranged in the same layer and material as the anode pattern.

[0127] Specifically, taking the use of indium tin oxide (ITO) and silver (Ag) to form a stacked anode pattern as an example, the steps of making the reflective light shielding layer 20 and the anode pattern specifically include: depositing a first ITO film, an Ag film, and a second ITO film in a stacked arrangement in a direction from close to the substrate to away from the substrate, and then continuing to form a photoresist on the second ITO film, exposing the photoresist to form a photoresist retention area and a photoresist removal area, wherein the photoresist retention area corresponds to the area where the reflective light shielding layer 20 and the anode pattern are located, and the photoresist removal area corresponds to the area where the reflective light shielding layer 20 and the anode pattern are located. The other areas except the area where the reflective light shielding layer 20 and the anode pattern are located should be removed, and then the exposed photoresist is developed to remove the photoresist located in the photoresist removal area to expose the second ITO film located in the photoresist removal area, and then the first ITO film, the Ag film, and the second ITO film located in the photoresist removal area are etched to remove the first ITO film, the Ag film, and the second ITO film located in the photoresist removal area, and finally the photoresist located in the photoresist retention area is stripped to form the reflective light shielding layer 20 and the anode pattern. It is worth noting that the reflective light shielding layer 20 and the anode pattern are both formed by the first ITO pattern, the Ag pattern, and the second ITO pattern stacked.

[0128] It can be seen that the reflective light shielding layer 20 and the anode pattern are set in the same layer and material, so that the reflective light shielding layer 20 and the anode pattern can be formed simultaneously in the same composition process, avoiding the addition of an additional composition process for the production of the reflective light shielding layer 20, and greatly saving the production process flow of the display panel.

[0129] like Fig.12 As shown, in some embodiments, the display panel further includes:

[0130] a light emitting control signal line extending in the same direction as the initialization signal line, and a power supply signal line extending in a direction perpendicular to the initialization signal line;

[0131] The sub-pixel driving circuits are arranged in an array, and are divided into a plurality of rows of sub-pixel driving circuits along the extension direction of the rows, and are divided into a plurality of columns of sub-pixel driving circuits along the column direction perpendicular to the extension direction of the rows. The initialization signal lines and the light-emitting control signal lines correspond one-to-one to the plurality of rows of sub-pixel driving circuits, and the sub-pixel driving circuits in the same row share a corresponding light-emitting control signal line and a corresponding initialization signal line; the power signal lines correspond one-to-one to the plurality of columns of sub-pixel driving circuits, and the sub-pixel driving circuits in the same column share a corresponding power signal line;

[0132] The positive projection of the imaging pinhole 91 on the substrate is located between the positive projection of the light emitting control signal line corresponding to the previous row of sub-pixel driving circuits on the substrate and the positive projection of the initialization signal line corresponding to the adjacent next row of sub-pixel driving circuits on the substrate; and / or,

[0133] The orthographic projection of the imaging pinhole 91 on the substrate is located between the orthographic projection of the metal pattern corresponding to the target sub-pixel on the substrate and the orthographic projection of the power signal line corresponding to the target sub-pixel on the substrate.

[0134] Specifically, Fig.12 The structure shown includes initialization signal lines VINT(n) and VINT(n+1), light emitting control signal lines EM(n) and EM(n+1), power signal lines VDD(n) and VDD(n+1), and the metal graphics corresponding to each sub-pixel are located at the via hole between the fifth transistor T5 and the seventh transistor T7.

[0135] When setting the specific position of the imaging pinhole 91, exemplarily, the orthographic projection of the imaging pinhole 91 on the substrate can be set to be located between the orthographic projection of the light emitting control signal line corresponding to the previous row of sub-pixel driving circuits on the substrate and the orthographic projection of the initialization signal line corresponding to the adjacent subsequent row of sub-pixel driving circuits on the substrate; and / or, the orthographic projection of the imaging pinhole 91 on the substrate can be set to be located between the orthographic projection of the metal pattern corresponding to the target sub-pixel on the substrate and the orthographic projection of the power signal line corresponding to the target sub-pixel on the substrate.

[0136] Since the light-emitting control signal line, the initialization signal line, the metal pattern and the power signal line are generally made of opaque metal materials, the imaging pinhole 91 is set in the above manner to avoid the light-emitting control signal line, the initialization signal line, the metal pattern and the power signal line from blocking the imaging pinhole 91 as much as possible, thereby ensuring the luminous flux of the imaging pinhole 91 to the light reflected by the fingerprint, so that the display panel has a higher fingerprint recognition accuracy.

[0137] In some embodiments, the minimum distance between the orthographic projection of the imaging pinhole 91 on the substrate and the orthographic projection of the light-emitting control signal line on the substrate, the minimum distance between the orthographic projection of the imaging pinhole 91 on the substrate and the orthographic projection of the initialization signal on the substrate, the minimum distance between the orthographic projection of the imaging pinhole 91 on the substrate and the orthographic projection of the power signal line on the substrate, and the minimum distance between the orthographic projection of the imaging pinhole 91 on the substrate and the orthographic projection of the metal pattern on the substrate are all greater than a preset reference value.

[0138] Specifically, setting the above distances to be greater than the preset reference value can better ensure the luminous flux of the imaging hole 91 to the light reflected by the fingerprint, which is beneficial to further improve the fingerprint recognition accuracy of the display panel; illustratively, the preset reference value is 0.5μm, but is not limited to this.

[0139] In some embodiments, the driving circuit layer includes: a power signal line, a light-emitting control signal line, a data signal line, an initialization signal line and a reset signal line; the multiple sub-pixel driving circuits are arranged in an array, and each of the sub-pixel driving circuits includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor and a sixth transistor; wherein the source of the fourth transistor is connected to the power signal line, the drain of the fourth transistor is connected to the source of the first transistor, the gate of the fourth transistor is connected to the light-emitting control signal line, the gate of the second transistor is connected to the gate control signal line, the source of the second transistor is connected to the data signal line, the drain of the second transistor is connected to the source of the first transistor, the gate of the third transistor is connected to the gate control signal line, the source of the third transistor is connected to the drain of the first transistor, the drain of the third transistor is connected to the gate of the first transistor, the gate of the fifth transistor is connected to the light-emitting control signal line, the source of the fifth transistor is connected to the drain of the first transistor, the drain of the fifth transistor is connected to the first electrode of the corresponding sub-pixel, the gate of the sixth transistor is connected to the reset signal line, the source of the sixth transistor is connected to the initialization signal line, and the drain of the sixth transistor is connected to the gate of the first transistor.

[0140] The orthographic projection of the imaging pinhole on the substrate is located between two adjacent rows of the sub-pixel driving circuits, and the distance between the orthographic projection of the imaging pinhole on the substrate and the orthographic projection of the channel of the nearest fifth transistor in the sub-pixel driving circuits in the previous row on the substrate is smaller than the distance between the orthographic projection of the imaging pinhole on the substrate and the orthographic projection of the channel of the nearest sixth transistor in the sub-pixel driving circuits in the next row on the substrate; and smaller than the distance between the orthographic projection of the imaging pinhole on the substrate and the orthographic projection of the channel of the nearest third transistor in the sub-pixel driving circuits in the next row on the substrate.

[0141] Specifically, if Fig.10 and Fig.12 As shown, the distance between the imaging aperture 91 and the channel region of the nearest sixth transistor T6 in the next row of sub-pixel driving circuits, and the distance between the imaging aperture 91 and the channel region of the nearest third transistor T3 in the next row of sub-pixel driving circuits can be set to be relatively far, as shown in FIG. Fig.12As shown in the figure, the distance d1 between the imaging hole 91 and the channel region of the sixth transistor T6 is greater than the distance d2 between the imaging hole 91 and the channel region of the fifth transistor T5. This arrangement can reduce the influence of the light passing through the imaging hole 91 on the working performance of the sixth transistor T6 and the third transistor T3, and further avoids the influence on the node N1, thereby effectively improving the stability of the operation of the sub-pixel driving circuit.

[0142] In some embodiments, the aperture of the imaging pinhole 91 may be set between 2 μm and 20 μm. Furthermore, the aperture of the imaging pinhole 91 may be set between 4 μm and 7 μm.

[0143] Specifically, the imaging holes 91 are arranged within the above range, so that the imaging holes 91 occupy a smaller space while meeting the fingerprint recognition requirements, thereby being more conducive to the arrangement of the conductive patterns in the display panel.

[0144] In some embodiments, the imaging pinhole 91 is located in any local area 30 within the display area of ​​the display panel, such as Figure 8 As shown; alternatively, the imaging holes 91 are distributed throughout the display area.

[0145] Specifically, according to actual application needs, the fingerprint recognition area in the display panel 10 can be set in a local area 30 in the display area, or the entire display area can be set as the fingerprint recognition area. When the fingerprint recognition area is set in the local area 30 of the display area, the imaging holes 91 can be set in the local area 30. When the entire display area is set as the fingerprint recognition area, the imaging holes 91 can be evenly distributed in the entire display area.

[0146] It is worth noting that when setting the imaging pinhole 91, it is not necessary to set one imaging pinhole 91 for each pixel unit, and one imaging pinhole 91 can be set every few pixel units.

[0147] like Fig. 9 As shown, in some embodiments, the plurality of imaging holes 91 included in the display panel may be distributed in an array.

[0148] Specifically, the plurality of imaging holes 91 included in the display panel may be distributed according to actual needs. For example, the plurality of imaging holes 91 may be arranged to be distributed in an array, and the lateral spacing and the longitudinal spacing of the plurality of imaging holes 91 may be the same or different.

[0149] Distributing the plurality of imaging holes 91 included in the display panel in an array is more conducive to all-round collection of fingerprints, and further improves the fingerprint recognition accuracy of the display panel.

[0150] An embodiment of the present invention further provides a display device, comprising the display panel provided by the above embodiment.

[0151] Since in the display panel provided in the above embodiment, the brightness of the light used for fingerprint recognition is moderate by controlling the light component passing through the imaging hole 91, thereby effectively improving the fingerprint recognition accuracy, the display device provided in the embodiment of the present invention also has the above-mentioned beneficial effects when including the display panel provided in the above embodiment, which will not be repeated here.

[0152] It should be noted that the display device may be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, and a tablet computer.

[0153] An embodiment of the present invention further provides a method for manufacturing a display panel, the method comprising:

[0154] A light shielding layer 90 is formed on the substrate 40, and a plurality of imaging pinholes 91 are provided on the light shielding layer 90;

[0155] A driving circuit layer is fabricated on the substrate 40, wherein the driving circuit layer includes a plurality of sub-pixel driving circuits;

[0156] A metal pattern corresponding to the sub-pixel driving circuit is formed on a side of the driving circuit layer facing away from the substrate 40;

[0157] A plurality of pixel units are made on the side of the metal pattern facing away from the substrate 40, each of the pixel units includes at least two sub-pixels, and the sub-pixels correspond one-to-one to the sub-pixel driving circuit; the orthographic projection of the imaging hole 91 on the substrate 40 is located within a preset range around the orthographic projection of the target sub-pixel on the substrate 40, and the luminous efficiency of the target sub-pixel is less than a threshold value; the sub-pixel includes an anode pattern, an organic light-emitting unit and a cathode layer which are stacked in sequence in a direction away from the substrate 40, and the anode pattern is electrically connected to the corresponding sub-pixel driving circuit through the corresponding metal pattern.

[0158] Specifically, the plurality of pixel units included in the display panel may be distributed in an array on the substrate, and each pixel unit may include a plurality of sub-pixels. The colors of the sub-pixels may be set according to actual needs. For example, each pixel unit includes at least a red sub-pixel, a green sub-pixel, and a blue sub-pixel. Among the various sub-pixels of different colors included in the pixel unit, the sub-pixels with a luminous efficiency less than a threshold are defined as target sub-pixels, and the sub-pixels with a luminous efficiency greater than or equal to the threshold are defined as non-target sub-pixels. The size of the threshold may be determined according to actual needs, as long as the brightness of the light emitted by the target sub-pixel does not exceed the recognition capability of the fingerprint recognition module when passing through the imaging pinhole 91 for fingerprint recognition, and the accuracy of fingerprint recognition can be improved.

[0159] The light shielding layer 90 included in the above-mentioned display panel can be directly formed on the surface of the substrate using metal materials, or formed on the side of the sub-pixel driving circuit facing away from the substrate, but is not limited thereto. When the imaging pinhole 91 is formed on the light shielding layer 90, the position of the imaging pinhole 91 can be set according to actual needs. For example, the positive projection of the imaging pinhole 91 on the substrate is set to be located within the peripheral preset range of the positive projection of the target sub-pixel on the substrate. The peripheral preset range can also be set according to actual needs, as long as most of the light passing through the imaging pinhole 91 is the light emitted by the target sub-pixel, and only a small part of the light emitted by the non-target sub-pixel passes through the imaging pinhole 91; or, the light passing through the imaging pinhole 91 is all the light emitted by the target sub-pixel, and no light emitted by the non-target sub-pixel passes through the imaging pinhole 91.

[0160] In the display panel manufactured by the manufacturing method provided by the embodiment of the present invention, by setting the imaging pinhole 91 on the shading layer 90 around the target sub-pixel whose luminous efficiency is less than the threshold, when fingerprint recognition is performed, most or all of the light passing through the imaging pinhole 91 is emitted by the target sub-pixel, and the luminous efficiency of the target sub-pixel is less than the threshold, so that when the same data signal is input to each sub-pixel, the luminous brightness of the target sub-pixel is darker than the luminous brightness of the non-target pixel, that is, the brightness of the light emitted by the target sub-pixel is more suitable for the recognition ability of the fingerprint recognition module, so that when the fingerprint recognition module performs fingerprint recognition based on the light emitted by the target sub-pixel, the fingerprint recognition accuracy is higher; it can be seen that in the display panel manufactured by the manufacturing method provided by the embodiment of the present invention, by controlling the light component passing through the imaging pinhole 91, the brightness of the light used for fingerprint recognition is moderate, thereby effectively improving the fingerprint recognition accuracy.

[0161] In some embodiments, the manufacturing method also includes: manufacturing a reflective light shielding layer 20 on the side of the imaging pinhole 91 facing away from the substrate, the orthographic projection of the reflective light shielding layer 20 on the substrate being located between the orthographic projection of the target sub-pixel on the substrate and the orthographic projection of at least one non-target sub-pixel on the substrate; the orthographic projection of the imaging pinhole 91 on the substrate being located between the orthographic projection of the target sub-pixel on the substrate and the orthographic projection of the reflective light shielding layer 20 on the substrate; or, the orthographic projection of the target sub-pixel on the substrate being located between the orthographic projection of the imaging pinhole on the substrate and the orthographic projection of the reflective light shielding layer on the substrate.

[0162] Specifically, a reflective light shielding layer 20 may be formed on the side of the imaging pinhole 91 facing away from the substrate, and the reflective light shielding layer 20 is used to block light emitted by non-target sub-pixels from passing through the imaging pinhole 91 after being reflected by the fingerprint. The specific formation position of the reflective light shielding layer 20 can be set according to actual needs. For example, the orthographic projection of the reflective light shielding layer 20 on the substrate is set to be located between the orthographic projection of the target sub-pixel on the substrate and the orthographic projection of at least one non-target sub-pixel on the substrate, and the orthographic projection of the imaging hole 91 on the substrate is set to be located between the orthographic projection of the target sub-pixel on the substrate and the orthographic projection of the reflective light shielding layer 20 on the substrate; or, the orthographic projection of the target sub-pixel on the substrate is set to be located between the orthographic projection of the imaging hole on the substrate and the orthographic projection of the reflective light shielding layer on the substrate; this setting method makes it possible that when fingerprint recognition is performed, the light emitted by the target sub-pixel will not be blocked by the reflective light shielding layer 20 after being reflected by the fingerprint, and can directly pass through the imaging hole 91 to be received by the fingerprint recognition module, thereby ensuring a high-precision fingerprint recognition function; at the same time, the light emitted by the non-target sub-pixel will be blocked by the reflective light shielding layer 20 after being reflected by the fingerprint, and cannot pass through the imaging hole 91 to be received by the fingerprint recognition module.

[0163] It can be seen that making the above-mentioned reflective light shielding layer 20 in the display panel can ensure that when the display panel is performing fingerprint recognition, the reflected light passing through the imaging hole 91 is only the light emitted by the target sub-pixel, or most of the reflected light passing through the imaging hole 91 is the light emitted by the target sub-pixel, thereby making the brightness of the reflected light used for fingerprint recognition more in line with the recognition capability of the fingerprint recognition module, further improving the fingerprint recognition accuracy.

[0164] In some embodiments, the sub-pixel includes an anode pattern, an organic light-emitting unit, and a cathode layer stacked in sequence from close to the substrate to away from the substrate; the step of making the reflective light shielding layer 20 on the side of the imaging pinhole 91 facing away from the substrate specifically includes:

[0165] The reflective light shielding layer 20 and the anode pattern are formed simultaneously through one patterning process.

[0166] Specifically, taking the use of indium tin oxide (ITO) and silver (Ag) to form a stacked anode pattern as an example, the steps of making the reflective light shielding layer 20 and the anode pattern specifically include: depositing a first ITO film, an Ag film, and a second ITO film in a stacked arrangement in a direction from close to the substrate to away from the substrate, and then continuing to form a photoresist on the second ITO film, exposing the photoresist to form a photoresist retention area and a photoresist removal area, wherein the photoresist retention area corresponds to the area where the reflective light shielding layer 20 and the anode pattern are located, and the photoresist removal area corresponds to the area where the reflective light shielding layer 20 and the anode pattern are located. The other areas except the area where the reflective light shielding layer 20 and the anode pattern are located should be removed, and then the exposed photoresist is developed to remove the photoresist located in the photoresist removal area to expose the second ITO film located in the photoresist removal area, and then the first ITO film, the Ag film, and the second ITO film located in the photoresist removal area are etched to remove the first ITO film, the Ag film, and the second ITO film located in the photoresist removal area, and finally the photoresist located in the photoresist retention area is stripped to form the reflective light shielding layer 20 and the anode pattern. It is worth noting that the reflective light shielding layer 20 and the anode pattern are both formed by the first ITO pattern, the Ag pattern, and the second ITO pattern stacked.

[0167] It can be seen that when the reflective light shielding layer 20 and the anode pattern are manufactured using the manufacturing method provided in the above embodiment, the reflective light shielding layer 20 and the anode pattern can be formed simultaneously in the same composition process, thereby avoiding the need to add an additional composition process to manufacture the reflective light shielding layer 20, thereby greatly saving the manufacturing process flow of the display panel.

[0168] It should be noted that each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the method embodiment, since it is basically similar to the product embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the product embodiment.

[0169] Unless otherwise defined, the technical terms or scientific terms used in the present invention should be understood by people with ordinary skills in the field to which the present invention belongs. The words "first", "second" and similar words used in the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0170] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0171] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0172] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A display panel, characterized in that: It comprises a substrate, a driving circuit layer arranged on the substrate, and a plurality of pixel units arranged on a side of the driving circuit layer facing away from the substrate; Each of the pixel units includes at least two sub-pixels; The driving circuit layer includes sub-pixel driving circuits corresponding to the sub-pixels one by one; The sub-pixel comprises an anode pattern, an organic light-emitting unit and a cathode layer which are sequentially stacked in a direction from close to the substrate to far away from the substrate; The display panel further includes a metal pattern corresponding to the anode pattern one by one, wherein the metal pattern is located between the corresponding sub-pixel driving circuit and the corresponding anode pattern in a direction perpendicular to the substrate, and the anode pattern is electrically connected to the corresponding sub-pixel driving circuit through the corresponding metal pattern; The display panel further comprises: a light shielding layer disposed on the substrate, the light shielding layer being provided with a plurality of imaging pinholes, the orthographic projections of the imaging pinholes on the substrate being located within a preset range around the orthographic projections of target sub-pixels on the substrate, and the luminous efficiency of the target sub-pixels being less than a threshold value; The light shielding layer and the metal pattern are provided in the same layer and made of the same material; Each of the pixel units includes a first color sub-pixel, a second color sub-pixel and a third color sub-pixel; wherein the luminous efficiency of the first color sub-pixel is greater than the luminous efficiency of the second color sub-pixel, and the luminous efficiency of the second color sub-pixel is greater than the luminous efficiency of the third color sub-pixel; The target sub-pixel includes the second color sub-pixel and / or the third color sub-pixel; There is a first distance between the orthographic projection of the imaging pinhole on the substrate and the orthographic projection of the first color sub-pixel on the substrate, there is a second distance between the orthographic projection of the imaging pinhole on the substrate and the orthographic projection of the second color sub-pixel on the substrate, there is a third distance between the orthographic projection of the imaging pinhole on the substrate and the orthographic projection of the third color sub-pixel on the substrate, the second distance is smaller than the first distance, and / or the third distance is smaller than the first distance.

2. The display panel according to claim 1, characterized in that: The first color sub-pixel includes a green sub-pixel, the second color sub-pixel includes a red sub-pixel, and the third color sub-pixel includes a blue sub-pixel; The plurality of pixel units are distributed in an array, and each of the pixel units includes a red sub-pixel, a blue sub-pixel and two green sub-pixels.

3. The display panel according to claim 2, characterized in that: In the pixel units located in the same row, the red sub-pixels and the blue sub-pixels included in each pixel unit are distributed in one row, and the green sub-pixels included in each pixel unit are distributed in another row; There is one green sub-pixel between the adjacent red sub-pixel and the blue sub-pixel in a direction parallel to the row; the direction parallel to the row refers to a direction parallel to the arrangement direction of multiple pixel units in the same row of pixel units.

4. The display panel according to claim 2, characterized in that: The two green sub-pixels included in each pixel unit form a green sub-pixel group, and the two green sub-pixels in the green sub-pixel group are arranged in a direction perpendicular to the row; In the pixel units located in the same row, the red sub-pixel, the blue sub-pixel and the green sub-pixel group included in each pixel unit are all distributed in one row.

5. The display panel according to claim 1, characterized in that: The display panel further includes: a reflective light shielding layer located on a side of the imaging pinhole facing away from the substrate, wherein an orthographic projection of the reflective light shielding layer on the substrate is located between an orthographic projection of the target sub-pixel on the substrate and an orthographic projection of at least one non-target sub-pixel on the substrate; The orthographic projection of the imaging pinhole on the substrate is located between the orthographic projection of the target sub-pixel on the substrate and the orthographic projection of the reflective light shielding layer on the substrate.

6. The display panel according to claim 1, characterized in that: The display panel further includes: a reflective light shielding layer located on a side of the imaging pinhole facing away from the substrate, wherein an orthographic projection of the reflective light shielding layer on the substrate is located between an orthographic projection of the target sub-pixel on the substrate and an orthographic projection of at least one non-target sub-pixel on the substrate; The orthographic projection of the target sub-pixel on the substrate is located between the orthographic projection of the imaging pinhole on the substrate and the orthographic projection of the reflective light shielding layer on the substrate.

7. The display panel according to claim 5 or 6, characterized in that: The orthographic projection of the reflective light shielding layer on the substrate is located between the orthographic projections of the pixel units in adjacent rows on the substrate.

8. The display panel according to claim 7, characterized in that: The display panel also includes a signal line extending along the extension direction of the row, the signal line is located between the imaging hole and the reflective light shielding layer, the reflective light shielding layer has the same extension direction as the signal line, and the reflective light shielding layer is connected in parallel with the signal line; the extension direction along the row refers to: the arrangement direction of multiple pixel units in the same row of pixel units.

9. The display panel according to claim 8, characterized in that: There is an overlapping area between the orthographic projection of the reflective light shielding layer on the substrate and the orthographic projection of the signal line on the substrate, and the reflective light shielding layer and the signal line are connected in parallel via a via hole arranged in the overlapping area.

10. The display panel according to claim 9, characterized in that: The display panel includes a display area and a non-display area arranged around the display area, and the via hole is located in the display area or the non-display area.

11. The display panel according to claim 8, characterized in that: The signal lines include initialization signal lines.

12. The display panel according to claim 11, characterized in that: The display panel further includes: a light emitting control signal line extending in the same direction as the initialization signal line, and a power supply signal line extending in a direction perpendicular to the initialization signal line; The sub-pixel driving circuits are arranged in an array, and are divided into a plurality of rows of sub-pixel driving circuits along the extension direction of the rows, and are divided into a plurality of columns of sub-pixel driving circuits along the column direction perpendicular to the extension direction of the rows. The initialization signal lines and the light-emitting control signal lines correspond one-to-one to the plurality of rows of sub-pixel driving circuits, and the sub-pixel driving circuits in the same row share a corresponding light-emitting control signal line and a corresponding initialization signal line; the power signal lines correspond one-to-one to the plurality of columns of sub-pixel driving circuits, and the sub-pixel driving circuits in the same column share a corresponding power signal line; The orthographic projection of the imaging pinhole on the substrate is located between the orthographic projection of the light emitting control signal line corresponding to the sub-pixel driving circuit of the previous row on the substrate and the orthographic projection of the initialization signal line corresponding to the sub-pixel driving circuit of the next adjacent row on the substrate; and / or, The orthographic projection of the imaging pinhole on the substrate is located between the orthographic projection of the metal pattern corresponding to the target sub-pixel on the substrate and the orthographic projection of the power signal line corresponding to the target sub-pixel on the substrate.

13. The display panel according to claim 12, characterized in that: The minimum distance between the orthographic projection of the imaging pinhole on the substrate and the orthographic projection of the light-emitting control signal line on the substrate, the minimum distance between the orthographic projection of the imaging pinhole on the substrate and the orthographic projection of the initialization signal on the substrate, the minimum distance between the orthographic projection of the imaging pinhole on the substrate and the orthographic projection of the power signal line on the substrate, and the minimum distance between the orthographic projection of the imaging pinhole on the substrate and the orthographic projection of the metal pattern on the substrate are all greater than a preset reference value.

14. The display panel according to claim 5 or 6, characterized in that: The reflective light shielding layer and the anode pattern are provided in the same layer and with the same material.

15. The display panel according to claim 1, characterized in that: The plurality of imaging pinholes are distributed in an array, and the imaging pinholes are located in any local area within the display area of ​​the display panel; or, the imaging pinholes are distributed throughout the display area.

16. A display device, characterized in that: The invention comprises the display panel according to any one of claims 1 to 15.

17. A method for manufacturing a display panel, characterized in that: The production method comprises: A light shielding layer is formed on the substrate, wherein a plurality of imaging pinholes are arranged on the light shielding layer; Manufacturing a driving circuit layer on the substrate, wherein the driving circuit layer includes a plurality of sub-pixel driving circuits; Making a metal pattern corresponding to the sub-pixel driving circuit on a side of the driving circuit layer facing away from the substrate; A plurality of pixel units are fabricated on a side of the metal pattern facing away from the substrate, each of the pixel units includes at least two sub-pixels, and the sub-pixels correspond to the sub-pixel driving circuits one by one; the positive projection of the imaging pinhole on the substrate is located within a preset range around the positive projection of the target sub-pixel on the substrate, and the luminous efficiency of the target sub-pixel is less than a threshold; the sub-pixel includes an anode pattern, an organic light-emitting unit, and a cathode layer that are sequentially stacked in a direction away from the substrate, and the anode pattern is electrically connected to the corresponding sub-pixel driving circuit through the corresponding metal pattern; The light shielding layer and the metal pattern are provided in the same layer and made of the same material; Each of the pixel units includes a first color sub-pixel, a second color sub-pixel and a third color sub-pixel; wherein the luminous efficiency of the first color sub-pixel is greater than the luminous efficiency of the second color sub-pixel, and the luminous efficiency of the second color sub-pixel is greater than the luminous efficiency of the third color sub-pixel; The target sub-pixel includes the second color sub-pixel and / or the third color sub-pixel; There is a first distance between the orthographic projection of the imaging pinhole on the substrate and the orthographic projection of the first color sub-pixel on the substrate, there is a second distance between the orthographic projection of the imaging pinhole on the substrate and the orthographic projection of the second color sub-pixel on the substrate, there is a third distance between the orthographic projection of the imaging pinhole on the substrate and the orthographic projection of the third color sub-pixel on the substrate, the second distance is smaller than the first distance, and / or the third distance is smaller than the first distance.

18. The method for manufacturing a display panel according to claim 17, characterized in that: The production method further comprises: A reflective light shielding layer is formed on the side of the imaging pinhole facing away from the substrate, wherein the orthographic projection of the reflective light shielding layer on the substrate is located between the orthographic projection of the target sub-pixel on the substrate and the orthographic projection of at least one non-target sub-pixel on the substrate; The orthographic projection of the imaging pinhole on the substrate is located between the orthographic projection of the target sub-pixel on the substrate and the orthographic projection of the reflective light shielding layer on the substrate; or, The orthographic projection of the target sub-pixel on the substrate is located between the orthographic projection of the imaging pinhole on the substrate and the orthographic projection of the reflective light shielding layer on the substrate.

19. The method for manufacturing a display panel according to claim 18, characterized in that: The step of making a reflective light shielding layer on the side of the imaging pinhole facing away from the substrate specifically comprises: The reflective light shielding layer and the anode pattern are formed simultaneously through one patterning process.

Images