Semiconductor packages and package-on-package types

Abstract

A semiconductor package includes: a first packaging substrate; a first semiconductor device, the first semiconductor device being mounted on the first packaging substrate; a second packaging substrate, the second packaging substrate being arranged on an upper portion of the first semiconductor device; and a heat dissipation material layer, the heat dissipation material layer being arranged between the first semiconductor device and the second packaging substrate and having a thermal conductivity of approximately 0.5 W / m·K to approximately 20 W / m·K, wherein the heat dissipation material layer is in direct contact with an upper surface of the first semiconductor device and a conductor of the second packaging substrate.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0146960, filed on November 15, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to a semiconductor package and a package-on-package (PoP) type package, and more particularly, to a semiconductor package and a PoP type package capable of smoothly releasing heat generated from a semiconductor device located at a lower portion of the semiconductor package and the PoP type package. Background Art

[0004] As the operating speed of semiconductor components increases, the heat generated from the semiconductor components also increases. Unless the generated heat is dissipated smoothly from the semiconductor components, the semiconductor device including the semiconductor components may be damaged or its performance may be reduced. Therefore, there is a need for a method for quickly dissipating the heat generated from the semiconductor components to maintain the reliability of the semiconductor components and enable the semiconductor components to operate smoothly. In particular, when the heat generated from the lower package in a PoP-type semiconductor package is not quickly dissipated, the heat may accumulate in the lower package, thereby damaging the lower package or affecting its performance. Summary of the Invention

[0005] The inventive concept provides a semiconductor package capable of smoothly dissipating heat generated from a semiconductor device.

[0006] The inventive concept also provides a package-on-package (PoP) type package capable of smoothly dissipating heat generated from a semiconductor device located at a lower portion thereof.

[0007] According to an embodiment of the inventive concept, a semiconductor package includes: a first packaging substrate; a first semiconductor device located on the first packaging substrate; a second packaging substrate located on an upper portion of the first semiconductor device; and a heat dissipation material layer located between the first semiconductor device and the second packaging substrate. The heat dissipation material layer has a thermal conductivity of approximately 0.5 W / m·K to approximately 20 W / m·K. The heat dissipation material layer is in direct contact with an upper surface of the first semiconductor device and a conductor of the second packaging substrate.

[0008] According to another embodiment of the inventive concept, a package-on-package (PoP) type package includes: a first package; a second package, the second package being located on an upper portion of the first package; and a heat dissipation material layer. The first package includes a first semiconductor device located on a first package substrate. The second package includes a second semiconductor device located on a second package substrate. The second package substrate includes: a core layer; an upper wiring extending on an upper surface of the core layer; a lower wiring extending on a lower surface of the core layer; an upper insulator layer covering the upper surface of the core layer and at least a portion of the upper wiring; and a lower insulator layer covering the lower surface of the core layer and at least a portion of the lower wiring. The heat dissipation material layer is in physical contact with the exposed lower wiring through the lower insulator layer and the upper surface of the first semiconductor device. The lower insulator layer at least partially exposes the lower wiring to provide exposed lower wiring.

[0009] According to another embodiment of the inventive concept, a package-on-package (PoP) type package includes: a first package; a second package located on an upper portion of the first package; and a heat dissipation material layer located between the first package substrate and the second package substrate. The first package includes a first semiconductor device located on the first package substrate. The second package includes a second semiconductor device located on the second package substrate. The first package substrate includes a first core layer, a first upper pad located on an upper portion of the first core layer, and a first lower pad located on a lower portion of the first core layer. The second package substrate includes: a second core layer; a second upper pad located on an upper portion of the second core layer; a second lower pad located on a lower portion of the second core layer; a lower wiring extending on the lower portion of the second core layer; and a lower insulator layer forming a lower surface of the second package substrate while at least partially exposing the lower wiring to provide exposed lower wiring. The heat dissipation material layer includes a polymer matrix and insulating inorganic particles dispersed in the polymer matrix. The thermal conductivity of the insulating inorganic particles is 10 times or greater than that of the lower insulator layer, and the heat dissipation material layer is in physical contact with the exposed lower wiring of the second packaging substrate and with an upper surface of the first semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Embodiments of the inventive concept will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a side view of a semiconductor package according to an embodiment of the inventive concept;

[0012] Figure 2 is a top view of a wiring pattern exposed through a second lower insulator layer according to an embodiment of the inventive concept;

[0013] Figures 3A to 3C is a partial top view of a wiring pattern according to another embodiment of the inventive concept;

[0014] Figures 4 to 7 is a side view of a semiconductor package according to other embodiments of the inventive concept;

[0015] Figure 8 is a side view of a package-on-package (PoP) type package according to an embodiment of the inventive concept;

[0016] Figure 9 is a side view of a PoP type package when the second semiconductor device is a single package according to an embodiment of the inventive concept;

[0017] Figure 10 is a block diagram of an electronic system according to an embodiment of the inventive concept; and

[0018] Figure 11 is a side view of a portion of an electronic system according to an embodiment of the inventive concept. DETAILED DESCRIPTION

[0019] Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. In the accompanying drawings, like reference numerals denote like elements, and thus repeated description thereof will be omitted.

[0020] Figure 1 is a side view of a semiconductor package 100 according to an embodiment of the inventive concept.

[0021] Reference Figure 1 , the semiconductor package 100 may include a first package substrate 110 , a first semiconductor device 119 mounted on the first package substrate 110 , and a second package substrate 120 .

[0022] The first package substrate 110 includes a first core layer 112, a first upper insulator layer 114b disposed at an upper portion of the first core layer 112, and a first lower insulator layer 114a disposed at a lower portion of the first core layer 112. In addition, the first package substrate 110 may further include a first upper pad 116b exposed through the first upper insulator layer 114b and a first lower pad 116a exposed through the first lower insulator layer 114a.

[0023] The first core layer 112 may include at least one material selected from phenolic resin, epoxy resin, and polyimide. The first core layer 112 may include, for example, at least one material selected from flame retardant 4 (FR4), tetrafunctional epoxy resin, polyphenylene ether, epoxy / polyphenylene ether, bismaleimide triazine (BT), polyamide staple fiber mat (thermount), cyanate ester, polyimide, and liquid crystal polymer.

[0024] The first upper insulator layer 114b is disposed on the upper portion of the first core layer 112, and the first upper pad 116b is exposed through the first upper insulator layer 114b. The first upper insulator layer 114b may include, for example, solder resist. According to some embodiments of the inventive concept, the first upper insulator layer 114b may include epoxy-based resin.

[0025] The first lower insulator layer 114a is disposed at a lower portion of the first core layer 112, and the first lower pad 116a is exposed through the first lower insulator layer 114a. The first lower insulator layer 114a may include, for example, solder resist. According to some embodiments of the inventive concept, the first lower insulator layer 114a may include epoxy-based resin.

[0026] The external connection terminal 108 may be connected to the first lower pad 116a. The first connection terminal 134 that electrically connects the first package substrate 110 to the second package substrate 120 may be connected to the first upper pad 116b. The first lower pad 116a and the first upper pad 116b may each include, for example, aluminum (Al), copper (Cu), nickel (Ni), cobalt (Co), zinc (Zn), gold (Au), silver (Ag), platinum (Pt), or an alloy thereof.

[0027] Each of the external connection terminal 108 and the first connection terminal 134 may include a bump or a solder ball. According to some embodiments of the inventive concept, the first connection terminal 134 may include a conductor post.

[0028] The first package substrate 110 may include a wiring pattern 118 electrically connecting the first lower pad 116a to the first upper pad 116b, and a conductive path 118v electrically connecting between the wiring patterns 118. The wiring pattern 118 may be arranged on the upper surface, the lower surface, and / or inside the first core layer 112. The wiring pattern 118 may include, for example, at least one selected from the group consisting of an electrolytically deposited (ED) Cu foil, a rolled annealed (RA) Cu foil, a stainless steel foil, an Al foil, an ultra-thin Cu foil, sputtered Cu, a Cu alloy, and the like.

[0029] The conductive via 118v may pass through at least a portion of the first core layer 112. According to some embodiments of the inventive concepts, the conductive via 118v may include Cu, Ni, stainless steel, or beryllium Cu.

[0030] The first semiconductor device 119 may be mounted on the first packaging substrate 110. The first semiconductor device 119 may include a processing circuit, for example, a logic chip such as a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, or an application processor (AP) chip. According to some embodiments of the inventive concept, the first semiconductor device 119 may include, for example, a dynamic random access memory (DRAM) chip, a static random access memory (SRAM) chip, a flash memory chip, an electrically erasable programmable read-only memory (EEPROM) chip, a phase change random access memory (PRAM) chip, a magnetic random access memory (MRAM) chip, or a resistive random access memory (RRAM) chip.

[0031] The first semiconductor device 119 may be connected to the first package substrate 110 through the second connection terminals 119c. The second connection terminals 119c may include bumps or solder balls.

[0032] The space between the first semiconductor device 119 and the first package substrate 110 can be filled with an underfill material layer 119u surrounding the second connection terminal 119c. The underfill material layer 119u may include, for example, an epoxy resin formed by a capillary underfill method. According to some embodiments of the inventive concept, the underfill material layer 119u may include a non-conductive film (NCF).

[0033] The second package substrate 120 includes a second core layer 122, a second upper insulator layer 124b disposed at an upper portion of the second core layer 122, and a second lower insulator layer 124a disposed at a lower portion of the second core layer 122. In addition, the second package substrate 120 may further include a second upper pad 126b exposed through the second upper insulator layer 124b and a second lower pad 126a exposed through the second lower insulator layer 124a.

[0034] The second core layer 122 may include at least one material selected from phenolic resin, epoxy resin, and polyimide. The second core layer 122 may include at least one material selected from, for example, FR4, tetrafunctional epoxy resin, polyphenylene ether, epoxy / polyphenylene ether, BT, polyamide staple fiber mat, cyanate ester, polyimide, and liquid crystal polymer.

[0035] The second upper insulator layer 124b is disposed on the upper portion of the second core layer 122, and the second upper pad 126b is exposed through the second upper insulator layer 124b. The second upper insulator layer 124b may include, for example, solder resist. According to some embodiments of the inventive concept, the second upper insulator layer 124b may include epoxy resin.

[0036] The second lower insulator layer 124a is disposed at the lower portion of the second core layer 122, and the second lower pad 126a is exposed through the second lower insulator layer 124a. The second lower insulator layer 124a may include, for example, a solder resist. According to some embodiments of the inventive concept, the second lower insulator layer 124a may include an epoxy resin. This will be described in more detail below.

[0037] The first connection terminal 134 may be connected to the second lower pad 126a. As described below, a connection terminal of another semiconductor device to be arranged above the second upper pad 126b may be connected to the second upper pad 126b. The second lower pad 126a and the second upper pad 126b may each include, for example, Al, Cu, Ni, Co, Zn, Au, Ag, Pt, or an alloy thereof.

[0038] The first connection terminals 134 may include bumps or solder balls. According to some embodiments of the inventive concept, the first connection terminals 134 may include conductor posts.

[0039] The second package substrate 120 may include a wiring pattern 128 electrically connecting the second lower pad 126a to the second upper pad 126b, and a conductive path 128v electrically connecting between the wiring patterns 128. The wiring pattern 128 may be arranged on the upper surface, the lower surface, and / or inside the second core layer 122. The wiring pattern 128 may include at least one selected from, for example, ED Cu foil, RA Cu foil, stainless steel foil, Al foil, ultra-thin Cu foil, sputtered Cu, Cu alloy, and the like.

[0040] The conductive via 128v may pass through at least a portion of the second core layer 122. According to some embodiments of the inventive concepts, the conductive via 128v may include Cu, Ni, stainless steel, or beryllium Cu.

[0041] The second lower insulator layer 124 a exposes the second lower pad 126 a therethrough, and partially exposes the wiring pattern 128 therethrough.

[0042] Figure 2 is a top view of the wiring pattern 128 exposed through the second lower insulator layer 124 a .

[0043] Reference Figure 1 and Figure 2, the wiring pattern 128 can be directly or indirectly connected to the second upper pad 126b and / or the second lower pad 126a. As described above, the wiring pattern 128 can be arranged on the upper surface, lower surface and / or inside the second core layer 122, but although the wiring pattern 128 is shown to be formed in three levels, it will be understood by those skilled in the art that the wiring pattern can be formed in only two levels on the upper and lower surfaces of the second core layer 122, or, for example, in four, five, six, or seven levels.

[0044] exist Figure 1 and Figure 2 In the illustrated embodiment, the upper wiring pattern 128_3 provided as the top level among the wiring patterns 128_1, 128_2, and 128_3 arranged in three levels may extend on the upper surface of the second core layer 122. The central wiring pattern 128_2 provided as the middle level among the wiring patterns 128_1, 128_2, and 128_3 arranged in three levels may extend inside the second core layer 122 in a direction parallel to the xy plane.

[0045] In addition, the lower wiring pattern 128_1, which is set as the bottom level among the wiring patterns 128_1, 128_2, and 128_3 arranged in three levels, can extend on the lower surface of the second core layer 122 and can be located at a level different from that of the second lower pad 126a. That is, the second lower pad 126a is exposed and not covered by the second lower insulator layer 124a, so that the second lower pad 126a can be connected to the first connection terminal 134. The lower surface of the second lower pad 126a (e.g., the surface facing the first connection terminal 134) can be closer to the first packaging substrate 110 than the lower surface of the second lower insulator layer 124a (e.g., the surface facing the first semiconductor device 119).

[0046] The lower surface (e.g., the surface facing the first semiconductor device 119) of the bottom-level lower wiring pattern 128_1 set in the second packaging substrate 120 can be farther away from the first packaging substrate 110 than the upper surface (e.g., the surface facing the second core layer 122) of the second lower insulator layer 124a or basically located in the same plane as the upper surface (e.g., the surface facing the second core layer 122) of the second lower insulator layer 124a.

[0047] According to some embodiments of the inventive concept, at least some of the lower wiring patterns 128_1 may be appropriately distributed and disposed to connect to the second lower pads 126a. According to some embodiments of the inventive concept, at least some of the lower wiring patterns 128_1 may be arranged in a relatively wide planar area in the central portion of the second package substrate 120 for power or ground purposes.

[0048] although Figure 1 The lower wiring pattern 128_1 arranged in the central portion is shown as being fully exposed over the entire planar area by the second lower insulator layer 124a. However, the second lower insulator layer 124a may expose only a portion of the planar area of ​​the lower wiring pattern 128_1. Since the second lower insulator layer 124a can be formed by, for example, screen printing, the second lower insulator layer 124a can be formed in any desired pattern. Similarly, the first lower insulator layer 114a, the first upper insulator layer 114b, and the second upper insulator layer 124b can be formed in the same manner.

[0049] The size of the lower wiring pattern 128_1 extending in a direction parallel to the xy plane exposed by the second lower insulator layer 124a may be larger than the size of the second lower pad 126a in the same direction. According to some embodiments of the inventive concept, the size W1 of the lower wiring pattern 128_1 in the first direction (x-axis direction), for example, may be about 2.5 times to about 100 times, about 3 times to about 95 times, about 4 times to about 90 times, about 5 times to about 85 times, about 6 times to about 80 times, about 7 times to about 75 times, about 8 times to about 70 times, about 9 times to about 65 times, or about 10 times to about 60 times the size W2 of the second lower pad 126a in the first direction.

[0050] When the dimension W1 of the lower wiring pattern 128_1 in the first direction is not sufficiently larger than the dimension W2 of the second lower pad 126a in the first direction, for example, when the difference between them is slight, the contribution of the lower wiring pattern 128_1 to heat release may be insufficient, as described below. Conversely, when the dimension W1 of the lower wiring pattern 128_1 in the first direction is too much larger than the dimension W2 of the second lower pad 126a in the first direction, the total area of ​​the second packaging substrate 120 may be inefficiently used.

[0051] The total planar area of ​​the lower wiring pattern 128_1 at least partially exposed by the second lower insulator layer 124a is much larger than the planar area of ​​the second lower pad 126a. Here, the total planar area of ​​the lower wiring pattern 128_1 refers to the planar area of ​​the lower wiring pattern 128_1 including the portion exposed by the second lower insulator layer 124a and the portion not exposed.

[0052] According to some embodiments of the inventive concept, the planar area of ​​the lower wiring pattern 128_1 projected onto the xy plane may be approximately 5 times to approximately 10,000 times, approximately 10 times to approximately 9,000 times, approximately 20 times to approximately 8,000 times, approximately 30 times to approximately 7,000 times, approximately 40 times to approximately 6,000 times, approximately 60 times to approximately 4,000 times, approximately 100 times to approximately 2,000 times, or approximately 200 times to approximately 1,000 times the planar area of ​​the second lower pad 126 a projected onto the xy plane.

[0053] When the planar area of ​​the lower wiring pattern 128_1 on the xy plane is not sufficiently larger than the planar area of ​​the second lower pad 126a on the xy plane, for example, when the difference between them is slight, the contribution of the lower wiring pattern 128_1 to heat release may be insufficient, as described below. Conversely, when the planar area of ​​the lower wiring pattern 128_1 on the xy plane is much larger than the planar area of ​​the second lower pad 126a on the xy plane, the total area of ​​the second packaging substrate 120 may be inefficiently used.

[0054] Reference Figure 1 The heat dissipation material layer 132 may be located between the first semiconductor device 119 and the second packaging substrate 120 .

[0055] The heat dissipation material layer 132 may include any material having a higher thermal conductivity than the second lower insulator layer 124a, for example, a composition in which insulating inorganic particles are dispersed in a polymer matrix. According to some embodiments of the inventive concept, the inorganic particles may be metal oxides, metalloid oxides, metal nitrides, or metalloid nitrides.

[0056] The thermal conductivity of the heat dissipation material layer 132 may be about 2 times or more, about 5 times or more, about 10 times or more, about 15 times or more, about 20 times or more, or about 30 times or more of the thermal conductivity of the second lower insulator layer 124a. If the thermal conductivity of the heat dissipation material layer 132 is too low, the effect of releasing heat generated from the first semiconductor device 119 may be insufficient. There is no particular upper limit for the thermal conductivity of the heat dissipation material layer 132, but the upper limit of the thermal conductivity of the heat dissipation material layer 132 may be within about 1000 times the thermal conductivity of the second lower insulator layer 124a.

[0057] According to some embodiments of the inventive concept, the thermal conductivity of the heat dissipation material layer 132 may be in a range of about 0.5 W / m·K to about 20 W / m·K, about 1.0 W / m·K to about 18 W / m·K, about 1.5 W / m·K to about 16 W / m·K, about 2.0 W / m·K to about 14 W / m·K, about 2.5 W / m·K to about 12 W / m·K, about 3.0 W / m·K to about 10 W / m·K, or about 3.5 W / m·K to about 8 W / m·K.

[0058] The polymer matrix may include at least one selected from, for example, epoxy, polyimide, polyester, polystyrene, polyethylene terephthalate, high-density polyethylene, low-density polyethylene, polyurethane, polybenzoxazine, polyvinylidene fluoride (PVdF), etc., but is not limited thereto.

[0059] The insulating inorganic particles may include at least one selected from, for example, silicon dioxide, silicon nitride, silicon carbide, aluminum oxide, titanium dioxide, zirconium oxide, ceria, aluminum nitride (AlN), boron nitride (BN), nanodiamond, etc., but are not limited thereto. The insulating inorganic particles may improve the thermal conductivity of the heat dissipation material layer 132 and may be, for example, any inorganic particles having a thermal conductivity of 20 W / m·K or greater and having excellent mixing properties with the polymer matrix.

[0060] The insulating inorganic particles in the heat dissipation material layer 132 may contain about 20% to about 85% by volume. According to some embodiments of the inventive concept, the insulating inorganic particles in the heat dissipation material layer 132 may contain about 25% to about 80% by volume, about 30% to about 75% by volume, about 35% to about 70% by volume, about 40% to about 65% by volume, or about 45% to about 60% by volume.

[0061] When the content of the insulating inorganic particles in the heat dissipation material layer 132 is too low, the thermal conductivity may be too low to produce sufficient heat dissipation effect. When the content of the insulating inorganic particles in the heat dissipation material layer 132 is too high, the processability may be poor and the dispersibility of the inorganic particles may be poor, making manufacturing difficult.

[0062] like Figure 1 As shown, heat dissipation material layer 132 contacts the lower surface of lower wiring pattern 128_1 and also contacts the upper surface of first semiconductor device 119. Heat generated from first semiconductor device 119 can be transferred to heat dissipation material layer 132 and then quickly transferred to lower wiring pattern 128_1.

[0063] According to the related art, the presence of second lower insulator layer 124a, located between first semiconductor device 119 and lower wiring pattern 128_1, acts as a bottleneck in the heat transfer path generated by first semiconductor device 119, reducing heat transfer efficiency. In other words, according to the prior art, because lower wiring pattern 128_1 is covered by second lower insulator layer 124a, heat transferred from first semiconductor device 119 must pass through second lower insulator layer 124a to reach lower wiring pattern 128_1. In this case, because second lower insulator layer 124a has an extremely low thermal conductivity of approximately 0.15 W / m·K to approximately 0.25 W / m·K, second lower insulator layer 124a becomes a bottleneck in heat transfer.

[0064] exist Figure 1 In the illustrated embodiment, since the first semiconductor device 119 is directly thermally connected to the lower wiring pattern 128_1 through the heat dissipation material layer 132 having relatively high thermal conductivity, Figure 1 The illustrated embodiment may have better heat dissipation characteristics compared to the related art.

[0065] The heat dissipation material layer 132 may be in contact not only with the lower wiring pattern 128_1 but also with the lower surface of the second lower insulator layer 124a. Furthermore, the heat dissipation material layer 132 may be partially in contact with the second lower pad 126a. In this case, heat generated from the first semiconductor device 119 may be sequentially released through the heat dissipation material layer 132 and the second lower pad 126a and through the lower wiring pattern 128_1 provided at the bottom layer level.

[0066] According to some embodiments of the inventive concepts, the heat dissipation material layer 132 may surround the side surface of the first connection terminal 134 at a first height h. According to some embodiments of the inventive concepts, the side surface of the heat dissipation material layer 132 may be aligned to be substantially coplanar with the side surface of the first packaging substrate 110. According to some embodiments of the inventive concepts, the side surface of the heat dissipation material layer 132 may be aligned to be substantially coplanar with the side surface of the second packaging substrate 120. According to some embodiments of the inventive concepts, the side surface of the heat dissipation material layer 132 may be exposed to the outside of the semiconductor package 100.

[0067] According to some embodiments of the inventive concept, an encapsulation layer 139 may be further provided between the heat dissipation material layer 132 and the first packaging substrate 110. That is, the encapsulation layer 139 may surround the side surfaces of the first connection terminals 134 as to the remaining height of the first connection terminals 134 except the first height h.

[0068] The encapsulation layer 139 may include a polymer material such as epoxy molding compound (EMC), and the encapsulation layer 139 may not include such inorganic particles mixed in the heat dissipation material layer 132 .

[0069] Figure 3A is a partial top view of a wiring pattern 128 a according to another embodiment of the inventive concept. Figure 3A The wiring pattern 128a partially shown in FIG. Figure 2 The central area of ​​the second packaging substrate 120.

[0070] Reference Figure 3A , the wiring pattern 128a may have a grid shape. That is, the wiring pattern 128a may include Figure 3A In addition, the wiring pattern 128a may include a plurality of horizontal extension portions 128he (also referred to as first extension portions) extending in the horizontal direction. Figure 3A The plurality of horizontally extending portions 128he and the plurality of vertically extending portions 128ve (also referred to as second extensions) may intersect with each other to generally form a mesh-like wiring pattern 128a.

[0071] Figure 3A The second lower insulator layer 124a partially shown in FIG. 1 may have an opening 124o to expose the wiring pattern 128a therethrough. The opening 124o may be surrounded by the first portion 124a1 of the second lower insulator layer 124a.

[0072] The wiring pattern 128a may include a plurality of perforated portions 128p passing through the entire thickness of the wiring pattern 128a. The islands of the second lower insulator layer 124a may be arranged on the perforated portions 128p, and the islands may form the second portion 124a2 of the second lower insulator layer 124a.

[0073] That is, the opening 124o may be defined by the first portion 124a1 and the second portion 124a2. It will be understood by those skilled in the art that the entire planar area or only a portion of the planar area of ​​the wiring pattern 128a may be exposed through the opening 124o.

[0074] Figure 3B is a partial top view of a wiring pattern 128 b according to another embodiment of the inventive concept. Figure 3B The wiring pattern 128b partially shown in FIG. Figure 2 The central area of ​​the second packaging substrate 120.

[0075] Reference Figure 3B , the wiring pattern 128b may have a flat plate shape. In this case, the second lower insulator layer 124a' may have a plurality of openings 124o through which the wiring pattern 128b is partially exposed. The plurality of openings 124o may be arranged in a grid shape. Although Figure 3BThe opening 124o is shown to have a circular shape, but one of ordinary skill in the art will appreciate that the opening 124o may be formed in different shapes (eg, polygonal shapes such as triangles, quadrilaterals, or hexagons, ellipses, or other regular or irregular shapes).

[0076] exist Figure 3B In the illustrated embodiment, the wiring pattern 128b may be only partially exposed by the second lower insulator layer 124a'. Therefore, the heat dissipation material layer 132 may only contact the wiring pattern 128b at the portion exposed by the opening 124o. The second lower insulator layer 124a' may also include a first portion 124a1' that does not overlap with the wiring pattern 128b and a second portion 124a2' that overlaps with the wiring pattern 128b.

[0077] Figure 3C FIG is a partial top view of a wiring pattern 128c according to another embodiment of the inventive concept. Figure 3C The wiring pattern 128c partially shown in FIG. Figure 2 The central area of ​​the second packaging substrate 120.

[0078] Reference Figure 3C , the wiring pattern 128c may have a flat plate shape. In this case, the second lower insulator layer 124a" may have a single opening 124o through which the wiring pattern 128b is partially exposed.

[0079] exist Figure 3C In the illustrated embodiment, the wiring pattern 128c may be only partially exposed by the second lower insulator layer 124a". Thus, the heat dissipation material layer 132 may contact the wiring pattern 128c only at the portion exposed by the opening 124o. The second lower insulator layer 124a" may also include a first portion 124a1" that does not overlap with the wiring pattern 128c and a second portion 124a2" that overlaps with the wiring pattern 128.

[0080] Figure 4 is a side view of a semiconductor package 100 a according to another embodiment of the inventive concept.

[0081] Figure 4 The semiconductor package 100a shown is similar to the Figure 1 The semiconductor package 100 described is different in that the side surface of the heat dissipation material layer 132a does not extend to the side surface of the semiconductor package 100a. Therefore, the following mainly describes the difference and does not repeat the above description.

[0082] Reference Figure 4The heat dissipation material layer 132a is not exposed to the outside of the semiconductor package 100a. According to some embodiments of the inventive concept, the side surface of the heat dissipation material layer 132a may be substantially aligned with the side surface of the first semiconductor device 119. The heat dissipation material layer 132a may not contact the first connection terminal 134.

[0083] In this case, the entire side surface of the first connection terminal 134 may be surrounded by the encapsulation layer 139 .

[0084] In addition, in this case, since the heat dissipation material layer 132a does not extend laterally from the side surface of the first semiconductor device 119, the heat dissipation material layer 132a is substantially not in contact with the first connection terminal 134. Therefore, the heat dissipation material layer 132a may include a material having electrical conductivity, such as metal. Figure 1 The heat dissipation material layer 132 may be made of the same material as described above, or may include Cu, Al, Au, Ag, Pt, Fe, Co, Ni, Zn, or alloys thereof. However, the heat dissipation material layer 132a according to the present embodiment is not limited thereto. In this case, the thermal conductivity of the heat dissipation material layer 132a may be approximately 70 W / m·K to approximately 450 W / m·K. For example, the thermal conductivity of the heat dissipation material layer 132a may be approximately 200 W / m·K to approximately 440 W / m·K or approximately 300 W / m·K to approximately 430 W / m·K.

[0085] Figure 5 is a side view of a semiconductor package 100 b according to another embodiment of the inventive concept.

[0086] Figure 5 The semiconductor package 100b shown is similar to the Figure 1 The difference between the semiconductor package 100 described above and the semiconductor package 100 is that the side surface of the heat dissipation material layer 132b extends laterally beyond the side surface of the first semiconductor device 119, but does not extend to the side surface of the semiconductor package 100b. Therefore, the following mainly describes the difference, and the above description is not repeated.

[0087] Reference Figure 5 , the heat dissipation material layer 132b is not exposed outside the semiconductor package 100b. According to some embodiments of the inventive concept, the side surface of the heat dissipation material layer 132b may not be aligned with the side surface of the first semiconductor device 119 and may extend laterally beyond the side surface of the first semiconductor device 119.

[0088] The heat dissipation material layer 132b may partially contact the first connection terminals 134. According to some embodiments of the inventive concept, the heat dissipation material layer 132b may contact some of the plurality of first connection terminals 134 and may not contact other first connection terminals 134.

[0089] When the heat dissipation material layer 132 b contacts some of the first connection terminals 134 , the heat dissipation material layer 132 b may surround the side surfaces of the some of the first connection terminals 134 at a first height h. As for the remaining heights of the some of the first connection terminals 134 except the first height h, the encapsulation layer 139 may surround the side surfaces of the some of the first connection terminals 134.

[0090] The entire side surfaces of the other first connection terminals 134 that are not in contact with the heat dissipation material layer 132 b may be surrounded by the encapsulation layer 139 .

[0091] Figure 6 is a side view of a semiconductor package 100 c according to another embodiment of the inventive concept.

[0092] Figure 6 The semiconductor package 100c shown is similar to the Figure 1 The semiconductor package 100 described is different in that the heat dissipation material layer 132c at least partially contacts the side surface of the first semiconductor device 119. Therefore, hereinafter, the difference is mainly described, and the above description is not repeated.

[0093] Reference Figure 6 , the heat dissipation material layer 132c can be compared with the reference Figure 1 The heat dissipation material layer 132 in the described embodiment is thick. Therefore, the heat dissipation material layer 132c can surround the side surface of the first connection terminal 134 with a second height h' greater than the first height h. As for the remaining height of the first connection terminal 134 except the second height h', the encapsulation layer 139 can surround the side surface of the first connection terminal 134.

[0094] The heat dissipation material layer 132c may at least partially contact the side surface of the first semiconductor device 119. That is, the contact area between the heat dissipation material layer 132c and the first semiconductor device 119 may be larger than that of the reference semiconductor device 119. Figure 1 Therefore, heat generated from the first semiconductor device 119 can be removed more quickly.

[0095] Figure 7 is a side view of a semiconductor package 100 d according to another embodiment of the inventive concept.

[0096] Figure 7 The semiconductor package 100d shown is similar to the Figure 1The semiconductor package 100 described is different in that the heat dissipation material layer 132d also serves as an encapsulation layer. Therefore, in the following, the difference is mainly described, and the above description is not repeated.

[0097] Reference Figure 7 , the heat dissipation material layer 132d may be filled in the space between the first package substrate 110 and the second package substrate 120. That is, since the heat dissipation material layer 132d also serves as an encapsulation layer, reference is omitted. Figure 1 Encapsulation layer 139 in the depicted embodiment.

[0098] Thus, the heat dissipation material layer 132d may surround the side surface of the first connection terminal 134 over the entire height of the first connection terminal 134. In addition, the heat dissipation material layer 132d may contact at least a portion of the upper surface of the first packaging substrate 110. According to some embodiments of the inventive concept, the heat dissipation material layer 132d may contact the entire exposed upper surface of the first packaging substrate 110.

[0099] In addition, the contact area between the heat dissipation material layer 132d and the first semiconductor device 119 may be larger than that of the reference Figure 6 Therefore, heat generated from the first semiconductor device 119 can be removed more quickly.

[0100] Figure 8 is a side view of a package-on-package (PoP) type package 200 according to an embodiment of the inventive concept.

[0101] Reference Figure 8 , the PoP type package 200 may include a first package 101 and a second package 150 disposed on the first package 101 .

[0102] The first package 101 may include a first package substrate 110 and a first semiconductor device 119 mounted on the first package substrate 110 . The second package 150 may include a second package substrate 120 and a second semiconductor device 129 mounted on the second package substrate 120 .

[0103] Already referenced Figure 1 The first packaging substrate 110 , the second packaging substrate 120 , and the first semiconductor device 119 are described in detail, and thus additional description thereof is omitted here.

[0104] The second semiconductor device 129 may include a processing circuit, for example, a logic chip such as a CPU chip, a GPU chip, or an AP chip. According to some embodiments of the inventive concept, the second semiconductor device 129 may include, for example, a DRAM chip, an SRAM chip, a flash memory chip, an EEPROM chip, a PRAM chip, an MRAM chip, or an RRAM chip.

[0105] The second semiconductor device 129 may be a single chip or a single package.

[0106] When the second semiconductor device 129 is a single chip, a semiconductor element (eg, chip) may be formed on an active surface of a semiconductor substrate. Figure 8 In the example shown, the lower surface of the second semiconductor device 129 can be an active surface. The semiconductor substrate can be a silicon (Si) substrate. According to another embodiment of the inventive concept, the semiconductor substrate can include a semiconductor element such as germanium (Ge), or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP).

[0107] When the second semiconductor device 129 is a single package, the second semiconductor device 129 may include a separate package substrate, and the semiconductor chip may be mounted on the package substrate. In this case, the second package substrate 120 may be referred to as an interposer. In addition, the PoP in which the second semiconductor device 129 is a package may be referred to as an interposer PoP or simply i-PoP. Figure 9 This is described in more detail. The second semiconductor device 129 may be connected to the second package substrate 120 through the third connection terminal 129c. The third connection terminal 129c may include a bump or a solder ball.

[0108] When the semiconductor package according to the inventive concept is used, a PoP type package capable of smoothly releasing heat generated from a semiconductor device may be manufactured.

[0109] Figure 9 is a side view of a PoP type package 200 a when the second semiconductor device 129 is a single package.

[0110] Reference Figure 9 , the second semiconductor device 129 may include a plurality of semiconductor chips 320 sequentially stacked on a third packaging substrate 310. A memory control chip 330 may be connected to the plurality of semiconductor chips 320. The stacked structure of the plurality of semiconductor chips 320 and the memory control chip 330 may be sealed on the third packaging substrate 310 by an encapsulant 340 such as a thermosetting resin. Although Figure 9 A structure in which six semiconductor chips 320 are stacked vertically is shown, but the number of semiconductor chips 320 and their stacking direction are not limited thereto. Depending on the circumstances, the number of semiconductor chips 320 may be greater than or less than six. The plurality of semiconductor chips 320 may be arranged horizontally on the third packaging substrate 310, or may be arranged in a connection structure that is a mixture of vertical and horizontal mounting. According to some embodiments of the inventive concept, the memory control chip 330 may be omitted.

[0111] The third package substrate 310 may include a flexible printed circuit board, a rigid printed circuit board, or a combination thereof. The third package substrate 310 may include substrate internal wiring 312 and a connection terminal 314. The connection terminal 314 may be formed on one surface of the third package substrate 310. The third connection terminal 129c may be formed on another surface of the third package substrate 310. The connection terminal 314 may be electrically connected to the third connection terminal 129c via the substrate internal wiring 312.

[0112] According to some embodiments of the inventive concept, the second semiconductor device 129 may include via structure units 322 and 332. The via structure units 322 and 332 may be electrically connected to the connection terminal 314 of the third package substrate 310 through a connection member 350 such as a bump. According to some embodiments of the inventive concept, the via structure unit 332 may be omitted from the memory control chip 330.

[0113] Each of the plurality of semiconductor chips 320 may include a system large-scale integration (LSI) chip, flash memory, DRAM, SRAM, EEPROM, PRAM, MRAM, or RRAM. The memory control chip 330 may include a logic circuit including, for example, a serializer / deserializer (SER / DES) circuit.

[0114] Figure 10 is a block diagram of an electronic system 1900 according to an embodiment of the inventive concept.

[0115] The electronic system 1900 may include a memory 1910 and a memory controller 1920. The memory controller 1920 controls the memory 1910 to read data from the memory 1910 and / or write data to the memory 1910 in response to a request from a host 1930. According to some embodiments of the inventive concept, the memory controller 1920 may be a reference Figure 8 The first package 101 described, and the memory 1910 may be referred to Figure 8 The second package 150 is described.

[0116] Figure 11 is a side view of a portion of electronic system 1900 .

[0117] Reference Figure 10 and Figure 11 , the electronic system 1900 may include a mainboard 170 of a host 1930 and a PoP type package 200 mounted on the mainboard 170. Figure 8 The PoP type package 200 is described, and therefore, the above description will not be repeated here.

[0118] Mainboard 170 may include a mainboard core layer 172 and a mainboard insulator layer 174 covering the upper surface of mainboard core layer 172. Mainboard core layer 172 may include at least one material selected from phenolic resin, epoxy resin, and polyimide. Mainboard core layer 172 may include, for example, at least one material selected from FR4, tetrafunctional epoxy resin, polyphenylene ether, epoxy / polyphenylene ether, BT, polyamide staple fiber mat, cyanate ester, polyimide, and liquid crystal polymer.

[0119] The main board insulator layer 174 may include, for example, a solder resist. According to some embodiments of the inventive concept, the main board insulator layer 174 may include an epoxy-based resin.

[0120] According to some embodiments of the inventive concept, the first package 101 and the second package substrate 120 in the PoP type package 200 on the main board 170 may be encapsulated by the encapsulation layer 1939. According to some embodiments of the inventive concept, the encapsulation layer 1939 may be formed to expose the upper surface of the second semiconductor device 129 therethrough.

[0121] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor package, comprising: a first packaging substrate; a first semiconductor device, wherein the first semiconductor device is located on the first packaging substrate; a second packaging substrate, the second packaging substrate being located on an upper portion of the first semiconductor device, the second packaging substrate comprising a conductor vertically overlapping the first semiconductor device; and a heat dissipation material layer located between the first semiconductor device and the second packaging substrate, the heat dissipation material layer having a thermal conductivity of 0.5 W / m·K to 20 W / m·K, and the heat dissipation material layer being in direct contact with the upper surface of the first semiconductor device and the entire lower surface of the conductor of the second packaging substrate.

2. The semiconductor package according to claim 1, wherein The second packaging substrate includes: a lower pad connected to the first semiconductor device via a connection terminal, the lower pad being located on a first surface of the second packaging substrate facing the first semiconductor device; a lower wiring located on the first surface of the second packaging substrate, the lower wiring not being connected to the first semiconductor device through the connection terminal; and A lower insulator layer is located on the first surface of the second package substrate, and the lower insulator layer exposes the lower pad and the lower wiring.

3. The semiconductor package according to claim 2, wherein The conductor of the second package substrate is the lower wiring of the second package substrate.

4. The semiconductor package according to claim 3, wherein The exposed portion of the lower wiring is exposed through the opening in the lower insulator layer, and The heat dissipation material layer contacts the lower wiring over an entire area of ​​the exposed portion of the lower wiring.

5. The semiconductor package according to claim 4, wherein The lower insulator layer includes a plurality of openings exposing lower surfaces of the lower wirings, and The heat dissipation material layer contacts the lower wirings through the plurality of openings.

6. The semiconductor package according to claim 4, wherein The lower insulator layer comprises: a first portion surrounding a periphery of the opening; and a second portion in the form of an island surrounded by and spaced apart from the first portion; and The opening is defined by the first portion and the second portion.

7. The semiconductor package according to claim 2, wherein A size of the lower wiring in a direction parallel to a lower surface of the second package substrate is 2.5 to 100 times a size of the lower pad.

8. The semiconductor package according to claim 2, wherein A planar area of ​​the lower wiring protruding onto the lower surface of the second package substrate is 5 to 10,000 times larger than a planar area of ​​the lower pad.

9. The semiconductor package according to claim 8, wherein The lower wiring includes a through-hole portion passing through the lower wiring.

10. The semiconductor package according to claim 1, wherein The heat dissipation material layer includes a polymer matrix and insulating inorganic particles dispersed in the polymer matrix, and The inorganic particles include at least one of metal oxides, metalloid oxides, metal nitrides, and metalloid nitrides.

11. The semiconductor package according to claim 1, wherein The heat dissipation material layer contacts a side surface of the first semiconductor device.

12. The semiconductor package according to claim 11, wherein The heat dissipation material layer contacts at least a portion of the upper surface of the first packaging substrate.

13. A package-on-package type package, comprising: a first package comprising a first semiconductor device on a first package substrate; a second package, the second package being located on an upper portion of the first package, The second package includes a second semiconductor device located on a second package substrate, The second packaging substrate includes a core layer, an upper wiring extending on an upper surface of the core layer, a lower wiring extending on a lower surface of the core layer and vertically overlapping the first semiconductor device, an upper insulator layer covering the upper surface of the core layer and at least a portion of the upper wiring, and a lower insulator layer covering the lower surface of the core layer, the lower insulator layer exposing the lower wiring to provide exposed lower wiring; and A heat dissipation material layer is in physical contact with the entire lower surface of the exposed lower wiring through the lower insulator layer and in physical contact with the upper surface of the first semiconductor device.

14. The package-on-package type package according to claim 13, further comprising: a connecting terminal connecting the first packaging substrate to the second packaging substrate in a lateral direction of the first semiconductor device, The second package substrate further includes a lower terminal in contact with the connection terminal at the lower portion of the core layer, and The first package substrate includes an upper terminal in contact with the connection terminal.

15. The package-on-package type package according to claim 14, wherein The heat dissipation material layer surrounds side surfaces of the connection terminal.

16. The package-on-package type package according to claim 15, wherein A side surface of the heat dissipation material layer is coplanar with a side surface of the first packaging substrate.

17. The package-on-package type package according to claim 16, wherein The heat dissipation material layer further includes insulating inorganic particles, and The thermal conductivity of the inorganic particles is 10 times or greater than that of the lower insulator layer.

18. The package-on-package type package according to claim 14, wherein The heat dissipation material layer surrounds the side surface of the connection terminal at a first height, and A remaining height of the connection terminal except the first height is surrounded by an encapsulation layer.

19. The package-on-package type package according to claim 13, wherein The first semiconductor device is a logic chip, and The second semiconductor device is a memory chip.

20. A package-on-package type package, comprising: The first package, The first package includes a first semiconductor device located on a first package substrate, The first package substrate includes a first core layer, a first upper pad located on an upper portion of the first core layer, and a first lower pad located on a lower portion of the first core layer, and a second package, the second package being located on an upper portion of the first package, the second package comprising a second semiconductor device located on a second package substrate, the second packaging substrate including a second core layer, a second upper pad located on an upper portion of the second core layer, a second lower pad located on a lower portion of the second core layer, a lower wiring extending on the lower portion of the second core layer and vertically overlapping the first semiconductor device, and a lower insulator layer forming a lower surface of the second packaging substrate while exposing the lower wiring to provide exposed lower wiring; and a heat dissipation material layer, the heat dissipation material layer being located between the first packaging substrate and the second packaging substrate, The heat dissipation material layer includes insulating inorganic particles dispersed in a polymer matrix, The thermal conductivity of the insulating inorganic particles is 10 times or greater than that of the lower insulator layer, and The heat dissipation material layer is in physical contact with the entire lower surface of the exposed lower wiring of the second packaging substrate and is in physical contact with an upper surface of the first semiconductor device.

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