A method and circuit for accelerating the operation of a high-flexibility and low-bandwidth SSD master control chip

Abstract

The present invention discloses a method and circuit for accelerating the operation of a high-flexibility and low-bandwidth SSD main control chip, including: an interconnect array, an operation array and a memory; the operation array includes a command reading unit, a write-back control unit and a plurality of operation modules; each operation module includes an input queue processing unit, a logic operation unit and an output queue processing unit; the above scheme connects all the logic operation units through the interconnect array, and each operation module automatically sends the operation result to the next operation module through the interconnect array after completing its corresponding logic operation, and after all operations are completed, the final operation result is stored in the memory through the write control unit, and read back through the command reading unit. When different logic operations need to be performed, it is only necessary to edit the command data packet of the corresponding level and input it into the acceleration circuit of the present invention, thereby greatly improving the efficiency and flexibility of the logic operation.

Description

Technical Field

[0001] The present invention relates to the field of chip circuit design, and in particular to a calculation acceleration method and circuit for a high-flexibility and low-bandwidth SSD main control chip. Background Art

[0002] SSD data storage has gradually become the main storage medium for consumer device data storage and cloud storage. For SSD data storage, data error correction is of great significance, especially for personal key data and data related to government agencies. The SSD main control chip is the brain of the SSD storage device. Its error correction performance and encryption and decryption performance directly determine the durability of the SSD hard drive.

[0003] At present, the error correction function and encryption and decryption function of the SSD main control chip are all realized by a fixed acceleration circuit that implements a specific error correction algorithm or encryption and decryption algorithm. This circuit can only realize a relatively fixed logical operation process. Once the SSD hard disk is produced, it is impossible to upgrade the error correction performance and perform more complex logical operations. In the face of the ever-changing technological development environment, this SSD solid state hard disk that only performs fixed logical operations is very easy to be eliminated. Summary of the invention

[0004] Therefore, it is necessary to provide a technical solution for a computing acceleration circuit of a SSD master control chip with high flexibility and low bandwidth, so as to solve the problems of fixed computing power and poor flexibility of the SSD master control chip in the prior art.

[0005] To achieve the above-mentioned object, the first aspect of the present invention provides a method for accelerating the operation of a high-flexibility and low-bandwidth SSD master control chip, the method being applied to an operation acceleration circuit of a high-flexibility and low-bandwidth SSD master control chip, the operation acceleration circuit comprising an interconnect array and an operation array; the operation array comprising a command reading unit and a plurality of operation modules; each operation module comprising an input queue processing unit, a logic operation unit and an output queue processing unit;

[0006] The method comprises the following steps:

[0007] The command reading unit reads a first command data packet, and broadcasts the first command data packet to the input queue processing units of all computing modules through the interconnect array; the first command data packet includes first command information and first-level data information, and the first command information includes at least one level identification information;

[0008] Each of the input queue processing units monitors the first command data packet broadcasted in the current interconnect array, and when it is determined that the level identification information to be processed in the first command information is consistent with the identification information of the computing module where the input queue processing unit is located, obtains the first command data packet broadcasted in the current interconnect array;

[0009] The input queue processing unit of the computing module receiving the first command data packet transmits the first-level data information to the logic computing unit in the same computing module for computing to obtain second-level data information; and transmits the second-level data information and the first command information to the output queue processing unit in the same computing module for first processing to obtain a second command data packet, and transmits the second command data packet back to the interconnect array;

[0010] The first processing includes: deleting the level identification information corresponding to the current operation module in the first command information to obtain the second command information, and combining the second command information with the second level data information to obtain the second command data packet.

[0011] Furthermore, the method further comprises:

[0012] Each of the input queue processing units monitors the second command data packet broadcasted in the current interconnect array, and when it is determined that the level identification information to be processed in the second command information is consistent with the identification information of the computing module where the input queue processing unit is located, obtains the second command data packet broadcasted in the current interconnect array;

[0013] The input queue processing unit of the computing module receiving the second command data packet transmits the second-level data information to the logic computing unit in the same computing module for computing to obtain third-level data information; and transmits the third-level data information and the second command information to the output queue processing unit in the same computing module for second processing to obtain a third command data packet, and transmits the third command data packet back to the interconnect array;

[0014] The second processing includes: deleting the level identification information corresponding to the current operation module in the second command information to obtain third command information, and combining the third command information with the third level data information to obtain a third command data packet.

[0015] Furthermore, the operation acceleration circuit also includes a memory and a write-back control unit;

[0016] The method comprises:

[0017] The command reading unit reads a first command data packet from the memory;

[0018] When the output queue processing unit determines that all the level identification information contained in the command information in the received command data packet has been deleted, the level data information obtained by the logic operation performed by the current logic operation unit is transmitted to the write-back control unit as the final operation result;

[0019] The write-back control unit writes the final operation result back to the memory.

[0020] Furthermore, the first command information also includes operation parallelism; the logic operation unit includes a plurality of logic operators;

[0021] The method further comprises:

[0022] The input queue processing unit of the operation module that receives the first command data packet calls a corresponding number of logic operators from the logic operation unit of the current operation module to operate on the first-level data information according to the operation parallelism in the first command information to obtain second-level data information.

[0023] Furthermore, the first command information also includes operation precision; the logic operation unit includes a plurality of logic operators with different precisions;

[0024] The method further comprises:

[0025] The input queue processing unit of the operation module that receives the first command data packet calls the logic operator of the corresponding precision from the logic operation unit of the current operation module to operate on the first-level data information according to the operation precision in the first command information to obtain the second-level data information.

[0026] Furthermore, the first command information also includes a clock beat operation time, and the clock beat operation time includes at least one clock cycle;

[0027] The method comprises:

[0028] The output queue processing unit of the operation module that receives the first command data packet determines the clock cycle required for the current logic operation unit to perform the operation according to the clock beat operation time, and samples the data after the operation by the current logic operation unit after waiting for the corresponding clock cycle, and uses the sampling result as the second-level data information.

[0029] Furthermore, the method comprises:

[0030] When the level identification information corresponds to multiple types of logic operations, the interconnect array sends the command data packet corresponding to the current level identification information to the operation modules where the corresponding multiple logic operation units are located.

[0031] The second aspect of the present invention further provides a high-flexibility, low-bandwidth SSD master control chip computing acceleration circuit, and the computing acceleration circuit is a high-flexibility, low-bandwidth SSD master control chip computing acceleration circuit as described in any one of the first aspect of the present invention.

[0032] Furthermore, the logic operation unit includes any one of a multiplication operation array, an addition operation array, and a subtraction operation array; the logic operator includes any one of a multiplication operator, an addition operator, and a subtraction operator.

[0033] Further, when the logic operation unit is a multiplication operation array, the multiplication operation array includes any one of an 8-bit precision multiplier array unit, a 16-bit precision multiplier array unit, a 32-bit precision multiplier array unit, and a 64-bit precision multiplier array unit; each multiplier array unit includes a plurality of multipliers of corresponding precision;

[0034] When the logic operation unit is an addition operation array, the addition operation array includes any one of an 8-bit precision adder array unit, a 16-bit precision adder array unit, a 32-bit precision adder array unit, and a 64-bit precision adder array unit; each adder array unit includes a plurality of adders of corresponding precision;

[0035] When the logic operation unit is a subtraction operation array, the subtraction operation array includes any one of an 8-bit precision subtractor array unit, a 16-bit precision subtractor array unit, a 32-bit precision subtractor array unit, and a 64-bit precision subtractor array unit; each subtractor array unit includes multiple subtractors of corresponding precision.

[0036] Different from the prior art, the above scheme connects all logic operation units through an interconnection array, and then reads the command data packet through the command reading unit to automatically form an operation data packet through the data stream. After each operation module completes its corresponding logic operation, it automatically sends the operation result to the next operation module through the interconnection array. After all operations are completed, the final operation result is stored in the memory through the write control unit and read back through the command reading unit. When different logic operations are required, it is only necessary to edit the command data packet of the corresponding level and input it into the acceleration circuit of the present invention, thereby greatly improving the efficiency and flexibility of logic operations. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 It is a flow chart of a method for accelerating the operation of a high-flexibility and low-bandwidth SSD master control chip according to an embodiment of the present invention;

[0038] Figure 2 It is a flow chart of a method for accelerating a calculation of a high-flexibility and low-bandwidth SSD master control chip according to another embodiment of the present invention;

[0039] Figure 3 It is a flow chart of a method for accelerating a calculation of a high-flexibility and low-bandwidth SSD master control chip according to another embodiment of the present invention;

[0040] Figure 4 A schematic diagram of the structure of a computing acceleration circuit of a high-flexibility and low-bandwidth SSD main control chip according to an embodiment of the present invention;

[0041] Description of reference numerals:

[0042] 101. Computation acceleration circuit of SSD main control chip with high flexibility and low bandwidth;

[0043] 20. Interconnect array;

[0044] 30. Operation array;

[0045] 301, command reading unit;

[0046] 302, write-back control unit;

[0047] 303, operation module; 3031, input queue processing unit; 3032, logic operation unit; 3033, output queue processing unit;

[0048] 40. Memory. DETAILED DESCRIPTION

[0049] In order to explain the technical content, structural features, achieved objectives and effects of the technical solution in detail, the following is a detailed description in conjunction with specific embodiments and accompanying drawings.

[0050] See also Figure 1 , is a method for accelerating the operation of a high-flexibility and low-bandwidth SSD master chip. The method is applied to an operation acceleration circuit of a high-flexibility and low-bandwidth SSD master chip, wherein the operation acceleration circuit comprises an interconnect array and an operation array; the operation array comprises a command reading unit and a plurality of operation modules; each operation module comprises an input queue processing unit, a logic operation unit and an output queue processing unit;

[0051] The method comprises the following steps:

[0052] First, in step S101, the command reading unit reads a first command data packet, and broadcasts the first command data packet to the input queue processing units of all operation modules through the interconnect array; the first command data packet includes first command information and first-level data information, and the first command information includes at least one level identification information;

[0053] Then, in step S102, each of the input queue processing units monitors the first command data packet broadcasted in the current interconnect array, and when it is determined that the level identification information to be processed in the first command information is consistent with the identification information of the computing module where the input queue processing unit is located, obtains the first command data packet broadcasted in the current interconnect array;

[0054] Then, in step S103, the input queue processing unit of the computing module receiving the first command data packet transmits the first-level data information to the logic computing unit in the same computing module for computing to obtain second-level data information; and transmits the second-level data information and the first command information to the output queue processing unit in the same computing module for first processing to obtain a second command data packet, and transmits the second command data packet back to the interconnect array;

[0055] The first processing includes: deleting the level identification information corresponding to the current operation module in the first command information to obtain the second command information, and combining the second command information with the second level data information to obtain the second command data packet.

[0056] Preferably, the command data packet is message information. The message header is a command segment storing command information, and the rest of the message is a data segment storing hierarchical data information. The input queue processing unit in each operation module identifies the hierarchical identification information to be processed by monitoring the message header command segment. The hierarchical identification information to be processed refers to the hierarchical identification information corresponding to the ongoing operation. For example, if the operation A1*B1+A2*B2 is currently required, after compilation, a 2-level command data packet can be obtained. The command data packet of the first level is a multiplication operation with an ID of 1 and a parallelism of 2, and the command data packet of the second level is an addition operation with an ID of 2 and a parallelism of 1. Then the hierarchical identification information 1 corresponds to a multiplication operation (with a parallelism of 2), and the hierarchical identification information 2 corresponds to an addition operation (with a parallelism of 1).

[0057] like Figure 2 As shown, in some embodiments, the method further includes:

[0058] First, in step S201, each of the input queue processing units monitors the second command data packet broadcast in the current interconnect array, and when it is determined that the level identification information to be processed in the second command information is consistent with the identification information of the computing module where the input queue processing unit is located, obtains the second command data packet broadcast in the current interconnect array;

[0059] Then, in step S202, the input queue processing unit of the computing module receiving the second command data packet transmits the second-level data information to the logic computing unit in the same computing module for computing to obtain third-level data information; and transmits the third-level data information and the second command information to the output queue processing unit in the same computing module for second processing to obtain a third command data packet, and transmits the third command data packet back to the interconnect array;

[0060] The second processing includes: deleting the level identification information corresponding to the current operation module in the second command information to obtain third command information, and combining the third command information with the third level data information to obtain a third command data packet.

[0061] like Figure 3 As shown, the operation acceleration circuit also includes a memory and a write-back control unit; the method includes: the command reading unit reads a first command data packet from the memory. And step S301 when the output queue processing unit determines that the level identification information contained in the command information in the received command data packet has been completely deleted, the level data information obtained by the logic operation of the current logic operation unit is transmitted to the write-back control unit as the final operation result; then enter step S302, the write-back control unit writes the final operation result back to the memory.

[0062] In this way, when performing complex logical operations, data only needs to be read from the memory once, and each operation module in the operation acceleration circuit can automatically complete the operation according to the logical operation level corresponding to each data, and write the final result of the operation back to the memory. Compared with the method in the prior art where each logical operation needs to be continuously read from the storage, the operation efficiency is greatly improved.

[0063] In some embodiments, the first command information also includes operation parallelism; the logic operation unit includes multiple logic operators; the method also includes: the input queue processing unit of the operation module that receives the first command data packet calls a corresponding number of logic operators from the logic operation unit of the current operation module to operate the first-level data information according to the operation parallelism in the first command information to obtain the second-level data information. For example, for the operation A1*B1+A2*B2, the command data packet of the first level is a multiplication operation with an ID of 1 and a parallelism of 2. In the first-level operation, the input queue processing unit will call 2 multipliers from the multiplication operation array for operation, one of which has inputs of A1 and B1, and the other has inputs of A2 and B2.

[0064] In some embodiments, the first command information also includes operation precision; the logic operation unit includes multiple logic operators with different precisions; the method also includes: the input queue processing unit of the operation module that receives the first command data packet calls the logic operator of the corresponding precision from the logic operation unit of the current operation module to operate on the first-level data information according to the operation precision in the first command information to obtain the second-level data information. Preferably, the operation precision includes 8bit, 16bit or 32bit. The operation module can identify the command information in the command data packet to learn the data precision that needs to be output at present, and then call the logic operation unit of the corresponding precision to perform the operation, so as to meet the needs of different operation scenarios.

[0065] In some embodiments, the first command information also includes a clock beat operation time, and the clock beat operation time includes at least one clock cycle; the method includes: the output queue processing unit of the operation module that receives the first command data packet determines the clock cycle required for the current logic operation unit to perform the operation according to the clock beat operation time, and samples the data after the operation of the current logic operation unit after waiting for the corresponding clock cycle, and uses the sampling result as the second-level data information. Preferably, the clock beat operation time is the longest clock cycle required for all logic operation units that are performing the current level operation to complete their corresponding operations.

[0066] In some embodiments, the method includes: when the level identification information corresponds to multiple types of logic operations, the interconnect array sends the command data packet corresponding to the current level identification information to the operation modules where the corresponding multiple logic operation units are located.

[0067] For example, the first-level operation is an addition operation with ID 2, a parallelism of 6 (six addition circuits in the addition array work in parallel), and a multi-beat operation time of 1 clock cycle. The second-level operation is an addition operation with ID 1, a multiplication operation with ID 2, and a subtraction operation with ID 3. The parallelisms are 5, 4, and 6 respectively, and the multi-beat operation time is 2 clock cycles (determined by the time of the longest operation module, assuming that the multiplication circuit requires 2 clock cycles for multiplication. Since the time required for the multiplication operation module is usually higher than that of the addition or subtraction operation among the three operations, the multi-beat operation time of the second-level operation can be defined as 2 clock cycles). Then, three results are output after the operation is completed. The three results correspond to the operations of addition first and then addition, addition first and then multiplication, and addition first and then subtraction.

[0068] The second aspect of the present invention also provides a high-flexibility and low-bandwidth SSD main control chip computing acceleration circuit, see Figure 4, is a schematic diagram of the structure of a high-flexibility, low-bandwidth SSD master control chip computing acceleration circuit according to an embodiment of the present invention. The computing acceleration circuit includes: an interconnect array 20, a computing array 30, and a memory 40;

[0069] The operation array 30 includes a command reading unit 301, a write-back control unit 302 and a plurality of operation modules 303; each operation module 303 includes an input queue processing unit 3031, a logic operation unit 3032 and an output queue processing unit 3033;

[0070] The input queue processing unit 3031 is connected to the logic operation unit 3032, and the logic operation unit 3032 is connected to the output queue processing unit 3033; the input queue processing unit 3031 in each operation module 303 is connected to the interconnect array 20 and the command reading unit 301, and the output queue processing unit 3033 in each operation module 303 is connected to the interconnect array 20 and the write-back control unit 302; the write-back control unit 302 is connected to the memory 40, and the memory 40 is connected to the command reading unit 301.

[0071] The above scheme connects all logic operation units through an interconnection array, and then reads the command data packet through the command reading unit to automatically form a calculation data packet through the data stream. After each calculation module completes its corresponding logic operation, it automatically sends the calculation result to the next calculation module through the interconnection array. After all operations are completed, the final calculation result is stored in the memory through the write control unit and read back through the command reading unit. When different logic operations are required, it is only necessary to edit the command data packet of the corresponding level and input it into the acceleration circuit of the present invention, thereby greatly improving the efficiency and flexibility of logic operations.

[0072] Compared with the method that each logical operation needs to read data from the memory and write back data, the acceleration circuit involved in the present invention only needs to read data from the memory once, and the final operation result can be obtained through the operation of each module in the acceleration circuit, and the final operation result obtained is written back to the memory, thereby greatly saving the storage bandwidth. At the same time, the data read in once can be broadcasted to multiple operation modules through the interconnection array for use, which can greatly improve the data use efficiency in operations with more data reuse.

[0073] In some embodiments, the command reading unit is a NAND read / write controller, the interconnect array is a configurable connection bus, the write-back control unit is a CPU, the input queue processing unit is an MCU processor, and the output queue processing unit is an MCU processor.

[0074] The logic operation unit includes any one of a multiplication operation array, an addition operation array, and a subtraction operation array. Preferably, when the logic operation unit is a multiplication operation array, the multiplication operation array includes any one of an 8-bit precision multiplier array unit, a 16-bit precision multiplier array unit, a 32-bit precision multiplier array unit, and a 64-bit precision multiplier array unit; when the logic operation unit is an addition operation array, the addition operation array includes any one of an 8-bit precision adder array unit, a 16-bit precision adder array unit, a 32-bit precision adder array unit, and a 64-bit precision adder array unit; when the logic operation unit is a subtraction operation array, the subtraction operation array includes any one of an 8-bit precision subtractor array unit, a 16-bit precision subtractor array unit, a 32-bit precision subtractor array unit, and a 64-bit precision subtractor array unit.

[0075] In some embodiments, the command reading unit is used to read command information, and the command information includes operation data and operation level; the operation level is determined according to the order of each logical operation in the current formula. The data input to the acceleration circuit of the present invention each time can be obtained in the following way: after the new algorithm is designed, the design is completed in C language, and then the operation in C language is compiled into the basic logical operation of assembly language by the compiler, and then the basic logical operation in the assembly is mapped to the operation of the operation acceleration unit supported in the circuit through the operation driver mapping tool, and the order of operation, parallelism, multi-cycle waiting time, etc. are marked to obtain command information (i.e., command data packet). The content of the command data packet includes the order and identification information of various logical operations.

[0076] For example, if the operation A1*B1+A2*B2 needs to be performed, after compilation, a 2-level command data packet can be obtained. The first-level command data packet is a multiplication operation with an ID of 1 and a parallelism of 2, and the second-level command data packet is an addition operation with an ID of 2 and a parallelism of 1. The input data of the original command data packet is A1, B1, A2, B2. When using the acceleration circuit of the present application for calculation, the command data packet with an ID of 1 is first sent to the input queue processing unit 1, and then two multiplication units are called to perform multiplication operations with a parallelism of 2, and the results of A1*B1 and A2*B2 are calculated, and the two result values ​​are used as the input of the second-level command data packet, and the second-level command data packet re-enters the interconnect array. When the logic operation unit is an addition operation module that detects that the header ID of the current command data packet is the same as its own, it will obtain a secondary command data packet from the interconnect array, and transmit the command data packet with ID 2 to the input queue processing unit 2, and then call an addition operation unit to perform an operation with a parallel degree of 1 to calculate the result of A1*B1+A2*B2. At this time, the output queue processing unit 2 determines that the level in the command information has been completely deleted, which means that the current output is the final result of this operation, and therefore the final result of this operation will be written back to the memory.

[0077] After the operation acceleration circuit of the present application starts working, the operation array first reads the source data packet with command information from the memory, and then broadcasts the source data packet to the input queue processing units of all operation modules through the interconnection array. Then, the input queue processing unit of each operation module retrieves whether it is the target operation unit that needs to perform the current operation according to the command information in the broadcasted data packet (there will be ID information in the command packet header to determine whether the ID information in the currently monitored data packet is consistent with the ID information of its own operation module). If not, no response will be given. If yes, the data of the data packet will be sent to the subsequent operation unit for calculation. Then, the operation module decides to call several operators (such as multipliers, adders or subtractors) in the logic operation unit according to the parallelism in the command information to complete the calculation in parallel, and sends the calculated data to the corresponding output queue processing unit.

[0078] Then, the output queue processing unit samples the output result of the operation module after waiting for the corresponding number of clock cycles according to the multi-beat operation time in the command information, and then uses the calculation result data as the data segment content in the new data packet, and at the same time, the remaining command information after deleting the information of the current level in the command information is merged with the current operation result data as a new data packet and sent to the interconnect array, and this cycle is repeated until all the levels of the command information are deleted. If all the levels in the command information have been deleted, it means that the current operation array has completed all logical operations, and the output queue processing unit of the last operation module will send the current operation result data to the write-back control unit, and the final operation result will be written back to the memory through the write-back control unit.

[0079] The present invention discloses a method and circuit for accelerating the operation of a high-flexibility and low-bandwidth SSD main control chip, including: an interconnect array, an operation array and a memory; the operation array includes a command reading unit, a write-back control unit and a plurality of operation modules; each operation module includes an input queue processing unit, a logic operation unit and an output queue processing unit; the above scheme connects all the logic operation units through the interconnect array, and each operation module automatically sends the operation result to the next operation module through the interconnect array after completing its corresponding logic operation, and after all operations are completed, the final operation result is stored in the memory through the write control unit, and read back through the command reading unit. When different logic operations need to be performed, it is only necessary to edit the command data packet of the corresponding level and input it into the acceleration circuit of the present invention, thereby greatly improving the efficiency and flexibility of the logic operation.

[0080] It should be noted that, although the above embodiments have been described in this article, the patent protection scope of the present invention is not limited thereby. Therefore, based on the innovative concept of the present invention, changes and modifications made to the embodiments described herein, or equivalent structures or equivalent process changes made using the contents of the present invention specification and drawings, directly or indirectly applying the above technical solutions to other related technical fields, are all included in the patent protection scope of the present invention.

Claims

1. A method for accelerating the operation of a high-flexibility and low-bandwidth SSD master control chip, characterized in that: The method is applied to a computing acceleration circuit of a high-flexibility and low-bandwidth SSD master control chip, wherein the computing acceleration circuit comprises an interconnect array and a computing array; the computing array comprises a command reading unit and a plurality of computing modules; each computing module comprises an input queue processing unit, a logic computing unit and an output queue processing unit; The method comprises the following steps: The command reading unit reads a first command data packet, and broadcasts the first command data packet to the input queue processing units of all computing modules through the interconnect array; the first command data packet includes first command information and first-level data information, and the first command information includes at least one level identification information; Each of the input queue processing units monitors the first command data packet broadcasted in the current interconnect array, and when it is determined that the level identification information to be processed in the first command information is consistent with the identification information of the computing module where the input queue processing unit is located, obtains the first command data packet broadcasted in the current interconnect array; The input queue processing unit of the computing module receiving the first command data packet transmits the first-level data information to the logic computing unit in the same computing module for computing to obtain second-level data information; and transmits the second-level data information and the first command information to the output queue processing unit in the same computing module for first processing to obtain a second command data packet, and transmits the second command data packet back to the interconnect array; The first processing includes: deleting the level identification information corresponding to the current operation module in the first command information to obtain the second command information, and combining the second command information with the second level data information to obtain the second command data packet.

2. The method for accelerating the operation of a high-flexibility and low-bandwidth SSD master control chip according to claim 1, characterized in that: The method further comprises: Each of the input queue processing units monitors the second command data packet broadcasted in the current interconnect array, and when it is determined that the level identification information to be processed in the second command information is consistent with the identification information of the computing module where the input queue processing unit is located, obtains the second command data packet broadcasted in the current interconnect array; The input queue processing unit of the computing module receiving the second command data packet transmits the second-level data information to the logic computing unit in the same computing module for computing to obtain third-level data information; and transmits the third-level data information and the second command information to the output queue processing unit in the same computing module for second processing to obtain a third command data packet, and transmits the third command data packet back to the interconnect array; The second processing includes: deleting the level identification information corresponding to the current operation module in the second command information to obtain third command information, and combining the third command information with the third level data information to obtain a third command data packet.

3. The method for accelerating the operation of a high-flexibility and low-bandwidth SSD master control chip according to claim 1 or 2, characterized in that: The operation acceleration circuit also includes a memory and a write-back control unit; The method comprises: The command reading unit reads a first command data packet from the memory; When the output queue processing unit determines that all the level identification information contained in the command information in the received command data packet has been deleted, the level data information obtained by the logic operation performed by the current logic operation unit is transmitted to the write-back control unit as the final operation result; The write-back control unit writes the final operation result back to the memory.

4. The method for accelerating the operation of a high-flexibility and low-bandwidth SSD master control chip according to claim 1, characterized in that: The first command information also includes the degree of parallelism of operation; the logic operation unit includes a plurality of logic operators; The method further comprises: The input queue processing unit of the operation module that receives the first command data packet calls a corresponding number of logic operators from the logic operation unit of the current operation module to operate on the first-level data information according to the operation parallelism in the first command information to obtain second-level data information.

5. The method for accelerating the operation of a high-flexibility and low-bandwidth SSD main control chip according to claim 1, characterized in that: The first command information also includes operation precision; the logic operation unit includes a plurality of logic operators with different precisions; The method further comprises: The input queue processing unit of the operation module that receives the first command data packet calls the logic operator of the corresponding precision from the logic operation unit of the current operation module to operate on the first-level data information according to the operation precision in the first command information to obtain the second-level data information.

6. The method for accelerating the operation of a high-flexibility and low-bandwidth SSD master control chip according to claim 1, characterized in that: The first command information also includes a clock beat operation time, and the clock beat operation time includes at least one clock cycle; The method comprises: The output queue processing unit of the operation module that receives the first command data packet determines the clock cycle required for the current logic operation unit to perform the operation according to the clock beat operation time, and samples the data after the operation by the current logic operation unit after waiting for the corresponding clock cycle, and uses the sampling result as the second-level data information.

7. The method for accelerating the operation of a high-flexibility and low-bandwidth SSD main control chip according to claim 1, characterized in that: The method comprises: When the level identification information corresponds to multiple types of logic operations, the interconnect array sends the command data packet corresponding to the current level identification information to the operation modules where the corresponding multiple logic operation units are located.

8. A high-flexibility and low-bandwidth SSD master control chip computing acceleration circuit, characterized in that: The operation acceleration circuit is an operation acceleration circuit of a high-flexibility and low-bandwidth SSD master control chip as described in any one of claims 1 to 7.

9. The high-flexibility and low-bandwidth SSD main control chip computing acceleration circuit as claimed in claim 8, characterized in that: The logic operation unit includes any one of a multiplication operation array, an addition operation array, and a subtraction operation array.

10. The high-flexibility and low-bandwidth SSD main control chip computing acceleration circuit according to claim 9, characterized in that: When the logic operation unit is a multiplication operation array, the multiplication operation array includes any one of an 8-bit precision multiplier array unit, a 16-bit precision multiplier array unit, a 32-bit precision multiplier array unit, and a 64-bit precision multiplier array unit; each multiplier array unit includes a plurality of multipliers of corresponding precision; When the logic operation unit is an addition operation array, the addition operation array includes any one of an 8-bit precision adder array unit, a 16-bit precision adder array unit, a 32-bit precision adder array unit, and a 64-bit precision adder array unit; each adder array unit includes a plurality of adders of corresponding precision; When the logic operation unit is a subtraction operation array, the subtraction operation array includes any one of an 8-bit precision subtractor array unit, a 16-bit precision subtractor array unit, a 32-bit precision subtractor array unit, and a 64-bit precision subtractor array unit; each subtractor array unit includes multiple subtractors of corresponding precision.

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