Method and storage device for quickly accessing HMB

Abstract

This application discloses a method and storage device for quickly accessing a host memory cache (HMB). The disclosed method for quickly accessing a host memory cache specifically includes the following steps: in response to accessing the host memory cache, obtaining an address in a control unit address space; obtaining an entry number and offset value in a corresponding mapping table based on the address in the control unit address space; obtaining a starting address of a corresponding storage block based on the entry number; and obtaining a host address corresponding to the address in the control unit address space based on the combination of the starting address and the offset value of the storage block, and using the host address to access the host memory cache.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a method for quickly accessing HMB (Host Memory Buffer) in a storage device and a storage device using the method. Background Art

[0002] Figure 1A A block diagram of a solid-state storage device is shown. A solid-state storage device 102 is coupled to a host to provide storage capabilities for the host. The host and solid-state storage device 102 can be coupled in a variety of ways, including but not limited to connecting the host and solid-state storage device 102 via, for example, SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIE (Peripheral Component Interconnect Express, PCIe), NVMe (NVM Express), Ethernet, Fibre Channel, wireless communication networks, and the like. The host can be an information processing device capable of communicating with the storage device in the above manner, such as a personal computer, tablet computer, server, portable computer, network switch, router, cellular phone, personal digital assistant, and the like. The storage device 102 includes an interface 103 , a control component 104 , one or more NVM chips 105 , and a DRAM (Dynamic Random Access Memory) 110 .

[0003] NAND flash memory, phase change memory, FeRAM (Ferroelectric RAM), MRAM (Magnetic Random Access Memory), RRAM (Resistive Random Access Memory), etc. are common NVMs.

[0004] The interface 103 may be adapted to exchange data with the host via, for example, SATA, IDE, USB, PCIE, NVMe, SAS, Ethernet, Fibre Channel, or the like.

[0005] The control component 104 is used to control data transmission between the interface 103, the NVM chip 105 and the DRAM 110, and is also used for storage management, mapping of host logical addresses to flash physical addresses, erase leveling, bad block management, etc. The control component 104 can be implemented in a variety of ways such as software, hardware, firmware or a combination thereof. For example, the control component 104 can be in the form of an FPGA (Field-programmable gate array), an ASIC (Application Specific Integrated Circuit) or a combination thereof. The control component 104 can also include a processor or a controller, in which software is executed to manipulate the hardware of the control component 104 to process IO (Input / Output) commands. The control component 104 can also be coupled to the DRAM 110 and can access data in the DRAM 110. The FTL table and / or cached IO command data can be stored in the DRAM.

[0006] The control unit 104 includes a flash memory interface controller (also known as a media interface controller or a flash memory lane controller). The flash memory interface controller is coupled to the NVM chip 105 and issues commands to the NVM chip 105 in accordance with the interface protocol of the NVM chip 105 to operate the NVM chip 105, and receives command execution results output from the NVM chip 105. Known NVM chip interface protocols include "Toggle" and "ONFI".

[0007] A memory target is one or more logic units (LUNs) within a NAND flash memory package that share a chip enable (CE) signal. A NAND flash memory package may include one or more dies. Typically, a logic unit corresponds to a single die. A logic unit may include multiple planes. Multiple planes within a logic unit can be accessed in parallel, and multiple logic units within a NAND flash memory chip can execute commands and report status independently of each other.

[0008] Data on storage media is typically stored and read in pages. Data is erased in blocks. A block (also called a physical block) contains multiple pages. Pages on storage media (called physical pages) have a fixed size, for example, 17,664 bytes. Physical pages can also have other sizes.

[0009] In storage devices, the Flash Translation Layer (FTL) maintains mapping information from logical addresses to physical addresses. Logical addresses constitute the storage space of solid-state storage devices as perceived by upper-layer software such as the operating system. Physical addresses are used to access the physical storage units of solid-state storage devices. In related technologies, address mapping can also be implemented using intermediate address formats. For example, logical addresses can be mapped to intermediate addresses, which can then be further mapped to physical addresses.

[0010] The table structure that stores the mapping information from logical addresses to physical addresses is called an FTL table. The FTL table is important metadata in storage devices. The data items in the FTL table record the address mapping relationship in the storage device based on data units.

[0011] NVMe protocol version 1.4 provides a solution for storage devices to use the host's memory. The host memory used by the storage device is called the Host Memory Buffer (HMB).

[0012] Figure 1B A schematic diagram of HMB is shown.

[0013] HMB is a storage space that utilizes host memory (e.g., RAM) for use by the storage device. By using HMB, the storage device 102 can omit DRAM 110 to further reduce costs. There are also other ways to use HMB without having to omit DRAM 110.

[0014] According to the NVMe protocol, storage devices can request the use of HMBs from the host. HMBs can be distributed discretely rather than continuously within the host memory. A Host Memory Descriptor List (HMBDL) is used to describe the addresses of one or more storage blocks used by the host to provide HMBs.

[0015] An entry in the host memory descriptor list describes a memory block provided by the host to the HMB, including the starting address and size of the memory block. Therefore, each entry in the host memory descriptor list can describe a different size of memory block. All memory blocks described in the host memory descriptor list together constitute the HMB provided by the host to the storage device.

[0016] Figure 2 Schematic diagram of HMB and HMBDL is shown.

[0017] For example, the host provides a total HMB of 64 KB to the storage device, and the HMB is provided by four storage blocks. Figure 2In the example, block 0 is 16KB, block 1 is 32KB, block 2 is 4KB, and block 3 is 12KB. These four blocks together provide 64KB of storage space. The HMBDL includes four entries (HMBDL Entry 0, HMBDL Entry 1, HMBDL Entry 2, and HMBDL Entry 3), each of which records the starting address and size of one of the corresponding blocks. Thus, through the HMBDL, the storage device learns the HMB provided by the host and is able to use the HMB.

[0018] The control unit of a storage device needs to use the HMB. Typically, the control unit has its own address space and uses memory or other control unit units by accessing this address space. The control unit's address space is different from the host's address space. To use the HMB, the control unit must establish a mapping between its own address space and the host's address space, allowing it to use the HMB in the same way or in a similar manner as it uses its own address space.

[0019] See also Figure 2 , the control unit uses the control unit address space (from control unit address 0 to control unit 64KB-1) to access the HMB, and Figure 2 The corresponding relationship between the control unit address space and the various memory blocks described in HMBDL is also shown. The address range 0 to 16KB-1 of the control unit address space is mapped to memory block 0, the address range 16KB to 48KB-1 of the control unit address space is mapped to memory block 1, the address range 48KB to 52KB-1 of the control unit address space is mapped to memory block 2, and the address range 52KB to 64KB-1 of the control unit address space is mapped to memory block 3. Furthermore, the mapping between the control unit address space and each memory block is linear.

[0020] To access the HMB using the address in the control component address space, the control component needs to traverse the HMBDL to calculate the host address. For example, if the storage device wants to access the address 60KB in the control component address space, it will obtain the host address through the following steps.

[0021] (1) Access the first entry of HMBDL (e.g., Figure 2 The HMBDL entry 0 of the control component is obtained, and the size of the corresponding storage block 0 is 16KB, which is less than 60KB, indicating that the address 60KB of the control component address space to be accessed does not fall within the address range of the storage block 0.

[0022] (2) Access the next entry of HMBDL ( Figure 2HMBDL entry 1), the size of the corresponding storage block 1 is 32KB, the sizes of the storage blocks that have been accessed are accumulated, 16+32=48KB<60KB, indicating that the address 60KB of the control component address space to be accessed does not fall within the address range of storage block 1.

[0023] (3) Access the next entry of HMBDL ( Figure 2 HMBDL entry 2), the size of the corresponding storage block 2 is 4KB, and the size of the storage blocks that have been accessed is accumulated to 52KB (<60KB), indicating that the address 60KB of the control component address space to be accessed does not fall within the address range of storage block 2.

[0024] (4) Access the next entry of HMBDL ( Figure 2 HMBDL entry 3), the size of the corresponding storage block 3 is 12KB, and the size of the storage blocks that have been accessed is accumulated to 64KB (>60KB), indicating that the address 60KB of the control component address space to be accessed falls within the address range of storage block 3.

[0025] (5) The starting address of storage block 3 is obtained from HMBDL entry 3 as the base address. The address of the control component address space to be accessed (60K) is subtracted from the addresses of all storage blocks that have been traversed (16+32+4=52KB) to obtain 8KB as the offset value. The base address plus the offset value is used to obtain the host address for accessing the HMB. Summary of the Invention

[0026] To use the HMB, each HMB access requires traversing one or more entries in the HMBDL and calculating the host address. In the worst case, the entire HMBDL must be traversed to obtain the host address corresponding to the address in the control component address space to be accessed. This reduces access efficiency and leads to inconsistent HMB access latency. HMB access efficiency worsens when the HMB space is large and / or when there are many storage blocks providing the HMB. It is desirable to address the aforementioned issues with HMB access.

[0027] This application proposes a new solution for controlling components to access HMB, which improves the efficiency of accessing HMB and shortens the access time of HMB.

[0028] According to the first aspect of the present application, a first method for quickly accessing a host memory cache according to the first aspect of the present application is provided, which specifically includes the following steps: in response to accessing the host memory cache, obtaining the address of the control component address space; according to the address of the control component address space, obtaining the entry number and offset value of the corresponding mapping table; according to the entry number, obtaining the starting address of the corresponding storage block; according to the combination of the starting address and the offset value of the storage block, obtaining a host address corresponding to the address of the control component address space, and using the address to access the host memory cache.

[0029] According to the first method for quickly accessing the host memory cache of the first aspect of the present application, a second method for quickly accessing the host memory cache of the first aspect of the present application is provided, which further includes establishing a mapping table in the initialization phase, and the mapping table entries record the host address corresponding to the address of the control component address space.

[0030] According to the first or second method for quickly accessing the host memory cache of the first aspect of the present application, a third method for quickly accessing the host memory cache of the first aspect of the present application is provided, wherein the mapping table includes several entries, and the size of the control component address space corresponding to each entry in the mapping table is determined according to the size described by the memory page size.

[0031] According to the third method for quickly accessing the host memory cache of the first aspect of the present application, a fourth method for quickly accessing the host memory cache of the first aspect of the present application is provided, wherein the number of mapping table entries is determined based on the size described by the memory page size and the size of the host memory cache provided by the host.

[0032] According to the method for quickly accessing the host memory cache according to any one of the first to fourth items of the first aspect of the present application, a fifth method for quickly accessing the host memory cache according to the first aspect of the present application is provided, wherein the host memory cache includes multiple storage blocks, and each storage block is split into one or more small storage blocks according to the memory page size, and the size of each small storage block is the memory page size.

[0033] According to the method for quickly accessing the host memory cache according to any one of the third to fifth items of the first aspect of the present application, a sixth method for quickly accessing the host memory cache according to the first aspect of the present application is provided, wherein the number of entries in the mapping table is the same as the number of storage blocks of the divided storage blocks in the host memory cache.

[0034] According to the method for quickly accessing the host memory cache according to any one of the first to sixth items of the first aspect of the present application, a seventh method for quickly accessing the host memory cache according to the first aspect of the present application is provided, wherein each entry in the mapping table indicates the mapping relationship between the address of the control component address space and the storage block, so that each entry records the address of the host address space of the storage block corresponding to the entry.

[0035] According to the method for quickly accessing the host memory cache according to any one of the first to seventh items of the first aspect of the present application, an eighth method for quickly accessing the host memory cache according to the first aspect of the present application is provided, wherein the mapping table is recorded in a memory inside the control component, or in a dynamic random access memory coupled to the control component.

[0036] According to the eighth method for quickly accessing the host memory cache of the first aspect of the present application, a ninth method for quickly accessing the host memory cache of the first aspect of the present application is provided, wherein the address of the storage block corresponding to a certain entry in the host address space is obtained by querying a certain entry in the mapping table, and the host memory cache is accessed using the queried address of the storage block in the host address space.

[0037] According to the eighth method for quickly accessing the host memory cache of the first aspect of the present application, a tenth method for quickly accessing the host memory cache of the first aspect of the present application is provided, wherein the starting address of the storage block corresponding to a certain entry in the host address space is obtained by querying a certain entry in the mapping table, and the starting address is added to the offset value to obtain the address to be accessed in the host address space to access the host memory cache.

[0038] According to the first to ten methods for quickly accessing the host memory cache of the first aspect of the present application, an eleventh method for quickly accessing the host memory cache of the first aspect of the present application is provided, wherein the address of the control component address space is divided by the memory page size, the quotient obtained is the entry number, and the remainder obtained is used as the offset value.

[0039] According to the eleventh method for quickly accessing the host memory cache of the first aspect of the present application, a twelfth method for quickly accessing the host memory cache of the first aspect of the present application is provided, wherein the specified bits of the address of the control component address space are used as the entry number and the other bits are used as the offset value.

[0040] According to a second aspect of the present application, a first storage device according to the second aspect of the present application is provided, which includes a control component and a non-volatile storage medium, and the control component executes the method of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in this application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0042] Figure 1A is a block diagram of a prior art solid-state storage device;

[0043] Figure 1B is a schematic diagram of HMB in the prior art;

[0044] Figure 2 It is a schematic diagram of the mapping between HMB and HMBDL in the prior art;

[0045] Figure 3 Schematic diagram of mapping the control component address space to the host address space in an embodiment of the present application;

[0046] Figure 4 This is a flowchart of converting the control component address space address into the host address space address according to an embodiment of the present application. DETAILED DESCRIPTION

[0047] The following is a clear and complete description of the technical solutions in the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0048] Figure 3 A schematic diagram of mapping the control component address space to the host address space according to an embodiment of the present application is shown.

[0049] See Figure 3 In an embodiment, a mapping table is created to establish a direct mapping relationship between the control component address space and the host address space. The mapping table is created based on the HMBDL. After obtaining the mapping table, the mapping table is queried based on the address of the control component address space. The queried mapping table entry records the host address corresponding to the address of the control component address space. Therefore, regardless of the value of the control component address space to be accessed, the latency of querying the mapping table is consistent, namely, the time it takes to access the mapping table.

[0050] The mapping table includes a plurality of entries. Figure 3The mapping table shown in includes entry 0, entry 1...entry 15, a total of 16 entries. The size of the address space of the same control component corresponding to the entry of the mapping table is determined according to the size described by CC.MPS (memory page size) of the NVMe protocol. As an example, the memory page size described by CC.MPS is 4KB, and the mapping table is created according to each entry representing 4KB of space. And the number of entries in the mapping table is determined according to the size of the HMB provided by the host. For example, when the size of the HMB is 64KB, the mapping table requires 16 entries (64 / 4=16).

[0051] All memory blocks provided by the host to the HMB are also split into multiple small memory blocks according to the size described by CC.MPS. CC.MPS describes the minimum memory allocation unit, so the size of all memory blocks provided by the host to the HMB must be an integer multiple of CC.MPS. By traversing the HMBDL, all memory blocks provided by the host to the HMB are obtained and each memory block is split into small memory blocks.

[0052] For example, see also Figure 3 The HMB consists of memory block 0, memory block 1, memory block 2, and memory block 3. The size of memory block 0 is 16KB, and the memory page size described by CC.MPS is 4KB. Therefore, memory block 0 is split into four consecutive memory blocks. Memory block 0 is located in the host address space, extending 4KB backward from the start address of memory block 0 (the memory page size described by CC.MPS). Memory block 1 is located in the host address space, extending 4KB backward from the start address of memory block 0 to 8KB backward from the start address of memory block 0 (that is, 4KB backward from the end of memory block 0). Similarly, memory block 2 is located in the host address space, extending 8KB backward from the start address of memory block 0 to 12KB backward from the start address of memory block 0. Memory block 1 is divided into eight memory blocks (memory blocks 4 to 11). Similarly, memory block 3 is divided into three memory blocks: memory blocks 13, 14, and 15. It can be understood that storage block 4 is located in the host address space and extends 4KB backward from the starting address of storage block 1, and storage block 13 is located in the host address space and extends 4KB backward from the starting address of storage block 3.

[0053] Thus, the number of entries in the mapping table is the same as the number of memory blocks into which all memory blocks provided by the host to the HMB are divided. Figure 3, there is a one-to-one correspondence between the 15 entries of the mapping table and the 15 storage blocks. To establish the mapping table, the address of the host address space of the corresponding storage block is recorded in each entry of the mapping table. Thus, the i-th entry of the mapping table indicates the mapping relationship between the address i * CC.MPS of the control unit address space and the storage block i, and the address of the storage block i in the host address space is recorded in the i-th entry.

[0054] The establishment of the mapping table occurs during the initialization phase of the control unit, and the mapping table is created based on the information described by HMBDL and CC.MPS. The mapping table is recorded in the memory inside the control unit or in, for example, DRAM110 coupled to the control unit. After the mapping table is established, it generally does not need to be modified unless the host updates HMBDL. And the mapping table is used to accelerate the address conversion process from the control unit address space to the host address space.

[0055] Thus, when the control unit wishes to access the address i * CC.MPS of the control unit address space provided by the HMB, the address of the storage block i in the host address space is obtained by querying the i-th entry of the mapping table, and the HMB is accessed using the obtained address of the storage block i in the host address space. As another example, when the control unit wishes to access the address i * CC.MPS + offset of the control unit address space provided by the HMB (where offset represents an offset value, 0 < offset < 4K), the starting address of the storage block i in the host address space (denoted as Ai) is obtained by querying the i-th entry of the mapping table, and then Ai + offset is used to obtain the address in the host address space to be accessed to access the HMB.

[0056] Figure 4 Shows a flowchart for converting the address of the control unit address space to the address of the host address space according to an embodiment of the present application.

[0057] As an example, the control unit wishes to access the HMB. The 64KB HMB is mapped to a 64KB range of the control unit address space. The control unit accesses this 64KB address space of the control unit address space to use the HMB.

[0058] To access the HMB, the control unit obtains the address of the control unit address space (denoted as CA) (410). According to the address CA of the control unit address space, the entry number i and the offset value (offset) of the corresponding mapping table are obtained (420). For example, divide CA by CC.MPS, the quotient obtained is the number i, and the remainder is used as the offset value. Another example is to take the specified bits of CA (for example, the lower 4 bits, the middle 4 bits, or the higher 4 bits) as the number i, and the other bits as the offset value.

[0059] The mapping table is queried and the starting address A of storage block i is obtained from the value recorded in mapping table entry i (430). Starting address A is the address in the host space. An offset value is then added to starting address A to obtain the host address corresponding to address CA in the control unit address space. This address is used to access the HMB (440).

[0060] According to the embodiments of the present application, the conversion time of the address in the control component address space to the host address can be greatly reduced, thereby improving the efficiency of the control component accessing the HMB.

[0061] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A method for quickly accessing a host memory cache, characterized in that: The specific steps include: Responsive to accessing the host memory cache, obtaining an address of the control component address space; According to the address of the control component address space, obtain the entry number and offset value of the corresponding mapping table; Obtaining a starting address of a corresponding storage block according to the entry number; wherein the storage block provided by the host to the host memory cache is split into storage blocks according to the memory page size, and the storage block size is equal to the memory page size; According to the combination of the starting address of the storage block and the offset value, a host address corresponding to the address of the control component address space is obtained, and the host memory cache is accessed by using the address.

2. The method for quickly accessing a host memory cache according to claim 1, wherein: The method further includes establishing a mapping table during the initialization phase, wherein the mapping table entries record the host addresses corresponding to the addresses in the control component address space.

3. The method for quickly accessing a host memory cache according to claim 1 or 2, wherein: The mapping table includes several entries, and the size of the control component address space corresponding to each entry in the mapping table is determined according to the size described by the memory page size.

4. The method for quickly accessing a host memory cache according to claim 3, wherein: The number of mapping table entries is determined based on the size described by the memory page size and the size of the host memory cache provided by the host.

5. The method for quickly accessing a host memory cache according to any one of claims 1 to 2, wherein: The host memory cache includes multiple storage blocks. Each storage block is split into one or more small storage blocks according to the memory page size. The size of each small storage block is the memory page size.

6. The method for quickly accessing a host memory cache according to claim 3, wherein: The number of entries of the mapping table is the same as the number of memory chunks of the memory blocks in the divided host memory cache.

7. The method for quickly accessing a host memory cache according to any one of claims 1 to 2, wherein: Each entry in the mapping table indicates a mapping relationship between an address in the control component address space and a storage block, so that each entry records an address in the host address space of the storage block corresponding to the entry.

8. The method for quickly accessing a host memory cache according to any one of claims 1 to 2, wherein: The mapping table is recorded in a memory inside the control component, or in a dynamic random access memory coupled with the control component.

9. The method for quickly accessing a host memory cache according to claim 8, wherein: The address of the storage block corresponding to a certain entry in the host address space is obtained by querying a certain entry in the mapping table, and the host memory cache is accessed using the queried address of the storage block in the host address space.

10. A storage device, characterized in that: The device comprises a control component and a non-volatile storage medium, wherein the control component executes the method according to any one of claims 1 to 9.

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