A high-precision test method for self-calibration of carrier plates
By setting up a chip-specific test tube base and relay connection circuit on the test vehicle board, the problems of component parameter errors of test vehicle board and input impedance deviation of the chip being tested are solved, and high-precision gain measurement is achieved, reducing the testing cost and avoid regular shutdown inspections.
Patent Information
- Application Number
- CN202110026572.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-01-08
- Publication Date
- 2024-12-13
- Estimated Expiration
- 2041-01-08
AI Technical Summary
In the prior art, the component parameter error of the test vehicle board and the deviation of the input impedance of the chip being tested leads to inaccurate input signal amplitude, resulting in errors in the test results, increasing the burden of post-commissioning, and the automatic test machine needs to be regularly Shut down for calibration, increasing testing costs.
Design a high-precision test method for self-calibration of the vehicle board. By providing a connection circuit for a dedicated chip test tube base and 4 relays on the test vehicle board, the input signal of the chip to be tested is bypassed during self-calibration mode. Store the analog signal collector as a reference level, switch back to the normal path during normal test mode, collect the output signal to calculate the gain, and eliminate the input line error factor.
The gain measurement value of each chip is achieved to achieve the optimal effect, reducing the testing cost, avoiding regular downtime inspection, improving the testing accuracy, and reducing parameter differences between systems.
Smart Images
Figure CN112858978B_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the technical field of semiconductor testing, in particular to a high-precision testing method for self-calibration of a carrier plate. Background Art
[0002] The test of high-fidelity audio power amplifier chip generally includes two parts. The first part is the harmonic distortion ratio test: 1. After the chip under test is powered on, the digital test channel of the automatic test machine provides 1.5V voltage to the "CTL" port of the chip under test, so that the chip under test enters the follow-up mode, that is, the amplitude of the output signal is equal to the amplitude of the input signal, and the gain is 1; 2. The analog signal generator of the automatic test machine generates a 1kHz sine signal, 1Vpp, that is, a differential signal with a peak-to-peak value of 1.0V, and AC-couples the audio signal input "IN+, IN-" of the chip under test; 3. When the power drive output terminal "OUT+, OUT-" of the chip under test is connected to the speaker equivalent load resistor (usually 33 ohms, 1 watt power resistor, plus series inductance), the analog signal collector of the automatic test machine performs discrete sampling on the output differential signal; 4. The sampled data is processed by the background software for signal processing and spectrum analysis, and the harmonic distortion ratio is calculated; The second part is the adjustable gain mode test: 1. After the chip under test is powered on, the digital test channel of the automatic test machine increases the voltage of the chip state control input "CTL" to 2.0V, and adjusts the output gain to 6dB, that is, the output is twice the input; 2. The analog signal generator sends a 1Vpp 1kHz sine signal, and the analog signal collector grabs the discrete sampling of the differential signal at the output end; 3. The sampled data is processed by the background software to calculate the peak-to-peak voltage. By comparing with the input voltage, it can be determined whether the gain meets the passing standard (6dB+ / -0.5dB), and the error range is about + / -6%. The above two tests have strict requirements on the accuracy of the signal amplitude at the input end of the chip under test. According to the usual standards of the measurement profession, it needs to be at least 5 times better than the allowable error of the item under test, that is, less than 1.2%.
[0003] However, the current test scheme is: 1. The analog signal generator generates a differential sinusoidal signal of Vin = 1Vpp, which is sent to the chip under test through the test cable and the test carrier board, and then through the DC blocking capacitor. After the load is added to the power drive output end of the chip, the analog signal collector performs discrete sampling. The background software performs signal processing to obtain the peak-to-peak value Vout of the output signal, and then performs logarithmic calculation on the ratio with Vin to make a judgment. 2. The chip differential input has a built-in 20k input impedance. The equivalent impedance of the DC blocking capacitor for a 1kHz signal is Zc = 1 / (2*3.14*1000*0.1*100000) = 1.56k. The final signal amplitude loaded to the chip input is: Vin@DUT = 1Vpp * [20k / (20k + 2*1.56k)] = 0.863Vpp. 3. The DC blocking capacitor here usually selects a high-quality X7R capacitor, whose nominal tolerance can reach + / -10%. The effect of capacitance deviation on the input signal amplitude change can reach Error = + / -[2*1.56k*10% / (20k + 2*1.56k)] = + / -1.37%, which has exceeded the 1.2% allowable error range of the signal source. 4. In addition, since there are uncontrollable differences in the capacitance value of each test carrier board, even qualified carrier boards actually have different attenuation coefficients for the input signal. In addition, as passive components, capacitors have uncontrollable temperature drift and aging parameter drift. The automatic chip testers are open 24 hours a day throughout the year. The uncontrollable changes in these parameters will lead to large intra-batch parameter differences in chips that have passed the test of different batches and different machines, which will cause a burden of later debugging for subsequent chip machine applications.
[0004] In order to deal with the above problems, the test factory will shut down the machine regularly and send the test carrier board to the maintenance team for parameter calibration. If necessary, components need to be replaced to correct the circuit with excessive deviation. However, this approach has disadvantages: 1. Regular shutdown for carrier board inspection and maintenance will reduce the utilization rate of the test machine and increase the amortized test cost. 2. Even for different machines within the specifications, there will be system deviations caused by characteristic drift. 3. The deviation of the built-in input impedance of each chip under test cannot be taken into account, which will further cause the deviation of the test results to expand. Summary of the invention
[0005] In order to overcome the deficiencies of the prior art, the present invention provides a high-precision test method for self-calibration of a carrier board, which does not require consideration of the influence of input signal deviation caused by component parameter errors on the test carrier board on the output signal; does not require consideration of the influence of input signal amplitude caused by the deviation of the internal input impedance of each chip under test; the gain measurement value of each chip can achieve the optimal test effect, and the automatic test machine does not need to be shut down regularly to inspect the test carrier board, thereby reducing the test cost.
[0006] In order to achieve the above purpose, a high-precision test method for self-calibration of a carrier plate is designed, including a test carrier plate and a chip-specific test tube holder, characterized in that the specific test method is as follows:
[0007] S1: A connection circuit between a chip-specific test socket and four relays is provided on the test carrier board of the automatic test machine;
[0008] S2: Place the chip under test on the chip-specific test tube holder;
[0009] S3: When the test carrier board is in self-calibration mode, the ports of the four relays are simultaneously input with a voltage of 0V, and the signal of the input differential end of the chip under test is bypassed and sent to the analog signal collector of the automatic test machine;
[0010] S5: After the analog signal collector of the automatic test machine captures the signal, it is stored as the reference level Vin;
[0011] S6: When the chip under test is in normal test mode, the Relay ports of the four relays are simultaneously input with a voltage of 5V, and the collector of the automatic test machine captures the actual output signal of the chip under test and finds the output signal level Vout;
[0012] S7: The gain G=Vout / Vin is calculated.
[0013] The connection circuit between the chip-specific test tube holder and the four relays includes a power amplifier, a relay, an inductor, a capacitor, and a resistor. Port No. 1 of the power amplifier is respectively connected to one end of capacitor one and port No. 3 of relay one; port No. 2 of the power amplifier is respectively connected to one end of capacitor two and port No. 3 of relay two; port No. 3 of the power amplifier is respectively connected to one end of the inductor and port No. 7 of relay three; port No. 4 of the power amplifier is respectively connected to one end of the resistor and port No. 7 of relay four; the other end of the resistor is connected to the other end of the inductor; the other end of the capacitor one is connected to port No. 6 of relay three; the other end of the capacitor two is connected to port No. 6 of relay four; port No. 5 of the power amplifier is respectively connected to one end of capacitor three and a 5V voltage, and the other end of capacitor three is grounded; port No. 6 of the power amplifier is grounded; port No. 1 of relay one is connected to a 5V voltage, port No. 4 of relay one is connected to port No. 5 of relay three, and port No. 1 of relay three is connected to a 5V voltage; port No. 1 of relay two is connected to a 5V voltage, port No. 4 of relay two is connected to port No. 5 of relay four, and port No. 1 of relay four is connected to a 5V voltage.
[0014] The model of the relay 1, relay 2, relay 3 and relay 4 is G6K-2P-5VDC.
[0015] The distance between the relay 1, the relay 2, the relay 3, the relay 4 and the power amplifier is 1-2 mm.
[0016] The model of the power amplifier is HA396.
[0017] Compared with the prior art, the present invention provides a high-precision test method for self-calibration of a carrier board, which does not need to consider the influence of input signal deviation caused by parameter errors of components on the test carrier board on the output signal; does not need to consider the influence of input signal amplitude caused by the deviation of the internal input impedance of each chip under test; the gain measurement value of each chip can achieve the optimal test effect, and the automatic test machine does not need to be shut down regularly to inspect the test carrier board, thereby reducing the test cost. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] Figure 1 Schematic diagram of a high-fidelity audio power amplifier chip.
[0019] Figure 2 Schematic diagram of the test vehicle board.
[0020] Figure 3 FIG. 4 is a circuit diagram of a test carrier board of the present invention.
[0021] Figure 4 FIG. 4 is a schematic diagram of signal flow of the test carrier board of the present invention in the self-calibration mode.
[0022] Figure 5 It is a schematic diagram of the signal flow of the chip under test in the test mode of the present invention. DETAILED DESCRIPTION
[0023] The present invention will be further described below with reference to the accompanying drawings.
[0024] like Figure 1As shown, the test of high-fidelity audio power amplifier chip generally includes two parts. The first part is the harmonic distortion ratio test: 1. After the chip under test is powered on, the digital test channel of the automatic test machine provides 1.5V voltage to the "CTL" port of the chip under test, so that the chip under test enters the follow-up mode, that is, the amplitude of the output signal is equal to the amplitude of the input signal, and the gain is 1; 2. The analog signal generator of the automatic test machine generates a 1kHz sine signal, 1Vpp, that is, a differential signal with a peak-to-peak value of 1.0V, and AC-couples the audio signal input "IN+, IN-" of the chip under test; 3. When the power drive output terminal "OUT+, OUT-" of the chip under test is connected to the speaker equivalent load resistor (usually 33 ohms, 1 watt power resistor, plus series inductance), the analog signal collector of the automatic test machine performs discrete sampling on the output differential signal; 4. The sampled data is processed by the background software for signal processing and spectrum analysis, and the harmonic distortion ratio is calculated; The second part is the adjustable gain mode test: 1. After the chip under test is powered on, the digital test channel of the automatic test machine increases the voltage of the chip state control input "CTL" to 2.0V, and adjusts the output gain to 6dB, that is, the output is twice the input; 2. The analog signal generator sends a 1Vpp 1kHz sine signal, and the analog signal collector grabs the discrete sampling of the differential signal at the output end; 3. The sampled data is processed by the background software to calculate the peak-to-peak voltage. By comparing with the input voltage, it can be determined whether the gain meets the passing standard (6dB + / -0.5dB), and the error range is about + / -6%. The above two tests have strict requirements on the accuracy of the signal amplitude at the input end of the chip under test. According to the usual standards of the measurement profession, it needs to be at least 5 times better than the allowable error of the item under test, that is, less than 1.2%.
[0025] However, the current test scheme is: 1. The analog signal generator generates a differential sinusoidal signal of Vin = 1Vpp, which is sent to the chip under test through the test cable and the test carrier board, and then through the DC blocking capacitor. After the load is added to the power drive output end of the chip, the analog signal collector performs discrete sampling. The background software performs signal processing to obtain the peak-to-peak value Vout of the output signal, and then performs logarithmic calculation on the ratio with Vin to make a judgment. 2. The chip differential input has a built-in 20k input impedance. The equivalent impedance of the DC blocking capacitor for a 1kHz signal is Zc = 1 / (2*3.14*1000*0.1*100000) = 1.56k. The final signal amplitude loaded to the chip input is: Vin@DUT = 1Vpp * [20k / (20k + 2*1.56k)] = 0.863Vpp. 3. The DC blocking capacitor here usually selects a high-quality X7R capacitor, whose nominal tolerance can reach + / -10%. The effect of capacitance deviation on the input signal amplitude change can reach Error = + / -[2*1.56k*10% / (20k + 2*1.56k)] = + / -1.37%, which has exceeded the 1.2% allowable error range of the signal source. 4. In addition, since there are uncontrollable differences in the capacitance value of each test carrier board, even qualified carrier boards actually have different attenuation coefficients for the input signal. In addition, as passive components, capacitors have uncontrollable temperature drift and aging parameter drift. The automatic chip testers are open 24 hours a day throughout the year. The uncontrollable changes in these parameters will lead to large intra-batch parameter differences in chips that have passed the test of different batches and different machines, which will cause a burden of later debugging for subsequent chip machine applications.
[0026] like Figure 2 As shown, considering that the test item of the present invention focuses on the output gain G, rather than requiring the absolute accuracy of the input signal amplitude. Therefore, the real signal amplitude of the input end is expressed as Vin=Vin_awg-ΔVin, then the output signal amplitude is Vout=G*Vin, then the output gain is G=Vout / Vin. It can be seen that G here has eliminated the influence of the error caused by the input end line. The above can be achieved by simply adding 4 relays to the carrier board, bypassing the signal of the input differential end of the chip under test to the analog signal collector of the automatic test machine. After the collector captures the signal, it is stored as the reference level Vin, and then the relay is switched back to the normal test path. The collector captures the actual output signal of the chip under test, finds the output signal level Vout, and calculates G=Vout / Vin. In order not to affect the signal quality on the normal test path, these 4 relays are placed as close as possible to the signal path to be bypassed. The distance between these 4 relays and the test carrier board is 1~2 mm to ensure that the signal bifurcation path is the shortest.
[0027] The specific test method is as follows:
[0028] S1: A connection circuit between a chip-specific test socket and four relays is provided on the test carrier board of the automatic test machine;
[0029] S2: Place the chip under test on the chip-specific test tube holder;
[0030] S3: When the test carrier board is in self-calibration mode, the ports of the four relays are simultaneously input with a voltage of 0V, and the signal of the input differential end of the chip under test is bypassed and sent to the analog signal collector of the automatic test machine;
[0031] S5: After the analog signal collector of the automatic test machine captures the signal, it is stored as the reference level Vin;
[0032] S6: When the chip under test is in normal test mode, the Relay ports of the four relays are simultaneously input with a voltage of 5V, and the collector of the automatic test machine captures the actual output signal of the chip under test and finds the output signal level Vout;
[0033] S7: The gain G=Vout / Vin is calculated.
[0034] like Figure 3 As shown, the connection circuit between the chip dedicated test socket and the four relays includes a chip, a relay, an inductor, a capacitor, and a resistor. Port 1 of the power amplifier U1 is respectively connected to one end of capacitor C1 and port 3 of relay K1; port 2 of the power amplifier U1 is respectively connected to one end of capacitor C2 and port 3 of relay K2; port 3 of the power amplifier U1 is respectively connected to one end of inductor L1 and port 7 of relay K3; port 4 of the power amplifier U1 is respectively connected to one end of resistor R1 and port 7 of relay K4; the other end of resistor R1 is connected to the other end of inductor L1; the other end of capacitor C1 is connected to Connect to port 6 of relay three K3; the other end of capacitor two C2 is connected to port 6 of relay four K4; port 5 of power amplifier U1 is respectively connected to one end of capacitor three C3 and 5V voltage, and the other end of capacitor three C3 is grounded; port 6 of power amplifier U1 is grounded; port 1 of relay one K1 is connected to 5V voltage, port 4 of relay one K1 is connected to port 5 of relay three K3, and port 1 of relay three K3 is connected to 5V voltage; port 1 of relay two K2 is connected to 5V voltage, port 4 of relay two K2 is connected to port 5 of relay four K4, and port 1 of relay four K4 is connected to 5V voltage.
[0035] Port 8 (i.e. Relay) of Relay 1 K1, Relay 2 K2, Relay 3 K3, and Relay 4 K4 are all control pins. There is a coil between pin 1 and pin 8. When current passes through, an electromagnetic field will be generated, and the magnetic force of the electromagnetic field will be used to attract the switch blade to complete the switching of the signal path. Therefore, the signal names "Relay1, Relay2, Relay3, Relay4" here are all externally applied control signals, which can form a current loop with the 5V power supply on each pin 1 to control the presence or absence of the electromagnetic field, thereby realizing the signal switching of each relay.
[0036] The model of relay 1 K1, relay 2 K2, relay 3 K3, and relay 4 K4 is G6K-2P-5VDC.
[0037] The model of power amplifier U1 is HA396.
[0038] The above relays K1, K2, K3 and K4 can also be connected with two relays, K1 and K2. However, in such a connection, the connection between the back end and the analog signal collector is bifurcated, so there will be noise in the path, causing interference. Therefore, the connection of 4 relays is the best solution.
[0039] like Figure 4 As shown in the figure, when the test carrier board is in the self-calibration mode, the Relay ports (i.e. port 8) of the four relays are simultaneously input with a voltage of 0V, bypassing the signal of the differential input end of the chip under test to the analog signal collector of the automatic tester. After the collector captures the signal, it is stored as the reference level Vin.
[0040] like Figure 5 As shown in the figure, when the chip under test is in the test mode, the Relay ports of the four relays (i.e. port 8) are simultaneously input with a voltage of 5V. At this time, the collector of the automatic test machine captures the actual output signal of the chip under test, finds the output signal level Vout, and then calculates G=Vout / Vin.
[0041] The present invention does not need to consider the impact of input signal deviation caused by component parameter errors on the test carrier board on the output signal, because it has been eliminated by the calculation process; there is no need to consider the impact of input signal amplitude caused by the deviation of the internal input impedance of each chip under test, because each chip will have its own independently measured Vin, and the unknown input impedance deviation is compensated before the gain is calculated; the gain measurement value of each chip can achieve the optimal test effect, and its accuracy truly reaches the optimal level guaranteed by the analog signal generator and collector, providing reliable data for the later chip internal fuse compensation mechanism; there is no need to shut down regularly to inspect the test carrier board, which reduces the test cost; the system error between automatic testers is optimally processed to avoid statistical deviations in large-scale mass production data between systems.
Claims
1. A high-precision test method for self-calibration of a carrier plate, comprising a test carrier plate and a chip-specific test tube holder, characterized in that: The specific test method is as follows: S1: A connection circuit between a chip-specific test socket and four relays is provided on the test carrier board of the automatic test machine; S2: Place the chip under test on the chip-specific test tube holder; S3: When the test carrier board is in self-calibration mode, the ports of the four relays are simultaneously input with a voltage of 0V, and the signal of the input differential end of the chip under test is bypassed and sent to the analog signal collector of the automatic test machine; S5: After the analog signal collector of the automatic test machine captures the signal, it is stored as the reference level Vin; S6: When the chip under test is in normal test mode, the Relay ports of the four relays are simultaneously input with a voltage of 5V, and the collector of the automatic test machine captures the actual output signal of the chip under test and finds the output signal level Vout; S7: Calculate and obtain the gain G=Vout / Vin; The connection circuit between the chip-specific test socket and the four relays comprises a power amplifier, a relay, an inductor, a capacitor, and a resistor. Port 1 of the power amplifier (U1) is respectively connected to one end of capacitor 1 (C1) and port 3 of relay 1 (K1); port 2 of the power amplifier (U1) is respectively connected to one end of capacitor 2 (C2) and port 3 of relay 2 (K2); port 3 of the power amplifier (U1) is respectively connected to one end of inductor (L1) and port 7 of relay 3 (K3); port 4 of the power amplifier (U1) is respectively connected to one end of resistor (R1) and port 7 of relay 4 (K4); the other end of the resistor (R1) is connected to the other end of the inductor (L1); the other end of capacitor 1 (C1) is connected to the other end of the inductor (L1); The first end of the capacitor (C2) is connected to the No. 6 port of the relay three (K3); the other end of the capacitor two (C2) is connected to the No. 6 port of the relay four (K4); the No. 5 port of the power amplifier (U1) is respectively connected to one end of the capacitor three (C3) and a 5V voltage, and the other end of the capacitor three (C3) is grounded; the No. 6 port of the power amplifier (U1) is grounded; the No. 1 port of the relay one (K1) is connected to the 5V voltage, the No. 4 port of the relay one (K1) is connected to the No. 5 port of the relay three (K3), and the No. 1 port of the relay three (K3) is connected to the 5V voltage; the No. 1 port of the relay two (K2) is connected to the 5V voltage, the No. 4 port of the relay two (K2) is connected to the No. 5 port of the relay four (K4), and the No. 1 port of the relay four (K4) is connected to the 5V voltage.
2. A high-precision test method for self-calibration of a carrier plate according to claim 1, characterized in that: The model of relay 1 (K1), relay 2 (K2), relay 3 (K3) and relay 4 (K4) is G6K-2P-5VDC.
3. A high-precision test method for self-calibration of a carrier plate according to claim 1, characterized in that: The distances between the relay 1 (K1), the relay 2 (K2), the relay 3 (K3), the relay 4 (K4) and the power amplifier (U1) are 1 to 2 millimeters.
4. A high-precision test method for self-calibration of a carrier plate according to claim 1, characterized in that: The model of the power amplifier (U1) is HA396.