Memory device and memory module performing self-calibration by recognizing location information

Abstract

A memory device of a memory module includes a command / address (CA) buffer that receives CA signals through a bus shared by memory devices other than the memory device of the memory module, and calibration logic circuitry that identifies location information of the memory device on the bus. The memory device recognizes its own position on the bus in the memory module to perform self-calibration, so that the memory device can operate properly even under operating conditions that vary depending on the position in the memory module.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0144108, filed on November 12, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Example embodiments of this disclosure relate to a memory device that performs self-calibration by recognizing location information and a memory module that includes the memory device. Background Technology

[0004] A memory module is a printed circuit board on which one or more memory devices are mounted. Memory modules can be used in various computing systems, such as servers, workstations, and personal computers. As the operating speed of memory modules and the memory devices mounted on them increases, various calibration or training operations can be performed on the memory devices. Due to the standards, size, wiring space, etc., of memory modules, multiple memory devices within the module can share a bus with multiple transmission paths to access each other. However, the locations of the multiple memory devices placed on the bus within the memory module can differ.

[0005] Calibration is the process of determining deviations from a standard and establishing correction factors to reduce, eliminate, or compensate for those deviations. Calibration may include adjusting specific functions to improve effectiveness.

[0006] Training is the process of making instruction appropriate, qualified, or proficient. Training can reduce, eliminate, or compensate for errors that might occur if training is not performed. Summary of the Invention

[0007] An example embodiment provides a memory device that performs self-calibration by recognizing location information, and a memory module including the memory device.

[0008] According to an aspect of an example embodiment, a memory device for a memory module is provided, the memory device including: a command / address (CA) buffer configured to receive command / address (CA) signals via a bus shared by a second memory device different from the memory module; and calibration logic circuitry configured to identify location information of the memory device on the bus.

[0009] According to an aspect of an example embodiment, a memory device for a memory module is provided, the memory device comprising: a command / address (CA) buffer configured to receive CA signals via a bus shared by a second memory device different from the memory device of the memory module; an equalizer configured to compensate for CA signals received from the CA buffer via the bus; and calibration logic circuitry configured to identify location information of the memory device, wherein the location information indicates the transmission length of the bus measured from the CA pin of the memory module to the CA buffer, and to adjust the equalizer based on the location information.

[0010] According to an example embodiment, a memory module is provided, comprising: a first memory device; and a second memory device sharing a bus with the first memory device, wherein the first memory device includes a first command / address (CA) buffer configured to receive a CA signal via the bus; and a first calibration logic circuit configured to identify first location information of the first memory device on the bus, and wherein the second memory device includes a second CA buffer configured to receive a CA signal via the bus, and a second calibration logic circuit configured to identify second location information of the second memory device on the bus. Attached Figure Description

[0011] The above and other aspects will become clear from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0012] Figure 1 A block diagram of a computing system according to an example embodiment is shown;

[0013] Figure 2 Detailed illustration Figure 1 A block diagram of the memory module;

[0014] Figure 3 , Figure 4 and Figure 5 They are shown respectively Figure 2 A block diagram of a memory device;

[0015] Figure 6 It shows Figures 1 to 5 A block diagram of a memory device;

[0016] Figure 7 Detailed illustration Figure 6 Receivers and equalizers for memory devices;

[0017] Figure 8 Detailed illustration Figure 6 Receivers and equalizers for memory devices;

[0018] Figure 9 Detailed illustration Figure 6 Serializers and transmitters for memory devices;

[0019] Figure 10 , Figure 11 and Figure 12 A block diagram of a memory module according to an example embodiment is shown; and

[0020] Figure 13 and Figure 14 A block diagram of a computing system according to an example embodiment is shown. Detailed Implementation

[0021] Figure 1 A block diagram of a computing system according to an example embodiment is shown. The computing system 10 may also be referred to as an "electronic system" or a "memory system" and may be implemented on an electronic device. The computing system 10 may include a memory controller 11 and a memory module 100. The memory controller 11 may control the memory module 100 in response to requests from a processor supporting various applications, such as server applications, personal computer (PC) applications, and mobile applications. For example, the memory controller 11 may send a CA signal to the memory module 100. In this specification, "CA" may refer to a command and address or a command / address. For example, a CA signal may constitute a command or address for accessing memory devices 110 and 120.

[0022] Memory module 100 may include memory devices 110 and 120 and a bus 130. Memory device 110 may include a CA buffer 111 and calibration logic circuitry 112. Memory device 120 may include a CA buffer 121 and calibration logic circuitry 122. Bus 130 may include a path for sending CA signals to memory devices 110 and 120. For example, bus 130 may also be referred to as a "CA bus". Memory devices 110 and 120 may be connected to bus 130 and may share bus 130. CA buffers 111 and 121 may receive the same CA signals through bus 130. Memory devices 110 and 120 may be connected to bus 130 in a multi-drop or multi-point manner. For example, CA signals may be sent in the direction from memory device 110 to memory device 120 through bus 130, and memory device 110 may receive CA signals earlier than memory device 120. The memory controller 11 can send CA signals to memory devices 110 and 120 using a fly-by topology, but time-of-flight skew may exist between memory devices 110 and 120. A memory device can also be referred to as a "memory chip".

[0023] Calibration logic circuit 112 can identify (or recognize, check, determine, etc.) the location information LI1 of memory device 110 on bus 130. Calibration logic circuit 122 can identify (or recognize, check, determine, etc.) the location information LI2 of memory device 120 on bus 130. That is, memory devices 110 and 120 can each identify their respective location information LI1 and LI2. Location information LI1 can be provided to calibration logic circuit 112, and location information LI2 can be provided to calibration logic circuit 122. The location information can be determined by a specific memory device based on an evaluation circuit connected to a specific resistor. The value of the specific resistor can be a function of the location of the specific memory device on the bus. When manufacturing the circuit board on which memory devices 110 and 120 are mounted, the specific resistor is installed at a specific location along with the specific memory device.

[0024] As described above, memory devices 110 and 120 can respectively identify their respective location information LI1 and LI2. Generally, this identification by calibration logic circuit 112 can be performed using pin voltage levels (e.g., related to resistors electrically connected to pins of memory device 110), ID information in the registers of memory device 110, or information programmed into the fuse array of memory device 110. Similarly, identification by calibration logic circuit 122 can be performed using pin voltage levels of memory device 120, second ID information in the registers of memory device 120, or information programmed into the fuse array of memory device 120.

[0025] The purpose of calibration is to allow efficient reading and writing of data on a high-speed bus. As bus speeds increase and supply voltages decrease, waveform edges become less sharp and may be misread as "1" or "0". The shape of the waveform edges depends on the physical location on the bus, as waveform shape depends on signal propagation along the bus. The embodiments provided herein reduce, eliminate, or compensate for this error. Therefore, by calibrating or training according to a function of location on the bus, the efficiency of reading or writing data can be improved by reducing the occurrence of this error.

[0026] As an example, efficiency can be improved by using a receiver to sample the DQS signal driven by the transmitter of the memory device. In this example, the receiver provides a signal to a write leveling circuit, which is configured to know the position information using one of the methods described herein. An example embodiment is provided by Figure 6 Components 1303 (receiver), 1306 (transmitter), and 1304 (write leveling) are provided.

[0027] The calibration logic circuit 112 can perform calibration operations (or training operations) on the operation of the memory device 110 using the location information LI1, and can adjust the operating parameters of the memory device 110.

[0028] In some embodiments, for example, a delay lock loop (DLL) can determine a timing adjustment for optimal sampling of data on the bus based on location. For example, the timing adjustment can be a function of location information LI1. This adjustment can be referred to as training or calibration. Calibration logic circuitry 122 can perform a calibration operation (or training operation) on the operation of memory device 120 using location information LI2, and can adjust the operating parameters of memory device 120. In the example above, the delay lock loop can determine the timing adjustment for optimal sampling of data on the bus as a function of location information LI2.

[0029] For example, location information LI1 and location information LI2 can be different. Location information LI1 can indicate that the location of memory device 110 on bus 130 is relatively close to memory controller 11, and location information LI2 can indicate that the location of memory device 120 on bus 130 is relatively far from memory controller 11. Location information LI1 can indicate the distance of bus 130 between memory device 110 and memory controller 11, or it can indicate the distance from the memory module 100 through its pin where it receives CA signals to CA buffer 111. Location information LI2 can indicate the distance of bus 130 between memory device 120 and memory controller 11, or it can indicate the distance from the memory module 100 through its pin where it receives CA signals to CA buffer 121. For another example, memory device 110 and memory device 120 can be adjacent to each other, and location information LI1 and location information LI2 can be the same.

[0030] Figure 2 Detailed illustration Figure 1A block diagram of the memory module is provided. Memory device 110 may also include an equalizer 113, and memory device 120 may also include an equalizer 123. Equalizer 113 can recover the CA signal transmitted via bus 130 and received or sampled by CA buffer 111. Bus 130 may be a channel, such as a coaxial cable or PCB trace. Therefore, when the CA signal is transmitted at high speed via bus 130, the bandwidth of bus 130 may be limited due to the load of bus 130, surface effect and dielectric loss, intersymbol interference (ISI), etc., and the high-frequency components of the CA signal on CA buffer 111 may be attenuated. Equalizer 113 can boost or reinforce the high-frequency components of the CA signal received by CA buffer 111. Unlike bus 130, which has a frequency response such as a low-pass filter, equalizer 113 may have a frequency response such as a high-pass filter. As in equalizer 113, equalizer 123 can boost the high-frequency components of the CA signal received by CA buffer 121.

[0031] Calibration logic circuit 112 can adjust equalizer 113 using position information LI1 from memory device 110 on bus 130. Calibration logic circuit 122 can adjust equalizer 123 using position information LI2 from memory device 120 on bus 130. For example, the degree to which calibration logic circuit 112 adjusts equalizer 113 and the degree to which calibration logic circuit 122 adjusts equalizer 123 can differ when position information LI1 and position information LI2 are different. The degree to which equalizer 113 adjusted by calibration logic circuit 112 amplifies the high-frequency components of the CA signal received by CA buffer 111 can differ from the degree to which equalizer 123 adjusted by calibration logic circuit 122 amplifies the high-frequency components of the CA signal received by CA buffer 121. In another example, calibration logic circuits 112 and 122 can determine whether to enable equalizers 113 and 123 by using position information LI1 and LI2 respectively. In another example, when location information LI1 and location information LI2 are the same, the degree to which calibration logic circuit 112 adjusts equalizer 113 and the degree to which calibration logic circuit 122 adjusts equalizer 123 can be the same.

[0032] Figure 3 , Figure 4 and Figure 5 They are shown respectively Figure 2 A block diagram of a memory device. (See also...) Figure 1 and Figure 2 describe Figures 3 to 5Furthermore, memory devices 110_1 to 110_3 can be examples of memory devices 110 / 120. Memory device 120 can be implemented substantially the same as memory device 110. (See reference...) Figures 3 to 5 In each of the memory devices 110_1 to 110_3, the CA buffer 111 can receive the CA signal through the CA pin 101 and output the received CA signal as the internal CA signal ICA. The equalizer 113 can recover the high-frequency components of the internal CA signal ICA. The calibration logic circuit 112 can adjust the equalizer 113 using the position information LI1. (Reference) Figure 3 The calibration logic circuit 112 can identify the location information LI of the memory device 110_1 on the bus 130 by checking the voltage level input through pin 102. The voltage level can be the power supply voltage level or ground voltage level of the memory device 110_1, or any voltage level between the power supply voltage level and the ground voltage level. For another example, the number of pins 102 can be two or more, and the calibration logic circuit 112 can identify the location information LI of the memory device 110_1 on the bus 130 by decoding multiple voltage levels input through pins 102. (See reference...) Figure 4 The memory device 110_2 may include a mode register 114. The mode register 114 may store various information about the operating conditions of the memory device 110_2, depending on a request from the memory controller 11. For example, the memory controller 11 may write various values, including location information, into the mode register 114 by issuing a mode register write command (MRW) or a mode register set command (MRS). The calibration logic circuit 112 can identify the location information LI (②) of the memory device 110_2 on the bus 130 by using the location information LI stored in the mode register 114. (See reference...) Figure 5 The memory device 110_3 may include a fuse array 115. The fuse array 115 may store various information about the operating conditions of the memory device 110_3. For example, information indicating the location of the memory device 110_3 installed in the memory module 100 (i.e., the location information of the memory device 110_3 on the bus 130) may be pre-programmed in the fuse array 115. The calibration logic circuit 112 can identify the location information LI (③) of the memory device 110_3 on the bus 130 by using the location information LI stored in the fuse array 115.

[0033] Figure 6 It shows Figures 1 to 5A block diagram of a memory device. Memory device 1000 may be an example of the memory devices 110 / 120 described above. Memory device 1000 may include a bank 1100. Bank 1100 may include a memory cell array 1101, a row decoder 1102, a column decoder 1103, a write driver 1104, and an input / output sense amplifier 1105. Memory cell array 1101 may include memory cells selected by row decoder 1102 and column decoder 1103 and connected to word lines and bit lines. For example, each of the memory cells can be one of a static random access memory (SRAM) cell, a dynamic random access memory (DRAM) cell, a thyristor random access memory (TRAM) cell, a NAND flash memory cell, a NOR flash memory cell, a resistive random access memory (RRAM) cell, a ferroelectric random access memory (FRAM) cell, a phase change random access memory (PRAM) cell, and a magnetic random access memory (MRAM) cell, or the memory cell can be implemented using a combination of the above cells.

[0034] Row decoder 1102 can decode the row address included in the CA signal CA[A:0] (where A is a natural number), enable the word line(s) corresponding to that row address, and select the memory cell connected to that word line. Column decoder 1103 can decode the column address included in the CA signal CA[A:0], enable the column select line(s) corresponding to that column address, and select the memory cell connected to the bit line connected to that column select line. Write driver 1104 can write "write data" to the memory cell selected by row decoder 1102 and column decoder 1103. Input / output sense amplifier 1105 can sense and amplify read data from the selected memory cell. The number of memory banks 1100 can be one or more, and multiple memory banks 1100 can constitute a memory bank group.

[0035] The memory device 1000 may further include a clock pin 1201, a clock buffer 1202, a delay circuit 1203, a CA pin 1204, a voltage generator 1205, a CA buffer 1206, an equalizer 1207, a sampler 1208, a command decoder 1209, a mode register 1210, and calibration logic circuitry 1211. The clock pin 1201 may be connected to one path of the CA bus corresponding to bus 130 and may receive a clock signal CK (e.g., the CA bus may also be referred to as the "CK / CA bus"). The clock buffer 1202 may be a receiver that can receive the clock signal CK through the clock pin 1201, amplify the received clock signal CK, and generate an internal clock signal ICK. The clock buffer 1202 may also receive a complementary clock signal CKb through a complementary clock pin connected to another path of the CA bus. The delay circuit 1203 may delay the internal clock signal ICK and generate a delayed clock signal ICKD.

[0036] The CA pin 1204 can be connected to multiple paths of the CA bus corresponding to bus 130, and can receive the CA signal CA[A:0]. As described above, the CA signal CA[A:0] can include various commands associated with the memory device 1000 (e.g., activation command ACT, precharge command PRE, auto refresh command AREF, self refresh command SREF, write command WR, read command RD, mode register write command MRW, mode register set command MRS, mode register read command MRR, and multi-purpose command MPC), indicating the memory bank address of the memory bank 1100, and the row and column addresses indicating the word lines and column select lines of the memory cell array 1101, respectively. The voltage generator 1205 can generate a reference voltage VREFCA and can provide the reference voltage VREFCA to the CA buffer 1206.

[0037] CA buffer 1206 can receive the CA signal CA[A:0] via CA pin 1204. CA buffer 1206 can compare the voltage level of the CA signal CA[A:0] with the level of a reference voltage VREFCA. For example, the reference voltage VREFCA can be an internal voltage used to determine the voltage level of the CA signal CA[A:0] corresponding to a logic value. CA buffer 1206 can amplify the CA signal CA[A:0] based on the reference voltage VREFCA and can provide the internal CA signal ICA[A:0] to sampler 1208 respectively. Each of the CA buffers 1206 can correspond to a reference voltage. Figures 1 to 5The CA buffers 111 / 121 are described. Equalizer 1207 can compensate for or recover the high-frequency components of the CA signal CA[A:0] input to CA buffer 1206 via the CA bus and CA pin 1204, respectively. Each of equalizers 1207 can correspond to a reference. Figures 2 to 5 The equalizers 113 / 123 are described. The sampler 1208 can sample the internal CA signal ICA[A:0] based on the delayed clock signal ICKD. The sampler 1208 can sample the logic value of the CA signal CA[A:0] at the rising or falling edge of the clock signal CK. For example, the sampler 1208 can be a flip-flop that latches, holds, and stores the sampled logic value of the CA signal CA[A:0] at the rising or falling edge of the delayed clock signal ICKD.

[0038] Command decoder 1209 can receive the logical value of CA signal CA[A:0] sampled by sampler 1208, and can decode (multiple) commands included in CA signal CA[A:0]. For example, command decoder 1209 can control memory bank 1100 based on the decoding result. Command decoder 1209 can provide the row address and column address of CA signal CA[A:0] to row decoder 1102 and column decoder 1103 respectively based on the decoding result. Figure 6 An example of command decoder 1209 controlling memory 1100 is shown, but command decoder 1209 can also control Figure 6 Any other components of the memory device 1000 shown, as well as the storage unit 1100.

[0039] The operation of mode register 1210 can be similar to Figure 4 The operation of mode register 114. Mode register 1210 can store operands, opcodes, data, etc., included in the CA signal CA[A:0] associated with the operating conditions of memory device 1000, under the control of command decoder 1209 which decodes mode register write command MRW or mode register set command MRS. The information stored in mode register 1210 can be output to memory controller 11 under the control of command decoder 1209 which decodes mode register read command MRR. For example, the information stored in mode register 1210 can be included in DQ signal DQ[B:0] (B is a natural number) for output through DQ pin 1401.

[0040] In the example embodiment, a portion of the mode register 1210 may store position information LI(①) input via pin 1600 of the memory device 1000. Pin 1600 may be connected to... Figure 3The pins 102 are essentially the same, and the position information LI input via pin 1600 can be essentially the same as the position information LI input via pin 102. For example, a portion of the mode register 1210 can store the position information LI as a CA on-die termination (ODT) strap value. The memory controller 11 can read the CA ODT strap value stored in the mode register 1210 by issuing a mode register read command MRR, and can determine the position of the memory device 1000 on bus 130 in the memory module 100 by identifying the CA ODT strap value.

[0041] In another example embodiment, the remainder of the mode register 1210 may store identification (ID) information about the memory device 1000. The memory controller 11 may generate a mode register write command (MRW) and the ID information. The ID information stored in the remainder of the mode register 1210 may be used as location information LI (②). The location information LI corresponding to this ID information may be used with... Figure 4The location information LI is basically the same. The mode register 1210 that stores the location information LI(①) input via pin 1600 and the mode register 1210 that stores the ID information as location information LI(②) are different and have different mode register addresses. The CA signal CA[A:0] may include the mode register write command MRW and ID information. In order to prevent the same ID information from being written into the mode registers 1210 of different memory devices 110 and 120 when the CA signal CA[A:0] is sent to the corresponding memory devices 110 and 120 via bus 130, the memory controller 11 may allow the memory device 1000 to enter per DRAM addressability (PDA) mode. For example, memory devices 110 and 120 may share the CA bus, but not the DQ bus (or data input / output bus) through which the DQ signal DQ[B:0] is sent (which will be described later). The DQ bus for memory device 110 and the DQ bus for memory device 120 may be respectively set between the memory controller 11 and the memory module 100. The memory controller 11 can allow memory devices 110 and 120 to enter PDA mode. It can send a CA signal CA[A:0], including a mode register write command (MRW) and ID information for memory device 110, to each of the memory devices 110 and 120 via bus 130. It can also send a DQ signal DQ[0] with a first logic value (e.g., low) and a DQ signal DQ[B:1] with a second logic value (e.g., high) to memory device 110, and a DQ signal DQ[B:0] with a second logic value to memory device 120. The command decoder 1209 of memory device 110 can check the first logic value of the DQ signal DQ[0] and can effectively process the mode register write command (MRW) from the memory controller 11. Conversely, the command decoder 1209 of memory device 120 can check the second logic value of the DQ signal DQ[0] and can choose not to process the mode register write command (MRW) from the memory controller 11. The memory controller 11 can store different ID information in the mode register 1210 of the memory devices 110 and 120 using PDA mode.

[0042] In another example embodiment, a portion of the mode register 1210 may store position information LI (③) pre-programmed in the fuse array 1800. The position information LI pre-programmed in the fuse array 1800 may be... Figure 5The position information LI programmed in the fuse array 115 is essentially the same. A portion of the mode register 1210 can store the above position information LI as a CAODT value. For example, if the position information LI is pre-programmed in the fuse array 1800, the memory device 1000 may not include pin 1600. For another example, if the position information LI is input via pin 1600, the position information LI may not be pre-programmed in the fuse array 1800. In summary, the memory device 1000 can identify the position information LI via pin 1600 (①), can identify the ID information sent from the memory controller 11 as the position information LI (②), or can identify the position information LI pre-programmed in the fuse array 1800 (③).

[0043] The calibration logic circuit 1211 can adjust the equalizer 1207 separately using the position information LI1. The calibration logic circuit 1211 can identify the position information LI, check whether the position of the memory device 1000 on the bus 130 is relatively close to or relatively far from the memory controller 11, and can adjust the equalizer 1207 differently depending on the position information LI. When the position of the memory device 1000 on the bus 130 is relatively close to the memory controller 11, the calibration logic circuit 1211 can relatively reduce the degree to which the equalizer 1207 amplifies the high-frequency components of the internal CA signal ICA[A:0], or can disable the equalizer 1207. When the position of the memory device 1000 on the bus 130 is relatively far from the memory controller 11, the calibration logic circuit 1211 can relatively increase the degree to which the equalizer 1207 amplifies the high-frequency components of the internal CA signal ICA[A:0], or can enable the equalizer 1207. The calibration logic circuit 1211 can perform training between the clock signal CK and the CA signal CA[A:0] using the position information LI. Generally, the phrase "training between" refers to adjusting aspects of the circuitry at the memory device based on its location. For example, as used herein, "training between" includes delaying the internal CA signal ICA as described below. Calibration logic 1211 can adjust the degree to which the delayed clock signal ICKD, delayed by delay circuit 1203 for sampling the internal CA signal ICA[A:0], is deferred using location information LI. Calibration logic 1211 can also delay the internal CA signal ICA[A:0] using location information LI1. Calibration logic 1211 can also perform training between the internal CA signals ICA[A:0] using location information LI1. By delaying the internal CA signal ICA[A:0] differently, calibration logic 1211 can reduce, eliminate, or compensate for the skew of the internal CA signal ICA[A:0] due to the skew of pin 1204, and can align the internal CA signal ICA[A:0] with the delayed clock signal ICKD.

[0044] Voltage generator 1205 can adjust the level of reference voltage VREFCA using location information LI. For example, voltage generator 1205 can adjust the level of reference voltage VREFCA differently depending on whether the location information LI indicates that the memory device 1000 on bus 130 is relatively close to or relatively far from memory controller 11.

[0045] Memory device 1000 may further include a DQS pin 1301, a DQS buffer 1302, a write leveling circuit 1304, and a DQS signal generator 1305. The DQS pin 1301 may be connected to a path of the DQ bus between memory controller 11 and one of memory devices 110 and 120, and may receive or transmit a DQS signal (or a data strobe signal). Here, "DQS" may refer to a data strobe. The DQS buffer 1302 may include a receiver 1303 and a transmitter 1306. The receiver 1303 may receive the DQS signal, amplify the received DQS signal, and generate an internal DQS signal IDQS. The DQS signal received by the receiver 1303 may correspond to a write DQS signal. The receiver 1303 may also receive a complementary DQS signal DQSb via a complementary DQS pin connected to another path of the DQ bus.

[0046] The write leveling circuit 1304 can perform training between the clock signal CK and the DQS signal DQS using position information LI. As used herein, "training between" includes aligning the internal DQS signal with the internal clock as described below. The write leveling circuit 1304 can align the internal DQS signal IDQS with the internal clock signal ICK by adjusting the delay amount of the internal DQS signal IDQS using the position information LI. The internal DQS signal IDQS, output by receiver 1303 and adjusted by write leveling circuit 1304, can be used to sample the write data included in the DQ signal DQ[B:0].

[0047] Under the control of command decoder 1209, DQS signal generator 1305 can generate and output a DQS signal from the internal clock signal ICK. Transmitter 1306 can send and output the DQS signal generated by DQS signal generator 1305 to memory controller 11 via pin 1301 and the DQ bus. The DQS signal generated by DQS signal generator 1305 and output by transmitter 1306 can correspond to the read DQS signal. DQS signal generator 1305 may include a delay-locked loop (DLL) that fixes or adjusts the delay between internal clock signal ICK and DQS signal. Delay-locked loop DLL may include one or more delay circuits. Delay-locked loop DLL can align DQS signal with internal clock signal ICK by using position information LI to delay internal clock signal ICK, DQS signal, or internal signal from one or more internal delay circuits.

[0048] Memory device 1000 may further include a DQ pin 1401, a voltage generator 1402, a DQ buffer 1403, an equalizer 1405, a deserializer 1406, a serializer 1407, a pre-emphasis circuit 1409, and a calibration logic circuit 1410. The DQ pin 1401 may be connected to a path on the DQ bus between memory controller 11 and one of memory devices 110 and 120, and may receive or transmit the DQ signal DQ[B:0], respectively. As mentioned above, "DQ" may refer to data input / output. The voltage generator 1402 may generate a reference voltage VREFDQ and may provide the reference voltage VREFDQ to the receiver 1404 of the DQ buffer 1403.

[0049] DQ buffer 1403 may include receiver 1404 and transmitter 1408. Receiver 1404 may receive DQ signal DQ[B:0] via DQ pin 1401. Receiver 1404 may compare the voltage level of DQ signal DQ[B:0] with the level of reference voltage VREFDQ. For example, reference voltage VREFDQ may be an internal voltage used to determine the voltage level of DQ signal DQ[B:0] corresponding to a logic value, and may be the same as or different from reference voltage VREFCA. Receiver 1404 may amplify DQ signal DQ[B:0] based on reference voltage VREFDQ and may provide write DQ signal WDQ[B:0] to deserializer 1406.

[0050] Equalizer 1405 can compensate for and recover the high-frequency components of the DQ signal DQ[B:0] input to receiver 1404 via the DQ bus and DQ pin 1401, respectively. When the DQ signal DQ[B:0] is transmitted at high speed via the DQ bus, the high-frequency components of the DQ signal DQ[B:0] on receiver 1404 may be attenuated due to the limited bandwidth of the DQ bus. For example, the operation of equalizer 1405 can be similar to that of equalizer 1207.

[0051] Under the control of command decoder 1209, deserializer 1406 can sample the logic value of the written DQ signal WDQ[B:0] at the edge of the internal DQS signal IDQS, parallelize the sampled logic values, generate write data WDATA, and output the write data WDATA to write driver 1104. Figure 6In this process, the DQS signal is provided to 1406. Serializer 1407, under the control of command decoder 1209, can receive read data RDATA from the input / output sense amplifier 1105 of memory bank 1100. Serializer 1407 can serialize the read data RDATA and generate a read DQ signal RDQ[B:0]. Serializer 1407 can align the read DQ signal RDQ[B:0] with the DQS signal generated by DQS signal generator 1305. Figure 6 In this process, the DQS signal is provided to the serializer 1407.

[0052] Transmitter 1408 can send or output the read DQ signal RDQ[B:0] generated by serializer 1407 as the DQ signal DQ[B:0] to memory controller 11 via DQ pin 1401 and the DQ bus. Transmitter 1408 can drive the transmission paths of the DQ bus connected to DQ pin 1401 respectively, depending on the logic value of the read DQ signal RDQ[B:0]. Pre-emphasis circuit 1409 can perform pre-emphasis operation on the read DQ signal RDQ[B:0] generated by serializer 1407. Even when the DQ signal DQ[B:0] is transmitted at high speed from transmitter 1408 to memory controller 11 via the DQ bus, the high-frequency components of the DQ signal DQ[B:0] on memory controller 11 may be weakened due to the limited bandwidth of the DQ bus. The pre-emphasis circuit 1409 can pre-distort the DQ signal DQ[B:0] by amplifying the high-frequency components of the read DQ signal RDQ[B:0], and can compensate for the high-frequency components of the DQ signal DQ[B:0] on the memory controller 11. For example, the pre-emphasis circuit 1409 can perform the pre-emphasis operation using two methods: pre-shot and de-emphasis.

[0053] The calibration logic circuit 1410 can adjust the equalizer 1405 separately using the position information LI. The calibration logic circuit 1410 can adjust the equalizer 1405 differently depending on whether the position of the memory device 1000 on the bus 130 indicated by the position information LI is relatively close to or relatively far from the memory controller 11. The calibration logic circuit 1410 can also adjust the pre-emphasis circuit 1409 using the position information LI, i.e., the pre-emphasis circuit 1409 amplifies the degree to which the read DQ signal RDQ[B:0] is amplified. The calibration logic circuit 1410 can adjust the pre-emphasis circuit 1409 differently depending on whether the position of the memory device 1000 on the bus 130 indicated by the position information LI is relatively close to or relatively far from the memory controller 11.

[0054] The calibration logic circuit 1410 can perform training between the DQ signal DQ[B:0] and the DQS signal DQS using position information LI. As used herein, “training between” includes adjusting the delay amount of the internal DQS signal as described below. For example, the calibration logic circuit 1410 can adjust the delay amount of the internal DQS signal IDQS to be provided to the deserializer 1406 using the position information LI. The memory device 1000 may also include delay circuitry that delays the internal DQS signal IDQS under the control of the calibration logic circuit 1410. The calibration logic circuit 1410 can control the deserializer 1406 using the position information LI, and the deserializer 1406 can align the written DQ signal WDQ[B:0] with the internal DQS signal IDQS under the control of the calibration logic circuit 1410. The calibration logic circuit 1410 can control the serializer 1407 using position information LI, and under the control of the calibration logic circuit 1410, it can align the read DQ signal RDQ[B:0] with the DQS signal generated by the DQS signal generator 1305. The calibration logic circuit 1410 can also perform training between write DQ signals WDQ[B:0] using position information LI. As used herein, “training between” includes compensating for skew in the write DQ signal as described below. The calibration logic circuit 1410 can reduce, eliminate, or compensate for skew in the write DQ signal WDQ[B:0] due to the skew of pin 1401 by different delays in the write DQ signal WDQ[B:0], and can align the write DQ signal WDQ[B:0] with the internal DQS signal IDQS. The calibration logic circuit 1410 can perform training between read DQ signals RDQ[B:0] using position information LI. As used herein, “training between” includes compensating for skew in the write DQS signal as described below. The calibration logic circuit 1410 can reduce, eliminate, or compensate for the skewness of the DQS signal DQS[B:0] caused by the skewness of pin 1401 by reading the DQS signal RDQS[B:0] with different delays.

[0055] Voltage generator 1402 can adjust the level of reference voltage VREFDQ using location information LI. For example, voltage generator 1402 can adjust the level of reference voltage VREFDQ differently depending on whether the location information LI indicates that the memory device 1000 on bus 130 is relatively close to or relatively far from memory controller 11.

[0056] The memory device 1000 may also include pin 1501, ZQ calibration logic circuitry 1502, and ODT circuitry 1503 to 1505. Pin 1501 may be connected to an external resistor RZQ located outside the memory device 1000. The external resistor RZQ may be a passive component unaffected by PVT (process, voltage, temperature) variations of the memory device 1000. For example, the external resistor RZQ may have a resistance value of 240Ω, and a tolerance of + / -1% may be allowed for the external resistor RZQ. The ZQ calibration logic circuitry 1502 can generate and output the code ZQCODE by performing a calibration operation based on the external resistor RZQ.

[0057] ODT circuit 1503 can provide ODT resistance values ​​to DQ pin 1401 based on code ZQCODE. ODT circuit 1504 can provide ODT resistance values ​​to DQ pin 1301 based on code ZQCODE. ODT circuit 1505 can provide ODT resistance values ​​to CA pin 1204 based on code ZQCODE. For example, each of the ODT resistance values ​​provided to DQ pin 1401, DQS pin 1301, and CA pin 1204 can be, for example, RZQ / n (e.g., 240Ω, 120Ω, 80Ω, 60Ω, 48Ω, 40Ω, or 34Ω) (n is a natural number). The ODT resistance values ​​provided to DQ pin 1401, DQS pin 1301, and CA pin 1204 can be the same or different. Here, "n" can be determined differently depending on the data stored in mode register 1210 according to the mode register write command MRW from memory controller 11.

[0058] The memory device 1000 may further include a temperature sensor 1701 and a refresh controller 1702. The temperature sensor 1701 can sense the temperature of the memory device 1000 under the control of the refresh controller 1702 and can provide temperature information to the refresh controller 1702. The refresh controller 1702 can adjust the update cycle of the temperature sensor 1701 (i.e., the cycle in which the temperature sensor 1701 senses the temperature) using the position information LI. The refresh controller 1702 can adjust the refresh cycle associated with the memory cell array 1101 based on the temperature information. The refresh controller 1702 may include a counter circuit that generates a row address indicating the word line connected to the memory cell to be refreshed under the control of the command decoder 1209. The fuse array 1800 may include a plurality of anti-fuses. The fuse array 1800 may include anti-fuses in which the logic value of the position information LI(③) is programmed. The anti-fuses may be damaged by electrical signals. The anti-fuses may be changed from a high-resistance state to a low-resistance state by electrical signals. Antifuses can be non-volatile and can be one-time programmable (OTP) memory.

[0059] Voltage generator 1900 can generate various internal voltages IV to be supplied to memory bank 1100 using the power supply voltage of memory device 1000. For example, internal voltages IV may include word line enable voltage, word line disable voltage, column select line enable voltage, precharge voltage, etc. Voltage generator 1900 can adjust at least one or more levels of internal voltages IV using location information LI. For example, the location information LI provided to voltage generator 1900 can be the same as the location information LI provided to voltage generators 1205 and 1402 and calibration logic circuits 1211 and 1410. In this case, the location information LI may indicate the power management integrated circuit (PMIC) (see reference LI) described later. Figure 13The distance of the power path (1310) supplying power voltage to memory device 1000, and the distance of bus 130 between memory device 1000 and memory controller 11. As the distance between memory device 1000 and PMIC increases, the power integrity (PI) of the operating voltage supplied to memory device 1000 may decrease. The voltage generators 1205 and 1402 described above may be included in voltage generator 1900. For another example, the location information LI provided to voltage generator 1900 may be different from the location information LI provided to voltage generators 1205 and 1402 and calibration logic circuits 1211 and 1410. The location information LI provided to voltage generators 1205 and 1402 and calibration logic circuits 1211 and 1410 may indicate the distance of bus 130 between memory device 1000 and memory controller 11. The location information LI provided to voltage generator 1900 may indicate the distance between memory device 1000 and PMIC. Location information LI can be provided to voltage generator 1900 via pin 1600 or any other pin, or it can be provided to voltage generator 1900 from fuse array 1800. In either case, location information LI1 can indicate the distance of bus 130 between memory device 1000 and memory controller 11, or the distance between memory device 1000 and PMIC.

[0060] Figure 7 Detailed illustration Figure 6 The receiver and equalizer of the memory device. Receiver 1206 can be a receiver that receives the CA signal CA[0]. Figure 6An example of receiver 1206. Receiver 1206 may include transistors M1 and M2, resistors R1 and R2, and a current source CS1. Receiver 1206 can compare a CA signal CA[0] with a reference voltage VREFCA, can amplify the voltage difference between the CA signal CA[0] and the reference voltage VREFCA, and can generate internal CA signals ICA[0] and ICAB[0] at nodes n1 and n2. Transistor M1 can receive the CA signal CA[0] through its gate terminal. The source terminal of transistor M1 can be connected to the current source CS1, and the drain terminal of transistor M1 can be connected to node n1 and resistor R1. Transistor M2 can receive the reference voltage VREFCA through its gate terminal. The source terminal of transistor M2 can be connected to the current source CS1, and the drain terminal of transistor M2 can be connected to node n2 and resistor R2. Current source CS1 can generate a bias current flowing through transistors M1 and M2. The gain of receiver 1206 may vary depending on the magnitude of the bias current. Receiver 1206 can also be referred to as a "variable gain amplifier (VGA)". For example, calibration logic circuit 1211 can adjust the gain of receiver 1206 by adjusting the amplitude of the bias current depending on the location information LI. Current source CS1 can be implemented using a transistor having a gate terminal configured to receive the bias voltage, a drain terminal connected to transistors M1 and M2, and a source terminal connected to ground voltage GND. Resistor R1 can be connected between the power supply voltage VDDQ and the drain terminal of transistor M1. Resistor R2 can be connected between the power supply voltage VDDQ and the drain terminal of transistor M2. Each of resistors R1 and R2 can be implemented using passive components or transistors. For example, except that different signals are input to the gate terminals of transistors M1 and M2, Figure 6 The remaining receivers 1206, 1303 and 1404 can be implemented as substantially the same as receiver 1206.

[0061] Equalizer 1207 may be connected to receiver 1206 that receives CA signal CA[0]. Figure 6An example of equalizer 1207. Equalizer 1207 may include transistors M3 and M4, resistor R3, capacitor C3, and current sources CS2 and CS3. The drain terminal of transistor M3 and the gate terminal of transistor M4 may be connected to node n1. The gate terminal of transistor M3 and the drain terminal of transistor M4 may be connected to node n2. The source terminal of transistor M3 may be connected to current source CS2, a first terminal of resistor R3, and a first terminal of capacitor C3. The source terminal of transistor M4 may be connected to current source CS3, a second terminal of resistor R3, and a second terminal of capacitor C3. Transistors M3 and M4 may form a cross-coupled pair. Current source CS2 may generate a bias current flowing through transistor M3. Current source CS3 may generate a bias current flowing through transistor M4. Each of current sources CS2 and CS3 may be implemented using a transistor having a gate terminal configured to receive a bias voltage, a drain terminal connected to a corresponding one of transistors M3 and M4, and a source terminal connected to ground voltage GND. Equalizer 1207 can be a high-pass filter that boosts the high-frequency components of the internal CA signals ICA[0] and ICAB[0]. Transistors M3 and M4 can amplify the internal CA signals ICA[0] and ICAB[0] in a positive feedback manner. Equalizer 1207 can provide negative impedance or negative capacitance to nodes n1 and n2. Equalizer 1207 can be a negative capacitance equalizer (NCE) or a continuous time linear equalizer (CTLE). Calibration logic circuit 1211 can adjust the degree to which equalizer 1207 amplifies the internal CA signals ICA[0] and ICAB[0], i.e., the strength (or intensity) of equalizer 1207, by adjusting the magnitude of the bias current of current sources CS2 and CS3 depending on the position information LI. Figure 6 The remaining equalizer 1207 can be implemented in a manner that is essentially the same as equalizer 1207. Figure 7 Transistors can be implemented using n-channel metal oxide semiconductor field effect (NMOS) transistors, p-channel metal oxide semiconductor field effect (PMOS) transistors, or a combination of NMOS and PMOS transistors.

[0062] Figure 8 Detailed illustration Figure 6The receiver and equalizer of the memory device. Receiver 1404 can be a receiver that receives the DQ signal DQ[0]. Figure 6 Example of receiver 1404. In addition to the DQ signal DQ[0] and reference voltage VREFDQ being input to the gate terminals of transistors M1 and M2 respectively, receiver 1404 can be implemented as... Figure 7 The receiver 1206 is essentially the same. The receiver 1404, which receives the remaining DQ signal DQ[B:1], can be implemented in a manner essentially the same as receiver 1206. The calibration logic circuit 1410 can adjust the gain of receiver 1404 by adjusting the magnitude of the bias current depending on the position information LI1.

[0063] Equalizer 1405 may be connected to receiver 1404 that receives DQ signal DQ[0]. Figure 6 An example of equalizer 1405. For example, equalizer 1405 may be a decision feedback equalizer (DFE). Equalizer 1405 may include flip-flops 1405_1 and 1405_3, multipliers 1405_2 and 1405_4, and adder 1405_5. Flip-flops 1405_1 and multiplier 1405_2 may form a tap, and flip-flops 1405_3 and multiplier 1405_4 may form another tap. Flip-flops 1405_1 may sample the logic value written to the DQ signal WDQ[0] at the edge of the internal DQS signal IDQS, and flip-flops 1405_3 may sample the output value of flip-flops 1405_1 at the edge of the internal DQS signal IDQS. Multiplier 1405_2 may multiply the output value of flip-flops 1405_1 by the attenuation coefficient α1. Multiplier 1405_4 can multiply the output value of flip-flop 1405_3 by the attenuation coefficient α2. Adder 1405_5 can add the output of receiver 1404 to the outputs of multipliers 1405_2 and 1405_4, and can generate the write DQ signal WDQ[0]. Equalizer 1405 can reduce the ISI of the write DQ signal WDQ[0] currently sampled by receiver 1404 by using the DQ signal(s) DQ[0] previously sampled by receiver 1404.

[0064] The number of taps and the value of the decay coefficient can be updated based on training or calibration.

[0065] Depending on the location information LI, the calibration logic circuit 1410 can adjust the number of taps in the equalizer 1405, or it can adjust the attenuation coefficients α1 and α2. This is associated with the written DQ signal WDQ[B:1]. Figure 6 The remaining equalizer 1405 can be implemented in a manner that is essentially the same as equalizer 1405.

[0066] Figure 7 The equalizer 1207 is described as being associated with the CA signal CA[A:0]. Figure 6 An example of equalizer 1207, but it can be associated with the DQ signal DQ[B:0]. Figure 6 An example of the equalizer 1405. Additionally, Figure 8 The equalizer 1405 is described as being associated with the DQ signal DQ[B:0]. Figure 6 An example of equalizer 1405, but it can be associated with the CA signal CA[A:0]. Figure 6 Example of equalizer 1207.

[0067] Figure 9 Detailed illustration Figure 6 The serializer and transmitter of the memory device. The transmitter 1408 can be a receiver for reading the DQ signal RDQ[0]. Figure 6 An example of a transmitter 1408. Transmitter 1408 may be referred to as the “master driver” and may include pull-up units 1408_1 and pull-down units 1408_2. Depending on the read data serialized by serializer 1407, pull-up unit 1408_1 can drive the DQ signal DQ[0] with a voltage level corresponding to a second logic value (e.g., high). Depending on the read data serialized by serializer 1407, pull-down unit 1408_2 can drive the DQ signal DQ[0] with a voltage level corresponding to a first logic value (e.g., low). Depending on the position information LI, calibration logic circuit 1410 can adjust the number of pull-up units 1408_1 or the number of pull-down units 1408_2. Calibration logic circuit 1410 can adjust the drive capability of each of the pull-up units 1408_1 or the drive capability of each of the pull-down units 1408_2. Associated with the read DQ signal RDQ[B:1] Figure 6 The remaining transmitter 1408 can be implemented in a manner that is essentially the same as transmitter 1408.

[0068] The pre-emphasis circuit 1409 may be connected to the transmitter 1408 that receives and reads the DQ signal RDQ[0]. Figure 6An example of a pre-emphasis circuit 1409. The pre-emphasis circuit 1409 may include pull-up units 1409_1 and pull-down units 1409_2. When the logic value of the read data serialized by the serializer 1407 changes, the pull-up unit 1409_1 can drive the DQ signal DQ[0] with a voltage level corresponding to the second logic value, and the pull-down unit 1409_2 can drive the DQ signal DQ[0] with a voltage level corresponding to the first logic value. Depending on the position information LI, the calibration logic circuit 1410 can adjust the number of pull-up units 1409_1 or the number of pull-down units 1409_2. The calibration logic circuit 1410 can adjust the drive capability of each of the pull-up units 1409_1 or the drive capability of each of the pull-down units 1409_2. For example, the drive capability associated with the read DQ signal RDQ[B:1]. Figure 6 The remaining transmitter 1408 can be implemented as with Figure 9 The transmitter 1408 is essentially the same. It is associated with reading the DQ signal RDQ[B:1. Figure 6 The remaining pre-emphasis circuit 1409 can be implemented in a manner that is essentially the same as the pre-emphasis circuit 1409.

[0069] Figure 10 , Figure 11 and Figure 12 A block diagram of a memory module according to an example embodiment is shown. Memory modules 2000a to 2000c may be dual in-line memory modules (DIMMs) conforming to JEDEC (Joint Electron Device Engineering Council) standards. For example, memory module 2000a may be an unbuffered DIMM (UDIMM), memory module 2000b may be a registered DIMM (RDIMM), and memory module 2000c may be a load-reduced DIMM (LRDIMM). The memory module according to the example embodiment may be implemented using a fully buffered DIMM (FB-DIMM), a small outline DIMM (SO-DIMM), or any other memory module (e.g., a single in-line memory module (SIMM)) as well as the examples described above.

[0070] The memory module 2000a may include pins 2101 and 2201, a CA bus 2102, a DQ bus 2202, and memory devices MD1 to MD8. Each of the memory devices MD1 to MD8 can interact with... Figure 6 The memory devices are basically the same as those in the 1000 series.

[0071] Pin 2101 may include a clock pin and a CA pin for receiving clock signal CK and CA signal CA from memory controller 11, respectively. CA bus 2102 may include a transmission path that physically and electrically connects pin 2101 of memory module 2000a to pins 1201 and 1204 of each of memory devices MD1 to MD8. CA bus 2102 may correspond to bus 130. For example, refer to... Figure 6 The described location information LI can indicate the location of each of the memory devices MD1 to MD8 on the CA bus 2102 relative to pin 2101. Pin 2201 may include DQ pins and DQS pins for receiving (writing) DQ signals DQ and (writing) DQS signals DQS from the memory controller 11 or for receiving (reading) DQ signals DQ and (reading) DQS signals DQS from memory devices MD1 to MD8. The DQ bus 2202 may include a transmission path that physically and electrically connects pin 2201 of the memory module 2000a to pins 1401 and 1301 of the memory devices MD1 to MD8. As described above, the CA bus 2102 may be shared by memory devices MD1 to MD8, but the DQ bus 2202 may be provided to correspond to memory devices MD1 to MD8 respectively and may not be shared by memory devices MD1 to MD8.

[0072] Compared to memory module 2000a, memory module 2000b may further include a register clock driver RCD and a memory device MD9. CA bus 2102a may include a transmission path that physically and electrically connects the register clock driver RCD to pins 1201 and 1204 of each of memory devices MD1 to MD5. CA bus 2102b may include a transmission path that physically and electrically connects the register clock driver RCD to pins 1201 and 1204 of each of memory devices MD6 to MD9. The register clock driver RCD can receive clock signal CK and CA signal CA through pin 2101. The register clock driver RCD can send the received clock signal CK and received CA signal CA to memory devices MD1 to MD5 via CA bus 2102a, and send the received clock signal CK and received CA signal CA to memory devices MD6 to MD9 via CA bus 2102b. The register clock driver RCD may buffer the clock signal CK and CA signal CA. (Reference) Figure 6The described location information LI can indicate the location of each of the memory devices MD1 to MD5 on CA bus 2102a relative to the register clock driver RCD, or it can indicate the location of each of the memory devices MD6 to MD9 on CA bus 2102b relative to the register clock driver RCD.

[0073] Compared to memory module 2000b, memory module 2000c may further include memory devices MD1a to MD5a, MD1c to MD5c, MD6b to MD9b, and MD6d to MD9d, as well as data buffers DB1 to DB9. CA bus 2102a may include a transmission path that physically and electrically connects the register clock driver RCD to pins 1201 and 1204 of each of the memory devices MD1a to MD5a. CA bus 2102b may include a transmission path that physically and electrically connects the register clock driver RCD to pins 1201 and 1204 of each of the memory devices MD6b to MD9b. CA bus 2102c may include a transmission path that physically and electrically connects the register clock driver RCD to pins 1201 and 1204 of each of the memory devices MD1c to MD5c. CA bus 2102d may include a transmission path that physically and electrically connects the register clock driver RCD to pins 1201 and 1204 of each of the memory devices MD6d to MD9d. The register clock driver RCD can receive clock signal CK and CA signal CA via pin 2101. The RCD can transmit the received clock signal CK and CA signal CA to memory devices MD1a to MD5a via CA bus 2102a, to memory devices MD6b to MD9b via CA bus 2102b, to memory devices MD1c to MD5c via CA bus 2102c, and to memory devices MD6d to MD9d via CA bus 2102d. (Reference) Figure 6The described location information LI can indicate the position of each of the memory devices MD1a to MD5a on CA bus 2102a relative to the register clock driver RCD, the position of each of the memory devices MD6b to MD9b on CA bus 2102b relative to the register clock driver RCD, the position of each of the memory devices MD1c to MD5c on CA bus 2102c relative to the register clock driver RCD, or the position of each of the memory devices MD6d to MD9d on CA bus 2102d relative to the register clock driver RCD. Data buffer DB1 can be configured on the DQ bus 2202 between memory devices MD1a and MD1c and memory controller 11. Data buffer DB1 can be physically and electrically connected to pins 1301 and 1401 of each of memory devices MD1a and MD1c, and can also be physically and electrically connected to pin 2201. Data buffer DB1 can buffer the DQ signal DQ and the DQS signal DQS associated with memory devices MD1a and MD1c. Data buffer DB1 can send the buffered DQ signal DQ and the buffered DQS signal DQS to memory devices MD1a and MD1c or memory controller 11. The remaining data buffers DB2 to DB9 can be implemented similarly to data buffer DB1. In the example embodiment, as an example, in... Figures 10 to 12 The diagram shows one surface of memory modules 2000a to 2000c, but memory devices, data buffers, etc., can be mounted on the opposite surface of memory modules 2000a to 2000c. For example, memory devices mounted on one surface of each of memory modules 2000a to 2000c can form a memory rank. Furthermore, the number of memory devices included in each of memory modules 2000a to 2000c is not limited to... Figures 10 to 12 The example shown.

[0074] Figure 13 A block diagram of a computing system according to an example embodiment is shown. The computing system 3000 may correspond to the computing system 10 described above and may include memory modules 3100_1 to 3100_4 and a host 3200. Memory modules 3100_1 to 3100_4 may correspond to memory modules 100 / 2000a / 2000b / 2000c. Memory module 3100_1 may include a plurality of memory devices 3110, an RCD 3120, and a PMIC 3130. Each of the memory devices 3110 may be connected to... Figure 6 The memory device 1000 is basically the same. The RCD 3120 can be compared with the reference... Figure 11 and Figure 12The described register clock driver RCD is substantially the same, capable of receiving CK and CA signals from host 3200 and transmitting the received CK and CA signals to multiple memory devices 3110. PMIC 3130 can provide power to internal components 3110 and 3120 in memory module 3100_1. Each of memory modules 3100_2 through 3100_4 can be substantially the same as memory module 3100_1. Memory modules 3100_1 and 3100_2 can be assigned to channel CH1. Memory modules 3100_3 and 3100_4 can be assigned to channel CH2. Channel CH1 can include input / output paths for memory modules 3100_1 and 3100_2, and channel CH2 can include input / output paths for memory modules 3100_3 and 3100_4. The number of channels CH1 and CH2, the number of memory devices 3110, the number of memory modules 3100_1 to 3100_4, and the number of memory modules per channel are exemplary. The host 3200 can be an application processor (AP) or a system-on-chip (SoC). The host 3200 may include a system bus 3240 connecting the processor 3210, the on-chip memory 3220, and the memory controllers 3231 and 3232. The processor 3210 can execute various software (e.g., applications, operating systems, file systems, and device drivers) loaded onto the on-chip memory 3220. The processor 3210 may include homogeneous multi-core or heterogeneous multi-core. For example, the processor 3210 may include at least one of a central processing unit (CPU), an image signal processing unit (ISP), a digital signal processing unit (DSP), a graphics processing unit (GPU), a vision processing unit (VPU), and a neural processing unit (NPU). Applications, operating systems, file systems, device drivers, etc., used to drive the computing system 3000 can be loaded onto the on-chip memory 3220. The on-chip memory 3220 can be an SRAM or register implemented within the host 3200 and has a faster data input / output speed than memory modules 3100_1 to 3100_4. The on-chip memory 3220 can be referred to as a "buffer memory." Memory controllers 3231 and 3232 can correspond to the aforementioned memory controller 11.Memory controller 3231 can access memory modules 3100_1 and 3100_2 through channel CH1 under the control of processor 3210. Memory controller 3232 can access memory modules 3100_3 and 3100_4 through channel CH2 under the control of processor 3210.

[0075] Figure 14 A block diagram of a computing system according to an example embodiment is shown. The computing system 4000 may correspond to the computing system 10 / 3000 described above, and may include a memory module 4100, a host 4200, and a system PMIC 4300. The memory module 4100 may include an RCD 4110, a PMIC 4120, and memory devices 4131 to 4133. The RCD 4110 may correspond to a reference... Figure 11 and Figure 12 The described register clock driver RCD and reference Figure 13 The described RCD 3120. The RCD 4110 may include channels (see reference). Figure 13CH1 and CH2 are CK input pins and CA input pins respectively that receive the CK signal CK and CA signal CA sent from the memory controller 4240. RCD 4110 may include CK output pins and CA output pins that output the CK signal and CA signal to memory devices 4131 to 4133 respectively. RCD 4110 may include a VDDQ pin that provides the power supply voltage VDDQ from PMIC 4120. PMIC 4120 may include VIN1 pins and VIN2 pins that provide the input voltages VIN1 and VIN2 from system PMIC 4300. PMIC 4120 can generate power supply voltages VDD, VDDQ, and VPP using power supply voltages VIN1 and VIN2, and can provide power supply voltages VDD, VDDQ, and VPP to memory devices 4131 to 4133, and can provide power supply voltage VDDQ to RCD 4110. Memory devices 4131 to 4133 and RCD 4110 may correspond to load devices of PMIC 4120. For example, the input voltage VIN1 can be 12V, the input voltage VIN2 can be 3.3V, the power supply voltage VDD can be 1.1V, the power supply voltage VDDQ can be 1.1V, and the power supply voltage VPP can be 1.8V, and the embodiments are not limited to the above values. For example, the power supply voltage VDDQ can be provided to components 1205, 1206, 1207, 1505, 1202, 1302, 1304, 1305, 1504, 1402, 1403, 1405, 1409, 1503, and 1502 of pins 1201, 1204, 1301, 1401, and 1501 of memory device 1000, the power supply voltage VDD can be provided to the remaining components of memory device 1000, and the power supply voltage VPP can be used to generate the word line enable voltage of memory cell array 1101. Each of memory devices 4131 to 4133 can be connected to... Figure 6 The memory devices 1000 are basically the same. The CK and CA pins of each of the memory devices 4131 to 4133 can correspond to... Figure 6 Pins 1201 and 1204. The CK and CA pins of each of memory devices 4131 to 4133, and the CK output pin and CA output pin of RCD 4110, can be physically and electrically connected to each other, and this connection can form a CA bus. The DQ and DQS pins of each of memory devices 4131 to 4133 can correspond to Figure 6 Pins 1401 and 1301. Each of the memory devices 4131 to 4133 may include a VDD pin, a VDDQ pin, and a VPP pin, which are supplied with power supply voltages VDD, VDDQ, and VPP from the PMIC 4120. Data buffers 4141 to 4143 may be implemented as... Figure 12 The data buffers DB1 through DB9 are substantially the same. In the example embodiment, each of the memory devices 4131 through 4133 may include an ODT pin. The ODT pin may correspond to... Figure 6 Pin 1600. The location of memory device 4131 on the CA bus may be farther from RCD 4110 or PMIC 4120 than memory devices 4132 and 4133. A V1 voltage (e.g., power supply voltage or ground voltage) can be applied to the ODT pin of memory device 4131. Conversely, the location of memory devices 4132 and 4133 on the CA bus may be closer to RCD 4110 or PMIC 4120 than memory device 4131. A V2 voltage (e.g., ground voltage or power supply voltage), different from the V1 voltage, can be applied to the ODT pin of memory devices 4132 and 4133. Figure 14 An example is shown where RCD 4110 and PMIC 4120 are adjacent to each other, but the embodiment is not limited to this. For example, RCD 4110 and PMIC 4120 may not be adjacent to each other. In any case, the voltage to be applied to the ODT pin of each of the memory devices 4131 / 4133 can be determined based on the signal transmission distance from RCD 4110 to each of the memory devices 4131 / 4132 / 4133, the voltage to be applied to the ODT pin of each of the memory devices 4131 / 4133 can be determined based on the power supply distance from PMIC 4120 to each of the memory devices 4131 / 4132 / 4133, or the voltage to be applied to the ODT pin of each of the memory devices 4131 / 4133 can be determined based on the distance from RCD 4110 or PMIC 4120 to each of the memory devices 4131 / 4132 / 4133. The memory device 4131 can use the V1 voltage input to the ODT pin as a reference. Figure 6 The location information LI described, or memory devices 4132 and 4133, can use the V2 voltage input to the ODT pin as a reference. Figure 6 The location information LI is described. Host 4200 may correspond to host 3200 as described above. Host 4200 may include processors 4210 and 4220, on-chip memory 4230, memory controller 4240, intellectual property (IP) block 4250, and system bus 4260. Each of processors 4210 and 4220 may correspond to... Figure 13Processor 3210. Processor 4210 may include cores 4211 to 4214 and a shared cache 4215. Each of cores 4211 to 4214 can fetch and decode instructions, perform various operations based on those instructions, and write or read data from data storage spaces 4215, 4230, and 4100. The shared cache 4215 may be shared by cores 4211 to 4214 and cores 4211 to 4214 may be interconnected. Processor 4220 may include cores 4221 to 4224 and a shared cache 4225, and the operation of processor 4220 may be similar to that of processor 4210. On-chip memory 4230 may correspond to... Figure 13 The on-chip memory 3220. Memory controller 4240 may correspond to memory controllers 3231 and 3232. Memory controller 4240 may include clock generator 4241, command and address generator 4242, command queue 4243, write data queue 4244, read data queue 4245, and data transceiver 4246. Clock generator 4241 can generate a clock signal CK and send the clock signal CK to memory module 4100. Command and address generator 4242 can receive commands or addresses from command queue 4243 and send a CA signal including the command or address to memory module 4100. Command queue 4243 can store commands and addresses generated by processors 4210 and 4220. Write data queue 4244 can receive and store write data to be stored in memory module 4100 from shared caches 4215 and 4225 or on-chip memory 4230. Read data queue 4245 can store read data sent from memory module 4100 via read commands from memory controller 4240. Read data queue 4245 can send read data to shared caches 4215 and 4225 or on-chip memory 4230. Data transceiver 4246 can send write data from write data queue 4244 to memory module 4100. Data transceiver 4246 can receive read data from memory module 4100 and can store the read data in read data queue 4245. For example, IP block 4250 may include various circuits such as multimedia controller, display controller, temperature sensor, input / output device, and clock management circuitry. System bus 4260 can interconnect the aforementioned components 4210 to 4250 in host 4200. In an example embodiment, memory controller 4240 can issue a mode register read command MRR and can read mode register 1210 (see reference) stored in memory devices 4131 to 4133. Figure 6The CA ODT band value in the memory controller 4240 is as follows: Since voltages V1 and V2 are applied to the ODT pins of memory devices 4131 to 4133 respectively, the first CA ODT band value of memory device 4131 based on voltage V1 and the second CA ODT band value of each of memory devices 4132 and 4133 based on voltage V2 can be different. The memory controller 4240 can classify memory device 4131 with the first CA ODT band value into group B, and can classify memory devices 4132 and 4133 with the second CA ODT band value into group A. The number of memory devices included in memory module 4100 and the number of memory device groups classified by memory controller 4240 are not limited to this. Figure 14 The example shown. Memory controller 4240 can activate the CA pin 1204 (reference) of memory device 4131 belonging to group B by issuing the mode register write command MRW. Figure 6 The ODT value of each of the following is set to ODT1 (e.g., RZQ / X) (where X is a natural number). The memory controller 4240 can set the CA pin 1204 (reference) of memory devices 4132 and 4133 belonging to group A to ODT1 by issuing the mode register write command MRW. Figure 6 The ODT value of each of the following is set to ODT2 (e.g., RZQ / Y) (where Y is a natural number different from X). Furthermore, the memory controller 4240 can set the CA pin 1204 of the memory device 4133 (reference) by issuing the mode register write command MRW. Figure 6 The ODT value of each of the following is set to the open state (i.e., infinity). For example, to set the ODT values ​​of the CA pins of memory devices 4131 to 4133 differently, memory controller 4240 can allow memory devices 4131 to 4133 to enter PDA mode. System PMIC 4300 can provide power supply voltages to host 4200. System PMIC 4300 can provide power supply voltages VIN1 and VIN2 to memory module 4100. The power supply voltages VIN1 and VIN2 provided by system PMIC 4300 are not directly provided to memory devices 4131 to 4133. Instead, PMIC 4120 can generate power supply voltages VDD, VDDQ, and VPP using power supply voltages VIN1 and VIN2, and can provide power supply voltages VDD, VDDQ, and VPP to memory devices 4131 to 4143, and can provide power supply voltage VDDQ to RCD 4110.

[0076] The memory device according to one or more example embodiments can identify its own position on the bus in the memory module to perform self-calibration, so that the memory device can operate appropriately even under operating conditions that vary depending on its position in the memory module.

[0077] Although exemplary embodiments have been described, it will be apparent to those skilled in the art that various changes and modifications can be made to the exemplary embodiments without departing from the spirit and scope of this disclosure as set forth in the appended claims.

Claims

1. A memory device for a memory module, the memory device comprising: The command / address CA buffer is configured to receive CA signals via a bus shared by a second memory device that is different from the memory module. as well as The calibration logic circuit is configured to identify the location information of the memory device on the bus. The location information indicates the distance from the pin of the memory device through which the memory module receives the CA signal to the CA buffer.

2. The memory device of claim 1, wherein the calibration logic circuit is further configured to identify the location information of the memory device by checking the voltage level of the pin of the memory device, the terminal ODT band value on the CA die of the first mode register of the memory device, the identification ID information of the second mode register of the memory device, or the information of the fuse array of the memory device.

3. The memory device according to claim 1, wherein, The calibration logic circuit is also configured to perform a calibration operation on the memory device using the location information.

4. The memory device of claim 3, further comprising an equalizer configured to compensate for the CA signal received by the CA buffer via the bus. The calibration logic circuitry is further configured to adjust the equalizer based on the location information.

5. The memory device of claim 3, further comprising a clock buffer configured to receive a clock signal via the bus. The calibration logic circuit is further configured to sample the CA signal using an adjusted version of the clock signal based on the position information.

6. The memory device according to claim 3, wherein, The CA buffer is a first CA buffer, and the CA signal is a first CA signal. The memory device further includes a second CA buffer, configured to receive a second CA signal via the bus, and The calibration logic circuit is further configured as follows: Based on the location information, perform the first sampling of the first CA signal, and Based on the location information, a second sampling of the second CA signal is performed.

7. The memory device according to claim 3, further comprising: Equalizer; as well as A data input / output buffer includes a receiver and a transmitter, wherein the receiver is configured to receive a data input signal and the transmitter is configured to transmit a data output signal. The calibration logic circuit is further configured as follows: Adjust the equalizer based on the location information; and The pre-emphasis circuit of the transmitter is adjusted based on the location information.

8. The memory device according to claim 3, further comprising: A clock buffer is configured to receive a clock signal via the bus; The data strobe buffer is configured to receive or transmit data strobe signals; as well as The write leveling circuit is configured to adjust the data strobe signal relative to the clock signal based on the position information.

9. The memory device according to claim 3, further comprising: The data strobe buffer is configured to receive or transmit data strobe signals; as well as Data input / output buffers are configured to receive or transmit data input / output signals. The calibration logic circuit is further configured to adjust the timing of the clock edge of the data strobe signal relative to the data input / output signal based on the position information.

10. The memory device of claim 3, further comprising: The first data input / output buffer is configured to receive or transmit a first data input / output signal; as well as The second data input / output buffer is configured to receive or transmit a second data input / output signal. The calibration logic circuit is further configured as follows: Based on the location information, perform the first sampling of the first data input / output signal, and Based on the location information, perform a second sampling of the second data input / output signal.

11. The memory device of claim 3, further comprising: A temperature sensor, configured to sense temperature; as well as A refresh controller is configured to adjust the update cycle of the temperature sensor based on the location information.

12. The memory device of claim 3, further comprising: The data input / output buffer is configured to receive or transmit data input / output signals; Memory cell array; as well as The voltage generator is configured as follows: Generate at least one of the following voltages: a first voltage to be provided to the CA buffer, a second voltage to be provided to the data input / output buffer, or a third voltage to be provided to the memory cell array. The level of the at least one voltage is adjusted by using the location information.

13. The memory device of claim 3, further comprising: A clock buffer is configured to receive a clock signal via the bus; The data strobe buffer is configured to receive or transmit data strobe signals; as well as The delay-locked loop (DLL) is configured to adjust the delay between the clock signal and the data strobe signal based on the location information.

14. A memory device for a memory module, the memory device comprising: The command / address CA buffer is configured to receive CA signals via a bus shared by a second memory device that is different from the memory module. An equalizer is configured to compensate for the CA signal received by the CA buffer via the bus; as well as The calibration logic circuit is configured as follows: Identify the location information of the memory device, wherein the location information indicates the distance from the pin of the memory device through which the memory module receives the CA signal to the CA buffer, and The equalizer is adjusted based on the location information.

15. The memory device of claim 14, further comprising: The command decoder is configured to decode the first command from the CA buffer; as well as The mode register is configured to store the location information.

16. The memory device according to claim 15, wherein, The command decoder is configured as follows: Decoding mode register write command, Based on the decoding of the mode register write command, the position information is written into the mode register. Decoding mode register read command, and Based on the decoding of the mode register read command, the position information of the mode register is read.

17. A memory module, comprising: First memory device; as well as A second memory device that shares a bus with the first memory device. The first memory device includes: A first command / address CA buffer is configured to receive CA signals via the bus; and A first calibration logic circuit is configured to identify first location information of the first memory device on the bus, wherein the first location information indicates a first distance from a first pin of the first memory device through which the memory module receives the CA signal to the first CA buffer, and The second memory device includes: The second CA buffer is configured to receive the CA signal via the bus, and A second calibration logic circuit is configured to identify second location information of the second memory device on the bus, wherein the second location information indicates a second distance from a second pin of the second memory device through which the memory module receives the CA signal to the second CA buffer.

18. The memory module of claim 17, wherein the first memory device further comprises a first equalizer configured to compensate for the CA signal received by the first CA buffer via the bus. The second memory device further includes a second equalizer configured to compensate for the CA signal received by the second CA buffer via the bus. in, The first calibration logic circuit is further configured to adjust the first attenuation coefficient of the first equalizer based on the first position information, and The second calibration logic circuit is further configured to adjust the second attenuation coefficient of the second equalizer based on the second position information.

19. The memory module according to claim 17, wherein, When the first location information and the second location information are the same, the termination ODT value on the first die of the first CA buffer and the second ODT value of the second CA buffer are the same, and Wherein, when the first location information and the second location information are different, the first ODT value of the first CA buffer and the second ODT value of the second CA buffer are different.

20. The memory module according to claim 17, further comprising: A register clock driver is configured to send the CA signal to the first CA buffer and the second CA buffer via the bus.

21. A system comprising: The host computer includes the processor and memory; First memory device; as well as The second memory device shares a bus with the first memory device and the host's memory controller. The first memory device includes: The first command / address CA buffer is configured to receive CA signals via the bus. A first calibration device is configured to identify first location information of the first memory device on the bus. The first die terminates the ODT resistor, and The first ZQ pin is used to detect the first ZQCODE value. And the second memory device includes: The second CA buffer is configured to receive the CA signal via the bus. The second calibration device is configured to identify second location information of the second memory device on the bus. The second die terminates the ODT resistor, and The second ZQ pin is used to detect the second ZQCODE value.

22. The system according to claim 21, wherein, The first memory device further includes a first position indication device associated with the first calibration device; and The second memory device further includes a second position indication device associated with the second calibration device.

23. The system according to claim 22, wherein, The first position indication device includes: a first package pin for sensing a first resistance of a first resistor mounted on a circuit board on which the first memory device is mounted; a first fuse array for programming a first identifier indicating the first position information; or a first register for storing a first data value indicating the first position information. The second position indication device includes: a second package pin for sensing a second resistance of a second resistor mounted on the circuit board; a second fuse array for programming a second identifier indicating the second position information; or a second register for storing a second data value indicating the second position information.

24. The system according to claim 23, wherein, The host is configured to execute instructions stored in the memory to: Read the first register to determine the first location information of the first memory device; Read the second register to determine the second location information of the second memory device; Based on the first location information, it communicates with the first memory device at a first input / output speed; as well as Based on the second location information, the host communicates with the second memory device at a second input / output speed, thereby improving effective first communication between the host and the first memory device, and improving effective second communication between the host and the second memory device.

25. A system comprising: The host computer includes the processor and memory; First memory device; as well as The second memory device shares a bus with the first memory device and the host's memory controller. The first memory device includes: The first command / address CA buffer is configured to receive CA signals via the bus, and A first calibration device is configured to identify first location information of the first memory device on the bus. The second memory device includes: The second CA buffer is configured to receive the CA signal via the bus, and The second calibration device is configured to identify second location information of the second memory device on the bus. The host is configured to execute instructions stored in the memory to: Read the first register to determine the first location information of the first memory device. Read the second register to determine the second location information of the second memory device. Based on the first location information, it communicates with the first memory device at a first input / output speed, and Based on the second location information, the host communicates with the second memory device at a second input / output speed, thereby improving effective first communication between the host and the first memory device, and improving effective second communication between the host and the second memory device.

Images