Low-Voltage Level Shifter for Integrated Circuits

Abstract

The present invention is titled "Low-Voltage Level Shifter for Integrated Circuits". An improved level shifter is disclosed. The level shifter can achieve switching times below 1 ns with a relatively low voltage for VDDL (such as 0.75V). The improved level shifter includes a coupling stage and a level conversion stage. A related level shifting method is also disclosed.

Description

Technical Field

[0001] The present invention discloses an improved level shifter capable of operating at high speed and low operating voltage. Background Art

[0002] A level shifter is an important component in an integrated circuit. The level shifter converts a digital signal from a first voltage domain to a second voltage domain, which is an essential function when different parts of the integrated circuit operate in different voltage domains.

[0003] Figure 1 Illustrates the conceptual operation of a level shifter 100 (including level shifters known in the prior art). In this example, in voltage domain 101 (V1), "1" is represented by 1V and "0" is represented by 0V, and in voltage domain 102 (V2), "1" is represented by 2.5V and "0" is represented by 0V. The level shifter 100 converts "1" (1V) from voltage domain 101 to "1" (2.5V) in voltage domain 102, and converts "0" (0V) from voltage domain 101 to "0" (0V) in voltage domain 102. Other voltage domains using other voltages to represent "1" and "0" are known, and those of ordinary skill in the art will understand that Figure 1 and the voltage values provided herein are merely examples.

[0004] Now reference will be made to Figures 2 - 4 describe an embodiment of the level shifter 100. First, Figure 2 Illustrates inverters 201 and 202, where inverter 201 receives INPUT as a signal and produces A as an output (which is the complement of INPUT), and inverter 202 receives A as an input and produces A-BAR as an output (which is the complement of A and logically the same as INPUT). Here, the "1" values of A and A-BAR will each have a voltage VDDL, which can be, for example, 1V. VDDL can be a low-voltage core power supply voltage.

[0005] Figure 3 Illustrates a prior art level shifter 300, which is an example of the level shifter 100. The level shifter 300 includes NMOS transistors 301 and 302, PMOS transistors 303 and 304, and an inverter 305. The signal A from Figure 2 is set to the gate of NMOS transistor 301, and the signal A-BAR from Figure 2 is set to the gate of NMOS transistor 302.

[0006] When A is at a high level, the NMOS transistor 301 will conduct, and the transistor 302 will be cut off. The input to the inverter 305 will be pulled to ground through the NMOS transistor 301, which will also turn on the gate of the PMOS transistor 304. The output of the inverter 305 labeled OUTPUT will be at a high level, which will be the voltage VDDH here. It can be, for example, 2.5V. VDDH can be the high-voltage core power supply voltage.

[0007] When A is at a low level, the NMOS transistor 301 will be cut off, and the NMOS transistor 302 will conduct. The PMOS transistor 303 will conduct because its gate will be pulled to ground through the NMOS transistor 302, which will pull up the input of the inverter 305 through the PMOS transistor 303. Then OUTPUT will be at a low level.

[0008] The prior art level shifter 300 has significant limitations. Specifically, the level shifter 300 cannot operate with a switching time less than about 0.5 ns. In the worst case, the switching time can be as high as 1 ns or longer. This is due to the inherent variability in the current driving capabilities of each transistor. Additionally, if the peak voltages of A and A - BAR are too low (i.e., not sufficient to fully turn on the NMOS transistors 301 and 302 respectively) due to the low supply voltage VDDL in Figure 2 being too low, then the level shifter 300 may fail completely.

[0009] Figure 4 Depicted is a prior art level shifter 400, which is another example of a level shifter 100 and has a shorter switching time than the level shifter 300. The level shifter 400 includes NMOS transistors 401 and 402; PMOS transistors 403, 404, 405, and 406; and an inverter 407. The signal A from Figure 2 is set to the gates of the NMOS transistor 401 and the PMOS transistor 405, and the signal A - BAR from Figure 2 is set to the gates of the NMOS transistor 402 and the PMOS transistor 406.

[0010] When A is at a high level, the NMOS transistor 401 will conduct, the transistor 402 will be cut off, the PMOS transistor 405 will be cut off, and the PMOS transistor 406 will conduct. The input to the inverter 407 will be pulled to ground through the NMOS transistor 401, which will also pull down the gate of the PMOS transistor 404, thus turning on the PMOS transistor 404, which in turn will raise the gate of the PMOS transistor 403 to VDDH through the PMOS transistors 404 and 406. The output of the inverter 407 labeled OUTPUT will be at a high level, which will be the voltage VDDH here, which can be, for example, 2.5V.

[0011] When A is at a low level, the NMOS transistor 401 will be cut off, the NMOS transistor 402 will conduct, the PMOS transistor 405 will conduct, and the PMOS transistor 406 will be cut off. The PMOS transistor 403 will conduct because its gate will be pulled to ground through the NMOS transistor 402, which will raise the input to the inverter 407 to VDDH through the PMOS transistors 403 and 405. Then OUTPUT will be at a low level.

[0012] Although the level shifter 400 has a faster switching time than the level shifter 300, the level shifter 400 is still limited. Specifically, it cannot reduce the switching time below 1 ns. In addition, if the peak voltages of A and A - BAR are too low due to Figure 2 the low supply voltage VDDL in being too low, the level shifter 400 may fail completely.

[0013] The applicant recently proposed an improved level shifter in the Chinese Patent Application No. 201910733363.9, titled "Improved Level Shifter for Integrated Circuits", filed on August 9, 2019. Now, reference will be made to Figures 5 - 7 describe this design.

[0014] Figure 5 The level shifter 500 is depicted, which includes a coupling stage 600 and a level shifting stage 700. When the level shifter 500 receives "0" as an input (where "0" is the first voltage), it outputs "0", i.e., the first voltage, and when it receives "1" (which is the second voltage) of the first voltage domain (VDDL) as an input, and it outputs "1" of the second voltage domain (VDDH), which is a third voltage different from the first voltage or the second voltage.

[0015] Figure 6Depicts a coupling stage 600, which includes a first circuit 621 and a second circuit 622. The two circuits are powered by a low-voltage power supply 610 that outputs a voltage VDDL. The first circuit 621 includes an NMOS transistor 602; PMOS transistors 604, 606, and 608; and a capacitor 610. The second circuit 622 includes an NMOS transistor 601; PMOS transistors 603, 605, and 607; and a capacitor 609. The signal A from Figure 2 is set to the gates of NMOS transistor 601, PMOS transistor 603, and PMOS transistor 608, and the signal A-BAR from Figure 2 is set to the gates of NMOS transistor 602, PMOS transistor 604, and PMOS transistor 607.

[0016] Now the operation of the first circuit 621 will be described. When A is high, A-BAR is low, and NMOS transistor 602 is cutoff, PMOS transistor 604 is conducting, and PMOS transistor 608 is cutoff. Since NMOS transistor 602 is cutoff and PMOS transistor 608 is cutoff, the voltage AA will be floating and will be approximately 0V in the initial state after startup because any residual charge on capacitor 610 will dissipate without any power supply.

[0017] When A switches from high to low, A-BAR will switch from low to high, NMOS transistor 602 will turn on, PMOS transistor 604 will turn off, and PMOS transistor 608 will turn on. PMOS transistor 606 will also turn on because its gate will be pulled to ground through NMOS transistor 602. Capacitor 610 will start to charge, and the node labeled AA will approach the voltage VDDL because PMOS transistors 606 and 608 are conducting, and thus the node AA is coupled to the power supply providing VDDL through the series connection of PMOS transistors 606 and 608. It has been described above that the source of NMOS transistor 602 is connected to ground, however, this is not meant to be limiting in any way, and within the scope, any return voltage related to VDDH can be utilized throughout the document in place of ground. The first voltage, which is "0" in the second voltage domain, is a voltage close to the return voltage.

[0018] When A then switches from low to high, A-BAR will switch from high to low. The NMOS transistor 602 will be turned off, the PMOS transistor 604 will be turned on, and the PMOS transistor 608 will be turned off because A is set as the gate of the PMOS transistor 608. The gate of the PMOS transistor 606 will be at the voltage of node AA (which will start at VDDL) and will be cut off. Since A drives the top plate of the capacitor 610 from low to high (which is VDDL), node AA will be driven by the capacitor 610 to 2*VDDL.

[0019] When A then switches from high to low, the PMOS transistor 608 will turn on, the NMOS transistor 602 will turn on, thereby pulling the gate of the PMOS transistor 606 to ground and turning on the PMOS transistor 606, which pulls node AA to the voltage VDDL. Thus, node AA changes from VDDL to 2*VDDL in response to A switching from low to high, and node AA changes from 2*VDDL to VDDL in response to A switching from high to low.

[0020] The operation of the second circuit 622 will now be described. When A is low, A-BAR will be high, the NMOS transistor 601 will be cut off, the PMOS transistor 603 will be conducting, and the PMOS transistor 607 will be cut off. Since the NMOS transistor 601 and the PMOS transistor 607 are cut off, the voltage AA-BAR will be floating and will be approximately 0V in the initial state after startup because any residual charge on the capacitor 609 will dissipate without any power supply.

[0021] When A switches from low to high, A-BAR will switch from high to low, the NMOS transistor 601 will turn on, the PMOS transistor 603 will turn off, and the PMOS transistor 607 will turn on. The PMOS transistor 605 will also turn on because its gate will be pulled to ground through the NMOS transistor 601. The bottom plate of the capacitor 609 will be pulled to VDDL through the PMOS transistors 607 and 605, and the node labeled AA-BAR will acquire the voltage VDDL.

[0022] Then when A switches from high level to low level, A-BAR will switch from low level to high level, NMOS transistor 601 will be turned off, PMOS transistor 603 will be turned on, and PMOS transistor 607 will be turned off. The gate of PMOS transistor 605 will be at voltage AA-BAR (which will start from VDDL) through PMOS transistor 603 and thus will be cut off. Since A-BAR drives the top plate of capacitor 609 from low level to high level (which is VDDL), AA-BAR will be driven by capacitor 609 to 2*VDDL.

[0023] Then when A switches from low level to high level, A-BAR will switch from high level to low level, PMOS transistor 607 will be turned on, and NMOS transistor 601 will be turned on, thus pulling the gate of PMOS transistor 605 to ground and turning on PMOS transistor 605, which will pull node AA-BAR to voltage VDDL through PMOS transistors 605 and 607. Therefore, node AA-BAR changes from VDDL to 2*VDDL in response to A-BAR switching from low level to high level, and node AA-BAR changes from 2*VDDL to VDDL in response to A-BAR switching from high level to low level.

[0024] Figure 7 The voltage level shift stage 700 is depicted, which includes NMOS transistors 701, 702, 703, and 704, PMOS transistors 705 and 706, and a high power supply 710 for output voltage VDDH. The signal A from Figure 2 is set to the gate of NMOS transistor 701 and one terminal of NMOS transistor 704. The signal A-BAR from Figure 2 is set to the gate of NMOS transistor 702 and one terminal of NMOS transistor 703. The node AA from Figure 5 is set to the gate of NMOS transistor 703, and the node AA-BAR from Figure 5 is set to the gate of NMOS transistor 704. As shown above, node AA will oscillate between VDDL and 2*VDDL, and node AA-BAR will oscillate between 2*VDDL and VDDL.

[0025] When A switches from 1 (VDDL) to 0, A-BAR will switch from 0 to 1 (VDDL), AA will be VDDL, and AA-BAR will be 2*VDDL. NMOS transistor 701 will be cut off, NMOS transistor 702 will be turned on, NMOS transistor 703 will be cut off (because both AA and A-BAR will be VDDL), and NMOS transistor 704 will be turned on. This will pull the node OUTPUT to ground through transistors 702 and 704 and turn on PMOS transistor 705, which will ensure that PMOS transistor 706 is cut off.

[0026] When A switches from 0 to 1 (VDDL), A-BAR will switch from 1 to 0, AA will be 2*VDDL, and AA-BAR will be VDDL. NMOS transistor 701 will be turned on, NMOS transistor 702 will be cut off, NMOS transistor 703 will be turned on, and NMOS transistor 704 will be cut off (because both A and AA-BAR will be VDDL), and NMOS transistor 704 will be cut off. The gate of PMOS transistor 706 will be pulled to ground through NMOS transistors 701 and 703, which will turn on PMOS transistor 706 and pull OUPUT to VDDH, thus turning off PMOS transistor 705.

[0027] It should be noted that when A switches from 1 to 0, NMOS transistors 702 and 704 can pull the node OUTPUT to ground faster than level shifters 300 and 400 because the overdrive voltage of NMOS transistor 704 is twice as high. Specifically, the Vgs of the pull-down NMOS transistor 704 is 2*VDDL, while the Vgs of NMOS transistor 302 in level shifter 300 and the Vgs of NMOS transistor 402 in level shifter 400 are only VDDL. Therefore, OUTPUT in level shifter 700 can be pulled to '0' faster than in level shifter 400.

[0028] Similarly, when A switches from 0 to 1, NMOS transistors 701 and 703 can pull the gate of PMOS transistor 706 to ground faster than level shifters 300 and 400 because the overdrive voltage of NMOS transistor 703 is twice as high. Therefore, OUTPUT is pulled to VDDH in a very short time. Specifically, the Vgs of the pull-down NMOS transistor 703 is 2*VDDL, while the Vgs of NMOS transistor 301 in level shifter 300 and the Vgs of NMOS transistor 401 in level shifter 400 are only VDDL each. Therefore, the gate of PMOS transistor 706 will be quickly pulled down to '0', and OUTPUT will be pulled up to VDDH faster than in level shifters 300 and 400.

[0029] That is, the level shifter 500 can switch faster than the level shifters 300 and 400, which means that the switching time required for the level shifter 500 is less than the switching time required for the level shifters 300 and 400.

[0030] The applicant has conducted experiments to compare the shifting speeds of the level shifter 500 with the prior art level shifters 300 and 400. For the conditions VDDL = 0.94V to 1.26V, VDDH = 1.4V to 2.75V, and temperature = -40°C to 160°C, when A switches from 0 to 1, the level shifter 500 is 3.5 times faster, and when A switches from 1 to 0, the level shifter 500 is 5.7 times faster. Therefore, the level shifter 500 is at least 3.5 times faster than the level shifters 300 and 400 in terms of switching time.

[0031] However, even Figures 5 - 7 the improved design has some drawbacks. Specifically, the design does not work well in a system where the available supply voltage is 0.8V or lower because the level shifting stage 700 requires transistors using a 2.5V supply voltage. That is, if VDDL is relatively small (such as, 0.75V), the level shifter 500 does not work well.

[0032] In addition, Figures 5 - 7 the design is relatively complex and requires a relatively significant amount of space within the semiconductor die. For example, there are NMOS transistors 701 and 702 to maintain functionality during the standby mode.

[0033] What is needed is an improved level shifting design that can reduce its switching time to below 0.5 ns while using a VDDL as low as 0.75V. Summary of the Invention

[0034] The present invention discloses an improved level shifter. The level shifter can achieve a switching time of less than 1 ns while still using a relatively low voltage for VDDL, such as 0.75V - 1.26V. The improved level shifter includes a coupling stage and a level conversion stage. Brief Description of the Drawings

[0035] Figure 1 Depicts a prior art level shifter.

[0036] Figure 2 Depicts a prior art set of inverters.

[0037] Figure 3 Depicts a prior art level shifter.

[0038] Figure 4 Depicts another prior art level shifter.

[0039] Figure 5 depicts a level shifter recently proposed by the applicant.

[0040] Figure 6 depicts Figure 5 the coupling stage of the level shifter of

[0041] Figure 7 depicts Figure 5 the level shifting circuit of the level shifter of

[0042] Figure 8 depicts an improved level shifter.

[0043] Figure 9 depicts Figure 8 the coupling stage of the improved level shifter of

[0044] Figure 10 depicts Figure 8 the level shifting circuit of the improved level shifter of

[0045] Figure 11 depicts a method of performing level shifting. Detailed Description

[0046] Figure 8 depicts a level shifter 800, which includes a coupling stage 900 and a level shifting stage 1000. When the level shifter 800 receives "0" as an input (where "0" is the first voltage), it outputs "0", i.e., the first voltage, and when it receives "1" (which is the second voltage) of the first voltage domain (VDDL) as an input, it outputs "1" of the second voltage domain (VDDH, ranging between 1.4V and 2.75V), which is a third voltage different from the first voltage or the second voltage.

[0047] Figure 9Depicts coupling stage 900, which includes a first circuit 910 and a second circuit 920. The two circuits are powered by a low-voltage power supply 930 (VDDL) with a voltage range between 0.75V and approximately 1.26V. The first circuit 910 includes a PMOS transistor 912 and a capacitor 911. The second circuit 920 includes a PMOS transistor 922 and a capacitor 921. The gate of PMOS transistor 912 is connected to the first terminal of capacitor 911, the drain of PMOS transistor 912 is connected to the low-voltage power supply 930, and the source of PMOS transistor 912 is connected to the body of PMOS transistor 912 and to the second terminal of capacitor 911 (denoted as node CC). The gate of PMOS transistor 922 is connected to the first terminal of capacitor 921, the drain of PMOS transistor 922 is connected to the low-voltage power supply 930, and the source of PMOS transistor 922 is connected to the body of PMOS transistor 922 and to the second terminal of capacitor 921 (denoted as node CC-BAR).

[0048] Signals C and C_BAR here are the VDDL power domain voltages respectively and are set to the gates of PMOS transistors 912 and 922 respectively.

[0049] The operation of coupling stage 900 during the standby mode will now be described.

[0050] When powered on, VDDL rises from a low level to a high level (i.e., from 0 to 0.75V - 1.26V), C will rise from a low level to a high level (VDDL), and C-BAR remains at a low level state (0V). Node CC will be coupled from a low level to a high level (VDDL - VD) through capacitor 911, where VD is the forward voltage of the parasitic diode in PMOS transistor 912. Since there is no current passing through PMOS transistor 912, VD will be very small (∼20mV). Signal C-BAR remains at a low level state, and PMOS transistor 922 is turned on, so the voltage at node CC-BAR will rise from a low level to a high level (VDDL). Therefore, capacitor 911 is mostly discharged and has a small voltage (VD) across it, and capacitor 921 is charged with the voltage of VDDL across it.

[0051] Next, the operation of coupling stage 900 during the active mode will be described.

[0052] When C switches from high level to low level, the change in signal C will be coupled through capacitor 911, causing node CC to immediately switch from high level (VDDL - VD) to low level (∼0V), and then rise to high level (VDDL) because PMOS transistor 912 turns on. C - BAR switches from low level to high level, and the change in signal C - BAR will be coupled through capacitor 921, causing node CC - BAR to immediately switch from high level (VDDL) to a higher level (∼2*VDDL), and then drop to VDDL + Vth922 as capacitor 921 discharges through PMOS transistor 922 until the voltage at the source of PMOS transistor 922 drops to the threshold of PMOS transistor 922, turning it off. Vth922 is the threshold voltage of PMOS transistor 922.

[0053] When C switches from low level to high level, the change in signal C will be coupled through capacitor 911, causing node CC to immediately switch from high level (VDDL) to a higher level (∼2*VDDL), and then drop to high level (VDDL + Vth912) as capacitor 911 discharges through PMOS transistor 912 until the voltage at the source of PMOS transistor 912 drops to the threshold of PMOS transistor 912, turning it off. Vth921 is the threshold voltage of PMOS transistor 912. C - BAR will switch from high level to low level, and the change in signal C - BAR will be coupled through capacitor 921, causing node CC - BAR to immediately switch from high level (VDDL + Vth922) to low level (Vth922), and then rise to VDDL because PMOS transistor 922 turns on at this time.

[0054] Figure 10 The voltage - level shifting stage 1000 is depicted, which includes NMOS transistors 1001, 1002, 1003, and 1004, PMOS transistors 1005 and 1006, and a high - power supply 1007 for output voltage VDDH. Different from the level - shifting stage 700 in the voltage - level shifter 500, the voltage - level shifting stage 1000 can operate when VDDL is as low as 0.75V.

[0055] Signal C is set to the gate of NMOS transistor 1001. Signal C - BAR is set to the gate of NMOS transistor 1002. The node CC from Figure 9 is set to the gate of NMOS transistor 1003, and the node CC - BAR from Figure 9 is set to the gate of NMOS transistor 1004.

[0056] When C switches from a high level (VDDL) to a low level, C-BAR will switch from a low level to a high level (VDDL). The NMOS transistor 1001 will turn off, the NMOS transistor 1002 will turn on, the NMOS transistor 1003 will turn on, and the NMOS transistor 1004 will turn on. The node OUT will be pulled to ground through the transistors 1004 and 1002, thereby turning on the PMOS transistor 1005. Then the gate of the PMOS transistor 1006 will be pulled high through the PMOS transistor 1005, and the PMOS transistor 1006 will turn off.

[0057] When C switches from a low level to a high level (VDDL), C-BAR will switch from a high level to a low level. The NMOS transistor 1001 will turn on, the NMOS transistor 1002 will turn off, the NMOS transistor 1003 will turn on, and the NMOS transistor 1004 will turn on. The gate of the PMOS transistor 1006 will be pulled to ground through the NMOS transistors 1003 and 1001, which will turn on the PMOS transistor 1006 and pull OUPUT to VDDH, thus turning off the PMOS transistor 1005.

[0058] It should be noted that when C switches from a high level to a low level, the NMOS transistors 1002 and 1004 can pull the node OUTPUT to ground faster than the prior art level shifters 300 and 400, because the overdrive voltage (CC-BAR) of the NMOS transistor 1004 is twice as high (i.e., 2*VDDL). Specifically, the Vgs of the pull-down NMOS transistor 1004 is 2*VDDL, while the Vgs of the NMOS transistor 302 in the level shifter 300 and the Vgs of the NMOS transistor 402 in the level shifter 400 are only VDDL. Therefore, the OUTPUT in the level shifter 1000 can be pulled to '0' faster than in the level shifter 400.

[0059] Similarly, when C switches from a low level to a high level, the NMOS transistors 1003 and 1001 can pull the gate of the PMOS transistor 1006 to ground faster than the level shifters 300 and 400, because the overdrive voltage (CC) of the NMOS transistor 1003 is twice as high (i.e., 2*VDDL). Therefore, OUT is pulled to VDDH in a very short time. Specifically, the Vgs of the pull-down NMOS transistor 1003 is 2*VDDL, while the Vgs of the NMOS transistor 301 in the level shifter 300 and the Vgs of the NMOS transistor 401 in the level shifter 400 are only VDDL each. Therefore, OUT will be pulled to ground and pulled up to VDDH faster than in the level shifters 300 and 400.

[0060] That is to say, the level shifter 800 can switch faster than the level shifters 300 and 400, which means that the switching time required for the level shifter 800 is less than that required for the level shifters 300 and 400. In addition, the level shifter 800 can operate with a VDDL as low as 0.75V.

[0061] Figure 11 The level shifting method 1100 is depicted, which can be implemented using the level shifter 800. The first step is to receive the input of the first voltage domain, where "0" in the first voltage domain is the first voltage (e.g., 0V) and "1" in the first voltage domain is the second voltage (e.g., as low as 0.75V, preferably 0.75V to 1.26V) (step 1101). The second step is to generate a switching voltage equal to twice the second voltage (step 1102). The third step is to generate the output of the second voltage domain using the switching voltage, where "0" in the second voltage domain is the first voltage and is generated when the input is "0", and "1" in the second voltage domain is the third voltage (e.g., 2.75V) and is generated when the input is "1" (step 1103).

[0062] The applicant has conducted experiments to compare the shifting speeds of the level shifter 800 with the prior art level shifters 300 and 400. For the conditions VDDL = 0.75V to 1.26V, VDDH = 1.4V to 2.75V, and temperature = -40°C to 160°C, when A (which is relabeled as C) switches from 0 to 1, the level shifter 800 is 3 times faster, and when A (which is relabeled as C) switches from 1 to 0, the level shifter 800 is 5 times faster. Therefore, the level shifter 800 is at least 3 times faster than the level shifters 300 and 400 in terms of switching time.

[0063] When VDDL is greater than 0.87V, the level shifter 800 is not as fast as the level shifter 500. However, the level shifter 800 requires significantly less space on the semiconductor die and has a simpler design. In addition, when VDDL is as low as 0.75V, the level shifter 800 performs better than the level shifter 500.

[0064] It should be noted that, as used herein, the terms "above" and "on" both inclusively encompass "directly on" (with no intervening material, element, or space therebetween) and "indirectly on" (with intervening material, element, or space therebetween). Similarly, the term "adjacent" includes "directly adjacent" (with no intervening material, element, or space therebetween) and "indirectly adjacent" (with intervening material, element, or space therebetween), "mounted to" includes "directly mounted to" (with no intervening material, element, or space therebetween) and "indirectly mounted to" (with intervening material, element, or space therebetween), and "electrically coupled to" includes "directly electrically coupled to" (with no intervening material or element electrically connecting the components therebetween) and "indirectly electrically coupled to" (with intervening material or element electrically connecting the components therebetween). For example, forming an element "above a substrate" may include directly forming the element on the substrate with no intervening material / element therebetween, and indirectly forming the element on the substrate with one or more intervening material / elements therebetween.

Claims

1. A level shifter for receiving an input in a first voltage domain and generating an output in a second voltage domain, wherein "0" and "1" in the first voltage domain are a first voltage and a second voltage respectively, and "0" and "1" in the second voltage domain are the first voltage and a third voltage different from the second voltage respectively. The level shifter includes: A first power supply providing the third voltage; A first PMOS transistor including a first terminal coupled to the first power supply, a gate, and a second terminal; A second PMOS transistor including a first terminal coupled to the first power supply, a gate coupled to the second terminal of the first PMOS transistor, and a second terminal coupled to the gate of the first PMOS transistor and to an output node for providing the output; A first NMOS transistor including a first terminal coupled to the second terminal of the first PMOS transistor and a gate configured to receive a first signal; And a second terminal; A second NMOS transistor including a first terminal coupled to the second terminal of the first NMOS transistor, a gate configured to receive the input, and a second terminal coupled to the first voltage; A third NMOS transistor including a first terminal coupled to the output node, a gate coupled to receive a second signal, and a second terminal; And A fourth NMOS transistor including a first terminal coupled to the second terminal of the third NMOS transistor, a gate configured to receive the complement of the input, and a second terminal coupled to the first voltage; Wherein when the input is at the first voltage, the first signal is the second voltage, the second signal is twice the second voltage, the output is the first voltage, and When the input is at the second voltage, the first signal is twice the second voltage, the second signal is the second voltage, and the output is the third voltage.

2. The level shifter according to claim 1, further including a second power supply providing the second voltage.

3. The level shifter according to claim 2, wherein the first signal is generated by a first circuit including: A third PMOS transistor including a first terminal coupled to the second power supply, a gate, a second terminal, and a body; And A first capacitor including a first terminal coupled to the gate of the third PMOS transistor and a second terminal coupled to the second terminal of the third PMOS transistor and to the body of the third PMOS transistor.

4. The level shifter according to claim 3, wherein the second signal is generated by a second circuit including: A fourth PMOS transistor including a first terminal coupled to the second power supply, a gate, a second terminal, and a body; And A second capacitor, the second capacitor including a first terminal coupled to the gate of the fourth PMOS transistor and a second terminal coupled to the second terminal of the fourth PMOS transistor and the body of the fourth PMOS transistor.

5. The level shifter according to claim 1, wherein the second voltage is between 0.75 volts and 1.26 volts.

6. The level shifter according to claim 2, wherein the second voltage is between 0.75 volts and 1.26 volts.

7. The level shifter according to claim 3, wherein the second voltage is between 0.75 volts and 1.26 volts.

8. The level shifter according to claim 4, wherein the second voltage is between 0.75 volts and 1.26 volts.

9. A method of shifting from a first voltage domain to a second voltage domain using the level shifter according to claim 1, the method comprising: Receiving an input of a first voltage domain at the gate of the second NMOS transistor, wherein "0" and "1" in the first voltage domain are a first voltage and a second voltage, respectively; Receiving a complement of the input at the gate of the fourth NMOS transistor; Generating a switching voltage equal to twice the second voltage; Generating a first signal that switches between the second voltage and the switching voltage; Receiving the first signal at the gate of the first NMOS transistor; Generating a second signal that switches between the switching voltage and the second voltage in a complementary manner to the first signal; Receiving the second signal at the gate of the third NMOS transistor; And Generating an output of a second voltage domain at the second terminal of the second PMOS transistor, wherein "0" and "1" in the second voltage domain are the first voltage and a third voltage, respectively; Wherein when the input is at the first voltage, the first signal is the second voltage, the second signal is twice the second voltage, and the output is the first voltage, and When the input is at the second voltage, the first signal is twice the second voltage, the second signal is the second voltage, and the output is the third voltage.

10. The method according to claim 9, wherein the second voltage is between 0.75 volts and 1.26 volts.

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