A method and device for setting clock tree wiring rules
By calculating and optimizing the wiring factor of the clock tree and collaboratively adjusting the wiring width and spacing, the problem of high dynamic power consumption in traditional clock tree design is solved, and the low power consumption and good timing characteristics of the clock tree are achieved.
Patent Information
- Application Number
- CN202110290928.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-03-18
- Publication Date
- 2024-12-31
- Estimated Expiration
- 2041-03-18
AI Technical Summary
The lack of low-power design in the comprehensive design process of traditional clock trees leads to a high dynamic power consumption of the clock trees. How to reduce the dynamic power consumption of the clock trees is a technical problem that needs to be solved urgently.
By calculating the total value of the clock tree dynamic power consumption and hold time violations based on the wiring width and wiring spacing, calculating the wiring factor, and co-optimizing the wiring width and wiring spacing to minimize the wiring factor, reducing the dynamic power consumption of the clock tree and reducing hold time Violation.
The dynamic power consumption of the clock tree is reduced, while ensuring the reduction of maintaining time violations, satisfying the low power consumption and good timing characteristics of the clock tree.
Smart Images
Figure CN112906342B_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of integrated circuit design, and in particular to a method and device for setting clock tree wiring rules. Background Art
[0002] The clock tree is a mesh structure built by many buffer cells. The clock tree can manage the clock signal in the clock domain to ensure that the clock edge deviation of the register in the clock domain is minimized, thereby ensuring good timing characteristics. In the traditional clock tree synthesis design process, there is no low-power design for the clock tree wiring rules. The dynamic power consumption of the clock tree set according to the traditional wiring rules may be high. Therefore, how to reduce the dynamic power consumption of the clock tree is a technical problem that needs to be solved urgently in this field. Summary of the invention
[0003] In view of this, the purpose of the present application is to provide a method and device for setting clock tree wiring rules, which can reduce the dynamic power consumption of the clock tree while ensuring that the clock tree has few hold time violations.
[0004] In a first aspect, the present application provides a method for setting a clock tree wiring rule, comprising:
[0005] The total value of clock tree dynamic power consumption and hold time violation is obtained according to the wiring width and wiring spacing;
[0006] A wiring factor is calculated according to the clock tree dynamic power consumption and the total value of the hold time violation; the wiring factor is positively correlated to the absolute value of the clock tree dynamic power consumption and the total value of the hold time violation respectively;
[0007] The wiring width and the wiring pitch are optimized cooperatively to minimize the wiring factor.
[0008] Optionally, the calculating a wiring factor according to the clock tree dynamic power consumption and the total value of the hold time violation includes:
[0009] The product of the square of the clock tree dynamic power consumption and the absolute value of the total value of the hold time violation is used as the wiring factor.
[0010] Optionally, the collaboratively optimizing the wiring width and the wiring spacing to minimize the wiring factor includes:
[0011] Let the wiring spacing be the initial wiring spacing, and adjust the initial wiring width with the first step length to minimize the wiring factor to obtain the optimal wiring width;
[0012] The wiring width is set to the optimal wiring width, and the initial wiring spacing is adjusted with a second step size to minimize the wiring factor to obtain the optimal wiring spacing.
[0013] Optionally, the clock tree dynamic power consumption includes: clock tree short-circuit power consumption and clock tree switch power consumption.
[0014] Optionally, the total hold time violation value is obtained according to a pre-established model; the pre-established model is used to analyze the input wiring width and the wiring spacing to obtain the total hold time violation value.
[0015] In a second aspect, the present application provides a device for setting a clock tree wiring rule, comprising:
[0016] A first calculation unit, used for obtaining a total value of clock tree dynamic power consumption and hold time violation according to a wiring width and a wiring spacing;
[0017] A second calculation unit is used to calculate a wiring factor according to the clock tree dynamic power consumption and the total value of the hold time violation; the wiring factor is positively correlated to the absolute value of the clock tree dynamic power consumption and the total value of the hold time violation respectively;
[0018] An optimization unit is used to optimize the wiring width and the wiring spacing in a coordinated manner to minimize the wiring factor.
[0019] Optionally, the second computing unit includes:
[0020] The second calculation unit sub-unit is used to take the product of the square of the clock tree dynamic power consumption and the absolute value of the total value of the hold time violation as the wiring factor.
[0021] Optionally, the optimization unit includes:
[0022] A first adjustment unit is used to make the wiring spacing an initial wiring spacing, and adjust the initial wiring width with a first step length to minimize the wiring factor, so as to obtain an optimal wiring width;
[0023] The second adjustment unit is used to make the wiring width the optimal wiring width, adjust the initial wiring spacing with a second step size to minimize the wiring factor, and obtain the optimal wiring spacing.
[0024] Optionally, the clock tree dynamic power consumption includes: clock tree short-circuit power consumption and clock tree switch power consumption.
[0025] Optionally, the device further comprises:
[0026] The analysis unit is used to analyze the wiring width and the wiring spacing input into the model according to a pre-established model to obtain the total value of the hold time violation.
[0027] The embodiment of the present application provides a method and device for setting clock tree wiring rules, which can obtain the clock tree dynamic power consumption and the total value of hold time violations according to the wiring width and the wiring spacing, and calculate the wiring factor according to the clock tree dynamic power consumption and the total value of hold time violations; the wiring width and the wiring spacing are collaboratively optimized to minimize the wiring factor; because the wiring factor is positively correlated with the absolute values of the clock tree dynamic power consumption and the total value of hold time violations, respectively; when the wiring factor is minimum, both the low dynamic power consumption of the clock tree and the small hold time violations of the clock tree are satisfied. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0029] Figure 1 A conventional clock tree synthesis design flow chart provided by an embodiment of the present application is shown;
[0030] Figure 2 A schematic diagram of metal wiring provided by an embodiment of the present application is shown;
[0031] Figure 3 An analysis diagram of setup time and hold time provided by an embodiment of the present application is shown;
[0032] Figure 4 A flowchart of a method for setting clock tree wiring rules provided in an embodiment of the present application is shown;
[0033] Figure 5 A schematic diagram of a clock tree wiring rule setting device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION
[0034] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below with reference to the accompanying drawings.
[0035] In the following description, many specific details are set forth to facilitate a full understanding of the present application, but the present application may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.
[0036] As described in the background art, see Figure 1 As shown in the figure, the clock tree design process in the traditional digital integrated circuit back-end physical design is:
[0037] Step 1: Check before clock tree synthesis (check_physical_design). Check whether the design has been laid out and the clock constraints have been set;
[0038] Step 2: Remove the ideal clock (remove_ideal_network). Remove the ideal properties of the clock;
[0039] Step 3: Set the clock tree constraints (set_clock_tree_options), including the maximum clock deviation, maximum fan-out, maximum capacitance, etc.
[0040] Step 4: Set the clock tree driver (set_clock_tree_references). Set the type of clock tree driver and the choice of driving capability;
[0041] Step 5: Set the clock tree routing rules (define_routing_rule). This includes the selection of routing metal layers, routing width, routing spacing, and via settings;
[0042] Step 6: Perform clock tree synthesis.
[0043] That is, in the traditional digital integrated circuit back-end physical design, the clock tree synthesis design process has the step of setting wiring rules, but there is no low-power design for the clock tree. Therefore, a specific design method is urgently needed to guide the setting of wiring rules and thus realize the low-power design of the clock tree.
[0044] The calculation formula for the dynamic power consumption of the clock tree is shown in formula (1):
[0045]
[0046] Among them, P dynamic is the dynamic power consumption of the clock tree; P short is the short-circuit power consumption of the clock tree; P switch is the switching power consumption of the clock tree; α is the clock conversion factor; k is the transistor constant; τ is the conversion time of the clock signal, that is, the rise time or fall time of the clock signal; f clk is the clock frequency; V DD is the power supply voltage; V th is the transistor threshold voltage; C output is the load capacitance; it should be noted that, in this application, it is assumed that the rise time and fall time of the clock signal are equal.
[0047] From (1), it can be seen that under the premise of unchanged circuit performance, operating frequency, voltage and manufacturing process, by reducing the clock signal conversion time τ and the clock network load capacitance C output Can reduce clock tree dynamic power consumption P dynamic , and the settings of metal layer width and spacing in the clock tree routing rules can affect the conversion time of the clock signal and the load capacitance of the clock network.
[0048] According to signal and system knowledge, the conversion time of the clock signal τ = r0c0 (r0, c0 are the resistance and capacitance of the signal drive respectively). For the clock network, the resistance r0 driven by the signal includes the output impedance R0 of the logic unit driven by the signal and the parasitic resistance of the interconnection line. r , then
[0049] r0=R0+r (2)
[0050] The signal-driven capacitor c0 is composed of the input capacitor C0 of the standard cell and the parasitic capacitance c of the interconnection line.
[0051] c0=C0+c (3)
[0052] Since integrated circuits have entered deep submicron technology, as the chip scale has expanded, the length of interconnects has become longer, the width has decreased, and the spacing has become smaller, the capacitance and resistance of the interconnects have become the main components of interconnect delay, and the resistance and capacitance of the active devices themselves can be ignored. Therefore, we have:
[0053]
[0054] Model the routing structure of the clock network, refer to Figure 2 As shown in the figure, it is a schematic diagram of metal wiring. The parasitic resistance r and parasitic capacitance c of the interconnect line can be expressed as:
[0055]
[0056] Among them, c 邻层 、c 同层 、c 同向层 、c 对地 They are the capacitance between the clock signal line and the adjacent metal layer, the capacitance between the metals on the same layer, the capacitance between the metals on parallel adjacent layers, and the parasitic capacitance to the ground. r is the cross-sectional area of the clock signal line, ρ is the resistivity of the clock signal line, h is the thickness of the metal line, and w is the width of the metal line. ε1, ε2, ε3, and ε4 are the dielectric constants of the capacitor, and d1, d2, d3, and d4 are the spacing between the clock signal line and the adjacent metal layer, the spacing between the metals on the same layer, the vertical spacing between the parallel adjacent layers of metal, and the spacing between the clock signal line and the ground. l is the length of the clock signal line itself, l 1x (x=1,2,3...),l2y (y=1,2,3...),l 3z (z=1,2,3...) are respectively the length of the relative area between each segment of the clock signal line and the adjacent layer of metal, the length of each segment and the relative area between the same layer of metal, and the length of each segment and the parallel adjacent metal. l4 is the length of the clock signal line to the ground, and λ is the relative area coefficient of the capacitance between parallel adjacent metal layers. The larger the width, the larger the relative area.
[0057] Then substitute the calculation formula of formula (4) and (5) into formula (1) to obtain:
[0058]
[0059] For the short-circuit power consumption and switching power consumption in dynamic power consumption, we have:
[0060]
[0061] Where k is the transistor constant and c is the interconnect parasitic capacitance.
[0062] Assuming that copper is used as interconnect in the chip process, the resistivity at room temperature is 0.0185Ω·mm 2 / m=0.0185Ω·um, the interconnection line width w and thickness h are both less than 1 micron, and the clock tree interconnection line length is in the order of millimeters. Assume w=0.2um, h=0.2um, l=2mm. The general MOS tube constant k is about several hundred uA / V, and the power supply voltage V DD Taking 1.2V, expression (7) can be transformed into:
[0063]
[0064] From (8), we can see that switching power consumption is dominant in dynamic power consumption. l Since the positions of the clock input points of registers and other clocks are fixed, their sizes remain basically unchanged, and d1 and d3 are also fixed values. Therefore, for the two variables of the metal wire width w of the clock network and the metal wire wiring spacing d2 of the clock network, according to the switch power consumption P in formula (6): switch , reducing the metal wire width of the clock network can reduce the dynamic power consumption of the clock tree; increasing the spacing between the metal wires of the clock network can also reduce the dynamic power consumption of the clock tree. From formula (6), it can be seen that reducing the metal wire width w of the clock network has little effect on the area, and increasing the spacing d2 of the metal wires of the clock network will affect the routing rate and may increase the area of the chip. Therefore, in terms of reducing dynamic power consumption, the metal wire width w of the clock network can be optimized first, and then the metal wire spacing d2 of the clock network can be optimized.
[0065] As can be seen from Equation (6), reducing the metal line width of the clock network and increasing the metal line spacing of the clock network will have a certain impact on the timing of the clock tree. That is, the second term in Equation (6)P short The second term in the parentheses is part of the transition time. Reducing the metal line width of the clock network will increase the clock signal transition time, and increasing the metal line spacing of the clock network will decrease the clock signal transition time, which will in turn affect the timing of the clock tree.
[0066] On the premise of satisfying the constraint condition of the same maximum clock signal transition time max_transition, compared with the clock tree design before the wiring rule is changed, in order to reduce the dynamic power consumption of the clock tree, after reducing the metal line width of the clock network and increasing the metal line spacing of the clock network, the comprehensive impact is that the driving ability of the clock tree becomes relatively low and the transition time of the clock tree becomes relatively large. At this time, the impact on the setup time and hold time checks is as Figure 3 shown. CLK is the clock signal, T2setup and T2hold are the setup time and hold time of the data signal after reducing the metal line width of the clock network and increasing the metal line spacing of the clock network, respectively, and T1setup and T1hold are the setup time and hold time of the data signal before modifying the wiring rule, respectively. For the setup time: as Figure 3 shown, it is obvious that T2setup > T1setup. Therefore, after modifying the wiring rule, the time for the data signal to remain stable before the clock active edge arrives becomes larger, so it is beneficial for the setup time check; for the hold time: T2hold < T1hold, that is, after modifying the wiring rule, the hold time of the data signal becomes smaller than the hold time before modifying the rule, so it is not beneficial for the hold time check. Therefore, while reducing the dynamic power consumption by reducing the metal line width of the clock network and increasing the metal line spacing of the clock network, it will have an adverse impact on the hold time timing.
[0067] Therefore, the present application proposes a method for setting the clock tree wiring rule, which can ensure a relatively small total hold time violation while reducing the dynamic power consumption of the clock tree. The following will describe various non-limiting embodiments of the present application in detail with reference to the accompanying drawings.
[0068] Exemplary Methods
[0069] Refer to Figure 4 shown, which is a flowchart of a method for setting the clock tree wiring rule provided by an embodiment of the present application, including:
[0070] S101: Obtain the dynamic power consumption of the clock tree and the total hold time violation value according to the wiring width and wiring spacing.
[0071] In the embodiment of the present application, it can be known from formula (6) that the clock tree dynamic power consumption P can be calculated based on the wiring width w and the wiring spacing d2 and other parameters. dynamic , and the pre-established model can be input according to the wiring width w and the wiring spacing d2 to obtain the total hold time violation value TNS, in ns.
[0072] S102: Calculate a wiring factor according to the clock tree dynamic power consumption and the total value of the hold time violation; the wiring factor is positively correlated to the absolute value of the clock tree dynamic power consumption and the total value of the hold time violation respectively;
[0073] In an embodiment of the present application, in order to reduce the dynamic power consumption of the clock tree while ensuring that the total value of hold time violations is small, a parameter of wiring factor is proposed, so that the two variables of hold time timing and dynamic power consumption of the clock tree can be optimized together, which satisfies both the low dynamic power consumption of the clock tree and the small hold time violations of the entire system.
[0074] The routing factor is positively correlated to the absolute value of the clock tree dynamic power consumption and the total value of the hold time violation, so when the routing factor is minimum, both the clock tree dynamic power consumption and the total value of the hold time violation are satisfied.
[0075] Specifically, the routing factor can be equal to the product of the square of the clock tree dynamic power consumption and the absolute value of the total hold time violation value, that is, Q = P dynamic 2 ×|TNS|, where Q is the wiring factor, P dynamic is the clock tree dynamic power consumption, and TNS is the total hold time violation value.
[0076] S103: Co-optimizing the wiring width and the wiring spacing to minimize the wiring factor.
[0077] In an embodiment of the present application, since the wiring factor is positively correlated with the absolute value of the dynamic power consumption of the clock tree and the total value of the hold time violation, respectively, and changing the wiring width and wiring spacing of the clock tree can change the absolute value of the dynamic power consumption of the clock tree and the total value of the hold time violation, the wiring width and wiring spacing can be collaboratively optimized to minimize the wiring factor.
[0078] Co-optimizing the wiring width and wiring spacing to minimize the wiring factor can be:
[0079] Let the wiring spacing be the initial wiring spacing, adjust the initial wiring width with the first step length to minimize the wiring factor, and obtain the optimal wiring width; then let the wiring width be the optimal wiring width, adjust the initial wiring spacing with the second step length to minimize the wiring factor, and obtain the optimal wiring spacing.
[0080] Specifically, after setting the initial wiring rules, including the selection of the wiring metal layer, the wiring width, the wiring spacing and the setting of the through-hole, the wiring spacing is set to the initial wiring spacing s0, and the initial wiring width is w0. According to s0 and w0, let i and j = 0, and calculate the initial wiring factor Q(i, j) = Q(0,0), where Q is the wiring factor.
[0081] First, keep the wiring spacing at the initial wiring spacing s(j)=s0 unchanged, and reduce the wiring width by the first step length β, that is, w(i+1)=w(i)-β, then remove the existing clock tree, re-perform clock tree synthesis, and calculate the Q value Q(i+1,j).
[0082] Determine whether the Q value Q(i+1, j) obtained after reducing the width to w(i+1) is smaller than the Q value Q(i, j) obtained before reducing the width, and whether the width w(i+1) after reduction is larger than the minimum wiring width. If so, let i=i+1 and continue to reduce the wiring width with the first step. If not, the Q value corresponding to the width value w(i) before reducing the width is the optimal wiring width w opt .
[0083] When the optimal wiring width w is calculated opt , and then the initial wiring spacing is adjusted with a second step size to minimize the wiring factor and obtain the optimal wiring spacing.
[0084] Specifically, the wiring width can be set to the optimal wiring width w opt , increase the wiring spacing with a second step length γ, that is, s(j+1)=s(j)+γ, remove the existing clock, re-perform clock tree synthesis, and calculate the Q value Q(i, j+1).
[0085] Determine whether the Q value Q(i, j+1) obtained after increasing the spacing to s(j+1) is smaller than the Q value Q(i, j) obtained before increasing the spacing. If so, set j=j+1 and continue to increase the wiring spacing with the second step length. If not, the Q value corresponding to the width value s(j) before increasing the spacing is the optimal wiring spacing s opt .
[0086] At this time, the optimal wiring width and optimal wiring spacing corresponding to the optimal wiring factor are used as wiring parameters for low-power clock tree synthesis, which not only meet the requirements of low dynamic power consumption of the clock tree, but also meet the requirements of few hold time violations.
[0087] The embodiment of the present application provides a method for setting clock tree wiring rules, which can obtain the clock tree dynamic power consumption and the total value of hold time violations according to the wiring width and the wiring spacing, and calculate the wiring factor according to the clock tree dynamic power consumption and the total value of hold time violations; the wiring width and the wiring spacing are coordinated to minimize the wiring factor; because the wiring factor is positively correlated with the absolute values of the clock tree dynamic power consumption and the total value of hold time violations, respectively; when the wiring factor is minimum, both the low dynamic power consumption of the clock tree and the small hold time violations of the clock tree are satisfied.
[0088] Exemplary Devices
[0089] See also Figure 5 , is a schematic diagram of a device for setting clock tree wiring rules provided in an embodiment of the present application. It may include:
[0090] A first calculation unit 201 is used to obtain a total value of clock tree dynamic power consumption and hold time violation according to a wiring width and a wiring spacing;
[0091] A second calculation unit 202 is used to calculate a wiring factor according to the clock tree dynamic power consumption and the total value of the hold time violation; the wiring factor is positively correlated to the absolute value of the clock tree dynamic power consumption and the total value of the hold time violation respectively;
[0092] The optimization unit 203 is used to coordinately optimize the wiring width and the wiring spacing to minimize the wiring factor.
[0093] In some implementations, the second computing unit 202 includes:
[0094] The second calculation unit sub-unit is used to take the product of the square of the clock tree dynamic power consumption and the absolute value of the total value of the hold time violation as the wiring factor.
[0095] In some implementations, the optimization unit 203 includes:
[0096] A first adjustment unit is used to make the wiring spacing an initial wiring spacing, and adjust the initial wiring width with a first step length to minimize the wiring factor, so as to obtain an optimal wiring width;
[0097] The second adjustment unit is used to make the wiring width the optimal wiring width, adjust the initial wiring spacing with a second step size to minimize the wiring factor, and obtain the optimal wiring spacing.
[0098] In some implementations, the clock tree dynamic power consumption includes: clock tree short-circuit power consumption and clock tree switch power consumption.
[0099] In some embodiments, the device further comprises:
[0100] The analysis unit is used to analyze the wiring width and the wiring spacing input into the model according to a pre-established model to obtain the total value of the hold time violation.
[0101] An embodiment of the present application provides a device for setting clock tree wiring rules, which can obtain the clock tree dynamic power consumption and the total value of hold time violations according to the wiring width and the wiring spacing, and calculate the wiring factor according to the clock tree dynamic power consumption and the total value of hold time violations; the wiring width and the wiring spacing are collaboratively optimized to minimize the wiring factor; because the wiring factor is positively correlated with the absolute values of the clock tree dynamic power consumption and the total value of hold time violations, respectively; when the wiring factor is minimum, both the low dynamic power consumption of the clock tree and the small hold time violations of the clock tree are satisfied.
[0102] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.
[0103] The above is only a preferred implementation of the present application. Although the present application has been disclosed as a preferred embodiment, it is not intended to limit the present application. Any technician familiar with the art can use the above disclosed methods and technical contents to make many possible changes and modifications to the technical solution of the present application without departing from the scope of the technical solution of the present application, or modify it into an equivalent embodiment of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application still falls within the scope of protection of the technical solution of the present application.
Claims
1. A method for setting clock tree wiring rules, characterized in that: include: The total value of clock tree dynamic power consumption and hold time violation is obtained according to the wiring width and wiring spacing; A wiring factor is calculated according to the clock tree dynamic power consumption and the total value of the hold time violation; the wiring factor is positively correlated to the absolute value of the clock tree dynamic power consumption and the total value of the hold time violation respectively; Co-optimizing the wiring width and the wiring pitch to minimize the wiring factor; The calculating the wiring factor according to the clock tree dynamic power consumption and the total value of the hold time violation includes: The product of the square of the clock tree dynamic power consumption and the absolute value of the total value of the hold time violation is used as the wiring factor; The total value of the hold time violation is obtained according to a pre-established model; the pre-established model is used to analyze the input wiring width and the wiring spacing to obtain the total value of the hold time violation.
2. The method according to claim 1, characterized in that The step of synergistically optimizing the wiring width and the wiring spacing to minimize the wiring factor includes: Let the wiring spacing be the initial wiring spacing, and adjust the initial wiring width with the first step length to minimize the wiring factor to obtain the optimal wiring width; The wiring width is set to the optimal wiring width, and the initial wiring spacing is adjusted with a second step size to minimize the wiring factor to obtain the optimal wiring spacing.
3. The method according to claim 1, characterized in that The clock tree dynamic power consumption includes: clock tree short-circuit power consumption and clock tree switch power consumption.
4. A device for setting clock tree wiring rules, characterized in that: include: A first calculation unit, used for calculating the clock tree dynamic power consumption and the total value of the hold time violation according to the wiring width and the wiring spacing; A second calculation unit is used to obtain a wiring factor according to the clock tree dynamic power consumption and the total value of the hold time violation; the wiring factor is positively correlated to the absolute value of the clock tree dynamic power consumption and the total value of the hold time violation respectively; An optimization unit, configured to optimize the wiring width and the wiring spacing in a coordinated manner to minimize the wiring factor; The second computing unit comprises: A second calculation unit sub-unit is used to take the product of the square of the clock tree dynamic power consumption and the absolute value of the total value of the hold time violation as the wiring factor; The analysis unit is used to analyze the wiring width and the wiring spacing input into the model according to a pre-established model to obtain the total value of the hold time violation.
5. The device according to claim 4, characterized in that The optimization unit comprises: A first adjustment unit is used to make the wiring spacing an initial wiring spacing, and adjust the initial wiring width with a first step length to minimize the wiring factor, so as to obtain an optimal wiring width; The second adjustment unit is used to make the wiring width the optimal wiring width, adjust the initial wiring spacing with a second step size to minimize the wiring factor, and obtain the optimal wiring spacing.
6. The device according to claim 4, characterized in that The clock tree dynamic power consumption includes: clock tree short-circuit power consumption and clock tree switch power consumption.