An encapsulation component, an electronic device and an encapsulation method thereof

Abstract

The present application discloses a packaging component, an electronic device, and a packaging method. The packaging component includes: a substrate, a packaged chip, a first semiconductor chip, and a first molding compound. The first semiconductor chip is disposed on the substrate and is electrically connected to the substrate. The packaged chip is disposed on the substrate, adjacent to the first semiconductor chip, and is electrically connected to the substrate; the substrate, the first semiconductor chip, and the packaged chip are encapsulated using the first molding compound. Therefore, the packaged chip provided in the present application is disposed adjacent to the first semiconductor chip on the same substrate, which can reduce the packaging size of the substrate; and, by using the first molding compound to encapsulate the packaging substrate, the first semiconductor chip, and the packaged chip into a single packaging component, the length between electrical connection wires can be reduced, and the probabilities of occurrence of adverse phenomena such as signal attenuation, crosstalk, and parasitic capacitance in the wires can be reduced, thereby improving the integration degree.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, and particularly to a packaging component, an electronic device, and a packaging method. Background Art

[0002] Semiconductor chips are used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. With the continuous development of integrated electronic technology, the performance requirements for semiconductor chips are also increasing day by day, such as enhanced functions, reduced size, lower power consumption and cost.

[0003] To adapt to the development trends of multi-function, miniaturization, portability, high speed, low power consumption, and high reliability in microelectronic packaging technology, System in Package (SIP) technology, as an emerging heterogeneous integration technology, has become the packaging form for more and more chips. System-level packaging integrates multiple functional chips and components in one package to achieve a complete function. System-level packaging is a new type of packaging technology with advantages such as short development cycle, more functions, lower power consumption, better performance, lower cost, smaller size, and light weight.

[0004] However, in existing packaging components, the size of the packaging component is large, the wire bonding route is long, and the integration degree is low. Summary of the Invention

[0005] To solve the above problems existing in the semiconductor packaging components of the prior art, this application provides a packaging component, an electronic device, and a packaging method.

[0006] To solve the above problems, an embodiment of this application provides a packaging component, which includes: a substrate;

[0007] A first semiconductor chip disposed on the substrate, and the first semiconductor chip is electrically connected to the substrate;

[0008] A packaged chip disposed on the substrate and adjacent to the first semiconductor chip, and the packaged chip is electrically connected to the substrate;

[0009] A first molding compound for encapsulating the substrate, the first semiconductor chip, and the packaged chip.

[0010] To solve the above technical problems, this application also provides an electronic device, which includes the above packaging component.

[0011] To solve the above technical problems, this application also provides a packaging method, which includes:

[0012] Providing a substrate;

[0013] A first semiconductor chip is disposed on the substrate, and the first semiconductor chip is electrically connected to the substrate;

[0014] An encapsulated chip is disposed on the substrate, adjacent to the first semiconductor chip. The encapsulated chip is electrically connected to the first semiconductor chip and the encapsulated chip is electrically connected to the substrate;

[0015] The substrate, the first semiconductor chip and the encapsulated chip are encapsulated by a first molding compound.

[0016] Compared with the prior art, the encapsulation component of the present application includes: a substrate, an encapsulated chip, a first semiconductor chip and a first molding compound. The first semiconductor chip is disposed on the substrate and the first semiconductor chip is electrically connected to the substrate. The encapsulated chip is disposed on the substrate, adjacent to the first semiconductor chip, and the encapsulated chip is electrically connected to the substrate; the substrate, the first semiconductor chip and the encapsulated chip are encapsulated by the first molding compound. Therefore, the encapsulated chip provided in the present application is disposed adjacent to the first semiconductor chip on the same substrate, which can reduce the encapsulation size of the substrate; and, the encapsulated substrate, the first semiconductor chip and the encapsulated chip are encapsulated into an encapsulation component by the first molding compound, which can reduce the length between the electrical connection wires, reduce the occurrence probability of adverse phenomena such as signal attenuation, crosstalk, and parasitic capacitance in the wires, and improve the integration degree. Description of the Drawings

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0018] Figure 1 is a schematic structural diagram of an embodiment of the encapsulation component provided by the present application;

[0019] Figure 2 is Figure 1 a partial enlarged view of an embodiment of the first semiconductor chip in

[0020] Figure 3 is Figure 1 a partial enlarged view of another embodiment of the first semiconductor chip in

[0021] Figure 4 is a schematic flow chart of the encapsulation method provided by the present application.

[0022] The reference numerals are: encapsulation component 10; substrate 100; first semiconductor chip 200; encapsulated chip 300; first molding compound 400; chip body 210; redistribution layer 220; first surface 221; second surface 222; first pad 230; second pad 240; connection line 250; heat conducting member 260; first filling adhesive 510; second filling adhesive 520; first solder ball 310; second solder ball 110. Detailed implementation manners

[0023] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. It can be understood that the specific embodiments described herein are only used to explain the present application, rather than limiting the present application. In addition, it should be noted that for the convenience of description, only part of the structures related to the present application are shown in the drawings, rather than all the structures. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present application.

[0024] The terms "first", "second", and "third" in the present application are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first", "second", and "third" may explicitly or implicitly include at least one of such features. In the description of the present application, the meaning of "a plurality" is at least two, such as two, three, etc., unless otherwise specifically defined. All directional indications (such as up, down, left, right, front, back...) in the embodiments of the present application are only used to explain the relative positional relationship and movement conditions between components in a specific posture (as shown in the drawings). If the specific posture changes, the directional indications will also change accordingly. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but optionally further includes steps or units not listed, or optionally further includes other steps or units inherent to these processes, methods, products, or devices.

[0025] Referring to "embodiment" herein means that a specific feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application. The phrase appears in various places in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0026] See Figure 1 , Figure 1It is a schematic structural diagram of an embodiment of the encapsulation component 10 provided by the present application.

[0027] The present application provides an encapsulation component 10, which may include a substrate 100, a first semiconductor chip 200, an encapsulated chip 300, and a first molding compound 400.

[0028] The first semiconductor chip 200 may be disposed on the substrate 100, and the first semiconductor chip 200 is electrically connected to the substrate 100. Specifically, in one embodiment, the first semiconductor chip 200 may be a flip chip, and the first semiconductor chip 200 is disposed on the substrate 100 by means of chip bonding, and the first semiconductor chip 200 is electrically connected to the substrate 100. In another embodiment, the first semiconductor chip 200 may be electrically connected to the substrate 100 by means of wire bonding.

[0029] The encapsulated chip 300 may be disposed on the substrate 100, and the encapsulated chip 300 may be disposed adjacent to the first semiconductor chip 200, and the encapsulated chip 300 is electrically connected to the substrate 100.

[0030] The first molding compound 400 may be used to encapsulate the first semiconductor chip 200, the encapsulated chip 300, and the substrate 100.

[0031] Therefore, both the first semiconductor chip 200 and the encapsulated chip 300 of the encapsulation component 10 provided by the present application are disposed on the same substrate 100, and the first semiconductor chip 200 and the encapsulated chip 300 are disposed adjacent to each other, which can reduce the encapsulation size of the substrate 100, and further reduce the size of the encapsulation component 10. Moreover, by encapsulating the substrate 100, the first semiconductor chip 200, and the encapsulated chip 300 into an encapsulation component 10 with the first molding compound 400, the length between the electrical connection wires can be reduced, and the probabilities of occurrence of adverse phenomena such as signal attenuation, crosstalk, and parasitic capacitance in the wires can be reduced, and the integration degree can be improved.

[0032] See Figure 1 , the present application provides an encapsulation component 10.

[0033] The encapsulation component 10 may include a substrate 100. The substrate 100 may be made of the same material as that in the prior art. For example, the substrate 100 may be formed of a semiconductor material, and the semiconductor material is silicon, such as an organic material of bismaleimidetriazine (BT), polyimide, or Ajinomotobuild-up film (ABF).

[0034] The encapsulation component 10 may further include a first semiconductor chip 200, which may be disposed on the substrate 100 and electrically connected to the substrate 100.

[0035] The first semiconductor chip 200 may be a processor that performs logical operations on data. For example, the first semiconductor chip 200 may include a system - on - chip (SoC) such as an application processor that performs logical operations.

[0036] See Figure 1 、 Figure 2 and Figure 3 , Figure 2 is Figure 1 a partial enlarged view of an embodiment of the first semiconductor chip 200 in Figure 3 is Figure 1 a partial enlarged view of another embodiment of the first semiconductor chip 200 in

[0037] The first semiconductor chip 200 may include a chip body 210 and a redistribution layer 220. The redistribution layer 220 has a first surface 221 and a second surface 222 disposed opposite to each other, and the first surface 221 of the redistribution layer 220 is disposed on the surface of the chip body 210 closer to the substrate 100.

[0038] Specifically, the first surface 221 of the redistribution layer 220 may be closely attached to the surface of the chip body 210 closer to the substrate 100.

[0039] The second surface 222 of the redistribution layer 220 may be disposed parallel to the first surface 221 so that the first semiconductor chip 200 can be stably placed on the substrate 100.

[0040] The first semiconductor chip 200 may further include a first pad 230, which is disposed between the surface of the chip body 210 closer to the substrate 100 and the first surface 221 of the redistribution layer 220.

[0041] Refer to Figure 2 In one embodiment, the first pad 230 may be disposed on the surface where the chip body 210 contacts the first surface 221 of the redistribution layer 220, and the first pad 230 may be exposed on the surface where the chip body 210 contacts the first surface 221. The portion of the first pad 230 exposed on the surface where the chip body 210 contacts the first surface 221 may be located within the redistribution layer 220.

[0042] See Figure 3, in another embodiment, the first pad 230 may be embedded in the chip body 210, and the surface of the first pad 230 close to the first surface 221 of the redistribution layer 220 may be on the same horizontal plane as the surface of the chip body 210 close to the first surface 221 of the redistribution layer 220.

[0043] In one embodiment, the first pad 230 may be embedded in the chip body 210, and the first pad 230 may be partially exposed on the surface of the chip body 210 close to the first surface 221 of the redistribution layer 220. The portion of the first pad 230 exposed on the surface of the chip body 210 in contact with the first surface 221 may be located within the redistribution layer 220.

[0044] See Figures 1 - 3 , the first semiconductor chip 200 may further include a second pad 240, and the second pad 240 is disposed on the second surface 222 of the redistribution layer 220.

[0045] Specifically, the second pad 240 may be embedded in the redistribution layer 220, and the surface of the second pad 240 close to the second surface 222 of the redistribution layer 220 may be on the same horizontal plane as the second surface 222 of the redistribution layer 220, so that the first semiconductor chip 200 can be stably placed on the substrate 100.

[0046] In other embodiments, the second pad 240 may also be partially exposed on the second surface 222 of the redistribution layer 220.

[0047] The first semiconductor chip 200 may further include a connection line 250. The connection line 250 may be disposed in the redistribution layer 220, one end of the connection line 250 is connected to the first pad 230, and the other end of the connection line 250 may be connected to the second pad 240, so that the first semiconductor chip 200 can be electrically connected to the substrate 100 through the first pad 230, the second pad 240 and the connection line 250. Among them, the connection line 250 may include a gold wire, a copper wire, an alloy wire, etc.

[0048] Therefore, the first semiconductor chip 200 can form a flip chip together with the chip body 210, the redistribution layer 220, the first pad 230, the second pad 240, and the connection line 250. Compared with the wiring method of wire bonding in the prior art, the first semiconductor chip 200 can be disposed on the substrate 100 by means of chip mounting, which can effectively improve the yield rate of the packaging component 10. And when the first semiconductor chip 200 is disposed on the substrate 100, the second surface 222 of the redistribution layer 220 can be in contact with the surface of the substrate 100 close to the first semiconductor chip 200, and the first semiconductor chip 200 can be electrically connected to the substrate 100 through the first pad 230, the second pad 240, and the connection line 250 located in the redistribution layer 220, which can further reduce the length of the connection line 250 and greatly reduce the occurrence probability of adverse phenomena such as signal attenuation, crosstalk, and parasitic capacitance in the connection line 250.

[0049] See Figures 1 - 3 , the packaging component 10 may further include a heat conducting member 260, the heat conducting member 260 is disposed on the second pad 240, and the heat conducting member 260 may be exposed on the second surface 222 of the redistribution layer 220.

[0050] Specifically, when the heat conducting member 260 is disposed on the second surface 222 of the redistribution layer 220 and the heat conducting member 260 is exposed on the second surface 222 of the redistribution layer 220, when the first semiconductor chip 200 is disposed on the substrate 100, the heat conducting member 260 can be in contact with the substrate 100, and the heat generated when the first semiconductor chip 200 operates can be conducted to the substrate 100 through the heat conducting member 260, improving the heat dissipation effect of the first semiconductor chip 200.

[0051] The cross-sectional shape of the end of the heat conducting member 260 away from the second pad 240 may be arc-shaped, so as to reduce the contact area between the heat conducting member 260 and the substrate 100 when the first semiconductor chip 200 is disposed on the substrate 100. In other embodiments, the heat conducting member 260 may have different geometric shapes such as a conical shape or a columnar shape.

[0052] The heat conducting member 260 may be a metal heat conducting member 260. For example, the metal heat conducting member 260 may be a metal heat conducting element such as a solder ball or a copper column.

[0053] See Figure 1 , the packaging component 10 may further include a first encapsulant 510, the first encapsulant 510 may be disposed between the first semiconductor chip 200 and the substrate 100, so as to fill the gap between the first semiconductor chip 200 and the substrate 100 through the first encapsulant 510, thereby effectively preventing defects such as voids and bubbles from occurring between the first semiconductor chip 200 and the substrate 100 through the first encapsulant 510.

[0054] The encapsulation component 10 may further include an encapsulated chip 300. The encapsulated chip 300 may be disposed on the substrate 100, adjacent to the first semiconductor chip 200, and the encapsulated chip 300 may be electrically connected to the substrate 100. In this way, the encapsulated chip 300 and the first semiconductor chip 200 are disposed adjacent to each other on the same substrate 100, which can reduce the encapsulation size of the substrate 100 and further reduce the size of the encapsulation component 10.

[0055] The encapsulated chip 300 may include at least two second semiconductor chips (not shown in the figure). Among them, the second semiconductor chip may be a memory semiconductor chip for storing data. The memory semiconductor chip may be a cache memory chip that temporarily stores and provides data used in the logical operations of a system-on-chip (SoC).

[0056] Specifically, at least two second semiconductor chips may be encapsulated in a ball grid array (BGA) encapsulation manner to form the encapsulated chip 300. The encapsulated chip 300 is encapsulated in a BGA manner and directly disposed on the substrate 100. The solder balls or solder bumps near the surface of the substrate 100 of the encapsulated chip 300 are used as external leads, so that the encapsulated chip 300 is electrically connected to the substrate 100.

[0057] In this embodiment, the encapsulated chip 300 adopts a standard BGA encapsulation, and second semiconductor chips of different storage types can be encapsulated into the encapsulated chip 300 to save the encapsulation cost. For example, different types of memory chips may include volatile memory chips and / or non-volatile memory chips. Volatile memory chips may include, for example, dynamic random-access memory (DRAM), static random-access memory (SRAM), thyristor random-access memory (TRAM), zero capacitor random-access memory (ZRAM), etc. Non-volatile memory chips may include, for example, flash memory, magnetic random-access memory (MRAMO), spin-transfer torque MRAM (STT-MRAM), ferroelectric random-access memory (FRAM), phase change random-access memory (PRAM), resistive random-access memory (RRAM), etc.

[0058] Among them, at least two second semiconductor chips can be stacked, or at least two second semiconductor chips can be arranged in parallel.

[0059] Specifically, at least two second semiconductor chips can include two second semiconductor chips, and the two semiconductor chips can be stacked or arranged in parallel to increase the storage capacity of the packaged chip 300.

[0060] In an embodiment of the present application, at least two second semiconductor chips can include four second semiconductor chips, and the four second semiconductor chips can be stacked to increase the storage capacity of the packaged chip 300. Compared with the existing flat arrangement of multiple semiconductor chips, the size of the packaging substrate 100 is reduced.

[0061] In an embodiment of the present application, at least two second semiconductor chips can include six second semiconductor chips, and the six second semiconductor chips can be stacked to increase the storage capacity of the packaged chip 300. Compared with the existing flat arrangement of multiple semiconductor chips, the size of the packaging substrate 100 is reduced.

[0062] In an embodiment, at least two semiconductor chips can include eight second semiconductor chips, and the eight second semiconductor chips can be stacked to increase the storage capacity of the packaged chip 300. Compared with the existing flat arrangement of multiple semiconductor chips, the size of the packaging substrate 100 is reduced.

[0063] The packaged chip 300 may further include a second molding compound. The second molding compound can be used to package at least two second semiconductor chips to form the packaged chip 300.

[0064] Among them, the second molding compound can be made of the same material as in the prior art. For example: the second molding compound can be formed by epoxy resin, resin, moldable polymer, etc. The material of the second molding compound is not limited in this application.

[0065] The packaging component 10 further includes a first solder ball 310, and the first solder ball 310 is disposed on the surface of the packaged chip 300 close to the substrate 100. In this embodiment, the packaged chip 300 uses the Ball Grid Array packaging method to package at least two second semiconductor chips to form the packaged chip 300, so that the first solder ball 310 is used as the external lead of the packaged chip 300 to electrically connect the packaged chip 300 to the substrate 100.

[0066] The encapsulation component 10 may further include a second filling adhesive 520. The second filling adhesive 520 may be disposed between the encapsulated chip 300 and the substrate 100 to fill the gap between the first solder balls 310 and the substrate 100 through the second filling adhesive 520, so as to effectively prevent defects such as voids and bubbles from appearing between the encapsulated chip 300 and the substrate 100 through the second filling adhesive 520.

[0067] The encapsulation component 10 further includes second solder balls 110. The second solder balls 110 may be disposed on the surface of the substrate 100 away from the encapsulated chip 300 and away from the first semiconductor chip 200.

[0068] The encapsulation component 10 may further include a first molding compound 400. The first molding compound 400 may be used to encapsulate the first semiconductor chip 200, the encapsulated chip 300, and the substrate 100. Among them, the first molding compound 400 may adopt the same material as the second molding compound, which will not be elaborated here.

[0069] Therefore, the encapsulation component 10 provided in this application encapsulates multiple second semiconductor chips through BGA into an encapsulated chip 300 to expand the storage capacity of the encapsulated chip 300. Compared with the existing flat arrangement of multiple semiconductor chips, the size of the encapsulation substrate 100 is reduced. The first semiconductor chip 200 and the encapsulated chip 300 are both disposed on the same substrate 100, and the first semiconductor chip 200 and the encapsulated chip 300 are adjacent to each other, which can reduce the encapsulation size of the substrate 100, and further reduce the size of the encapsulation component 10. Moreover, the first semiconductor chip 200 forms a flip chip through the chip body 210, the redistribution layer 220, the first pad 230, the second pad 240, and the connection line 250. Compared with the wiring method of wire bonding in the prior art, the first semiconductor chip 200 can be disposed on the substrate 100 by means of chip mounting, which can effectively improve the yield rate of the encapsulation component 10. And the first semiconductor chip 200 is disposed on the substrate 100, the second surface 222 of the redistribution layer 220 can be in contact with the surface of the substrate 100 close to the first semiconductor chip 200, and the first semiconductor chip 200 is electrically connected to the substrate 100 through the first pad 230, the second pad 240, and the connection line 250 located in the redistribution layer 220, which can reduce the length of the connection line 250 and greatly reduce the occurrence probability of signal attenuation, crosstalk, and parasitic capacitance in the connection line 250 and other adverse phenomena. And the encapsulation substrate 100, the first semiconductor chip 200, and the encapsulated chip 300 are encapsulated into an encapsulation component 10 through the first molding compound 400, which can further reduce the length between the electrical connection wires compared with the prior art, reduce the occurrence probability of signal attenuation, crosstalk, parasitic capacitance in the wire and other adverse phenomena, and improve the integration degree.

[0070] The present application also provides an electronic device, which includes the encapsulation component 10 in any of the above embodiments. In different embodiments, the electronic device includes but is not limited to a cellular phone, a smart phone, other wireless communication devices, a personal digital assistant, an audio player, other media players, a music recorder, a video recorder, a camera, other media recorders, a radio, a medical device, a calculator, a programmable remote control, a pager, a netbook computer, a personal digital assistant (PDA), a portable multimedia player (PMP), a Moving Picture Experts Group (MPEG-1 or MPEG-2) Audio Layer 3 (MP3) player, a portable medical device, and a digital camera, and combinations thereof.

[0071] See Figure 4 , Figure 4 is a schematic flow chart of the encapsulation method provided by the present application.

[0072] The present application also provides an encapsulation method, which includes:

[0073] Step S101: Provide a substrate 100.

[0074] The substrate 100 can be made of the same materials as those in the prior art. For example, the substrate 100 can be formed of a semiconductor material, which is silicon, such as an organic material of bismaleimide triazine (BT), polyimide, or Ajinomotobuild-up film (ABF).

[0075] Step S102: Dispose a first semiconductor chip 200 on the substrate 100 and electrically connect the first semiconductor chip 200 to the substrate 100.

[0076] The first semiconductor chip 200 can be a processor that performs logical operations on data. For example, the first semiconductor chip 200 can include a system-on-chip (SoC) such as an application processor that performs logical operations.

[0077] Further, the first semiconductor chip 200 can include a chip body 210. Before step S102, the method can further include:

[0078] Dispose a redistribution layer 220 on the surface of the chip body 210 close to the substrate 100. The redistribution layer 220 has a first surface 221 and a second surface 222 that are oppositely disposed.

[0079] The first surface 221 of the redistribution layer 220 can be closely attached to the surface of the chip body 210 close to the substrate 100.

[0080] The second surface 222 of the redistribution layer 220 may be arranged parallel to the first surface 221 so that the first semiconductor chip 200 can be placed stably on the substrate 100.

[0081] The first semiconductor chip 200 may further include a first pad 230, and the first pad 230 is disposed between the surface of the chip body 210 close to the substrate 100 and the first surface 221 of the redistribution layer 220.

[0082] Participate Figure 2 , in one embodiment, the first pad 230 may be disposed on the surface where the chip body 210 contacts the first surface 221 of the redistribution layer 220, and the first pad 230 may be exposed on the surface where the chip body 210 contacts the first surface 221. The part of the first pad 230 exposed on the surface where the chip body 210 contacts the first surface 221 may be located within the redistribution layer 220.

[0083] See Figure 3 , in another example, the first pad 230 may be embedded in the chip body 210, and the surface of the first pad 230 close to the first surface 221 of the redistribution layer 220 may be on the same horizontal plane as the surface of the chip body 210 close to the first surface 221 of the redistribution layer 220.

[0084] In one embodiment, the first pad 230 may be embedded in the chip body 210, and the first pad 230 may be partially exposed on the surface of the chip body 210 close to the first surface 221 of the redistribution layer 220. The part of the first pad 230 exposed on the surface where the chip body 210 contacts the first surface 221 may be located within the redistribution layer 220.

[0085] See Figures 1 - 3 , the first semiconductor chip 200 may further include a second pad 240, and the second pad 240 is disposed on the second surface 222 of the redistribution layer 220.

[0086] Specifically, the second pad 240 may be embedded in the redistribution layer 220, and the surface of the second pad 240 close to the second surface 222 of the redistribution layer 220 may be on the same horizontal plane as the second surface 222 of the redistribution layer 220, so that the first semiconductor chip 200 can be placed stably on the substrate 100.

[0087] In other embodiments, the second pad 240 may also be partially exposed on the second surface 222 of the redistribution layer 220.

[0088] The first semiconductor chip 200 may further include a connection line 250. The connection line 250 may be disposed within the redistribution layer 220. One end of the connection line 250 is connected to the first pad 230, and the other end of the connection line 250 may be connected to the second pad 240, so that the first semiconductor chip 200 can be electrically connected to the substrate 100 through the first pad 230, the second pad 240, and the connection line 250. Among them, the connection line 250 may include a gold wire, a copper wire, an alloy wire, etc.

[0089] Further, after the redistribution layer 220 is disposed on the surface of the chip body 210 close to the substrate 100, the method may further include: disposing a heat conducting member 260 on the second pad 240. The heat conducting member 260 may be exposed on the second surface 222 of the redistribution layer 220.

[0090] Further, after step S102, the method may further include: disposing a first encapsulating adhesive 510 between the first semiconductor chip 200 and the substrate 100.

[0091] In this embodiment, the gap between the first semiconductor chip 200 and the substrate 100 can be filled with the first encapsulating adhesive 510, so that defects such as voids and bubbles between the first semiconductor chip 200 and the substrate 100 can be effectively prevented through the first encapsulating adhesive 510.

[0092] Step S103: Dispose a packaged chip 300 on the substrate 100, adjacent to the first semiconductor chip 200. The packaged chip 300 is electrically connected to the first semiconductor chip 200 and electrically connects the packaged chip 300 to the substrate 100.

[0093] The packaged chip 300 may include at least two second semiconductor chips (not shown in the figure). Among them, the second semiconductor chip may be a memory semiconductor chip for storing data. The memory semiconductor chip may be a cache memory chip, which temporarily stores and provides data used in the logical operations of a system-on-chip (SoC).

[0094] Further, before step S103, the method may further include: packaging at least two second semiconductor chips by a ball grid array (BGA) packaging method to form the packaged chip 300.

[0095] The packaged chip 300 adopts the ball grid array packaging method and is directly disposed on the substrate 100. By using the solder balls or solder bumps on the surface of the packaged chip 300 close to the substrate 100 as external leads, the packaged chip 300 is electrically connected to the substrate 100. Further, after at least two second semiconductor chips are packaged in the ball grid array (Ball Grid Array) packaging method to form the packaged chip 300 in step, the method may further include: implanting first solder balls 310 on the surface of the packaged chip 300 close to the substrate 100.

[0096] In this embodiment, the packaged chip 300 packages at least two second semiconductor chips in the ball grid array (Ball Grid Array) packaging method to form the packaged chip 300, so as to use the first solder balls 310 as the external leads of the packaged chip 300, so that the packaged chip 300 is electrically connected to the substrate 100.

[0097] Further, after step S103, the method may further include: disposing a second filling adhesive 520 between the packaged chip 300 and the substrate 100. Thus, the gap between the first solder balls 310 and the substrate 100 can be filled by the second filling adhesive 520, and thus defects such as voids and bubbles between the packaged chip 300 and the substrate 100 can be effectively prevented by the second filling adhesive 520.

[0098] Step S104: Package the substrate 100, the first semiconductor chip 200, and the packaged chip 300 with the first molding compound 400.

[0099] Further, after step S104, the method may further include: implanting second solder balls 110 on the surface of the substrate 100 away from the packaged chip 300.

[0100] Therefore, the encapsulation component 10 formed by the encapsulation method provided in this application encapsulates multiple second semiconductor chips through BGA to form an encapsulation chip 300, so as to expand the storage capacity of the encapsulation chip 300. Compared with the existing flat setting of multiple semiconductor chips, the size of the encapsulation substrate 100 is reduced. The first semiconductor chip 200 and the encapsulation chip 300 are both disposed on the same substrate 100, and the first semiconductor chip 200 and the encapsulation chip 300 are disposed adjacent to each other, which can reduce the encapsulation size of the substrate 100, and further reduce the size of the encapsulation component 10. Moreover, the first semiconductor chip 200 forms a flip chip through the chip body 210, the redistribution layer 220, the first pad 230, the second pad 240, and the second pad 240. Compared with the wiring method of wire bonding in the prior art, the first semiconductor chip 200 can be disposed on the substrate 10 by means of chip mounting, which can effectively improve the yield rate of the encapsulation component 10. And the first semiconductor chip 200 is disposed on the substrate 100, the second surface 222 of the redistribution layer 220 can be in contact with the surface of the substrate 100 close to the first semiconductor chip 200, and the first semiconductor chip 200 is electrically connected to the substrate 100 through the first pad 230, the second pad 240, and the connection line 250 located in the redistribution layer 220, which can reduce the length of the connection line 250 and greatly reduce the occurrence probability of adverse phenomena such as signal attenuation, crosstalk, and parasitic capacitance in the connection line 250. And the encapsulation substrate 100, the first semiconductor chip 200, and the encapsulation chip 300 are encapsulated into an encapsulation component 10 by the first molding compound 400. Compared with the prior art, the length between the electrical connection wires can be further reduced, the occurrence probability of adverse phenomena such as signal attenuation, crosstalk, and parasitic capacitance in the bonding wires can be reduced, and the integration degree can be improved.

[0101] In this article, specific examples are used to elaborate on the principle and implementation manner of this application. The description of the above embodiments is only used to help understand the method and its core idea of this application; at the same time, for those of ordinary skill in the art, according to the idea of this application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to this application.

Claims

1. An encapsulation component, characterized in that, The encapsulation component includes: A substrate; A first semiconductor chip, disposed on the substrate, the first semiconductor chip being electrically connected to the substrate, wherein the first semiconductor chip is disposed on the substrate by means of chip bonding; An encapsulated chip, disposed on the substrate and adjacent to the first semiconductor chip, the encapsulated chip being electrically connected to the substrate; A first molding compound for encapsulating the substrate, the first semiconductor chip, and the encapsulated chip; Wherein, the first semiconductor chip includes: A chip body; A redistribution layer having a first surface and a second surface disposed opposite to each other, the first surface of the redistribution layer being disposed on the surface of the chip body closer to the substrate; A first pad, disposed between the surface of the chip body closer to the substrate and the first surface of the redistribution layer, the first pad being embedded in the chip body, and the surface of the first pad closer to the first surface of the redistribution layer and the surface of the chip body closer to the first surface of the redistribution layer being located on the same horizontal plane; A second pad, disposed on the second surface of the redistribution layer; A connection line, disposed in the redistribution layer, one end of the connection line being connected to the first pad and the other end being connected to the second pad, so that the first semiconductor chip is electrically connected to the substrate through the first pad, the second pad, and the connection line.

2. The encapsulation component according to claim 1, characterized in that, The encapsulation component further includes: A heat conducting member, disposed on the second pad and exposed on the second surface of the redistribution layer.

3. The encapsulation component according to claim 2, wherein The encapsulation component further includes: A first filling adhesive, disposed between the first semiconductor chip and the substrate.

4. The packaging assembly according to claim 1, wherein: The encapsulated chip includes: At least two second semiconductor chips, the at least two second semiconductor chips being stacked or adjacent to each other; A second molding compound for encapsulating the at least two second semiconductor chips.

5. The encapsulation component according to claim 4, characterized in that, The encapsulated chip includes: A first solder ball, disposed on the surface of the encapsulated chip closer to the substrate.

6. The packaging assembly according to claim 5, wherein: The encapsulated chip includes: A second filling adhesive, disposed between the encapsulated chip and the substrate.

7. The encapsulation component according to any one of claims 1-6, characterized in that, The encapsulated chip includes: A second solder ball, disposed on the surface of the substrate away from the encapsulated chip and away from the first semiconductor chip.

8. An electronic device, characterized in that: The electronic device includes the encapsulation component according to any one of claims 1-7.

9. An encapsulation method, characterized in that: Providing a substrate; Disposing a first semiconductor chip on the substrate and electrically connecting the first semiconductor chip to the substrate, wherein the first semiconductor chip is disposed on the substrate by means of chip bonding; Disposing an encapsulated chip on the substrate, adjacent to the first semiconductor chip, electrically connecting the encapsulated chip to the first semiconductor chip, and electrically connecting the encapsulated chip to the substrate; Encapsulating the substrate, the first semiconductor chip, and the encapsulated chip with a first molding compound; Wherein, the first semiconductor chip includes: A chip body; A redistribution layer having a first surface and a second surface disposed opposite to each other, the first surface of the redistribution layer being disposed on the surface of the chip body closer to the substrate; a first pad disposed between a surface of the chip body close to the substrate and the first surface of the redistribution layer, wherein the first pad is embedded in the chip body, and a surface of the first pad close to the first surface of the redistribution layer and a surface of the chip body close to the first surface of the redistribution layer are located at the same level; A second pad is provided on the second surface of the redistribution layer; A connecting wire is arranged in the redistribution layer, one end of the connecting wire is connected to the first pad, and the other end is connected to the second pad, so that the first semiconductor chip is electrically connected to the substrate through the first pad, the second pad and the connecting wire.

Images