Storage device and control device and control method thereof

Abstract

The embodiment of the present invention discloses a storage device and a control device and a control method thereof. The storage device also includes a plurality of storage units. The control device includes: an execution module, the execution module is used to execute a first operation and generate a first clock control signal in the first operation stage; a clock module, the clock module is used to switch the clock frequency to a first clock frequency less than a preset clock frequency according to the first clock control signal. In the embodiment of the present invention, the higher the clock frequency, the greater the clock power consumption. The clock frequency of the clock module is not fixed, but the clock frequency is reduced in the first operation stage, so that the clock power consumption in the first operation stage is reduced, which correspondingly reduces the number of times the clock counter is used, improves the flexibility of the clock operation, and improves the problem of excessive power consumption in the operation stage.

Description

Technical Field

[0001] The embodiments of the present invention relate to storage technology, and in particular to a storage device and a control device and a control method thereof. Background Art

[0002] Nand flash memory is a type of flash memory that uses a nonlinear macrocell mode inside, providing a cheap and effective solution for the implementation of solid-state large-capacity memory. Nand flash memory has the advantages of large capacity and fast rewrite speed, and is suitable for storing large amounts of data. Therefore, it has been increasingly widely used in the industry, such as embedded products including digital cameras, MP3 player memory cards, and compact USB flash drives.

[0003] Nand flash has a clock inside, which is used to record the time of read, write and erase operations, so as to obtain the read, write and erase speed. At present, when Nand flash performs an erase operation, the internal clock keeps flipping during the entire erase process, which consumes a lot of power. Summary of the invention

[0004] The embodiment of the present invention provides a storage device and a control apparatus and a control method thereof to reduce clock power consumption.

[0005] An embodiment of the present invention provides a control device for a storage device, wherein the storage device further includes a plurality of storage units, and the control device includes:

[0006] An execution module, the execution module is used to execute a first operation and generate a first clock control signal in a first operation phase;

[0007] A clock module is used to switch the clock frequency to a first clock frequency less than a preset clock frequency according to the first clock control signal.

[0008] Furthermore, the execution module is further configured to execute the first operation and generate a second clock control signal during the first operation verification phase to enable the clock module to switch to the preset clock frequency.

[0009] Furthermore, the preset clock frequency is n times the first clock frequency, where n is a positive integer.

[0010] Furthermore, n=2 or 4.

[0011] Further, the first operation is an erase operation, and the first operation phase is an erase phase; or, the first operation is a program operation, and the first operation phase is a program phase.

[0012] Based on the same inventive concept, an embodiment of the present invention further provides a control method for a storage device, wherein the storage device further includes a plurality of storage units, and the control method includes:

[0013] Executing a first operation and generating a first clock control signal in a first operation phase;

[0014] According to the first clock control signal, the clock frequency is switched to a first clock frequency that is less than a preset clock frequency.

[0015] Furthermore, the control method further includes: generating a second clock control signal during the first operation verification phase;

[0016] According to the second clock control signal, the clock frequency is switched to the preset clock frequency.

[0017] Furthermore, the preset clock frequency is n times the first clock frequency, where n is a positive integer.

[0018] Furthermore, n=2 or 4.

[0019] Further, the first operation is an erase operation, and the first operation phase is an erase phase; or, the first operation is a program operation, and the first operation phase is a program phase.

[0020] Based on the same inventive concept, an embodiment of the present invention further provides a storage device, including:

[0021] one or more processors;

[0022] A storage module, used for storing one or more programs;

[0023] When the one or more programs are executed by the one or more processors, the one or more processors implement the control method of the storage device as described above.

[0024] In an embodiment of the present invention, the execution module is used to execute the first operation and generate a first clock control signal in the first operation stage; the clock module is used to switch the clock frequency to a first clock frequency less than the preset clock frequency according to the first clock control signal. In an embodiment of the present invention, the higher the clock frequency, the greater the clock power consumption. The clock frequency of the clock module is not fixed, but the clock frequency is reduced in the first operation stage, so that the clock power consumption in the first operation stage is reduced, and the number of times the clock counter is used is correspondingly reduced, the flexibility of the clock operation is improved, and the problem of excessive power consumption in the first operation stage is improved, which is particularly suitable for improving the problem of excessive power consumption in the erasing stage. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0026] Figure 1 is a schematic diagram of a storage device provided by an embodiment of the present invention;

[0027] Figure 2 is a schematic diagram of a control device for a storage device provided by an embodiment of the present invention;

[0028] Figure 3 is a schematic diagram of a storage unit of a storage device provided in an embodiment of the present invention;

[0029] Figure 4 is a schematic diagram of different clock frequencies of storage devices;

[0030] Figure 5 It is a schematic diagram of a control device of a storage device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described through implementation methods with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0032] refer to Figure 1 FIG. 1 is a schematic diagram of a storage device provided by an embodiment of the present invention, referring to FIG. Figure 2 As shown, it is a schematic diagram of a control device of a storage device provided in an embodiment of the present invention. The storage device provided in this embodiment may be a flash memory, such as Nand flash. The storage device provided in this embodiment also includes a plurality of storage units 1, and the storage unit 1 may be the smallest storage unit in the storage device, for example, the storage unit is a page storage unit of Nand flash. The control device 2 in the storage device performs an operation on the storage unit 1 according to the operation command, and the control device 2 may be implemented by software and / or hardware.

[0033] A control device for a storage device provided in this embodiment includes: an execution module 10, which is used to execute a first operation and generate a first clock control signal in a first operation stage; a clock module 20, which is used to switch the clock frequency to a first clock frequency less than a preset clock frequency according to the first clock control signal.

[0034] In this embodiment, the first operation includes a first operation phase and a first operation verification phase, and the first operation may be an erase operation or a program operation.

[0035] The first operation can be an erase operation, and the first operation stage is an erase stage. Correspondingly, the first operation verification stage is an erase verification stage. Taking the case where the first operation is an erase operation as an example, in this embodiment, an erase operation includes at least one group of erase stages and erase verification stages. The erase stage is marked as loop, and the erase verification stage is marked as evfy. Each erase stage is followed by an erase verification stage. An erase operation includes multiple erase stages and multiple erase verification stages. In the erase stage, the execution module 10 is used to erase the data of the storage unit to be erased; in the erase verification stage, the execution module 10 is used to verify the storage unit that has been erased to verify whether the erasure is successful. Taking an erase operation of Nand flash as an example, Figure 3 The storage unit of the Nand flash shown includes a floating gate FG, a control gate CG, a source source, a drain drain and a substrate substrate. After receiving an erase operation, it first enters the erase phase, and then enters the erase verification phase until the erase is successful. During the entire erase operation, the source and drain are in a floating state.

[0036] In the erase phase, a voltage close to 0V is applied to the word lines corresponding to all the memory cells to be erased, and a Vera voltage is applied to the substrates corresponding to all the memory cells to be erased. Since the Vera voltage applied to the substrate is a relatively high voltage, the electrons on the floating gate of the memory cell are eventually tunneled into the substrate. In the erase verification phase, it is verified whether the memory cell has been erased. If the verification result is a failure, it is switched to the erase phase, and the erase voltage is raised to Vera+△step to continue the erase operation. This is repeated until the erase verification is successful. An erase operation is completed. It should be noted that the erase phase takes a long time (usually at the ms level), and the erase verification time is shorter.

[0037] In this embodiment, the control device is pre-set with a preset clock frequency of the erasing operation, and different clock control signals are set according to different stages of the erasing. The execution module 10 performs the erasing operation after receiving the erasing command, and generates a first clock control signal during the erasing stage. The clock module 20 is used to switch the clock frequency to a first clock frequency that is less than the preset clock frequency according to the first clock control signal.

[0038] One clock cycle is one flip, and the number of clock flips per unit time is the clock frequency. In one erasing phase, the product of the total number of clock flips and the length of the clock cycle is the operation time of the erasing phase. In this embodiment, the clock module 20 is used to adjust the frequency of clock flips. In this embodiment, the clock module 20 switches the clock frequency to a first clock frequency that is less than the preset clock frequency according to the first clock control signal. This reduces the clock frequency in the erasing phase. It should be noted that the clock counter is used to count the number of clock flips. The clock and the clock counter are both integrated in the clock module 20.

[0039] The first operation can also be selected as a programming operation, and the first operation stage is a programming stage. Correspondingly, the first operation verification stage is a programming verification stage. Taking the first operation as a programming operation as an example, in this embodiment, a programming operation includes at least one group of programming stages and programming verification stages, and each programming stage is followed by a programming verification stage. A programming operation includes multiple programming stages and multiple programming verification stages. In the programming stage, the execution module 10 is used to program the storage cells to be programmed; in the programming verification stage, the execution module 10 is used to verify the storage cells that have been programmed to verify whether the programming is successful. Taking a programming operation of Nand flash as an example, after receiving the programming operation, it first enters the programming stage, and then enters the programming verification stage until the programming is successful.

[0040] In the programming phase, a higher voltage Vpgm (20V) is applied to the word lines corresponding to all the memory cells to be programmed, and a VSS voltage is applied to the substrates corresponding to all the memory cells to be programmed. Since Vpgm is much greater than VSS, the electrons on the substrate of the memory cells are eventually tunneled into the floating gate, and then the programming verification phase is entered; in the programming verification phase, it is verified whether the memory cells have been programmed. If the verification result is a failure, it is switched to the programming phase, and the word line voltage is controlled to be raised to Vpgm+△step to continue the programming operation, and this is repeated until the programming verification is successful. A programming operation is completed.

[0041] In this embodiment, a preset clock frequency of the programming operation is pre-set in the control device, and different clock control signals are set according to different stages of programming. The execution module 10 executes the programming operation after receiving the programming command, and generates a first clock control signal during the programming stage. The clock module 20 is used to switch the clock frequency to a first clock frequency less than the preset clock frequency according to the first clock control signal.

[0042] One clock cycle is one flip, and the number of clock flips per unit time is the clock frequency. In one programming phase, the product of the total number of clock flips and the length of the clock cycle time is the operation time of the programming phase. In this embodiment, the clock module 20 is used to adjust the frequency of clock flips. In this embodiment, the clock module 20 switches the clock frequency to a first clock frequency that is less than the preset clock frequency according to the first clock control signal. This reduces the clock frequency in the programming phase. It should be noted that the clock counter is used to count the number of clock flips. The clock and the clock counter are both integrated in the clock module 20.

[0043] It should be noted that when the first operation is different, the first clock frequency and the preset clock frequency may also be different, that is, the first clock frequency and the preset clock frequency corresponding to the erase operation may be different from the first clock frequency and the preset clock frequency corresponding to the programming operation. Relevant practitioners reasonably set the first clock frequency and the preset clock frequency according to the product operation, and no specific limitation is given here.

[0044] In this embodiment, the execution module is used to execute the first operation and generate a first clock control signal in the first operation stage; the clock module is used to switch the clock frequency to a first clock frequency less than the preset clock frequency according to the first clock control signal. In this embodiment, the higher the clock frequency, the greater the clock power consumption. The clock frequency of the clock module is not fixed, but the clock frequency is reduced in the first operation stage, so that the clock power consumption of the first operation stage is reduced, and the number of times the clock counter is used is correspondingly reduced, the flexibility of the clock operation is improved, and the problem of excessive power consumption in the first operation stage is improved, especially the problem of excessive power consumption in the erasing stage or the programming stage can be improved.

[0045] Exemplarily, on the basis of the above technical solution, the optional execution module is also used to execute the first operation and generate a second clock control signal to switch the clock module to a preset clock frequency during the first operation verification phase. Taking the first operation as an erase operation as an example, in this embodiment, the optional preset clock frequency corresponds to the erase verification phase, and when the storage unit is in the erase verification phase, the control switches to the preset clock frequency. In other embodiments, it is also optional that the execution module is also used to execute the erase operation and generate a second clock control signal during the erase verification phase to switch the clock module to a second clock frequency less than the preset clock frequency. It can be understood by those skilled in the art that the second clock frequency and the preset clock frequency are reasonably set frequencies of the clock module, and relevant practitioners can reasonably set the values ​​of the preset clock frequency and the second clock frequency according to the product requirements, which are not specifically limited in the present invention. When the first operation is a programming operation, the operation process is similar to the above process, but the specific parameters meet the parameter requirements of the programming operation.

[0046] Optionally, the preset clock frequency is n times the first clock frequency, where n is a positive integer. Optionally, n=2 or 4. Figure 4 As shown, n=2 or 4 can be selected. Taking the first operation as an erase operation as an example, the clock frequency is adjusted during the erase phase so that the first clock frequency is less than the preset clock frequency. Figure 4 As shown, the clock frequency of the first clock is fixed to the preset clock frequency; the clock frequency of the second clock is divided by 2 for the erasing stage E_clk, that is, the first clock frequency is 1 / 2 of the preset clock frequency, and the erasing verification stage evfy is the preset clock frequency; the clock frequency of the third clock is divided by 4 for the erasing stage, that is, the first clock frequency is 1 / 4 of the preset clock frequency, and the erasing verification stage is the preset clock frequency. Obviously, the control device provided in this embodiment has a small number of clock flips, which correspondingly reduces the clock power consumption. Those skilled in the art can understand that the specific value of the clock frequency and the multiples of different clock frequencies can be reasonably set and changed according to the product requirements, and are not specifically limited here. When the first operation is a programming operation, the operation process is similar to the above process, but the specific parameters meet the parameter requirements of the programming operation.

[0047] Based on the same inventive concept, an embodiment of the present invention further provides a control method for a storage device, wherein the storage device further comprises a plurality of storage units, and the control method for the storage device can be implemented by using the control device as described above. Figure 5 The control method of the storage device shown includes:

[0048] Step 110 , executing a first operation and generating a first clock control signal in a first operation phase.

[0049] Step 120: According to the first clock control signal, switch the clock frequency to a first clock frequency that is lower than the preset clock frequency.

[0050] Optionally, the control method further includes: generating a second clock control signal during the first operation verification phase; and switching the clock frequency to a preset clock frequency according to the second clock control signal.

[0051] Optionally, the preset clock frequency is n times the first clock frequency, where n is a positive integer. Optionally, n=2 or 4.

[0052] Optionally, the first operation is an erase operation, and the first operation phase is an erase phase; or, the first operation is a program operation, and the first operation phase is a program phase.

[0053] In this embodiment, when performing an erasing or programming operation, the erasing or programming clock is divided, for example, the clock of the erasing stage or the programming stage is divided by 2, 4, etc. The specific division setting can be set according to different situations. Compared with the prior art, since the clock frequency of the erasing stage or the programming stage is reduced, the power consumption of the erasing operation or the programming operation is reduced, and the use of the clock counter is also reduced, saving area.

[0054] Based on the same inventive concept, an embodiment of the present invention also provides a storage device, including: one or more processors; a storage module for storing one or more programs; when one or more programs are executed by one or more processors, the one or more processors implement the control method of the storage device described in any of the above embodiments.

[0055] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, combinations and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A control device for a storage device, characterized in that: The storage device further comprises a plurality of storage units, and the control device comprises: An execution module, the execution module is used to execute a first operation and generate a first clock control signal when the first operation phase starts; A clock module, the clock module being configured to switch a clock frequency to a first clock frequency that is less than a preset clock frequency according to the first clock control signal; Wherein, a preset clock frequency of the first operation is preset in the control device; The clock frequency is the number of clock flips per unit time, and one clock cycle is one flip; in a first operation phase, the product of the total number of clock flips and the length of the clock cycle is the operation time of the first operation phase; The execution module is further configured to execute the first operation and generate a second clock control signal during the first operation verification phase to enable the clock module to switch to the preset clock frequency.

2. The control device according to claim 1, characterized in that: The preset clock frequency is n times the first clock frequency, where n is a positive integer.

3. The control device according to claim 2, characterized in that: n=2 or 4.

4. The control device according to claim 1, characterized in that: The first operation is an erase operation, and the first operation phase is an erase phase; or, The first operation is a programming operation, and the first operation phase is a programming phase.

5. A method for controlling a storage device, characterized in that: The storage device further includes a plurality of storage units, and the control method includes: Performing a first operation and generating a first clock control signal at the beginning of the first operation phase; According to the first clock control signal, switching the clock frequency to a first clock frequency which is less than a preset clock frequency; Wherein, a preset clock frequency of the first operation is preset; The clock frequency is the number of clock flips per unit time, and one clock cycle is one flip; in a first operation phase, the product of the total number of clock flips and the length of the clock cycle is the operation time of the first operation phase; It also includes: generating a second clock control signal during the first operation verification phase; According to the second clock control signal, the clock frequency is switched to the preset clock frequency.

6. The control method according to claim 5, characterized in that: The preset clock frequency is n times the first clock frequency, where n is a positive integer.

7. The control method according to claim 6, characterized in that: n=2 or 4.

8. The control method according to claim 5, characterized in that: The first operation is an erase operation, and the first operation phase is an erase phase; or, The first operation is a programming operation, and the first operation phase is a programming phase.

9. A storage device, characterized in that: include: one or more processors; A storage module, used for storing one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors implement the control method of the storage device as described in any one of claims 5 to 8.

Images