Method and apparatus for controlling the shape of a pattern on a substrate

Abstract

The present invention relates to an apparatus and method for processing a substrate through a first stage and a second stage. In the first stage, a mixed gas application cycle is performed in a chamber holding the substrate. A first gas is introduced for a first time period to allow components of the first gas to adsorb onto the substrate. Subsequently, a second gas is introduced for a second time period to cause the second gas to react with the components of the first gas to provide a protective layer on sidewalls of a pattern of the substrate, and the second gas etches a bottom of the pattern, and a ratio of the first time period to the second time period is a usage ratio. Then, in the second stage, the mixed gas application cycle is repeated with different usage ratios corresponding to vertical dimensions of the pattern.

Description

[0001] Cross - reference to related applications

[0002] This application contains subject matter related to that described in pending U.S. patent application Ser. No. 16 / 212,847, entitled "Methods of Etching Films and Plasma Processing Equipment", filed on Dec. 7, 2018, the entire content of which is incorporated herein by reference in its entirety. Technical field

[0003] The present invention relates to semiconductor manufacturing equipment and generally relates to a method and apparatus for processing a substrate. More specifically, the present invention relates to a semiconductor manufacturing apparatus that uses processes such as atomic layer deposition (ALD), chemical vapor deposition (CVD), and atomic layer etching (ALE) to control the shape of patterns on a substrate. Background art

[0004] Over time, with the introduction of new technologies, semiconductor manufacturing methods have been improved, and as a result, the size of integrated circuits (ICs, microelectronic circuits, microchips, or simply "chips") manufactured as a single unit, as well as the feature sizes of the components on the ICs, have also decreased accordingly. Miniature active and passive semiconductor devices and interconnect devices are fabricated on a semiconductor substrate wafer (such as silicon). To form an integrated circuit, the wafer undergoes many processes such as doping, ion implantation, etching, thin - film deposition of various materials, and photolithographic patterning. Finally, the individual microcircuits are separated by wafer dicing and then individually packaged into integrated circuits.

[0005] Specific process steps for forming an IC on a substrate include atomic layer deposition (ALD), chemical vapor deposition (CVD), and atomic layer etching (ALE). Summary of the invention

[0006] In one embodiment, an apparatus and method for processing a substrate perform a mixed - gas application cycle in a chamber. In a first session, a first gas is introduced into the chamber for a first time period such that the components of the first gas are adsorbed onto the substrate. Subsequently, a second gas is introduced for a second time period such that the second gas reacts with the components of the first gas to provide a protective layer on the sidewalls of the pattern on the substrate and the second gas etches the bottom of the pattern, and the ratio of the first time period to the second time period is a use - ratio. The mixed - gas application cycle is repeated while maintaining the use - ratio. In a second stage, the mixed - gas application cycle is repeated with a different use - ratio corresponding to the vertical dimension of the pattern.

[0007] The present invention has been made in view of the inventors' recognition that conventional devices and methods do not vary the application time of an introduced precursor as an etch depth control relative to the application time of another gas during an etch operation. Additionally, the aspect ratio (A / R) of patterns (such as holes) formed during semiconductor manufacturing processes continues to increase. For example, in the case of a 3D NAND structure, the A / R can be as high as 45 or greater. While it is desirable to form holes with a uniform size at an exact location, using conventional methods, in certain regions of the holes, especially under the mask, the holes may exhibit downward tapering and / or bowing-out. In view of this challenge, the inventors have recognized the need to improve the dimensional control of high A / R patterns.

[0008] The foregoing paragraphs are provided in a general introductory fashion and are not intended to limit the scope of the following claims. The described embodiments, together with additional advantages, will be best understood from the following detailed description when read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The present invention, together with many of its attendant advantages, will be more fully understood when considered in conjunction with the following detailed description, which should be read in connection with the accompanying drawings, in which:

[0010] Figure 1 is a flow chart showing a process flow for processing a substrate according to an embodiment.

[0011] Figures 2A to 2D shows how a pattern is formed on a substrate. Specifically, Figure 2A shows the substrate provided in step S1 of Figure 1 ; Figure 2B shows the substrate on which the components of a first gas are adsorbed in step S2 of Figure 1 ; Figure 2C shows how the components of a second gas react with the adsorbed components of the first gas on the sidewalls of the holes in step S3 of Figure 1 ; and Figure 2D shows the substrate after performing all the steps in Figure 1 .

[0012] Figures 3A - 3C shows the results of performing consistent experiments according to the present invention.

[0013] Figure 4 is a diagram showing the resulting pattern in the substrate, showing which stage corresponds to the etch depth in the substrate.

[0014] Figure 5A shows the pattern obtained by performing the process of the embodiment.

[0015] Figure 5B shows the pattern obtained by performing a conventional method.

[0016] Figure 6 Shows Figure 1 A variant of step S3.

[0017] Figure 7 Is a schematic diagram of a device using capacitively coupled plasma.

[0018] Figure 8 Is a schematic diagram of a device using inductively coupled plasma.

[0019] Figure 9 Is a block diagram of a processing circuit system for performing the computer-based operations described in the present invention. Detailed implementation manners

[0020] The following description given in conjunction with the accompanying drawings is intended as a description of various embodiments of the disclosed subject matter and is not necessarily intended to represent the only embodiments. In certain instances, the description includes specific details for the purpose of providing an understanding of the disclosed subject matter. However, it will be apparent to those skilled in the art that the embodiments may be practiced without these specific details. In some instances, well-known structures and components may be shown in block diagram form to avoid obscuring the concepts of the disclosed subject matter.

[0021] References to "an embodiment" or "embodiments" throughout the specification mean that a particular feature, structure, characteristic, operation, or function described in connection with the embodiment is included in at least one embodiment of the disclosed subject matter. Thus, any occurrence of the phrases "in an embodiment" or "in embodiments" in the specification is not necessarily referring to the same embodiment. Additionally, in one or more embodiments, the particular features, structures, characteristics, operations, or functions may be combined in any suitable manner. Further, it is intended that the embodiments of the disclosed subject matter cover modifications and variations of the described embodiments.

[0022] It should be noted that, as used in the specification and the appended claims, unless the context clearly dictates otherwise, the singular forms "a", "an", and "the" include plural referents. That is, as used herein, the words "a" and "an" and the like carry the meaning of "one or more" unless clearly specified otherwise. Additionally, it should be understood that terms such as "left", "right", "top", "bottom", "front", "rear", "side", "height", "length", "width", "upper", "lower", "inner", "outer", "inside", "outside", etc., which may be used herein, merely describe reference points and need not limit the embodiments of the disclosed subject matter to any particular orientation or configuration. Further, terms such as "first", "second", "third", etc., merely identify one of a plurality of parts, components, reference points, operations, and / or functions as described herein and likewise need not limit the embodiments of the disclosed subject matter to any particular configuration or orientation.

[0023] Figure 1 is a flowchart showing a process flow for processing a substrate according to an embodiment. In step S1, a substrate having a pattern formed thereon (e.g., holes formed in one or more layers) is provided. For example, the substrate is transported into a chamber. One chamber is used in this embodiment, but different chambers may be used in steps S2 and S3. As will be discussed, according to the process of this embodiment, multiple "mixed gas application cycles" (applying a second gas after applying a first gas at a specific "usage ratio", where the second gas is applied immediately after the first gas, or after a certain time delay, or after performing one or more intermediate steps between applying the first gas or the second gas) are performed in each "phase" (a set of multiple mixed gas application cycles performed at the same usage ratio) to etch the holes to a first depth D1. Then, the process performs at least a second phase of multiple mixed gas application cycles at a "usage ratio" different from that used in the first phase to further etch the holes to a second depth D2. For clarity, although this specification uses the example of applying gases in steps S2 and S3, it should be understood that the teachings of the present invention are equally applicable to applying gas components in the form of plasma in steps S2 and S3, and to mixing the application of gas and / or plasma during all or part of either or both of steps S2 and S3. It should be understood that the term "mixed gas application cycle" includes the application of gas and / or plasma. In step S1, the cycle index c is initially set to 0, and the phase index is initially set to 1. The "usage ratio" is the ratio of the application time of the first gas to the second gas in one cycle.

[0024] Then, the process proceeds to step S2, where, as the first part of the first mixed gas application cycle, the first gas is applied to the chamber. Additionally, in step S2, the first gas (also referred to as the precursor), such as a silicon-containing gas, is applied to the chamber in which the substrate is placed. The precursor component of the first gas (such as Si, which is a component of the silicon-containing gas) adsorbs onto the substrate surface. For clarity, although Si is used as an exemplary precursor component in many places herein, it should be understood that precursor components other than or in addition to Si can also serve as viable precursor components that adsorb onto the substrate surface (such as the sidewalls). Furthermore, the present teachings are not intended to be limited to Si as the sole precursor component. The application of the first gas continues for a first time period t a .

[0025] Then, the process proceeds to step S3 (the second part of the mixed gas application cycle), where the second gas of the first mixed gas application cycle is supplied to the chamber for a duration t b . In the second step, the second gas (which can also be referred to as the reaction gas), such as an oxygen-containing gas (e.g., O* radicals), is supplied to the chamber. After step S2, step S3 continues the first cycle of the mixed gas application cycle, and as a result of performing step S3 of the first mixed gas application cycle, a protective layer is formed on the sidewalls of the holes while the bottom of the holes is partially etched. In the case where a silicon-containing gas is used as the precursor in step S2 and O* radicals are used as the gas in step S3, the protective layer formed on the sidewalls of the holes is SiO 2 .

[0026] The process proceeds to step S4, where the cycle index c is incremented by 1. Subsequently, in step S5, a determination is made as to whether the cycle index meets a threshold number C c,s , where "c" is the cycle index and "s" is the stage index. As an alternative decision reference, step S5 checks the etching depth at a specific stage. For example, referring to Figure 4 , D 1 corresponds to the etching depth at the completion of stage 1, D 2 corresponds to the etching depth at the completion of stage 2, D 3 corresponds to the etching depth at the end of stage 3. If the response to the determination in step S5 is negative, it means that more mixed gas application cycles need to be performed as part of the first stage. However, if the response to the determination in step S5 is positive, it means that the first stage is completed, and then the process proceeds to step S6

[0027] Step S6 performs another determination as to whether the stage index s has reached S maxIf the determination is affirmative, it means that all phases are completed. However, if the phase index s has not reached the maximum value, the process proceeds to step S7, where the phase index s is incremented by 1, and then the process proceeds to step S8.

[0028] In step S8, as part of the next phase, the usage ratio is changed, and the process returns to step S2 to perform another series of cycles with the new usage ratio until the next phase is completed. Finally, when the determination at step S6 confirms that the phase index s has reached S max the process ends. It should be noted that for Figure 4 the described embodiment, there are 3 time periods. However, as few as 2 phases can be performed, or more than 3 (such as 4 or more) phases can be performed.

[0029] The consecutive application of step S3 after step S2 is a single cycle of the mixed gas application cycle, which, as part of the first phase with a consistent usage ratio (the ratio of t a to t b ), can be repeated continuously multiple times. In addition, the repeated application of steps S2 and S3 continues for a predetermined number of cycles, which corresponds to the depth of the formed pattern reaching a first predetermined depth D1 (see Figure 4 ).

[0030] Regarding the usage ratio, the relative percentage (or absolute number) of the respective application times of the first gas and the second gas is changed according to the desired influence on the width or depth of the holes between the depth D1 and the deeper depth D2. In addition, the inventors have recognized that by controlling the amount of time for step S2 relative to the time allocated to step S3, the size (critical dimension) and shape of the pattern can be reliably formed. As a specific example, as part of a single mixed gas application cycle, step S2 can last for 15 seconds, after which step S3 can last for 10 seconds, and then this particular mixed gas application cycle can be repeated 7 more times until the depth D2 is reached. The repeated use of 8 consecutive single mixed gas application cycles can be referred to as the first mixed gas phase, or simply the "first phase". Then, in the second (and next) mixed gas phase, the usage ratio is changed relative to the usage ratio used in the first mixed gas phase.

[0031] The inventors have recognized that applying the first gas at a longer percentage (higher usage ratio) in step S2 will tend to provide a relatively thicker SiO at the sidewalls of the upper part (closer to the mask) of the holes 2A protective layer, whereby when the cations of the second gas bombard the bottom of the hole in step S3, the integrity and verticality of this part of the hole are maintained, thereby increasing the etching thickness. Subsequently, through the synergistic effect of repeating steps S2 and S3 during the first mixed gas stage for a predetermined number of cycles, the resulting hole will have a first characteristic shape reaching a predetermined depth. However, if the lower part of the hole is intended to be offset towards a curved profile (e.g., relative to a straight or tapered part), the shape of the bend at the lower depth can be controlled by changing the usage ratio of step S2 to step S3. Changing the usage ratio in favor of the amount of time for applying the second gas in step S3 means that the protective effect on the sidewalls due to applying the first gas in a shorter part in step S2 can be reduced. Subsequently, this will result in a wider (curved) part starting at depth D2, where the protective effect on the sidewalls is lower.

[0032] Figures 2A to 2D Shows a pattern formed on a substrate. Reference numeral 100 represents a lower layer formed on the substrate, such as a SiO 2 layer. Reference numeral 110 represents the layer to be etched, such as a Spin-On Carbon (SOC) layer. Reference numeral 120 represents a mask layer, such as a Si-containing anti-reflection coating (Si-ARC) layer. In Figures 2B - 2D a non-limiting example, "S" represents silicon or a silicon-containing component, "P" represents a cation, and "O" represents an O radical. Again, Si does not have to be the only adsorbed component, nor is it an exclusive component. Other components with or without Si can also be used on the sidewalls as a result of the adsorption process.

[0033] Figure 2A Shows the substrate to be provided in Figure 1 step S1.

[0034] Figure 2B Shows the substrate on which the precursor component S of the first gas is adsorbed on the surface of the mask layer 120 and the exposed part of the layer 110. Figure 2B Corresponds to Figure 1 step S2 in

[0035] Figure 2C Shows in Figure 1 step S3 how the components of the second gas react with Si (or other components adsorbed based on the precursor gas and / or plasma) on the hole sidewalls. In Figure 2C it is also shown that the cation P bombards and etches the bottom of the hole to deepen the hole. The sidewalls are shown to be formed by SiO formed by the combination of the Si precursor element S (from the first gas) and the O* radical particles O (from the second gas) 2Membrane protection. As described above, the aspect ratio and the depth of the holes can be controlled by the number of repetitions of Steps S2 and S3 and the usage ratio applied.

[0036] Figure 2D Shows the substrate after performing Steps S2 - S8 and achieving the depth D 3 When a protective layer is formed on the sidewalls, the bottom portion is etched away. Since the protective membrane is formed on the sidewalls, the aspect ratio can be well controlled without excessive taper or excessive bending.

[0037] Figures 3A - 3C Corresponds to the SEM image and shows the results of an exemplary process performed according to the process described above. Figure 3A Includes SEMs of three different patterns obtained from three different applications taught by the present invention. In each of Patterns A, B, and C, Step S2 ( Figure 1 ) lasts for 15 seconds, and then Step S3 ( Figure 1 ) lasts for 10 seconds, such that the usage ratio of a single mixed gas application cycle is 15 / 10 (or 1.5). Then, 7 (8 in total) mixed gas application cycles are increased. For Pattern A, the size of the holes is described by the width (critical dimension) at the top / arched region / bottom, so 30 / 34 / 25 in nanometers is provided at the bottom of the SEM. Patterns B and C provide other examples.

[0038] Figure 3B Similar, but in Step S2, the first gas is applied for 15 seconds, and in Step S3, the second gas is applied for 7.5 seconds (usage ratio of 15 / 7.5 or 2). A total of 11 mixed gas application cycles are performed for each of Patterns A, B, and C.

[0039] Figure 3C As another example, in this example, the first gas is applied for 15 seconds in Step S2, and the second gas is applied for 5 seconds in Step S3 (usage ratio of 15 / 5 or 3), and a total of 17 cycles are performed. By controlling the frequency (or usage ratio) of Step S2, the size (i.e., critical dimension) of the shape of the pattern can be controlled. There is no limitation on the material of the layer to be etched or the material of the layer formed by the first gas and the second gas.

[0040] The following describes obtaining Figures 3A - 3CConditions of the results shown in []. The length of the processing time was set such that the total time of step S3, i.e., the etching amount, was approximately the same for each of the three scenarios. The experiments were conducted based on the following conditions: In step S2, a silicon precursor / Ar (argon) flow rate of 100 / 300 sccm was used, and the silicon precursor (e.g., a gas mainly composed of aminosilane) was introduced into the chamber at a pressure of 200 mTorr for 15 seconds. The RF power applied to the upper and lower electrodes of the chamber was 0 W and 0 W, respectively. Subsequently, an optional purge step was performed, which purged the gas in the chamber at an Ar flow rate of 300 sccm, a pressure of 0 mTorr, and without applying RF power to the electrodes for 10 seconds. In step S3, RF power of 0 W and 350 W (40 MHz) was applied to the upper and lower electrodes, respectively, and an oxygen-containing gas was introduced into the chamber at a chamber pressure of 20 mTorr for the time mentioned above regarding Figures 3A - 3C The flow rates of O 2 / COS (carbonyl sulfide) were set to 350 / 50 sccm, respectively. This step is used to form a protective layer and simultaneously etch the bottom of the pattern. The above are the appropriate conditions for etching an organic film such as spin-on carbon (SOC).

[0041] The processing equipment has two electrodes, one located at the top of the chamber and the other at the bottom of the chamber. The RF values applied to the upper and lower electrodes are 60 / 40 MHz. Ar represents argon, and COS represents carbonyl sulfide. The temperature of the chamber part is not specifically limited. However, the temperature at the bottom of the chamber is preferably not too low. Approximately 40 degrees Celsius is appropriate because when the temperature at the bottom is low, the silicon precursor cannot be well adsorbed onto the substrate.

[0042] Figure 4 Indicates how the usage ratios in steps S2 and S3 ( Figure 1 ) change in phases 1, 2, and 3 to form the etching depths of D1, D2, and D3, respectively.

[0043] Similar to that shown by Figure 3A 、 3B and 3C in the SEM, Figure 5A shows the pattern obtained by performing the process according to the present embodiment. The chamber pressure, flow rate, temperature, and other conditions are the same as those discussed above for Figures 3A - 3C . However, in Figure 5AIn [the process], the three patterns (A, B, and C) are formed in three stages. In the first stage, there are 6 mixed gas application cycles. In each cycle of stage 1, the gas in step S2 is applied for 15 seconds and the gas in step S3 is applied for 5 seconds. The thickness of the SOC layer is 200 nm. In the second stage, there are 4 mixed gas application cycles, in which step S3 is applied for 7.5 seconds. In the third stage, there are 3 cycles, in which step S3 is applied for 10 seconds. The usage ratios used in stage 1 are 15 / 5 (or 3), in stage 2 are 15 / 7.5 (or 2), and in stage 3 are 15 / 10 (or 1.5). As a result, the top / center / bottom critical dimensions are quite uniform.

[0044] In contrast, Figure 5B shows the pattern obtained by performing the process according to the conventional etching method. Figure 5B corresponds to the SEM image. From the three patterns, it can be seen that each hole has a distinct bend under the Si-arc (ARC) mask and then a distinct taper at the bottom of the hole.

[0045] Figure 6 shows Figure 1 a variant of step S3. In Figure 2C , step S3 is shown as being performed in one step. However, step S3 can be divided into two steps, and the gases (or plasmas) used in steps S3-1 and S3-2 can be the same or different. In Figure 6 's embodiment, for step S3-1, the first condition can be set such that the second gas mainly reacts with the components on the sidewalls. Alternatively, the conditions of step S2 ( Figure 1 ) and step S3-1 can be set to achieve "fractal (sub-conformal)" ALD.. The conditions of step S3-2 are set to mainly etch the bottom of the hole. In Figure 6 's embodiment, the "usage ratio" refers to the ratio of the application time of the first gas in step S2 to the application time of the (second) gas in step S3-2 (i.e., etching). The application time of the second gas in step S3-1 is not a factor in the usage ratio of this embodiment.

[0046] Figure 7 What is shown is a capacitively coupled plasma (CCP) type plasma system. Figure 7The system includes: a chamber 1, an upper electrode 3, and a lower electrode 4. RF power is coupled from RF sources 6 and 7 to the upper electrode 3 and the lower electrode 4. The power coupling can include different RF frequencies 6, 7. The lower electrode 4 includes an electrostatic chuck (ESC) 5 for supporting and holding a substrate W. A gas source 8 is connected to the chamber 1 to supply a processing gas into the chamber 1. An exhaust device 9, such as a turbo molecular pump (TMP), is connected to the chamber 1 to evacuate the chamber 1. When RF power is supplied to at least one of the upper electrode 3 and the lower electrode 4, a plasma 2 is formed between the upper electrode 3 and the lower electrode 4 near the substrate W. Alternatively, multiple RF power sources 6, 7 can be coupled to the same electrode. In addition, a variable direct current (DC) power supply 10 can be coupled to the upper electrode 3.

[0047] Figure 8 An inductively coupled plasma (ICP) type plasma system is shown. The system includes: a chamber 11, a dielectric window 21, and a lower electrode 14. An inductive element (coil) 20 is placed above the dielectric window 21. RF power is coupled from RF sources 16, 17 to the inductive element 20 and the lower electrode 14. The power coupling can include different RF frequencies 16, 17. The lower electrode 14 includes an electrostatic chuck (ESC) 15 for supporting and holding a substrate W. A gas source 18 is connected to the chamber 11 to supply a processing gas into the chamber 11. An exhaust device 19, such as a turbo molecular pump (TMP), is connected to the chamber 11 to evacuate the chamber 11. When RF power is supplied to at least one of the dielectric window 21 and the lower electrode 14, a plasma 12 is formed between the dielectric window 21 and the lower electrode 14 near the substrate W.

[0048] Figure 9 A control circuit 130 that can be used to control any computer-based control process is shown. The descriptions or blocks in the flowcharts can be understood to represent modules, code segments, or portions of code, which include one or more executable instructions for implementing specific logical functions or steps in a process, and alternative implementations are included within the scope of the exemplary embodiments of the present invention, where the functions can be executed in the order shown or discussed, including substantially concurrently or in the reverse order, depending on the functions involved, as understood by those skilled in the art. The various elements, features, and processes described herein can be used independently of each other or can be combined in various ways. All feasible combinations and sub-combinations are intended to fall within the scope of the present invention.

[0049] In Figure 9In [the context], the processing circuit 130 includes a CPU 1200 that executes one or more of the control processes described above / below. Process data and instructions can be stored in the memory 1202. These processes and instructions can also be stored on a storage medium disk 1204 such as a hard disk (HDD) or a portable storage medium, or can be stored remotely. Additionally, the improvements claimed are not limited to the form of the computer-readable medium on which the instructions of the processes of the present invention are stored. For example, the instructions can be stored on a CD, DVD, flash memory, RAM, ROM, PROM, EPROM, EEPROM, hard disk, or any other information processing device (such as a server or a computer) that communicates with the processing circuit 130.

[0050] Additionally, the improvements claimed can be provided as a utility application, a background daemon, or an operating system component, or a combination thereof, so as to be executed in conjunction with the CPU 1200 and an operating system such as Microsoft Windows, UNIX, Solaris, LINUX, Apple MAC-OS, and other systems known to those skilled in the art.

[0051] To implement the processing circuit 130, its hardware elements can be implemented by various circuit system elements. Additionally, each function of the above-described embodiments can be implemented by a circuit including one or more processing circuits. The processing circuit includes a specially programmed processor, for example, a processor (CPU) 1200 as Figure 9 shown. The processing circuit also includes devices such as application-specific integrated circuits (ASICs) and conventional circuit components arranged to perform the functions.

[0052] In Figure 9 [the context], the processing circuitry 130 includes a CPU 1200 that executes the above processes. The processing circuit 130 can be a general-purpose computer or a specific dedicated machine. In one embodiment, when the processor 1200 is programmed to perform backscattering elimination from fog via time and space modulation (specifically, with reference to any one of the processes discussed in Figures 3A - 3C and Figure 1 ), the processing circuit 130 becomes a specific dedicated machine.

[0053] Alternatively or additionally, as recognized by those of ordinary skill in the art, the CPU 1200 can be implemented on an FPGA, ASIC, PLD, or using discrete logic circuits. Additionally, the CPU 1200 can be implemented as multiple processors working in parallel to execute the instructions of the above-described processes of the present invention.

[0054] Figure 9The processing circuit 130 therein further includes a network controller 1206 for interfacing with the network 1228, such as an Intel Ethernet PRO network interface card from Intel Corporation in the United States. It can be understood that the network 1228 can be a public network (such as the Internet) or a private network (such as a LAN or WAN network) or any combination thereof, and can also include a PSTN or ISDN subnet. The network 1228 can also be wired, such as an Ethernet network, or can be wireless, such as a cellular network including EDGE, 3G, and 4G wireless cellular systems. The wireless network can also be Wi-Fi, Bluetooth, or any known form of wireless communication.

[0055] The processing circuit 130 further includes a display controller 1208, such as a graphics card or graphics adapter for interfacing with a display 1210, such as a monitor. A general-purpose I / O interface 1212 is connected to a keyboard and / or mouse 1214 and a touchscreen panel 1216 on or separate from the display 1210. The general-purpose I / O interface is also connected to various peripheral devices 1218, including printers and scanners.

[0056] A general-purpose storage controller 1224 connects a storage medium disk 1204 to a communication bus 1226, which can be ISA, EISA, VESA, PCI, or the like, for interconnecting all components of the processing circuit 130. For the sake of brevity, the description of the general features and functions of the display 1210, the keyboard and / or mouse 1214, and the display controller 1208, the storage controller 1224, the network controller 1206, the sound controller 1220, and the general-purpose I / O interface 1212 is omitted here, because these features are known.

[0057] The exemplary circuit elements described in the context of the present invention can be replaced with other elements and can be organized in a manner different from the examples provided herein. In addition, a circuit system configured to perform the features described herein can be implemented with multiple circuit units (chips), or these features can be combined in a circuit system on a single chipset.

[0058] The functions and features described herein can also be performed by various distributed system components. For example, one or more processors can execute these system functions, where the processors are distributed among multiple components communicating in a network. In addition to various human-machine interfaces and communication devices (such as display monitors, smartphones, tablets, personal digital assistants (PDAs)), the distributed components can include one or more client and server machines. The network can be a private network, such as a LAN or WAN, or can be a public network, such as the Internet. System input can be received via direct user input or remotely in real time or as a batch process. Additionally, some embodiments can be performed on modules or hardware different from those described herein. Accordingly, other embodiments are within the scope of what can be claimed.

[0059] A process for fabricating a substrate with high aspect ratio patterns involves improvements in the dimensional control of the patterns formed. The process aims to control the size and shape of patterns (such as holes, trenches, line / space formed on a substrate). An example pattern is a hole. The process includes:

[0060] (a) Introducing a first gas (in the example, a Si precursor-containing gas) into a chamber to adsorb the components of the first gas onto the surface of the substrate.

[0061] (b) Introducing a second gas (in the example, O 2 ) into the chamber to react the second gas with the adsorbed Si precursor, thereby forming a protective layer on the sidewalls of the hole while the cations generated by the second gas directly bombard and etch the bottom of the hole. Steps (a) and (b) are repeatedly performed in this order until the depth of the hole reaches a predetermined level.

[0062] During this process, when the usage rate of step (a) is optimal (in other words, when the time of step (b) is shortened relative to the time of step (a)), the protective film on the sidewalls can be thickened. As a result, the sidewalls remain more intact, which is beneficial for preventing bending. When step (a) is performed at a lower usage rate (in other words, when the time of step (b) is extended relative to the time of step (a)), the formed protective film is thinner. As a result, the lower part of the sidewalls is etched and the bottom of the hole becomes wider, which is beneficial when vertically straight sidewalls are required. By controlling the frequency of (a), control over the size (i.e., critical dimension (CD)) and shape of the pattern can be obtained. There are no restrictions on the material of the layer to be etched or the formed layer, the first gas, and the second gas, and the combination can be appropriately determined.

[0063] A combined method of precursor adsorption and etching of a carbon hard mask (CHM) uses cyclic precursor adsorption followed by an organic film etching process with O* radicals. This method protects the sidewalls with a SiO 2 film while etching the organic film.

[0064] The present invention describes the formation of vertical holes without taper and bend or with a controllable amount of taper and / or bend. Using conventional processes, the holes typically taper towards the lower part of the hole. Here, the SOC layer is etched while the Si-ARC layer is used as a mask. After forming the holes in the SOC layer, the SiO 2 layer (which is thicker than indicated below) is etched while the SOC layer is used as a mask. Thus, the A / R ratio can be very high. The first gas and the second gas are cyclically applied such that the cumulative time period of the first gas and the second gas forms a relatively thick SiO 2 protective film on the sidewalls. In the second stage, the usage ratio is changed to prefer the second gas relative to the first gas, thereby widening the bottom of the hole (i.e., increasing the bottom CD) while preventing bending. In this way, the control of the A / R of relatively deep holes can be achieved. As can be seen from the SEM of Figure 5A and 5B , when the above process is adopted, the CD is more uniform. Figure 5A shows the new method of the present invention, while Figure 5B shows the result of conventional etching - O 2 / COS. In Figure 5B , the holes bend under the Si-ARC (mask) and then taper towards the bottom. While in Figure 5A , the top / center / bottom CD is more uniform.

[0065] The advantages of the present invention include flexibility. With flexibility, patterns of desired shapes or sizes can be obtained by controlling the frequency of precursor introduction. This method is basically applicable to various patterns. In the etching of organic films, the SiO 2 film with high etching selectivity can be used as a protective layer. Since the SiO 2 layer is formed thin, the possibility of hole blockage can be reduced. Since the protective layer is formed by a self-limiting reaction, the thickness of the formed film can be uniform across the entire substrate. Since the protective layer is formed by a self-limiting reaction, the protective layer can be formed with a high A / R pattern, and this process achieves high controllability in forming patterns.

[0066] Embodiments of the disclosed subject matter have now been described. It should be apparent to those skilled in the art that the foregoing is illustrative only and not limiting, presented merely by way of example. Thus, while specific configurations have been discussed herein, other configurations may also be employed. Many modifications and other embodiments (e.g., combinations, rearrangements, etc.) are enabled by the present invention and within the scope of those skilled in the art and are considered to fall within the scope of the disclosed subject matter and its equivalents. Features of the disclosed embodiments may be combined, rearranged, omitted, etc. within the scope of the present invention to obtain additional embodiments. Further, certain features may sometimes be used to advantage without correspondingly using other features. Accordingly, the applicant intends to cover all such alternatives, modifications, equivalents, and variations that are within the spirit and scope of the disclosed subject matter.

Claims

1. A method for processing a substrate, comprising the following steps: In a first stage, a mixed gas application cycle is performed in a chamber holding the substrate, including: introducing a first gas into the chamber for a first time period to adsorb the components of the first gas onto the substrate, and subsequently, introducing a second gas for a second time period to react the second gas with the components of the first gas to provide a protective layer on the sidewalls of the pattern on the substrate, and the second gas etches the bottom of the pattern, and the ratio of the first time period to the second time period is a usage ratio; and In a second stage, the mixed gas application cycle is repeated with a different usage ratio, and the different usage ratio corresponds to the vertical dimension of the pattern.

2. The method according to claim 1, wherein the first gas is a precursor and the second gas is a reaction gas.

3. The method according to claim 2, wherein the precursor is a silicon-containing gas and the reaction gas is an oxygen radical gas.

4. The method according to claim 1, wherein the pattern is a hole, and the usage ratio in the first stage is set to be less than the different usage ratio in the second stage to form a hole with a gradually narrowing shape.

5. The method according to claim 1, wherein the pattern is a hole, and the usage ratio used in the first stage is set to be greater than the different usage ratio in the second stage to form a hole with a wider dimension towards the bottom of the hole.

6. The method according to claim 1, further comprising: In the first stage, the mixed gas application cycle is repeated while maintaining the usage ratio.

7. The method according to claim 1, further comprising: Performing a third stage by repeating the mixed gas application cycle with a usage ratio greater than the usage ratio in the first stage and the different usage ratio in the second stage.

8. The method according to claim 7, wherein the number of mixed gas application cycles performed in the first stage is greater than the number of mixed gas application cycles performed in the second stage, and the usage ratio in the first stage is greater than the different usage ratio in the second stage.

9. The method according to claim 8, wherein the number of mixed gas application cycles performed in the second stage is greater than the number of mixed gas application cycles performed in the third stage, and the different usage ratio in the second stage is greater than the usage ratio in the third stage.

10. The method according to claim 1, wherein the mixed gas application cycle includes applying at least one of the first gas and the second gas as a plasma.

11. The method according to claim 1, wherein introducing the second gas includes introducing the second gas after a predetermined time has elapsed after the first time period.

12. The method according to claim 1, further comprising: In the first stage, an intermediate step is performed between introducing the first gas and introducing the second gas.

13. The method according to claim 1, wherein the chamber used in the step of introducing the first gas is different from the chamber used in the step of introducing the second gas.

14. A method of processing a substrate, comprising the steps of: In a first stage, performing a mixed gas application cycle in a chamber holding a substrate, the cycle including: introducing a first gas into the chamber for a first time period to allow the components of the first gas to adsorb onto the substrate, subsequently, introducing a second gas under a first condition to react the second gas with the components of the first gas to provide a protective layer on the sidewalls of the pattern on the substrate, and subsequently, introducing another gas under a second condition for a second time period to etch the bottom of the pattern, the ratio of the first time period to the second time period being a usage ratio; and In a second stage, repeating the mixed gas application cycle with a different usage ratio corresponding to the vertical dimension of the pattern.

15. The method according to claim 14, further comprising: in the first stage, repeating the mixed gas application cycle while maintaining the usage ratio.

16. The method according to claim 14, wherein the mixed gas application cycle includes applying at least one of the first gas and the second gas as a plasma.

17. An apparatus for processing a substrate in a chamber, the apparatus comprising: a non-transitory computer-readable memory having instructions stored therein; a circuit configured to execute the instructions to control plasma processing in the chamber, the plasma processing including: in a first stage, controlling the execution of a mixed gas application cycle in a chamber holding a substrate, the mixed gas application cycle including: introducing a first gas into the chamber for a first time period to allow the components of the first gas to adsorb onto the substrate, and subsequently, introducing a second gas for a second time period to react the second gas with the components of the first gas to provide a protective layer on the sidewalls of the pattern on the substrate, and the second gas etching the bottom of the pattern, the ratio of the first time period to the second time period being a usage ratio; and in a second stage, repeating the control of the mixed gas application cycle with a different usage ratio corresponding to the vertical dimension of the pattern.

18. The apparatus according to claim 17, wherein the circuit is further configured to repeat the mixed gas application cycle while maintaining the usage ratio, with at least one of the first gas and the second gas being used as a plasma.

19. The apparatus according to claim 17, wherein the pattern is a hole, and the usage ratio in the first stage is set to be less than the different usage ratio in the second stage to form a hole with a gradually narrowing shape.

20. The apparatus according to claim 17, wherein the pattern is a hole, and the usage ratio used in the first stage is set to be greater than the different usage ratio in the second stage to form a hole having a wider dimension towards the bottom of the hole.

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